181629cbaSAlex Deucher /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 281629cbaSAlex Deucher * 381629cbaSAlex Deucher * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 481629cbaSAlex Deucher * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 581629cbaSAlex Deucher * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 681629cbaSAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 781629cbaSAlex Deucher * 881629cbaSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 981629cbaSAlex Deucher * copy of this software and associated documentation files (the "Software"), 1081629cbaSAlex Deucher * to deal in the Software without restriction, including without limitation 1181629cbaSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1281629cbaSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1381629cbaSAlex Deucher * Software is furnished to do so, subject to the following conditions: 1481629cbaSAlex Deucher * 1581629cbaSAlex Deucher * The above copyright notice and this permission notice shall be included in 1681629cbaSAlex Deucher * all copies or substantial portions of the Software. 1781629cbaSAlex Deucher * 1881629cbaSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1981629cbaSAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2081629cbaSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2181629cbaSAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2281629cbaSAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2381629cbaSAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2481629cbaSAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2581629cbaSAlex Deucher * 2681629cbaSAlex Deucher * Authors: 2781629cbaSAlex Deucher * Kevin E. Martin <martin@valinux.com> 2881629cbaSAlex Deucher * Gareth Hughes <gareth@valinux.com> 2981629cbaSAlex Deucher * Keith Whitwell <keith@tungstengraphics.com> 3081629cbaSAlex Deucher */ 3181629cbaSAlex Deucher 3281629cbaSAlex Deucher #ifndef __AMDGPU_DRM_H__ 3381629cbaSAlex Deucher #define __AMDGPU_DRM_H__ 3481629cbaSAlex Deucher 35b3fcf36aSMichel Dänzer #include "drm.h" 3681629cbaSAlex Deucher 37cfa7152fSEmil Velikov #if defined(__cplusplus) 38cfa7152fSEmil Velikov extern "C" { 39cfa7152fSEmil Velikov #endif 40cfa7152fSEmil Velikov 4181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_CREATE 0x00 4281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_MMAP 0x01 4381629cbaSAlex Deucher #define DRM_AMDGPU_CTX 0x02 4481629cbaSAlex Deucher #define DRM_AMDGPU_BO_LIST 0x03 4581629cbaSAlex Deucher #define DRM_AMDGPU_CS 0x04 4681629cbaSAlex Deucher #define DRM_AMDGPU_INFO 0x05 4781629cbaSAlex Deucher #define DRM_AMDGPU_GEM_METADATA 0x06 4881629cbaSAlex Deucher #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 4981629cbaSAlex Deucher #define DRM_AMDGPU_GEM_VA 0x08 5081629cbaSAlex Deucher #define DRM_AMDGPU_WAIT_CS 0x09 5181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_OP 0x10 5281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_USERPTR 0x11 53eef18a82SJunwei Zhang #define DRM_AMDGPU_WAIT_FENCES 0x12 54cfbcacf4SChunming Zhou #define DRM_AMDGPU_VM 0x13 557ca24cf2SMarek Olšák #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 5652c6a62cSAndres Rodriguez #define DRM_AMDGPU_SCHED 0x15 5781629cbaSAlex Deucher 5881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 5981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 6081629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 6181629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 6281629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 6381629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 6481629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 6581629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 6634b5f6a6SChristian König #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 6781629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 6881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 6981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70eef18a82SJunwei Zhang #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71cfbcacf4SChunming Zhou #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 727ca24cf2SMarek Olšák #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 7352c6a62cSAndres Rodriguez #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 7481629cbaSAlex Deucher 75b646c1dcSSamuel Li /** 76b646c1dcSSamuel Li * DOC: memory domains 77b646c1dcSSamuel Li * 78b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79b646c1dcSSamuel Li * Memory in this pool could be swapped out to disk if there is pressure. 80b646c1dcSSamuel Li * 81b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82b646c1dcSSamuel Li * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83b646c1dcSSamuel Li * pages of system memory, allows GPU access system memory in a linezrized 84b646c1dcSSamuel Li * fashion. 85b646c1dcSSamuel Li * 86b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87b646c1dcSSamuel Li * carved out by the BIOS. 88b646c1dcSSamuel Li * 89b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90b646c1dcSSamuel Li * across shader threads. 91b646c1dcSSamuel Li * 92b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93b646c1dcSSamuel Li * execution of all the waves on a device. 94b646c1dcSSamuel Li * 95b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96b646c1dcSSamuel Li * for appending data. 97b646c1dcSSamuel Li */ 9881629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_CPU 0x1 9981629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GTT 0x2 10081629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_VRAM 0x4 10181629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GDS 0x8 10281629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GWS 0x10 10381629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_OA 0x20 1043f188453SChunming Zhou #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 1053f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GTT | \ 1063f188453SChunming Zhou AMDGPU_GEM_DOMAIN_VRAM | \ 1073f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GDS | \ 1083f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GWS | \ 1093f188453SChunming Zhou AMDGPU_GEM_DOMAIN_OA) 11081629cbaSAlex Deucher 11181629cbaSAlex Deucher /* Flag that CPU access will be required for the case of VRAM domain */ 11281629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 11381629cbaSAlex Deucher /* Flag that CPU access will not work, this VRAM domain is invisible */ 11481629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 11581629cbaSAlex Deucher /* Flag that USWC attributes should be used for GTT */ 11688671288SJammy Zhou #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 1174fea83ffSFlora Cui /* Flag that the memory should be in VRAM and cleared */ 1184fea83ffSFlora Cui #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119e7893c4bSChunming Zhou /* Flag that create shadow bo(GTT) while allocating vram bo */ 120e7893c4bSChunming Zhou #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 12103f48dd5SChristian König /* Flag that allocating the BO should use linear VRAM */ 12203f48dd5SChristian König #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 123e1eb899bSChristian König /* Flag that BO is always valid in this VM */ 124e1eb899bSChristian König #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 125177ae09bSAndres Rodriguez /* Flag that BO sharing will be explicitly synchronized */ 126177ae09bSAndres Rodriguez #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 127959a2091SYong Zhao /* Flag that indicates allocating MQD gart on GFX9, where the mtype 128fa5bde80SYong Zhao * for the second page onward should be set to NC. It should never 129fa5bde80SYong Zhao * be used by user space applications. 130959a2091SYong Zhao */ 131fa5bde80SYong Zhao #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 132d8f4981eSFelix Kuehling /* Flag that BO may contain sensitive data that must be wiped before 133d8f4981eSFelix Kuehling * releasing the memory 134d8f4981eSFelix Kuehling */ 135d8f4981eSFelix Kuehling #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 13635ce0060SAlex Deucher /* Flag that BO will be encrypted and that the TMZ bit should be 13735ce0060SAlex Deucher * set in the PTEs when mapping this buffer via GPUVM or 13835ce0060SAlex Deucher * accessing it with various hw blocks 13935ce0060SAlex Deucher */ 14035ce0060SAlex Deucher #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 14181629cbaSAlex Deucher 14281629cbaSAlex Deucher struct drm_amdgpu_gem_create_in { 14381629cbaSAlex Deucher /** the requested memory size */ 1442ce9dde0SMikko Rapeli __u64 bo_size; 14581629cbaSAlex Deucher /** physical start_addr alignment in bytes for some HW requirements */ 1462ce9dde0SMikko Rapeli __u64 alignment; 14781629cbaSAlex Deucher /** the requested memory domains */ 1482ce9dde0SMikko Rapeli __u64 domains; 14981629cbaSAlex Deucher /** allocation flags */ 1502ce9dde0SMikko Rapeli __u64 domain_flags; 15181629cbaSAlex Deucher }; 15281629cbaSAlex Deucher 15381629cbaSAlex Deucher struct drm_amdgpu_gem_create_out { 15481629cbaSAlex Deucher /** returned GEM object handle */ 1552ce9dde0SMikko Rapeli __u32 handle; 1562ce9dde0SMikko Rapeli __u32 _pad; 15781629cbaSAlex Deucher }; 15881629cbaSAlex Deucher 15981629cbaSAlex Deucher union drm_amdgpu_gem_create { 16081629cbaSAlex Deucher struct drm_amdgpu_gem_create_in in; 16181629cbaSAlex Deucher struct drm_amdgpu_gem_create_out out; 16281629cbaSAlex Deucher }; 16381629cbaSAlex Deucher 16481629cbaSAlex Deucher /** Opcode to create new residency list. */ 16581629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_CREATE 0 16681629cbaSAlex Deucher /** Opcode to destroy previously created residency list */ 16781629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_DESTROY 1 16881629cbaSAlex Deucher /** Opcode to update resource information in the list */ 16981629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_UPDATE 2 17081629cbaSAlex Deucher 17181629cbaSAlex Deucher struct drm_amdgpu_bo_list_in { 17281629cbaSAlex Deucher /** Type of operation */ 1732ce9dde0SMikko Rapeli __u32 operation; 17481629cbaSAlex Deucher /** Handle of list or 0 if we want to create one */ 1752ce9dde0SMikko Rapeli __u32 list_handle; 17681629cbaSAlex Deucher /** Number of BOs in list */ 1772ce9dde0SMikko Rapeli __u32 bo_number; 17881629cbaSAlex Deucher /** Size of each element describing BO */ 1792ce9dde0SMikko Rapeli __u32 bo_info_size; 18081629cbaSAlex Deucher /** Pointer to array describing BOs */ 1812ce9dde0SMikko Rapeli __u64 bo_info_ptr; 18281629cbaSAlex Deucher }; 18381629cbaSAlex Deucher 18481629cbaSAlex Deucher struct drm_amdgpu_bo_list_entry { 18581629cbaSAlex Deucher /** Handle of BO */ 1862ce9dde0SMikko Rapeli __u32 bo_handle; 18781629cbaSAlex Deucher /** New (if specified) BO priority to be used during migration */ 1882ce9dde0SMikko Rapeli __u32 bo_priority; 18981629cbaSAlex Deucher }; 19081629cbaSAlex Deucher 19181629cbaSAlex Deucher struct drm_amdgpu_bo_list_out { 19281629cbaSAlex Deucher /** Handle of resource list */ 1932ce9dde0SMikko Rapeli __u32 list_handle; 1942ce9dde0SMikko Rapeli __u32 _pad; 19581629cbaSAlex Deucher }; 19681629cbaSAlex Deucher 19781629cbaSAlex Deucher union drm_amdgpu_bo_list { 19881629cbaSAlex Deucher struct drm_amdgpu_bo_list_in in; 19981629cbaSAlex Deucher struct drm_amdgpu_bo_list_out out; 20081629cbaSAlex Deucher }; 20181629cbaSAlex Deucher 20281629cbaSAlex Deucher /* context related */ 20381629cbaSAlex Deucher #define AMDGPU_CTX_OP_ALLOC_CTX 1 20481629cbaSAlex Deucher #define AMDGPU_CTX_OP_FREE_CTX 2 20581629cbaSAlex Deucher #define AMDGPU_CTX_OP_QUERY_STATE 3 206bc1b1bf6SMonk Liu #define AMDGPU_CTX_OP_QUERY_STATE2 4 20781629cbaSAlex Deucher 208e90c2b21SLuben Tuikov /* Flag the command submission as secure */ 209e90c2b21SLuben Tuikov #define AMDGPU_CS_FLAGS_SECURE (1 << 0) 210e90c2b21SLuben Tuikov 211d94aed5aSMarek Olšák /* GPU reset status */ 212d94aed5aSMarek Olšák #define AMDGPU_CTX_NO_RESET 0 213675da0ddSChristian König /* this the context caused it */ 214675da0ddSChristian König #define AMDGPU_CTX_GUILTY_RESET 1 215675da0ddSChristian König /* some other context caused it */ 216675da0ddSChristian König #define AMDGPU_CTX_INNOCENT_RESET 2 217675da0ddSChristian König /* unknown cause */ 218675da0ddSChristian König #define AMDGPU_CTX_UNKNOWN_RESET 3 219d94aed5aSMarek Olšák 220bc1b1bf6SMonk Liu /* indicate gpu reset occured after ctx created */ 221bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 222bc1b1bf6SMonk Liu /* indicate vram lost occured after ctx created */ 223bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 224bc1b1bf6SMonk Liu /* indicate some job from this context once cause gpu hang */ 225bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 226ae363a21Sxinhui pan /* indicate some errors are detected by RAS */ 227ae363a21Sxinhui pan #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 228ae363a21Sxinhui pan #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 229bc1b1bf6SMonk Liu 230c2636dc5SAndres Rodriguez /* Context priority level */ 231f3d19bf8SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_UNSET -2048 2328bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 2338bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_LOW -512 234c2636dc5SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_NORMAL 0 235cf034477SEmil Velikov /* 236cf034477SEmil Velikov * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 237cf034477SEmil Velikov * CAP_SYS_NICE or DRM_MASTER 238cf034477SEmil Velikov */ 2398bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_HIGH 512 2408bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 241c2636dc5SAndres Rodriguez 24281629cbaSAlex Deucher struct drm_amdgpu_ctx_in { 243675da0ddSChristian König /** AMDGPU_CTX_OP_* */ 2442ce9dde0SMikko Rapeli __u32 op; 245675da0ddSChristian König /** For future use, no flags defined so far */ 2462ce9dde0SMikko Rapeli __u32 flags; 2472ce9dde0SMikko Rapeli __u32 ctx_id; 248cf034477SEmil Velikov /** AMDGPU_CTX_PRIORITY_* */ 249c2636dc5SAndres Rodriguez __s32 priority; 25081629cbaSAlex Deucher }; 25181629cbaSAlex Deucher 25281629cbaSAlex Deucher union drm_amdgpu_ctx_out { 25381629cbaSAlex Deucher struct { 2542ce9dde0SMikko Rapeli __u32 ctx_id; 2552ce9dde0SMikko Rapeli __u32 _pad; 25681629cbaSAlex Deucher } alloc; 25781629cbaSAlex Deucher 25881629cbaSAlex Deucher struct { 259675da0ddSChristian König /** For future use, no flags defined so far */ 2602ce9dde0SMikko Rapeli __u64 flags; 261d94aed5aSMarek Olšák /** Number of resets caused by this context so far. */ 2622ce9dde0SMikko Rapeli __u32 hangs; 263d94aed5aSMarek Olšák /** Reset status since the last call of the ioctl. */ 2642ce9dde0SMikko Rapeli __u32 reset_status; 26581629cbaSAlex Deucher } state; 26681629cbaSAlex Deucher }; 26781629cbaSAlex Deucher 26881629cbaSAlex Deucher union drm_amdgpu_ctx { 26981629cbaSAlex Deucher struct drm_amdgpu_ctx_in in; 27081629cbaSAlex Deucher union drm_amdgpu_ctx_out out; 27181629cbaSAlex Deucher }; 27281629cbaSAlex Deucher 273cfbcacf4SChunming Zhou /* vm ioctl */ 274cfbcacf4SChunming Zhou #define AMDGPU_VM_OP_RESERVE_VMID 1 275cfbcacf4SChunming Zhou #define AMDGPU_VM_OP_UNRESERVE_VMID 2 276cfbcacf4SChunming Zhou 277cfbcacf4SChunming Zhou struct drm_amdgpu_vm_in { 278cfbcacf4SChunming Zhou /** AMDGPU_VM_OP_* */ 279cfbcacf4SChunming Zhou __u32 op; 280cfbcacf4SChunming Zhou __u32 flags; 281cfbcacf4SChunming Zhou }; 282cfbcacf4SChunming Zhou 283cfbcacf4SChunming Zhou struct drm_amdgpu_vm_out { 284cfbcacf4SChunming Zhou /** For future use, no flags defined so far */ 285cfbcacf4SChunming Zhou __u64 flags; 286cfbcacf4SChunming Zhou }; 287cfbcacf4SChunming Zhou 288cfbcacf4SChunming Zhou union drm_amdgpu_vm { 289cfbcacf4SChunming Zhou struct drm_amdgpu_vm_in in; 290cfbcacf4SChunming Zhou struct drm_amdgpu_vm_out out; 291cfbcacf4SChunming Zhou }; 292cfbcacf4SChunming Zhou 29352c6a62cSAndres Rodriguez /* sched ioctl */ 29452c6a62cSAndres Rodriguez #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 295b5bb37edSBas Nieuwenhuizen #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 29652c6a62cSAndres Rodriguez 29752c6a62cSAndres Rodriguez struct drm_amdgpu_sched_in { 29852c6a62cSAndres Rodriguez /* AMDGPU_SCHED_OP_* */ 29952c6a62cSAndres Rodriguez __u32 op; 30052c6a62cSAndres Rodriguez __u32 fd; 301cf034477SEmil Velikov /** AMDGPU_CTX_PRIORITY_* */ 30252c6a62cSAndres Rodriguez __s32 priority; 303b5bb37edSBas Nieuwenhuizen __u32 ctx_id; 30452c6a62cSAndres Rodriguez }; 30552c6a62cSAndres Rodriguez 30652c6a62cSAndres Rodriguez union drm_amdgpu_sched { 30752c6a62cSAndres Rodriguez struct drm_amdgpu_sched_in in; 30852c6a62cSAndres Rodriguez }; 30952c6a62cSAndres Rodriguez 31081629cbaSAlex Deucher /* 31181629cbaSAlex Deucher * This is not a reliable API and you should expect it to fail for any 31281629cbaSAlex Deucher * number of reasons and have fallback path that do not use userptr to 31381629cbaSAlex Deucher * perform any operation. 31481629cbaSAlex Deucher */ 31581629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 31681629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 31781629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 31881629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 31981629cbaSAlex Deucher 32081629cbaSAlex Deucher struct drm_amdgpu_gem_userptr { 3212ce9dde0SMikko Rapeli __u64 addr; 3222ce9dde0SMikko Rapeli __u64 size; 323675da0ddSChristian König /* AMDGPU_GEM_USERPTR_* */ 3242ce9dde0SMikko Rapeli __u32 flags; 325675da0ddSChristian König /* Resulting GEM handle */ 3262ce9dde0SMikko Rapeli __u32 handle; 32781629cbaSAlex Deucher }; 32881629cbaSAlex Deucher 32900ac6f6bSAlex Deucher /* SI-CI-VI: */ 330fbd76d59SMarek Olšák /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 331fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 332fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 333fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 334fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 335fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 336fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 337fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 338fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 339fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 340fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 341fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 342fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 343fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 344fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 345fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 346fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 347fbd76d59SMarek Olšák 34800ac6f6bSAlex Deucher /* GFX9 and later: */ 34900ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 35000ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 351ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 352ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 353ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 354ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 355ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 356ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 357c5705372SMarek Olšák #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 358c5705372SMarek Olšák #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 359c5705372SMarek Olšák #define AMDGPU_TILING_SCANOUT_SHIFT 63 360c5705372SMarek Olšák #define AMDGPU_TILING_SCANOUT_MASK 0x1 36100ac6f6bSAlex Deucher 36200ac6f6bSAlex Deucher /* Set/Get helpers for tiling flags. */ 363fbd76d59SMarek Olšák #define AMDGPU_TILING_SET(field, value) \ 36400ac6f6bSAlex Deucher (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 365fbd76d59SMarek Olšák #define AMDGPU_TILING_GET(value, field) \ 36600ac6f6bSAlex Deucher (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 36781629cbaSAlex Deucher 36881629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 36981629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 37081629cbaSAlex Deucher 37181629cbaSAlex Deucher /** The same structure is shared for input/output */ 37281629cbaSAlex Deucher struct drm_amdgpu_gem_metadata { 373675da0ddSChristian König /** GEM Object handle */ 3742ce9dde0SMikko Rapeli __u32 handle; 375675da0ddSChristian König /** Do we want get or set metadata */ 3762ce9dde0SMikko Rapeli __u32 op; 37781629cbaSAlex Deucher struct { 378675da0ddSChristian König /** For future use, no flags defined so far */ 3792ce9dde0SMikko Rapeli __u64 flags; 380675da0ddSChristian König /** family specific tiling info */ 3812ce9dde0SMikko Rapeli __u64 tiling_info; 3822ce9dde0SMikko Rapeli __u32 data_size_bytes; 3832ce9dde0SMikko Rapeli __u32 data[64]; 38481629cbaSAlex Deucher } data; 38581629cbaSAlex Deucher }; 38681629cbaSAlex Deucher 38781629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in { 388675da0ddSChristian König /** the GEM object handle */ 3892ce9dde0SMikko Rapeli __u32 handle; 3902ce9dde0SMikko Rapeli __u32 _pad; 39181629cbaSAlex Deucher }; 39281629cbaSAlex Deucher 39381629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out { 394675da0ddSChristian König /** mmap offset from the vma offset manager */ 3952ce9dde0SMikko Rapeli __u64 addr_ptr; 39681629cbaSAlex Deucher }; 39781629cbaSAlex Deucher 39881629cbaSAlex Deucher union drm_amdgpu_gem_mmap { 39981629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in in; 40081629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out out; 40181629cbaSAlex Deucher }; 40281629cbaSAlex Deucher 40381629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in { 404675da0ddSChristian König /** GEM object handle */ 4052ce9dde0SMikko Rapeli __u32 handle; 406675da0ddSChristian König /** For future use, no flags defined so far */ 4072ce9dde0SMikko Rapeli __u32 flags; 408675da0ddSChristian König /** Absolute timeout to wait */ 4092ce9dde0SMikko Rapeli __u64 timeout; 41081629cbaSAlex Deucher }; 41181629cbaSAlex Deucher 41281629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out { 413675da0ddSChristian König /** BO status: 0 - BO is idle, 1 - BO is busy */ 4142ce9dde0SMikko Rapeli __u32 status; 415675da0ddSChristian König /** Returned current memory domain */ 4162ce9dde0SMikko Rapeli __u32 domain; 41781629cbaSAlex Deucher }; 41881629cbaSAlex Deucher 41981629cbaSAlex Deucher union drm_amdgpu_gem_wait_idle { 42081629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in in; 42181629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out out; 42281629cbaSAlex Deucher }; 42381629cbaSAlex Deucher 42481629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in { 425d7b1eeb2SMonk Liu /* Command submission handle 426d7b1eeb2SMonk Liu * handle equals 0 means none to wait for 427080b24ebSAlex Deucher * handle equals ~0ull means wait for the latest sequence number 428d7b1eeb2SMonk Liu */ 4292ce9dde0SMikko Rapeli __u64 handle; 430675da0ddSChristian König /** Absolute timeout to wait */ 4312ce9dde0SMikko Rapeli __u64 timeout; 4322ce9dde0SMikko Rapeli __u32 ip_type; 4332ce9dde0SMikko Rapeli __u32 ip_instance; 4342ce9dde0SMikko Rapeli __u32 ring; 4352ce9dde0SMikko Rapeli __u32 ctx_id; 43681629cbaSAlex Deucher }; 43781629cbaSAlex Deucher 43881629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out { 439675da0ddSChristian König /** CS status: 0 - CS completed, 1 - CS still busy */ 4402ce9dde0SMikko Rapeli __u64 status; 44181629cbaSAlex Deucher }; 44281629cbaSAlex Deucher 44381629cbaSAlex Deucher union drm_amdgpu_wait_cs { 44481629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in in; 44581629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out out; 44681629cbaSAlex Deucher }; 44781629cbaSAlex Deucher 448eef18a82SJunwei Zhang struct drm_amdgpu_fence { 449eef18a82SJunwei Zhang __u32 ctx_id; 450eef18a82SJunwei Zhang __u32 ip_type; 451eef18a82SJunwei Zhang __u32 ip_instance; 452eef18a82SJunwei Zhang __u32 ring; 453eef18a82SJunwei Zhang __u64 seq_no; 454eef18a82SJunwei Zhang }; 455eef18a82SJunwei Zhang 456eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in { 457eef18a82SJunwei Zhang /** This points to uint64_t * which points to fences */ 458eef18a82SJunwei Zhang __u64 fences; 459eef18a82SJunwei Zhang __u32 fence_count; 460eef18a82SJunwei Zhang __u32 wait_all; 461eef18a82SJunwei Zhang __u64 timeout_ns; 462eef18a82SJunwei Zhang }; 463eef18a82SJunwei Zhang 464eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out { 465eef18a82SJunwei Zhang __u32 status; 466eef18a82SJunwei Zhang __u32 first_signaled; 467eef18a82SJunwei Zhang }; 468eef18a82SJunwei Zhang 469eef18a82SJunwei Zhang union drm_amdgpu_wait_fences { 470eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in in; 471eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out out; 472eef18a82SJunwei Zhang }; 473eef18a82SJunwei Zhang 47481629cbaSAlex Deucher #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 475d8f65a23SMarek Olšák #define AMDGPU_GEM_OP_SET_PLACEMENT 1 47681629cbaSAlex Deucher 477675da0ddSChristian König /* Sets or returns a value associated with a buffer. */ 478675da0ddSChristian König struct drm_amdgpu_gem_op { 479675da0ddSChristian König /** GEM object handle */ 4802ce9dde0SMikko Rapeli __u32 handle; 481675da0ddSChristian König /** AMDGPU_GEM_OP_* */ 4822ce9dde0SMikko Rapeli __u32 op; 483675da0ddSChristian König /** Input or return value */ 4842ce9dde0SMikko Rapeli __u64 value; 485675da0ddSChristian König }; 486675da0ddSChristian König 48781629cbaSAlex Deucher #define AMDGPU_VA_OP_MAP 1 48881629cbaSAlex Deucher #define AMDGPU_VA_OP_UNMAP 2 489dc54d3d1SChristian König #define AMDGPU_VA_OP_CLEAR 3 49080f95c57SChristian König #define AMDGPU_VA_OP_REPLACE 4 49181629cbaSAlex Deucher 492fc220f65SChristian König /* Delay the page table update till the next CS */ 493fc220f65SChristian König #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 494fc220f65SChristian König 49581629cbaSAlex Deucher /* Mapping flags */ 49681629cbaSAlex Deucher /* readable mapping */ 49781629cbaSAlex Deucher #define AMDGPU_VM_PAGE_READABLE (1 << 1) 49881629cbaSAlex Deucher /* writable mapping */ 49981629cbaSAlex Deucher #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 50081629cbaSAlex Deucher /* executable mapping, new for VI */ 50181629cbaSAlex Deucher #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 502b85891bdSJunwei Zhang /* partially resident texture */ 503b85891bdSJunwei Zhang #define AMDGPU_VM_PAGE_PRT (1 << 4) 50466e02bc3SAlex Xie /* MTYPE flags use bit 5 to 8 */ 50566e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 50666e02bc3SAlex Xie /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 50766e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 50866e02bc3SAlex Xie /* Use NC MTYPE instead of default MTYPE */ 50966e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_NC (1 << 5) 51066e02bc3SAlex Xie /* Use WC MTYPE instead of default MTYPE */ 51166e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_WC (2 << 5) 51266e02bc3SAlex Xie /* Use CC MTYPE instead of default MTYPE */ 51366e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_CC (3 << 5) 51466e02bc3SAlex Xie /* Use UC MTYPE instead of default MTYPE */ 51566e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_UC (4 << 5) 516484deaedSOak Zeng /* Use RW MTYPE instead of default MTYPE */ 517484deaedSOak Zeng #define AMDGPU_VM_MTYPE_RW (5 << 5) 51881629cbaSAlex Deucher 51934b5f6a6SChristian König struct drm_amdgpu_gem_va { 520675da0ddSChristian König /** GEM object handle */ 5212ce9dde0SMikko Rapeli __u32 handle; 5222ce9dde0SMikko Rapeli __u32 _pad; 523675da0ddSChristian König /** AMDGPU_VA_OP_* */ 5242ce9dde0SMikko Rapeli __u32 operation; 525675da0ddSChristian König /** AMDGPU_VM_PAGE_* */ 5262ce9dde0SMikko Rapeli __u32 flags; 527675da0ddSChristian König /** va address to assign . Must be correctly aligned.*/ 5282ce9dde0SMikko Rapeli __u64 va_address; 529675da0ddSChristian König /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 5302ce9dde0SMikko Rapeli __u64 offset_in_bo; 531675da0ddSChristian König /** Specify mapping size. Must be correctly aligned. */ 5322ce9dde0SMikko Rapeli __u64 map_size; 53381629cbaSAlex Deucher }; 53481629cbaSAlex Deucher 53581629cbaSAlex Deucher #define AMDGPU_HW_IP_GFX 0 53681629cbaSAlex Deucher #define AMDGPU_HW_IP_COMPUTE 1 53781629cbaSAlex Deucher #define AMDGPU_HW_IP_DMA 2 53881629cbaSAlex Deucher #define AMDGPU_HW_IP_UVD 3 53981629cbaSAlex Deucher #define AMDGPU_HW_IP_VCE 4 540a50798b6SLeo Liu #define AMDGPU_HW_IP_UVD_ENC 5 54166e236f1SLeo Liu #define AMDGPU_HW_IP_VCN_DEC 6 542fcfc5a90SLeo Liu #define AMDGPU_HW_IP_VCN_ENC 7 54381d35014SBoyuan Zhang #define AMDGPU_HW_IP_VCN_JPEG 8 54481d35014SBoyuan Zhang #define AMDGPU_HW_IP_NUM 9 54581629cbaSAlex Deucher 54681629cbaSAlex Deucher #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 54781629cbaSAlex Deucher 54881629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_IB 0x01 54981629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_FENCE 0x02 5502b48d323SChristian König #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 551660e8558SDave Airlie #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 552660e8558SDave Airlie #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 553964d0fbfSAndrey Grodzovsky #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 55467dd1a36SAndrey Grodzovsky #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 5552624dd15SChunming Zhou #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 5562624dd15SChunming Zhou #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 557675da0ddSChristian König 55881629cbaSAlex Deucher struct drm_amdgpu_cs_chunk { 5592ce9dde0SMikko Rapeli __u32 chunk_id; 5602ce9dde0SMikko Rapeli __u32 length_dw; 5612ce9dde0SMikko Rapeli __u64 chunk_data; 56281629cbaSAlex Deucher }; 56381629cbaSAlex Deucher 56481629cbaSAlex Deucher struct drm_amdgpu_cs_in { 56581629cbaSAlex Deucher /** Rendering context id */ 5662ce9dde0SMikko Rapeli __u32 ctx_id; 56781629cbaSAlex Deucher /** Handle of resource list associated with CS */ 5682ce9dde0SMikko Rapeli __u32 bo_list_handle; 5692ce9dde0SMikko Rapeli __u32 num_chunks; 570e90c2b21SLuben Tuikov __u32 flags; 5712ce9dde0SMikko Rapeli /** this points to __u64 * which point to cs chunks */ 5722ce9dde0SMikko Rapeli __u64 chunks; 57381629cbaSAlex Deucher }; 57481629cbaSAlex Deucher 57581629cbaSAlex Deucher struct drm_amdgpu_cs_out { 5762ce9dde0SMikko Rapeli __u64 handle; 57781629cbaSAlex Deucher }; 57881629cbaSAlex Deucher 57981629cbaSAlex Deucher union drm_amdgpu_cs { 58081629cbaSAlex Deucher struct drm_amdgpu_cs_in in; 58181629cbaSAlex Deucher struct drm_amdgpu_cs_out out; 58281629cbaSAlex Deucher }; 58381629cbaSAlex Deucher 58481629cbaSAlex Deucher /* Specify flags to be used for IB */ 58581629cbaSAlex Deucher 58681629cbaSAlex Deucher /* This IB should be submitted to CE */ 58781629cbaSAlex Deucher #define AMDGPU_IB_FLAG_CE (1<<0) 58881629cbaSAlex Deucher 589ed834af2SMonk Liu /* Preamble flag, which means the IB could be dropped if no context switch */ 590cab6d57cSJammy Zhou #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 591aa2bdb24SJammy Zhou 59271aec257SMonk Liu /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 59371aec257SMonk Liu #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 59471aec257SMonk Liu 595d240cd9eSMarek Olšák /* The IB fence should do the L2 writeback but not invalidate any shader 596d240cd9eSMarek Olšák * caches (L2/vL1/sL1/I$). */ 597d240cd9eSMarek Olšák #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 598d240cd9eSMarek Olšák 59941cca166SMarek Olšák /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 60041cca166SMarek Olšák * This will reset wave ID counters for the IB. 60141cca166SMarek Olšák */ 60241cca166SMarek Olšák #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 60341cca166SMarek Olšák 60481629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib { 6052ce9dde0SMikko Rapeli __u32 _pad; 606675da0ddSChristian König /** AMDGPU_IB_FLAG_* */ 6072ce9dde0SMikko Rapeli __u32 flags; 608675da0ddSChristian König /** Virtual address to begin IB execution */ 6092ce9dde0SMikko Rapeli __u64 va_start; 610675da0ddSChristian König /** Size of submission */ 6112ce9dde0SMikko Rapeli __u32 ib_bytes; 612675da0ddSChristian König /** HW IP to submit to */ 6132ce9dde0SMikko Rapeli __u32 ip_type; 614675da0ddSChristian König /** HW IP index of the same type to submit to */ 6152ce9dde0SMikko Rapeli __u32 ip_instance; 616675da0ddSChristian König /** Ring index to submit to */ 6172ce9dde0SMikko Rapeli __u32 ring; 61881629cbaSAlex Deucher }; 61981629cbaSAlex Deucher 6202b48d323SChristian König struct drm_amdgpu_cs_chunk_dep { 6212ce9dde0SMikko Rapeli __u32 ip_type; 6222ce9dde0SMikko Rapeli __u32 ip_instance; 6232ce9dde0SMikko Rapeli __u32 ring; 6242ce9dde0SMikko Rapeli __u32 ctx_id; 6252ce9dde0SMikko Rapeli __u64 handle; 6262b48d323SChristian König }; 6272b48d323SChristian König 62881629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence { 6292ce9dde0SMikko Rapeli __u32 handle; 6302ce9dde0SMikko Rapeli __u32 offset; 63181629cbaSAlex Deucher }; 63281629cbaSAlex Deucher 633660e8558SDave Airlie struct drm_amdgpu_cs_chunk_sem { 634660e8558SDave Airlie __u32 handle; 635660e8558SDave Airlie }; 636660e8558SDave Airlie 6372624dd15SChunming Zhou struct drm_amdgpu_cs_chunk_syncobj { 6382624dd15SChunming Zhou __u32 handle; 6392624dd15SChunming Zhou __u32 flags; 6402624dd15SChunming Zhou __u64 point; 6412624dd15SChunming Zhou }; 6422624dd15SChunming Zhou 6437ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 6447ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 6457ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 6467ca24cf2SMarek Olšák 6477ca24cf2SMarek Olšák union drm_amdgpu_fence_to_handle { 6487ca24cf2SMarek Olšák struct { 6497ca24cf2SMarek Olšák struct drm_amdgpu_fence fence; 6507ca24cf2SMarek Olšák __u32 what; 65156e0349fSDave Airlie __u32 pad; 6527ca24cf2SMarek Olšák } in; 6537ca24cf2SMarek Olšák struct { 6547ca24cf2SMarek Olšák __u32 handle; 6557ca24cf2SMarek Olšák } out; 6567ca24cf2SMarek Olšák }; 6577ca24cf2SMarek Olšák 65881629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_data { 65981629cbaSAlex Deucher union { 66081629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib ib_data; 66181629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence fence_data; 66281629cbaSAlex Deucher }; 66381629cbaSAlex Deucher }; 66481629cbaSAlex Deucher 66581629cbaSAlex Deucher /** 66681629cbaSAlex Deucher * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 66781629cbaSAlex Deucher * 66881629cbaSAlex Deucher */ 66981629cbaSAlex Deucher #define AMDGPU_IDS_FLAGS_FUSION 0x1 670aafcafa0SMonk Liu #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 67181629cbaSAlex Deucher 67281629cbaSAlex Deucher /* indicate if acceleration can be working */ 67381629cbaSAlex Deucher #define AMDGPU_INFO_ACCEL_WORKING 0x00 67481629cbaSAlex Deucher /* get the crtc_id from the mode object id? */ 67581629cbaSAlex Deucher #define AMDGPU_INFO_CRTC_FROM_ID 0x01 67681629cbaSAlex Deucher /* query hw IP info */ 67781629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_INFO 0x02 67881629cbaSAlex Deucher /* query hw IP instance count for the specified type */ 67981629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_COUNT 0x03 68081629cbaSAlex Deucher /* timestamp for GL_ARB_timer_query */ 68181629cbaSAlex Deucher #define AMDGPU_INFO_TIMESTAMP 0x05 68281629cbaSAlex Deucher /* Query the firmware version */ 68381629cbaSAlex Deucher #define AMDGPU_INFO_FW_VERSION 0x0e 68481629cbaSAlex Deucher /* Subquery id: Query VCE firmware version */ 68581629cbaSAlex Deucher #define AMDGPU_INFO_FW_VCE 0x1 68681629cbaSAlex Deucher /* Subquery id: Query UVD firmware version */ 68781629cbaSAlex Deucher #define AMDGPU_INFO_FW_UVD 0x2 68881629cbaSAlex Deucher /* Subquery id: Query GMC firmware version */ 68981629cbaSAlex Deucher #define AMDGPU_INFO_FW_GMC 0x03 69081629cbaSAlex Deucher /* Subquery id: Query GFX ME firmware version */ 69181629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_ME 0x04 69281629cbaSAlex Deucher /* Subquery id: Query GFX PFP firmware version */ 69381629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_PFP 0x05 69481629cbaSAlex Deucher /* Subquery id: Query GFX CE firmware version */ 69581629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_CE 0x06 69681629cbaSAlex Deucher /* Subquery id: Query GFX RLC firmware version */ 69781629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_RLC 0x07 69881629cbaSAlex Deucher /* Subquery id: Query GFX MEC firmware version */ 69981629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_MEC 0x08 70081629cbaSAlex Deucher /* Subquery id: Query SMC firmware version */ 70181629cbaSAlex Deucher #define AMDGPU_INFO_FW_SMC 0x0a 70281629cbaSAlex Deucher /* Subquery id: Query SDMA firmware version */ 70381629cbaSAlex Deucher #define AMDGPU_INFO_FW_SDMA 0x0b 7046a7ed07eSHuang Rui /* Subquery id: Query PSP SOS firmware version */ 7056a7ed07eSHuang Rui #define AMDGPU_INFO_FW_SOS 0x0c 7066a7ed07eSHuang Rui /* Subquery id: Query PSP ASD firmware version */ 7076a7ed07eSHuang Rui #define AMDGPU_INFO_FW_ASD 0x0d 7083ac952b1SAlex Deucher /* Subquery id: Query VCN firmware version */ 7093ac952b1SAlex Deucher #define AMDGPU_INFO_FW_VCN 0x0e 710621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLC firmware version */ 711621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 712621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLG firmware version */ 713621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 714621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLS firmware version */ 715621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 7164d11b4b2SDavid Francis /* Subquery id: Query DMCU firmware version */ 7174d11b4b2SDavid Francis #define AMDGPU_INFO_FW_DMCU 0x12 7189b9ca62dSxinhui pan #define AMDGPU_INFO_FW_TA 0x13 719976e51a7SNicholas Kazlauskas /* Subquery id: Query DMCUB firmware version */ 720976e51a7SNicholas Kazlauskas #define AMDGPU_INFO_FW_DMCUB 0x14 721976e51a7SNicholas Kazlauskas 72281629cbaSAlex Deucher /* number of bytes moved for TTM migration */ 72381629cbaSAlex Deucher #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 72481629cbaSAlex Deucher /* the used VRAM size */ 72581629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_USAGE 0x10 72681629cbaSAlex Deucher /* the used GTT size */ 72781629cbaSAlex Deucher #define AMDGPU_INFO_GTT_USAGE 0x11 72881629cbaSAlex Deucher /* Information about GDS, etc. resource configuration */ 72981629cbaSAlex Deucher #define AMDGPU_INFO_GDS_CONFIG 0x13 73081629cbaSAlex Deucher /* Query information about VRAM and GTT domains */ 73181629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_GTT 0x14 73281629cbaSAlex Deucher /* Query information about register in MMR address space*/ 73381629cbaSAlex Deucher #define AMDGPU_INFO_READ_MMR_REG 0x15 73481629cbaSAlex Deucher /* Query information about device: rev id, family, etc. */ 73581629cbaSAlex Deucher #define AMDGPU_INFO_DEV_INFO 0x16 73681629cbaSAlex Deucher /* visible vram usage */ 73781629cbaSAlex Deucher #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 73883a59b63SMarek Olšák /* number of TTM buffer evictions */ 73983a59b63SMarek Olšák #define AMDGPU_INFO_NUM_EVICTIONS 0x18 740e0adf6c8SJunwei Zhang /* Query memory about VRAM and GTT domains */ 741e0adf6c8SJunwei Zhang #define AMDGPU_INFO_MEMORY 0x19 742bbe87974SAlex Deucher /* Query vce clock table */ 743bbe87974SAlex Deucher #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 74440ee5888SEvan Quan /* Query vbios related information */ 74540ee5888SEvan Quan #define AMDGPU_INFO_VBIOS 0x1B 74640ee5888SEvan Quan /* Subquery id: Query vbios size */ 74740ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_SIZE 0x1 74840ee5888SEvan Quan /* Subquery id: Query vbios image */ 74940ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_IMAGE 0x2 75044879b62SArindam Nath /* Query UVD handles */ 75144879b62SArindam Nath #define AMDGPU_INFO_NUM_HANDLES 0x1C 7525ebbac4bSAlex Deucher /* Query sensor related information */ 7535ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR 0x1D 7545ebbac4bSAlex Deucher /* Subquery id: Query GPU shader clock */ 7555ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 7565ebbac4bSAlex Deucher /* Subquery id: Query GPU memory clock */ 7575ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 7585ebbac4bSAlex Deucher /* Subquery id: Query GPU temperature */ 7595ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 7605ebbac4bSAlex Deucher /* Subquery id: Query GPU load */ 7615ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 7625ebbac4bSAlex Deucher /* Subquery id: Query average GPU power */ 7635ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 7645ebbac4bSAlex Deucher /* Subquery id: Query northbridge voltage */ 7655ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDNB 0x6 7665ebbac4bSAlex Deucher /* Subquery id: Query graphics voltage */ 7675ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 76860bbade2SRex Zhu /* Subquery id: Query GPU stable pstate shader clock */ 76960bbade2SRex Zhu #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 77060bbade2SRex Zhu /* Subquery id: Query GPU stable pstate memory clock */ 77160bbade2SRex Zhu #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 77268e2c5ffSMarek Olšák /* Number of VRAM page faults on CPU access. */ 77368e2c5ffSMarek Olšák #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 7741f7251b7SChristian König #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 7755cb77114Sxinhui pan /* query ras mask of enabled features*/ 7765cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 7775cb77114Sxinhui pan 7785cb77114Sxinhui pan /* RAS MASK: UMC (VRAM) */ 7795cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 7805cb77114Sxinhui pan /* RAS MASK: SDMA */ 7815cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 7825cb77114Sxinhui pan /* RAS MASK: GFX */ 7835cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 7845cb77114Sxinhui pan /* RAS MASK: MMHUB */ 7855cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 7865cb77114Sxinhui pan /* RAS MASK: ATHUB */ 7875cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 7885cb77114Sxinhui pan /* RAS MASK: PCIE */ 7895cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 7905cb77114Sxinhui pan /* RAS MASK: HDP */ 7915cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 7925cb77114Sxinhui pan /* RAS MASK: XGMI */ 7935cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 7945cb77114Sxinhui pan /* RAS MASK: DF */ 7955cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 7965cb77114Sxinhui pan /* RAS MASK: SMN */ 7975cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 7985cb77114Sxinhui pan /* RAS MASK: SEM */ 7995cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 8005cb77114Sxinhui pan /* RAS MASK: MP0 */ 8015cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 8025cb77114Sxinhui pan /* RAS MASK: MP1 */ 8035cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 8045cb77114Sxinhui pan /* RAS MASK: FUSE */ 8055cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 80681629cbaSAlex Deucher 80781629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 80881629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 80981629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 81081629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 81181629cbaSAlex Deucher 812000cab9aSHuang Rui struct drm_amdgpu_query_fw { 813000cab9aSHuang Rui /** AMDGPU_INFO_FW_* */ 814000cab9aSHuang Rui __u32 fw_type; 815000cab9aSHuang Rui /** 816000cab9aSHuang Rui * Index of the IP if there are more IPs of 817000cab9aSHuang Rui * the same type. 818000cab9aSHuang Rui */ 819000cab9aSHuang Rui __u32 ip_instance; 820000cab9aSHuang Rui /** 821000cab9aSHuang Rui * Index of the engine. Whether this is used depends 822000cab9aSHuang Rui * on the firmware type. (e.g. MEC, SDMA) 823000cab9aSHuang Rui */ 824000cab9aSHuang Rui __u32 index; 825000cab9aSHuang Rui __u32 _pad; 826000cab9aSHuang Rui }; 827000cab9aSHuang Rui 82881629cbaSAlex Deucher /* Input structure for the INFO ioctl */ 82981629cbaSAlex Deucher struct drm_amdgpu_info { 83081629cbaSAlex Deucher /* Where the return value will be stored */ 8312ce9dde0SMikko Rapeli __u64 return_pointer; 83281629cbaSAlex Deucher /* The size of the return value. Just like "size" in "snprintf", 83381629cbaSAlex Deucher * it limits how many bytes the kernel can write. */ 8342ce9dde0SMikko Rapeli __u32 return_size; 83581629cbaSAlex Deucher /* The query request id. */ 8362ce9dde0SMikko Rapeli __u32 query; 83781629cbaSAlex Deucher 83881629cbaSAlex Deucher union { 83981629cbaSAlex Deucher struct { 8402ce9dde0SMikko Rapeli __u32 id; 8412ce9dde0SMikko Rapeli __u32 _pad; 84281629cbaSAlex Deucher } mode_crtc; 84381629cbaSAlex Deucher 84481629cbaSAlex Deucher struct { 84581629cbaSAlex Deucher /** AMDGPU_HW_IP_* */ 8462ce9dde0SMikko Rapeli __u32 type; 84781629cbaSAlex Deucher /** 848675da0ddSChristian König * Index of the IP if there are more IPs of the same 849675da0ddSChristian König * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 85081629cbaSAlex Deucher */ 8512ce9dde0SMikko Rapeli __u32 ip_instance; 85281629cbaSAlex Deucher } query_hw_ip; 85381629cbaSAlex Deucher 85481629cbaSAlex Deucher struct { 8552ce9dde0SMikko Rapeli __u32 dword_offset; 856675da0ddSChristian König /** number of registers to read */ 8572ce9dde0SMikko Rapeli __u32 count; 8582ce9dde0SMikko Rapeli __u32 instance; 859675da0ddSChristian König /** For future use, no flags defined so far */ 8602ce9dde0SMikko Rapeli __u32 flags; 86181629cbaSAlex Deucher } read_mmr_reg; 86281629cbaSAlex Deucher 863000cab9aSHuang Rui struct drm_amdgpu_query_fw query_fw; 86440ee5888SEvan Quan 86540ee5888SEvan Quan struct { 86640ee5888SEvan Quan __u32 type; 86740ee5888SEvan Quan __u32 offset; 86840ee5888SEvan Quan } vbios_info; 8695ebbac4bSAlex Deucher 8705ebbac4bSAlex Deucher struct { 8715ebbac4bSAlex Deucher __u32 type; 8725ebbac4bSAlex Deucher } sensor_info; 87381629cbaSAlex Deucher }; 87481629cbaSAlex Deucher }; 87581629cbaSAlex Deucher 87681629cbaSAlex Deucher struct drm_amdgpu_info_gds { 87781629cbaSAlex Deucher /** GDS GFX partition size */ 8782ce9dde0SMikko Rapeli __u32 gds_gfx_partition_size; 87981629cbaSAlex Deucher /** GDS compute partition size */ 8802ce9dde0SMikko Rapeli __u32 compute_partition_size; 88181629cbaSAlex Deucher /** total GDS memory size */ 8822ce9dde0SMikko Rapeli __u32 gds_total_size; 88381629cbaSAlex Deucher /** GWS size per GFX partition */ 8842ce9dde0SMikko Rapeli __u32 gws_per_gfx_partition; 88581629cbaSAlex Deucher /** GSW size per compute partition */ 8862ce9dde0SMikko Rapeli __u32 gws_per_compute_partition; 88781629cbaSAlex Deucher /** OA size per GFX partition */ 8882ce9dde0SMikko Rapeli __u32 oa_per_gfx_partition; 88981629cbaSAlex Deucher /** OA size per compute partition */ 8902ce9dde0SMikko Rapeli __u32 oa_per_compute_partition; 8912ce9dde0SMikko Rapeli __u32 _pad; 89281629cbaSAlex Deucher }; 89381629cbaSAlex Deucher 89481629cbaSAlex Deucher struct drm_amdgpu_info_vram_gtt { 8952ce9dde0SMikko Rapeli __u64 vram_size; 8962ce9dde0SMikko Rapeli __u64 vram_cpu_accessible_size; 8972ce9dde0SMikko Rapeli __u64 gtt_size; 89881629cbaSAlex Deucher }; 89981629cbaSAlex Deucher 900e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info { 901e0adf6c8SJunwei Zhang /** max. physical memory */ 902e0adf6c8SJunwei Zhang __u64 total_heap_size; 903e0adf6c8SJunwei Zhang 904e0adf6c8SJunwei Zhang /** Theoretical max. available memory in the given heap */ 905e0adf6c8SJunwei Zhang __u64 usable_heap_size; 906e0adf6c8SJunwei Zhang 907e0adf6c8SJunwei Zhang /** 908e0adf6c8SJunwei Zhang * Number of bytes allocated in the heap. This includes all processes 909e0adf6c8SJunwei Zhang * and private allocations in the kernel. It changes when new buffers 910e0adf6c8SJunwei Zhang * are allocated, freed, and moved. It cannot be larger than 911e0adf6c8SJunwei Zhang * heap_size. 912e0adf6c8SJunwei Zhang */ 913e0adf6c8SJunwei Zhang __u64 heap_usage; 914e0adf6c8SJunwei Zhang 915e0adf6c8SJunwei Zhang /** 916e0adf6c8SJunwei Zhang * Theoretical possible max. size of buffer which 917e0adf6c8SJunwei Zhang * could be allocated in the given heap 918e0adf6c8SJunwei Zhang */ 919e0adf6c8SJunwei Zhang __u64 max_allocation; 9209f6163e7SJunwei Zhang }; 9219f6163e7SJunwei Zhang 922e0adf6c8SJunwei Zhang struct drm_amdgpu_memory_info { 923e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info vram; 924e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info cpu_accessible_vram; 925e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info gtt; 926cfa32556SJunwei Zhang }; 927cfa32556SJunwei Zhang 92881629cbaSAlex Deucher struct drm_amdgpu_info_firmware { 9292ce9dde0SMikko Rapeli __u32 ver; 9302ce9dde0SMikko Rapeli __u32 feature; 93181629cbaSAlex Deucher }; 93281629cbaSAlex Deucher 93381c59f54SKen Wang #define AMDGPU_VRAM_TYPE_UNKNOWN 0 93481c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR1 1 93581c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR2 2 93681c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR3 3 93781c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR4 4 93881c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR5 5 93981c59f54SKen Wang #define AMDGPU_VRAM_TYPE_HBM 6 94081c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR3 7 9411e09b053SHawking Zhang #define AMDGPU_VRAM_TYPE_DDR4 8 942d67383e6SHuang Rui #define AMDGPU_VRAM_TYPE_GDDR6 9 94381c59f54SKen Wang 94481629cbaSAlex Deucher struct drm_amdgpu_info_device { 94581629cbaSAlex Deucher /** PCI Device ID */ 9462ce9dde0SMikko Rapeli __u32 device_id; 94781629cbaSAlex Deucher /** Internal chip revision: A0, A1, etc.) */ 9482ce9dde0SMikko Rapeli __u32 chip_rev; 9492ce9dde0SMikko Rapeli __u32 external_rev; 95081629cbaSAlex Deucher /** Revision id in PCI Config space */ 9512ce9dde0SMikko Rapeli __u32 pci_rev; 9522ce9dde0SMikko Rapeli __u32 family; 9532ce9dde0SMikko Rapeli __u32 num_shader_engines; 9542ce9dde0SMikko Rapeli __u32 num_shader_arrays_per_engine; 955675da0ddSChristian König /* in KHz */ 9562ce9dde0SMikko Rapeli __u32 gpu_counter_freq; 9572ce9dde0SMikko Rapeli __u64 max_engine_clock; 9582ce9dde0SMikko Rapeli __u64 max_memory_clock; 95981629cbaSAlex Deucher /* cu information */ 9602ce9dde0SMikko Rapeli __u32 cu_active_number; 961dbfe85eaSFlora Cui /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 9622ce9dde0SMikko Rapeli __u32 cu_ao_mask; 9632ce9dde0SMikko Rapeli __u32 cu_bitmap[4][4]; 96481629cbaSAlex Deucher /** Render backend pipe mask. One render backend is CB+DB. */ 9652ce9dde0SMikko Rapeli __u32 enabled_rb_pipes_mask; 9662ce9dde0SMikko Rapeli __u32 num_rb_pipes; 9672ce9dde0SMikko Rapeli __u32 num_hw_gfx_contexts; 9682ce9dde0SMikko Rapeli __u32 _pad; 9692ce9dde0SMikko Rapeli __u64 ids_flags; 97081629cbaSAlex Deucher /** Starting virtual address for UMDs. */ 9712ce9dde0SMikko Rapeli __u64 virtual_address_offset; 97202b70c8cSJammy Zhou /** The maximum virtual address */ 9732ce9dde0SMikko Rapeli __u64 virtual_address_max; 97481629cbaSAlex Deucher /** Required alignment of virtual addresses. */ 9752ce9dde0SMikko Rapeli __u32 virtual_address_alignment; 97681629cbaSAlex Deucher /** Page table entry - fragment size */ 9772ce9dde0SMikko Rapeli __u32 pte_fragment_size; 9782ce9dde0SMikko Rapeli __u32 gart_page_size; 979a101a899SKen Wang /** constant engine ram size*/ 9802ce9dde0SMikko Rapeli __u32 ce_ram_size; 981cab6d57cSJammy Zhou /** video memory type info*/ 9822ce9dde0SMikko Rapeli __u32 vram_type; 98381c59f54SKen Wang /** video memory bit width*/ 9842ce9dde0SMikko Rapeli __u32 vram_bit_width; 985fa92754eSLeo Liu /* vce harvesting instance */ 9862ce9dde0SMikko Rapeli __u32 vce_harvest_config; 987df6e2c4aSJunwei Zhang /* gfx double offchip LDS buffers */ 988df6e2c4aSJunwei Zhang __u32 gc_double_offchip_lds_buf; 989bce23e00SAlex Deucher /* NGG Primitive Buffer */ 990bce23e00SAlex Deucher __u64 prim_buf_gpu_addr; 991bce23e00SAlex Deucher /* NGG Position Buffer */ 992bce23e00SAlex Deucher __u64 pos_buf_gpu_addr; 993bce23e00SAlex Deucher /* NGG Control Sideband */ 994bce23e00SAlex Deucher __u64 cntl_sb_buf_gpu_addr; 995bce23e00SAlex Deucher /* NGG Parameter Cache */ 996bce23e00SAlex Deucher __u64 param_buf_gpu_addr; 997408bfe7cSJunwei Zhang __u32 prim_buf_size; 998408bfe7cSJunwei Zhang __u32 pos_buf_size; 999408bfe7cSJunwei Zhang __u32 cntl_sb_buf_size; 1000408bfe7cSJunwei Zhang __u32 param_buf_size; 1001408bfe7cSJunwei Zhang /* wavefront size*/ 1002408bfe7cSJunwei Zhang __u32 wave_front_size; 1003408bfe7cSJunwei Zhang /* shader visible vgprs*/ 1004408bfe7cSJunwei Zhang __u32 num_shader_visible_vgprs; 1005408bfe7cSJunwei Zhang /* CU per shader array*/ 1006408bfe7cSJunwei Zhang __u32 num_cu_per_sh; 1007408bfe7cSJunwei Zhang /* number of tcc blocks*/ 1008408bfe7cSJunwei Zhang __u32 num_tcc_blocks; 1009408bfe7cSJunwei Zhang /* gs vgt table depth*/ 1010408bfe7cSJunwei Zhang __u32 gs_vgt_table_depth; 1011408bfe7cSJunwei Zhang /* gs primitive buffer depth*/ 1012408bfe7cSJunwei Zhang __u32 gs_prim_buffer_depth; 1013408bfe7cSJunwei Zhang /* max gs wavefront per vgt*/ 1014408bfe7cSJunwei Zhang __u32 max_gs_waves_per_vgt; 1015408bfe7cSJunwei Zhang __u32 _pad1; 1016dbfe85eaSFlora Cui /* always on cu bitmap */ 1017dbfe85eaSFlora Cui __u32 cu_ao_bitmap[4][4]; 10185b565e0eSChristian König /** Starting high virtual address for UMDs. */ 10195b565e0eSChristian König __u64 high_va_offset; 10205b565e0eSChristian König /** The maximum high virtual address */ 10215b565e0eSChristian König __u64 high_va_max; 102222e96fa6SHawking Zhang /* gfx10 pa_sc_tile_steering_override */ 102322e96fa6SHawking Zhang __u32 pa_sc_tile_steering_override; 1024cf21e76aSMarek Olšák /* disabled TCCs */ 1025cf21e76aSMarek Olšák __u64 tcc_disabled_mask; 102681629cbaSAlex Deucher }; 102781629cbaSAlex Deucher 102881629cbaSAlex Deucher struct drm_amdgpu_info_hw_ip { 102981629cbaSAlex Deucher /** Version of h/w IP */ 10302ce9dde0SMikko Rapeli __u32 hw_ip_version_major; 10312ce9dde0SMikko Rapeli __u32 hw_ip_version_minor; 103281629cbaSAlex Deucher /** Capabilities */ 10332ce9dde0SMikko Rapeli __u64 capabilities_flags; 103471062f43SKen Wang /** command buffer address start alignment*/ 10352ce9dde0SMikko Rapeli __u32 ib_start_alignment; 103671062f43SKen Wang /** command buffer size alignment*/ 10372ce9dde0SMikko Rapeli __u32 ib_size_alignment; 103881629cbaSAlex Deucher /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 10392ce9dde0SMikko Rapeli __u32 available_rings; 10402ce9dde0SMikko Rapeli __u32 _pad; 104181629cbaSAlex Deucher }; 104281629cbaSAlex Deucher 104344879b62SArindam Nath struct drm_amdgpu_info_num_handles { 104444879b62SArindam Nath /** Max handles as supported by firmware for UVD */ 104544879b62SArindam Nath __u32 uvd_max_handles; 104644879b62SArindam Nath /** Handles currently in use for UVD */ 104744879b62SArindam Nath __u32 uvd_used_handles; 104844879b62SArindam Nath }; 104944879b62SArindam Nath 1050bbe87974SAlex Deucher #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1051bbe87974SAlex Deucher 1052bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry { 1053bbe87974SAlex Deucher /** System clock */ 1054bbe87974SAlex Deucher __u32 sclk; 1055bbe87974SAlex Deucher /** Memory clock */ 1056bbe87974SAlex Deucher __u32 mclk; 1057bbe87974SAlex Deucher /** VCE clock */ 1058bbe87974SAlex Deucher __u32 eclk; 1059bbe87974SAlex Deucher __u32 pad; 1060bbe87974SAlex Deucher }; 1061bbe87974SAlex Deucher 1062bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table { 1063bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1064bbe87974SAlex Deucher __u32 num_valid_entries; 1065bbe87974SAlex Deucher __u32 pad; 1066bbe87974SAlex Deucher }; 1067bbe87974SAlex Deucher 106881629cbaSAlex Deucher /* 106981629cbaSAlex Deucher * Supported GPU families 107081629cbaSAlex Deucher */ 107181629cbaSAlex Deucher #define AMDGPU_FAMILY_UNKNOWN 0 1072295d0dafSKen Wang #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 107381629cbaSAlex Deucher #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 107481629cbaSAlex Deucher #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 107581629cbaSAlex Deucher #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 107639bb0c92SSamuel Li #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1077a8f1f1ceSAlex Deucher #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 10782ca8a5d2SChunming Zhou #define AMDGPU_FAMILY_RV 142 /* Raven */ 1079107c34bcSHuang Rui #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 108081629cbaSAlex Deucher 1081cfa7152fSEmil Velikov #if defined(__cplusplus) 1082cfa7152fSEmil Velikov } 1083cfa7152fSEmil Velikov #endif 1084cfa7152fSEmil Velikov 108581629cbaSAlex Deucher #endif 1086