181629cbaSAlex Deucher /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 281629cbaSAlex Deucher * 381629cbaSAlex Deucher * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 481629cbaSAlex Deucher * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 581629cbaSAlex Deucher * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 681629cbaSAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 781629cbaSAlex Deucher * 881629cbaSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 981629cbaSAlex Deucher * copy of this software and associated documentation files (the "Software"), 1081629cbaSAlex Deucher * to deal in the Software without restriction, including without limitation 1181629cbaSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1281629cbaSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1381629cbaSAlex Deucher * Software is furnished to do so, subject to the following conditions: 1481629cbaSAlex Deucher * 1581629cbaSAlex Deucher * The above copyright notice and this permission notice shall be included in 1681629cbaSAlex Deucher * all copies or substantial portions of the Software. 1781629cbaSAlex Deucher * 1881629cbaSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1981629cbaSAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2081629cbaSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2181629cbaSAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2281629cbaSAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2381629cbaSAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2481629cbaSAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2581629cbaSAlex Deucher * 2681629cbaSAlex Deucher * Authors: 2781629cbaSAlex Deucher * Kevin E. Martin <martin@valinux.com> 2881629cbaSAlex Deucher * Gareth Hughes <gareth@valinux.com> 2981629cbaSAlex Deucher * Keith Whitwell <keith@tungstengraphics.com> 3081629cbaSAlex Deucher */ 3181629cbaSAlex Deucher 3281629cbaSAlex Deucher #ifndef __AMDGPU_DRM_H__ 3381629cbaSAlex Deucher #define __AMDGPU_DRM_H__ 3481629cbaSAlex Deucher 3581629cbaSAlex Deucher #include <drm/drm.h> 3681629cbaSAlex Deucher 3781629cbaSAlex Deucher #define DRM_AMDGPU_GEM_CREATE 0x00 3881629cbaSAlex Deucher #define DRM_AMDGPU_GEM_MMAP 0x01 3981629cbaSAlex Deucher #define DRM_AMDGPU_CTX 0x02 4081629cbaSAlex Deucher #define DRM_AMDGPU_BO_LIST 0x03 4181629cbaSAlex Deucher #define DRM_AMDGPU_CS 0x04 4281629cbaSAlex Deucher #define DRM_AMDGPU_INFO 0x05 4381629cbaSAlex Deucher #define DRM_AMDGPU_GEM_METADATA 0x06 4481629cbaSAlex Deucher #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 4581629cbaSAlex Deucher #define DRM_AMDGPU_GEM_VA 0x08 4681629cbaSAlex Deucher #define DRM_AMDGPU_WAIT_CS 0x09 4781629cbaSAlex Deucher #define DRM_AMDGPU_GEM_OP 0x10 4881629cbaSAlex Deucher #define DRM_AMDGPU_GEM_USERPTR 0x11 4981629cbaSAlex Deucher 5081629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 5181629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 5281629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 5381629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 5481629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 5581629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 5681629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 5781629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 5881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, union drm_amdgpu_gem_va) 5981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 6081629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 6181629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 6281629cbaSAlex Deucher 6381629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_CPU 0x1 6481629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GTT 0x2 6581629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_VRAM 0x4 6681629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GDS 0x8 6781629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GWS 0x10 6881629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_OA 0x20 6981629cbaSAlex Deucher 7081629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_MASK 0x3F 7181629cbaSAlex Deucher 7281629cbaSAlex Deucher /* Flag that CPU access will be required for the case of VRAM domain */ 7381629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 7481629cbaSAlex Deucher /* Flag that CPU access will not work, this VRAM domain is invisible */ 7581629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 7681629cbaSAlex Deucher /* Flag that USWC attributes should be used for GTT */ 7788671288SJammy Zhou #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 7881629cbaSAlex Deucher 7981629cbaSAlex Deucher /* Flag mask for GTT domain_flags */ 8081629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_CPU_GTT_MASK \ 8188671288SJammy Zhou (AMDGPU_GEM_CREATE_CPU_GTT_USWC | \ 8281629cbaSAlex Deucher AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | \ 8381629cbaSAlex Deucher AMDGPU_GEM_CREATE_NO_CPU_ACCESS) 8481629cbaSAlex Deucher 8581629cbaSAlex Deucher struct drm_amdgpu_gem_create_in { 8681629cbaSAlex Deucher /** the requested memory size */ 8781629cbaSAlex Deucher uint64_t bo_size; 8881629cbaSAlex Deucher /** physical start_addr alignment in bytes for some HW requirements */ 8981629cbaSAlex Deucher uint64_t alignment; 9081629cbaSAlex Deucher /** the requested memory domains */ 9181629cbaSAlex Deucher uint64_t domains; 9281629cbaSAlex Deucher /** allocation flags */ 9381629cbaSAlex Deucher uint64_t domain_flags; 9481629cbaSAlex Deucher }; 9581629cbaSAlex Deucher 9681629cbaSAlex Deucher struct drm_amdgpu_gem_create_out { 9781629cbaSAlex Deucher /** returned GEM object handle */ 9881629cbaSAlex Deucher uint32_t handle; 9981629cbaSAlex Deucher uint32_t _pad; 10081629cbaSAlex Deucher }; 10181629cbaSAlex Deucher 10281629cbaSAlex Deucher union drm_amdgpu_gem_create { 10381629cbaSAlex Deucher struct drm_amdgpu_gem_create_in in; 10481629cbaSAlex Deucher struct drm_amdgpu_gem_create_out out; 10581629cbaSAlex Deucher }; 10681629cbaSAlex Deucher 10781629cbaSAlex Deucher /** Opcode to create new residency list. */ 10881629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_CREATE 0 10981629cbaSAlex Deucher /** Opcode to destroy previously created residency list */ 11081629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_DESTROY 1 11181629cbaSAlex Deucher /** Opcode to update resource information in the list */ 11281629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_UPDATE 2 11381629cbaSAlex Deucher 11481629cbaSAlex Deucher struct drm_amdgpu_bo_list_in { 11581629cbaSAlex Deucher /** Type of operation */ 11681629cbaSAlex Deucher uint32_t operation; 11781629cbaSAlex Deucher /** Handle of list or 0 if we want to create one */ 11881629cbaSAlex Deucher uint32_t list_handle; 11981629cbaSAlex Deucher /** Number of BOs in list */ 12081629cbaSAlex Deucher uint32_t bo_number; 12181629cbaSAlex Deucher /** Size of each element describing BO */ 12281629cbaSAlex Deucher uint32_t bo_info_size; 12381629cbaSAlex Deucher /** Pointer to array describing BOs */ 12481629cbaSAlex Deucher uint64_t bo_info_ptr; 12581629cbaSAlex Deucher }; 12681629cbaSAlex Deucher 12781629cbaSAlex Deucher struct drm_amdgpu_bo_list_entry { 12881629cbaSAlex Deucher /** Handle of BO */ 12981629cbaSAlex Deucher uint32_t bo_handle; 13081629cbaSAlex Deucher /** New (if specified) BO priority to be used during migration */ 13181629cbaSAlex Deucher uint32_t bo_priority; 13281629cbaSAlex Deucher }; 13381629cbaSAlex Deucher 13481629cbaSAlex Deucher struct drm_amdgpu_bo_list_out { 13581629cbaSAlex Deucher /** Handle of resource list */ 13681629cbaSAlex Deucher uint32_t list_handle; 13781629cbaSAlex Deucher uint32_t _pad; 13881629cbaSAlex Deucher }; 13981629cbaSAlex Deucher 14081629cbaSAlex Deucher union drm_amdgpu_bo_list { 14181629cbaSAlex Deucher struct drm_amdgpu_bo_list_in in; 14281629cbaSAlex Deucher struct drm_amdgpu_bo_list_out out; 14381629cbaSAlex Deucher }; 14481629cbaSAlex Deucher 14581629cbaSAlex Deucher /* context related */ 14681629cbaSAlex Deucher #define AMDGPU_CTX_OP_ALLOC_CTX 1 14781629cbaSAlex Deucher #define AMDGPU_CTX_OP_FREE_CTX 2 14881629cbaSAlex Deucher #define AMDGPU_CTX_OP_QUERY_STATE 3 14981629cbaSAlex Deucher 15081629cbaSAlex Deucher #define AMDGPU_CTX_OP_STATE_RUNNING 1 15181629cbaSAlex Deucher 152d94aed5aSMarek Olšák /* GPU reset status */ 153d94aed5aSMarek Olšák #define AMDGPU_CTX_NO_RESET 0 154d94aed5aSMarek Olšák #define AMDGPU_CTX_GUILTY_RESET 1 /* this the context caused it */ 155d94aed5aSMarek Olšák #define AMDGPU_CTX_INNOCENT_RESET 2 /* some other context caused it */ 156d94aed5aSMarek Olšák #define AMDGPU_CTX_UNKNOWN_RESET 3 /* unknown cause */ 157d94aed5aSMarek Olšák 15881629cbaSAlex Deucher struct drm_amdgpu_ctx_in { 15981629cbaSAlex Deucher uint32_t op; 16081629cbaSAlex Deucher uint32_t flags; 16181629cbaSAlex Deucher uint32_t ctx_id; 16281629cbaSAlex Deucher uint32_t _pad; 16381629cbaSAlex Deucher }; 16481629cbaSAlex Deucher 16581629cbaSAlex Deucher union drm_amdgpu_ctx_out { 16681629cbaSAlex Deucher struct { 16781629cbaSAlex Deucher uint32_t ctx_id; 16881629cbaSAlex Deucher uint32_t _pad; 16981629cbaSAlex Deucher } alloc; 17081629cbaSAlex Deucher 17181629cbaSAlex Deucher struct { 17281629cbaSAlex Deucher uint64_t flags; 173d94aed5aSMarek Olšák /** Number of resets caused by this context so far. */ 174d94aed5aSMarek Olšák uint32_t hangs; 175d94aed5aSMarek Olšák /** Reset status since the last call of the ioctl. */ 176d94aed5aSMarek Olšák uint32_t reset_status; 17781629cbaSAlex Deucher } state; 17881629cbaSAlex Deucher }; 17981629cbaSAlex Deucher 18081629cbaSAlex Deucher union drm_amdgpu_ctx { 18181629cbaSAlex Deucher struct drm_amdgpu_ctx_in in; 18281629cbaSAlex Deucher union drm_amdgpu_ctx_out out; 18381629cbaSAlex Deucher }; 18481629cbaSAlex Deucher 18581629cbaSAlex Deucher /* 18681629cbaSAlex Deucher * This is not a reliable API and you should expect it to fail for any 18781629cbaSAlex Deucher * number of reasons and have fallback path that do not use userptr to 18881629cbaSAlex Deucher * perform any operation. 18981629cbaSAlex Deucher */ 19081629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 19181629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 19281629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 19381629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 19481629cbaSAlex Deucher 19581629cbaSAlex Deucher struct drm_amdgpu_gem_userptr { 19681629cbaSAlex Deucher uint64_t addr; 19781629cbaSAlex Deucher uint64_t size; 19881629cbaSAlex Deucher uint32_t flags; 19981629cbaSAlex Deucher uint32_t handle; 20081629cbaSAlex Deucher }; 20181629cbaSAlex Deucher 20281629cbaSAlex Deucher #define AMDGPU_TILING_MACRO 0x1 20381629cbaSAlex Deucher #define AMDGPU_TILING_MICRO 0x2 20481629cbaSAlex Deucher #define AMDGPU_TILING_SWAP_16BIT 0x4 20581629cbaSAlex Deucher #define AMDGPU_TILING_R600_NO_SCANOUT AMDGPU_TILING_SWAP_16BIT 20681629cbaSAlex Deucher #define AMDGPU_TILING_SWAP_32BIT 0x8 20781629cbaSAlex Deucher /* this object requires a surface when mapped - i.e. front buffer */ 20881629cbaSAlex Deucher #define AMDGPU_TILING_SURFACE 0x10 20981629cbaSAlex Deucher #define AMDGPU_TILING_MICRO_SQUARE 0x20 21081629cbaSAlex Deucher #define AMDGPU_TILING_EG_BANKW_SHIFT 8 21181629cbaSAlex Deucher #define AMDGPU_TILING_EG_BANKW_MASK 0xf 21281629cbaSAlex Deucher #define AMDGPU_TILING_EG_BANKH_SHIFT 12 21381629cbaSAlex Deucher #define AMDGPU_TILING_EG_BANKH_MASK 0xf 21481629cbaSAlex Deucher #define AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT 16 21581629cbaSAlex Deucher #define AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK 0xf 21681629cbaSAlex Deucher #define AMDGPU_TILING_EG_TILE_SPLIT_SHIFT 24 21781629cbaSAlex Deucher #define AMDGPU_TILING_EG_TILE_SPLIT_MASK 0xf 21881629cbaSAlex Deucher #define AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT 28 21981629cbaSAlex Deucher #define AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK 0xf 22081629cbaSAlex Deucher 22181629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 22281629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 22381629cbaSAlex Deucher 22481629cbaSAlex Deucher /** The same structure is shared for input/output */ 22581629cbaSAlex Deucher struct drm_amdgpu_gem_metadata { 22681629cbaSAlex Deucher uint32_t handle; /* GEM Object handle */ 22781629cbaSAlex Deucher uint32_t op; /** Do we want get or set metadata */ 22881629cbaSAlex Deucher struct { 22981629cbaSAlex Deucher uint64_t flags; 23081629cbaSAlex Deucher uint64_t tiling_info; /* family specific tiling info */ 23181629cbaSAlex Deucher uint32_t data_size_bytes; 23281629cbaSAlex Deucher uint32_t data[64]; 23381629cbaSAlex Deucher } data; 23481629cbaSAlex Deucher }; 23581629cbaSAlex Deucher 23681629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in { 23781629cbaSAlex Deucher uint32_t handle; /** the GEM object handle */ 23881629cbaSAlex Deucher uint32_t _pad; 23981629cbaSAlex Deucher }; 24081629cbaSAlex Deucher 24181629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out { 24281629cbaSAlex Deucher uint64_t addr_ptr; /** mmap offset from the vma offset manager */ 24381629cbaSAlex Deucher }; 24481629cbaSAlex Deucher 24581629cbaSAlex Deucher union drm_amdgpu_gem_mmap { 24681629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in in; 24781629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out out; 24881629cbaSAlex Deucher }; 24981629cbaSAlex Deucher 25081629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in { 25181629cbaSAlex Deucher uint32_t handle; /* GEM object handle */ 25281629cbaSAlex Deucher uint32_t flags; 25381629cbaSAlex Deucher uint64_t timeout; /* Timeout to wait. If 0 then returned immediately with the status */ 25481629cbaSAlex Deucher }; 25581629cbaSAlex Deucher 25681629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out { 25781629cbaSAlex Deucher uint32_t status; /* BO status: 0 - BO is idle, 1 - BO is busy */ 25881629cbaSAlex Deucher uint32_t domain; /* Returned current memory domain */ 25981629cbaSAlex Deucher }; 26081629cbaSAlex Deucher 26181629cbaSAlex Deucher union drm_amdgpu_gem_wait_idle { 26281629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in in; 26381629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out out; 26481629cbaSAlex Deucher }; 26581629cbaSAlex Deucher 26681629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in { 26781629cbaSAlex Deucher uint64_t handle; 26881629cbaSAlex Deucher uint64_t timeout; 26981629cbaSAlex Deucher uint32_t ip_type; 27081629cbaSAlex Deucher uint32_t ip_instance; 27181629cbaSAlex Deucher uint32_t ring; 27266b3cf2aSJammy Zhou uint32_t ctx_id; 27381629cbaSAlex Deucher }; 27481629cbaSAlex Deucher 27581629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out { 27681629cbaSAlex Deucher uint64_t status; 27781629cbaSAlex Deucher }; 27881629cbaSAlex Deucher 27981629cbaSAlex Deucher union drm_amdgpu_wait_cs { 28081629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in in; 28181629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out out; 28281629cbaSAlex Deucher }; 28381629cbaSAlex Deucher 28481629cbaSAlex Deucher /* Sets or returns a value associated with a buffer. */ 28581629cbaSAlex Deucher struct drm_amdgpu_gem_op { 28681629cbaSAlex Deucher uint32_t handle; /* buffer */ 28781629cbaSAlex Deucher uint32_t op; /* AMDGPU_GEM_OP_* */ 28881629cbaSAlex Deucher uint64_t value; /* input or return value */ 28981629cbaSAlex Deucher }; 29081629cbaSAlex Deucher 29181629cbaSAlex Deucher #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 29281629cbaSAlex Deucher #define AMDGPU_GEM_OP_SET_INITIAL_DOMAIN 1 29381629cbaSAlex Deucher 29481629cbaSAlex Deucher #define AMDGPU_VA_OP_MAP 1 29581629cbaSAlex Deucher #define AMDGPU_VA_OP_UNMAP 2 29681629cbaSAlex Deucher 29781629cbaSAlex Deucher #define AMDGPU_VA_RESULT_OK 0 29881629cbaSAlex Deucher #define AMDGPU_VA_RESULT_ERROR 1 29981629cbaSAlex Deucher #define AMDGPU_VA_RESULT_VA_INVALID_ALIGNMENT 2 30081629cbaSAlex Deucher 30181629cbaSAlex Deucher /* Mapping flags */ 30281629cbaSAlex Deucher /* readable mapping */ 30381629cbaSAlex Deucher #define AMDGPU_VM_PAGE_READABLE (1 << 1) 30481629cbaSAlex Deucher /* writable mapping */ 30581629cbaSAlex Deucher #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 30681629cbaSAlex Deucher /* executable mapping, new for VI */ 30781629cbaSAlex Deucher #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 30881629cbaSAlex Deucher 30981629cbaSAlex Deucher struct drm_amdgpu_gem_va_in { 31081629cbaSAlex Deucher /* GEM object handle */ 31181629cbaSAlex Deucher uint32_t handle; 31281629cbaSAlex Deucher uint32_t _pad; 31381629cbaSAlex Deucher /* map or unmap*/ 31481629cbaSAlex Deucher uint32_t operation; 31581629cbaSAlex Deucher /* specify mapping flags */ 31681629cbaSAlex Deucher uint32_t flags; 31781629cbaSAlex Deucher /* va address to assign . Must be correctly aligned.*/ 31881629cbaSAlex Deucher uint64_t va_address; 31981629cbaSAlex Deucher /* Specify offset inside of BO to assign. Must be correctly aligned.*/ 32081629cbaSAlex Deucher uint64_t offset_in_bo; 32181629cbaSAlex Deucher /* Specify mapping size. If 0 and offset is 0 then map the whole BO.*/ 32281629cbaSAlex Deucher /* Must be correctly aligned. */ 32381629cbaSAlex Deucher uint64_t map_size; 32481629cbaSAlex Deucher }; 32581629cbaSAlex Deucher 32681629cbaSAlex Deucher struct drm_amdgpu_gem_va_out { 32781629cbaSAlex Deucher uint32_t result; 32881629cbaSAlex Deucher uint32_t _pad; 32981629cbaSAlex Deucher }; 33081629cbaSAlex Deucher 33181629cbaSAlex Deucher union drm_amdgpu_gem_va { 33281629cbaSAlex Deucher struct drm_amdgpu_gem_va_in in; 33381629cbaSAlex Deucher struct drm_amdgpu_gem_va_out out; 33481629cbaSAlex Deucher }; 33581629cbaSAlex Deucher 33681629cbaSAlex Deucher #define AMDGPU_HW_IP_GFX 0 33781629cbaSAlex Deucher #define AMDGPU_HW_IP_COMPUTE 1 33881629cbaSAlex Deucher #define AMDGPU_HW_IP_DMA 2 33981629cbaSAlex Deucher #define AMDGPU_HW_IP_UVD 3 34081629cbaSAlex Deucher #define AMDGPU_HW_IP_VCE 4 34181629cbaSAlex Deucher #define AMDGPU_HW_IP_NUM 5 34281629cbaSAlex Deucher 34381629cbaSAlex Deucher #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 34481629cbaSAlex Deucher 34581629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_IB 0x01 34681629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_FENCE 0x02 34781629cbaSAlex Deucher struct drm_amdgpu_cs_chunk { 34881629cbaSAlex Deucher uint32_t chunk_id; 34981629cbaSAlex Deucher uint32_t length_dw; 35081629cbaSAlex Deucher uint64_t chunk_data; 35181629cbaSAlex Deucher }; 35281629cbaSAlex Deucher 35381629cbaSAlex Deucher struct drm_amdgpu_cs_in { 35481629cbaSAlex Deucher /** Rendering context id */ 35581629cbaSAlex Deucher uint32_t ctx_id; 35681629cbaSAlex Deucher /** Handle of resource list associated with CS */ 35781629cbaSAlex Deucher uint32_t bo_list_handle; 35881629cbaSAlex Deucher uint32_t num_chunks; 35981629cbaSAlex Deucher uint32_t _pad; 36081629cbaSAlex Deucher /* this points to uint64_t * which point to cs chunks */ 36181629cbaSAlex Deucher uint64_t chunks; 36281629cbaSAlex Deucher }; 36381629cbaSAlex Deucher 36481629cbaSAlex Deucher struct drm_amdgpu_cs_out { 36581629cbaSAlex Deucher uint64_t handle; 36681629cbaSAlex Deucher }; 36781629cbaSAlex Deucher 36881629cbaSAlex Deucher union drm_amdgpu_cs { 36981629cbaSAlex Deucher struct drm_amdgpu_cs_in in; 37081629cbaSAlex Deucher struct drm_amdgpu_cs_out out; 37181629cbaSAlex Deucher }; 37281629cbaSAlex Deucher 37381629cbaSAlex Deucher /* Specify flags to be used for IB */ 37481629cbaSAlex Deucher 37581629cbaSAlex Deucher /* This IB should be submitted to CE */ 37681629cbaSAlex Deucher #define AMDGPU_IB_FLAG_CE (1<<0) 37781629cbaSAlex Deucher 37881629cbaSAlex Deucher /* GDS is used by this IB */ 37981629cbaSAlex Deucher #define AMDGPU_IB_FLAG_GDS (1<<1) 38081629cbaSAlex Deucher 381aa2bdb24SJammy Zhou /* CE Preamble */ 382aa2bdb24SJammy Zhou #define AMDGPU_IB_FLAG_PREAMBLE (1<<2) 383aa2bdb24SJammy Zhou 38481629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib { 38581629cbaSAlex Deucher /** 38681629cbaSAlex Deucher * Handle of GEM object to be used as IB or 0 if it is already in 38781629cbaSAlex Deucher * residency list. 38881629cbaSAlex Deucher */ 38981629cbaSAlex Deucher uint32_t handle; 39081629cbaSAlex Deucher uint32_t flags; /* IB Flags */ 39181629cbaSAlex Deucher uint64_t va_start; /* Virtual address to begin IB execution */ 39281629cbaSAlex Deucher uint32_t ib_bytes; /* Size of submission */ 39381629cbaSAlex Deucher uint32_t ip_type; /* HW IP to submit to */ 39481629cbaSAlex Deucher uint32_t ip_instance; /* HW IP index of the same type to submit to */ 39581629cbaSAlex Deucher uint32_t ring; /* Ring index to submit to */ 39681629cbaSAlex Deucher }; 39781629cbaSAlex Deucher 39881629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence { 39981629cbaSAlex Deucher uint32_t handle; 40081629cbaSAlex Deucher uint32_t offset; 40181629cbaSAlex Deucher }; 40281629cbaSAlex Deucher 40381629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_data { 40481629cbaSAlex Deucher union { 40581629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib ib_data; 40681629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence fence_data; 40781629cbaSAlex Deucher }; 40881629cbaSAlex Deucher }; 40981629cbaSAlex Deucher 41081629cbaSAlex Deucher /** 41181629cbaSAlex Deucher * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 41281629cbaSAlex Deucher * 41381629cbaSAlex Deucher */ 41481629cbaSAlex Deucher #define AMDGPU_IDS_FLAGS_FUSION 0x1 41581629cbaSAlex Deucher 41681629cbaSAlex Deucher /* indicate if acceleration can be working */ 41781629cbaSAlex Deucher #define AMDGPU_INFO_ACCEL_WORKING 0x00 41881629cbaSAlex Deucher /* get the crtc_id from the mode object id? */ 41981629cbaSAlex Deucher #define AMDGPU_INFO_CRTC_FROM_ID 0x01 42081629cbaSAlex Deucher /* query hw IP info */ 42181629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_INFO 0x02 42281629cbaSAlex Deucher /* query hw IP instance count for the specified type */ 42381629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_COUNT 0x03 42481629cbaSAlex Deucher /* timestamp for GL_ARB_timer_query */ 42581629cbaSAlex Deucher #define AMDGPU_INFO_TIMESTAMP 0x05 42681629cbaSAlex Deucher /* Query the firmware version */ 42781629cbaSAlex Deucher #define AMDGPU_INFO_FW_VERSION 0x0e 42881629cbaSAlex Deucher /* Subquery id: Query VCE firmware version */ 42981629cbaSAlex Deucher #define AMDGPU_INFO_FW_VCE 0x1 43081629cbaSAlex Deucher /* Subquery id: Query UVD firmware version */ 43181629cbaSAlex Deucher #define AMDGPU_INFO_FW_UVD 0x2 43281629cbaSAlex Deucher /* Subquery id: Query GMC firmware version */ 43381629cbaSAlex Deucher #define AMDGPU_INFO_FW_GMC 0x03 43481629cbaSAlex Deucher /* Subquery id: Query GFX ME firmware version */ 43581629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_ME 0x04 43681629cbaSAlex Deucher /* Subquery id: Query GFX PFP firmware version */ 43781629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_PFP 0x05 43881629cbaSAlex Deucher /* Subquery id: Query GFX CE firmware version */ 43981629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_CE 0x06 44081629cbaSAlex Deucher /* Subquery id: Query GFX RLC firmware version */ 44181629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_RLC 0x07 44281629cbaSAlex Deucher /* Subquery id: Query GFX MEC firmware version */ 44381629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_MEC 0x08 44481629cbaSAlex Deucher /* Subquery id: Query SMC firmware version */ 44581629cbaSAlex Deucher #define AMDGPU_INFO_FW_SMC 0x0a 44681629cbaSAlex Deucher /* Subquery id: Query SDMA firmware version */ 44781629cbaSAlex Deucher #define AMDGPU_INFO_FW_SDMA 0x0b 44881629cbaSAlex Deucher /* number of bytes moved for TTM migration */ 44981629cbaSAlex Deucher #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 45081629cbaSAlex Deucher /* the used VRAM size */ 45181629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_USAGE 0x10 45281629cbaSAlex Deucher /* the used GTT size */ 45381629cbaSAlex Deucher #define AMDGPU_INFO_GTT_USAGE 0x11 45481629cbaSAlex Deucher /* Information about GDS, etc. resource configuration */ 45581629cbaSAlex Deucher #define AMDGPU_INFO_GDS_CONFIG 0x13 45681629cbaSAlex Deucher /* Query information about VRAM and GTT domains */ 45781629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_GTT 0x14 45881629cbaSAlex Deucher /* Query information about register in MMR address space*/ 45981629cbaSAlex Deucher #define AMDGPU_INFO_READ_MMR_REG 0x15 46081629cbaSAlex Deucher /* Query information about device: rev id, family, etc. */ 46181629cbaSAlex Deucher #define AMDGPU_INFO_DEV_INFO 0x16 46281629cbaSAlex Deucher /* visible vram usage */ 46381629cbaSAlex Deucher #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 46481629cbaSAlex Deucher 46581629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 46681629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 46781629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 46881629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 46981629cbaSAlex Deucher 47081629cbaSAlex Deucher /* Input structure for the INFO ioctl */ 47181629cbaSAlex Deucher struct drm_amdgpu_info { 47281629cbaSAlex Deucher /* Where the return value will be stored */ 47381629cbaSAlex Deucher uint64_t return_pointer; 47481629cbaSAlex Deucher /* The size of the return value. Just like "size" in "snprintf", 47581629cbaSAlex Deucher * it limits how many bytes the kernel can write. */ 47681629cbaSAlex Deucher uint32_t return_size; 47781629cbaSAlex Deucher /* The query request id. */ 47881629cbaSAlex Deucher uint32_t query; 47981629cbaSAlex Deucher 48081629cbaSAlex Deucher union { 48181629cbaSAlex Deucher struct { 48281629cbaSAlex Deucher uint32_t id; 48381629cbaSAlex Deucher uint32_t _pad; 48481629cbaSAlex Deucher } mode_crtc; 48581629cbaSAlex Deucher 48681629cbaSAlex Deucher struct { 48781629cbaSAlex Deucher /** AMDGPU_HW_IP_* */ 48881629cbaSAlex Deucher uint32_t type; 48981629cbaSAlex Deucher /** 49081629cbaSAlex Deucher * Index of the IP if there are more IPs of the same type. 49181629cbaSAlex Deucher * Ignored by AMDGPU_INFO_HW_IP_COUNT. 49281629cbaSAlex Deucher */ 49381629cbaSAlex Deucher uint32_t ip_instance; 49481629cbaSAlex Deucher } query_hw_ip; 49581629cbaSAlex Deucher 49681629cbaSAlex Deucher struct { 49781629cbaSAlex Deucher uint32_t dword_offset; 49881629cbaSAlex Deucher uint32_t count; /* number of registers to read */ 49981629cbaSAlex Deucher uint32_t instance; 50081629cbaSAlex Deucher uint32_t flags; 50181629cbaSAlex Deucher } read_mmr_reg; 50281629cbaSAlex Deucher 50381629cbaSAlex Deucher struct { 50481629cbaSAlex Deucher /** AMDGPU_INFO_FW_* */ 50581629cbaSAlex Deucher uint32_t fw_type; 50681629cbaSAlex Deucher /** Index of the IP if there are more IPs of the same type. */ 50781629cbaSAlex Deucher uint32_t ip_instance; 50881629cbaSAlex Deucher /** 50981629cbaSAlex Deucher * Index of the engine. Whether this is used depends 51081629cbaSAlex Deucher * on the firmware type. (e.g. MEC, SDMA) 51181629cbaSAlex Deucher */ 51281629cbaSAlex Deucher uint32_t index; 51381629cbaSAlex Deucher uint32_t _pad; 51481629cbaSAlex Deucher } query_fw; 51581629cbaSAlex Deucher }; 51681629cbaSAlex Deucher }; 51781629cbaSAlex Deucher 51881629cbaSAlex Deucher struct drm_amdgpu_info_gds { 51981629cbaSAlex Deucher /** GDS GFX partition size */ 52081629cbaSAlex Deucher uint32_t gds_gfx_partition_size; 52181629cbaSAlex Deucher /** GDS compute partition size */ 52281629cbaSAlex Deucher uint32_t compute_partition_size; 52381629cbaSAlex Deucher /** total GDS memory size */ 52481629cbaSAlex Deucher uint32_t gds_total_size; 52581629cbaSAlex Deucher /** GWS size per GFX partition */ 52681629cbaSAlex Deucher uint32_t gws_per_gfx_partition; 52781629cbaSAlex Deucher /** GSW size per compute partition */ 52881629cbaSAlex Deucher uint32_t gws_per_compute_partition; 52981629cbaSAlex Deucher /** OA size per GFX partition */ 53081629cbaSAlex Deucher uint32_t oa_per_gfx_partition; 53181629cbaSAlex Deucher /** OA size per compute partition */ 53281629cbaSAlex Deucher uint32_t oa_per_compute_partition; 53381629cbaSAlex Deucher uint32_t _pad; 53481629cbaSAlex Deucher }; 53581629cbaSAlex Deucher 53681629cbaSAlex Deucher struct drm_amdgpu_info_vram_gtt { 53781629cbaSAlex Deucher uint64_t vram_size; 53881629cbaSAlex Deucher uint64_t vram_cpu_accessible_size; 53981629cbaSAlex Deucher uint64_t gtt_size; 54081629cbaSAlex Deucher }; 54181629cbaSAlex Deucher 54281629cbaSAlex Deucher struct drm_amdgpu_info_firmware { 54381629cbaSAlex Deucher uint32_t ver; 54481629cbaSAlex Deucher uint32_t feature; 54581629cbaSAlex Deucher }; 54681629cbaSAlex Deucher 54781629cbaSAlex Deucher struct drm_amdgpu_info_device { 54881629cbaSAlex Deucher /** PCI Device ID */ 54981629cbaSAlex Deucher uint32_t device_id; 55081629cbaSAlex Deucher /** Internal chip revision: A0, A1, etc.) */ 55181629cbaSAlex Deucher uint32_t chip_rev; 55281629cbaSAlex Deucher uint32_t external_rev; 55381629cbaSAlex Deucher /** Revision id in PCI Config space */ 55481629cbaSAlex Deucher uint32_t pci_rev; 55581629cbaSAlex Deucher uint32_t family; 55681629cbaSAlex Deucher uint32_t num_shader_engines; 55781629cbaSAlex Deucher uint32_t num_shader_arrays_per_engine; 55881629cbaSAlex Deucher uint32_t gpu_counter_freq; /* in KHz */ 55981629cbaSAlex Deucher uint64_t max_engine_clock; /* in KHz */ 56081629cbaSAlex Deucher /* cu information */ 56181629cbaSAlex Deucher uint32_t cu_active_number; 56281629cbaSAlex Deucher uint32_t cu_ao_mask; 56381629cbaSAlex Deucher uint32_t cu_bitmap[4][4]; 56481629cbaSAlex Deucher /** Render backend pipe mask. One render backend is CB+DB. */ 56581629cbaSAlex Deucher uint32_t enabled_rb_pipes_mask; 56681629cbaSAlex Deucher uint32_t num_rb_pipes; 56781629cbaSAlex Deucher uint32_t num_hw_gfx_contexts; 56881629cbaSAlex Deucher uint32_t _pad; 56981629cbaSAlex Deucher uint64_t ids_flags; 57081629cbaSAlex Deucher /** Starting virtual address for UMDs. */ 57181629cbaSAlex Deucher uint64_t virtual_address_offset; 57202b70c8cSJammy Zhou /** The maximum virtual address */ 57302b70c8cSJammy Zhou uint64_t virtual_address_max; 57481629cbaSAlex Deucher /** Required alignment of virtual addresses. */ 57581629cbaSAlex Deucher uint32_t virtual_address_alignment; 57681629cbaSAlex Deucher /** Page table entry - fragment size */ 57781629cbaSAlex Deucher uint32_t pte_fragment_size; 57881629cbaSAlex Deucher uint32_t gart_page_size; 57981629cbaSAlex Deucher }; 58081629cbaSAlex Deucher 58181629cbaSAlex Deucher struct drm_amdgpu_info_hw_ip { 58281629cbaSAlex Deucher /** Version of h/w IP */ 58381629cbaSAlex Deucher uint32_t hw_ip_version_major; 58481629cbaSAlex Deucher uint32_t hw_ip_version_minor; 58581629cbaSAlex Deucher /** Capabilities */ 58681629cbaSAlex Deucher uint64_t capabilities_flags; 58781629cbaSAlex Deucher /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 58881629cbaSAlex Deucher uint32_t available_rings; 58981629cbaSAlex Deucher uint32_t _pad; 59081629cbaSAlex Deucher }; 59181629cbaSAlex Deucher 59281629cbaSAlex Deucher /* 59381629cbaSAlex Deucher * Supported GPU families 59481629cbaSAlex Deucher */ 59581629cbaSAlex Deucher #define AMDGPU_FAMILY_UNKNOWN 0 59681629cbaSAlex Deucher #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 59781629cbaSAlex Deucher #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 59881629cbaSAlex Deucher #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 59981629cbaSAlex Deucher #define AMDGPU_FAMILY_CZ 135 /* Carrizo */ 60081629cbaSAlex Deucher 60181629cbaSAlex Deucher #endif 602