181629cbaSAlex Deucher /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 281629cbaSAlex Deucher * 381629cbaSAlex Deucher * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 481629cbaSAlex Deucher * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 581629cbaSAlex Deucher * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 681629cbaSAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 781629cbaSAlex Deucher * 881629cbaSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 981629cbaSAlex Deucher * copy of this software and associated documentation files (the "Software"), 1081629cbaSAlex Deucher * to deal in the Software without restriction, including without limitation 1181629cbaSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1281629cbaSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1381629cbaSAlex Deucher * Software is furnished to do so, subject to the following conditions: 1481629cbaSAlex Deucher * 1581629cbaSAlex Deucher * The above copyright notice and this permission notice shall be included in 1681629cbaSAlex Deucher * all copies or substantial portions of the Software. 1781629cbaSAlex Deucher * 1881629cbaSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1981629cbaSAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2081629cbaSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2181629cbaSAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2281629cbaSAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2381629cbaSAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2481629cbaSAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2581629cbaSAlex Deucher * 2681629cbaSAlex Deucher * Authors: 2781629cbaSAlex Deucher * Kevin E. Martin <martin@valinux.com> 2881629cbaSAlex Deucher * Gareth Hughes <gareth@valinux.com> 2981629cbaSAlex Deucher * Keith Whitwell <keith@tungstengraphics.com> 3081629cbaSAlex Deucher */ 3181629cbaSAlex Deucher 3281629cbaSAlex Deucher #ifndef __AMDGPU_DRM_H__ 3381629cbaSAlex Deucher #define __AMDGPU_DRM_H__ 3481629cbaSAlex Deucher 35b3fcf36aSMichel Dänzer #include "drm.h" 3681629cbaSAlex Deucher 37cfa7152fSEmil Velikov #if defined(__cplusplus) 38cfa7152fSEmil Velikov extern "C" { 39cfa7152fSEmil Velikov #endif 40cfa7152fSEmil Velikov 4181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_CREATE 0x00 4281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_MMAP 0x01 4381629cbaSAlex Deucher #define DRM_AMDGPU_CTX 0x02 4481629cbaSAlex Deucher #define DRM_AMDGPU_BO_LIST 0x03 4581629cbaSAlex Deucher #define DRM_AMDGPU_CS 0x04 4681629cbaSAlex Deucher #define DRM_AMDGPU_INFO 0x05 4781629cbaSAlex Deucher #define DRM_AMDGPU_GEM_METADATA 0x06 4881629cbaSAlex Deucher #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 4981629cbaSAlex Deucher #define DRM_AMDGPU_GEM_VA 0x08 5081629cbaSAlex Deucher #define DRM_AMDGPU_WAIT_CS 0x09 5181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_OP 0x10 5281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_USERPTR 0x11 53eef18a82SJunwei Zhang #define DRM_AMDGPU_WAIT_FENCES 0x12 54cfbcacf4SChunming Zhou #define DRM_AMDGPU_VM 0x13 557ca24cf2SMarek Olšák #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 5652c6a62cSAndres Rodriguez #define DRM_AMDGPU_SCHED 0x15 5781629cbaSAlex Deucher 5881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 5981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 6081629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 6181629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 6281629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 6381629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 6481629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 6581629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 6634b5f6a6SChristian König #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 6781629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 6881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 6981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70eef18a82SJunwei Zhang #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71cfbcacf4SChunming Zhou #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 727ca24cf2SMarek Olšák #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 7352c6a62cSAndres Rodriguez #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 7481629cbaSAlex Deucher 75b646c1dcSSamuel Li /** 76b646c1dcSSamuel Li * DOC: memory domains 77b646c1dcSSamuel Li * 78b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79b646c1dcSSamuel Li * Memory in this pool could be swapped out to disk if there is pressure. 80b646c1dcSSamuel Li * 81b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82b646c1dcSSamuel Li * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83b646c1dcSSamuel Li * pages of system memory, allows GPU access system memory in a linezrized 84b646c1dcSSamuel Li * fashion. 85b646c1dcSSamuel Li * 86b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87b646c1dcSSamuel Li * carved out by the BIOS. 88b646c1dcSSamuel Li * 89b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90b646c1dcSSamuel Li * across shader threads. 91b646c1dcSSamuel Li * 92b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93b646c1dcSSamuel Li * execution of all the waves on a device. 94b646c1dcSSamuel Li * 95b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96b646c1dcSSamuel Li * for appending data. 97b646c1dcSSamuel Li */ 9881629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_CPU 0x1 9981629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GTT 0x2 10081629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_VRAM 0x4 10181629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GDS 0x8 10281629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GWS 0x10 10381629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_OA 0x20 1043f188453SChunming Zhou #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 1053f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GTT | \ 1063f188453SChunming Zhou AMDGPU_GEM_DOMAIN_VRAM | \ 1073f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GDS | \ 1083f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GWS | \ 1093f188453SChunming Zhou AMDGPU_GEM_DOMAIN_OA) 11081629cbaSAlex Deucher 11181629cbaSAlex Deucher /* Flag that CPU access will be required for the case of VRAM domain */ 11281629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 11381629cbaSAlex Deucher /* Flag that CPU access will not work, this VRAM domain is invisible */ 11481629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 11581629cbaSAlex Deucher /* Flag that USWC attributes should be used for GTT */ 11688671288SJammy Zhou #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 1174fea83ffSFlora Cui /* Flag that the memory should be in VRAM and cleared */ 1184fea83ffSFlora Cui #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119e7893c4bSChunming Zhou /* Flag that create shadow bo(GTT) while allocating vram bo */ 120e7893c4bSChunming Zhou #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 12103f48dd5SChristian König /* Flag that allocating the BO should use linear VRAM */ 12203f48dd5SChristian König #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 123e1eb899bSChristian König /* Flag that BO is always valid in this VM */ 124e1eb899bSChristian König #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 125177ae09bSAndres Rodriguez /* Flag that BO sharing will be explicitly synchronized */ 126177ae09bSAndres Rodriguez #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 127959a2091SYong Zhao /* Flag that indicates allocating MQD gart on GFX9, where the mtype 128959a2091SYong Zhao * for the second page onward should be set to NC. 129959a2091SYong Zhao */ 130959a2091SYong Zhao #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) 13181629cbaSAlex Deucher 13281629cbaSAlex Deucher struct drm_amdgpu_gem_create_in { 13381629cbaSAlex Deucher /** the requested memory size */ 1342ce9dde0SMikko Rapeli __u64 bo_size; 13581629cbaSAlex Deucher /** physical start_addr alignment in bytes for some HW requirements */ 1362ce9dde0SMikko Rapeli __u64 alignment; 13781629cbaSAlex Deucher /** the requested memory domains */ 1382ce9dde0SMikko Rapeli __u64 domains; 13981629cbaSAlex Deucher /** allocation flags */ 1402ce9dde0SMikko Rapeli __u64 domain_flags; 14181629cbaSAlex Deucher }; 14281629cbaSAlex Deucher 14381629cbaSAlex Deucher struct drm_amdgpu_gem_create_out { 14481629cbaSAlex Deucher /** returned GEM object handle */ 1452ce9dde0SMikko Rapeli __u32 handle; 1462ce9dde0SMikko Rapeli __u32 _pad; 14781629cbaSAlex Deucher }; 14881629cbaSAlex Deucher 14981629cbaSAlex Deucher union drm_amdgpu_gem_create { 15081629cbaSAlex Deucher struct drm_amdgpu_gem_create_in in; 15181629cbaSAlex Deucher struct drm_amdgpu_gem_create_out out; 15281629cbaSAlex Deucher }; 15381629cbaSAlex Deucher 15481629cbaSAlex Deucher /** Opcode to create new residency list. */ 15581629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_CREATE 0 15681629cbaSAlex Deucher /** Opcode to destroy previously created residency list */ 15781629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_DESTROY 1 15881629cbaSAlex Deucher /** Opcode to update resource information in the list */ 15981629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_UPDATE 2 16081629cbaSAlex Deucher 16181629cbaSAlex Deucher struct drm_amdgpu_bo_list_in { 16281629cbaSAlex Deucher /** Type of operation */ 1632ce9dde0SMikko Rapeli __u32 operation; 16481629cbaSAlex Deucher /** Handle of list or 0 if we want to create one */ 1652ce9dde0SMikko Rapeli __u32 list_handle; 16681629cbaSAlex Deucher /** Number of BOs in list */ 1672ce9dde0SMikko Rapeli __u32 bo_number; 16881629cbaSAlex Deucher /** Size of each element describing BO */ 1692ce9dde0SMikko Rapeli __u32 bo_info_size; 17081629cbaSAlex Deucher /** Pointer to array describing BOs */ 1712ce9dde0SMikko Rapeli __u64 bo_info_ptr; 17281629cbaSAlex Deucher }; 17381629cbaSAlex Deucher 17481629cbaSAlex Deucher struct drm_amdgpu_bo_list_entry { 17581629cbaSAlex Deucher /** Handle of BO */ 1762ce9dde0SMikko Rapeli __u32 bo_handle; 17781629cbaSAlex Deucher /** New (if specified) BO priority to be used during migration */ 1782ce9dde0SMikko Rapeli __u32 bo_priority; 17981629cbaSAlex Deucher }; 18081629cbaSAlex Deucher 18181629cbaSAlex Deucher struct drm_amdgpu_bo_list_out { 18281629cbaSAlex Deucher /** Handle of resource list */ 1832ce9dde0SMikko Rapeli __u32 list_handle; 1842ce9dde0SMikko Rapeli __u32 _pad; 18581629cbaSAlex Deucher }; 18681629cbaSAlex Deucher 18781629cbaSAlex Deucher union drm_amdgpu_bo_list { 18881629cbaSAlex Deucher struct drm_amdgpu_bo_list_in in; 18981629cbaSAlex Deucher struct drm_amdgpu_bo_list_out out; 19081629cbaSAlex Deucher }; 19181629cbaSAlex Deucher 19281629cbaSAlex Deucher /* context related */ 19381629cbaSAlex Deucher #define AMDGPU_CTX_OP_ALLOC_CTX 1 19481629cbaSAlex Deucher #define AMDGPU_CTX_OP_FREE_CTX 2 19581629cbaSAlex Deucher #define AMDGPU_CTX_OP_QUERY_STATE 3 196bc1b1bf6SMonk Liu #define AMDGPU_CTX_OP_QUERY_STATE2 4 19781629cbaSAlex Deucher 198d94aed5aSMarek Olšák /* GPU reset status */ 199d94aed5aSMarek Olšák #define AMDGPU_CTX_NO_RESET 0 200675da0ddSChristian König /* this the context caused it */ 201675da0ddSChristian König #define AMDGPU_CTX_GUILTY_RESET 1 202675da0ddSChristian König /* some other context caused it */ 203675da0ddSChristian König #define AMDGPU_CTX_INNOCENT_RESET 2 204675da0ddSChristian König /* unknown cause */ 205675da0ddSChristian König #define AMDGPU_CTX_UNKNOWN_RESET 3 206d94aed5aSMarek Olšák 207bc1b1bf6SMonk Liu /* indicate gpu reset occured after ctx created */ 208bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 209bc1b1bf6SMonk Liu /* indicate vram lost occured after ctx created */ 210bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 211bc1b1bf6SMonk Liu /* indicate some job from this context once cause gpu hang */ 212bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 213ae363a21Sxinhui pan /* indicate some errors are detected by RAS */ 214ae363a21Sxinhui pan #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 215ae363a21Sxinhui pan #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 216bc1b1bf6SMonk Liu 217c2636dc5SAndres Rodriguez /* Context priority level */ 218f3d19bf8SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_UNSET -2048 2198bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 2208bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_LOW -512 221c2636dc5SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_NORMAL 0 222c2636dc5SAndres Rodriguez /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */ 2238bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_HIGH 512 2248bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 225c2636dc5SAndres Rodriguez 22681629cbaSAlex Deucher struct drm_amdgpu_ctx_in { 227675da0ddSChristian König /** AMDGPU_CTX_OP_* */ 2282ce9dde0SMikko Rapeli __u32 op; 229675da0ddSChristian König /** For future use, no flags defined so far */ 2302ce9dde0SMikko Rapeli __u32 flags; 2312ce9dde0SMikko Rapeli __u32 ctx_id; 232c2636dc5SAndres Rodriguez __s32 priority; 23381629cbaSAlex Deucher }; 23481629cbaSAlex Deucher 23581629cbaSAlex Deucher union drm_amdgpu_ctx_out { 23681629cbaSAlex Deucher struct { 2372ce9dde0SMikko Rapeli __u32 ctx_id; 2382ce9dde0SMikko Rapeli __u32 _pad; 23981629cbaSAlex Deucher } alloc; 24081629cbaSAlex Deucher 24181629cbaSAlex Deucher struct { 242675da0ddSChristian König /** For future use, no flags defined so far */ 2432ce9dde0SMikko Rapeli __u64 flags; 244d94aed5aSMarek Olšák /** Number of resets caused by this context so far. */ 2452ce9dde0SMikko Rapeli __u32 hangs; 246d94aed5aSMarek Olšák /** Reset status since the last call of the ioctl. */ 2472ce9dde0SMikko Rapeli __u32 reset_status; 24881629cbaSAlex Deucher } state; 24981629cbaSAlex Deucher }; 25081629cbaSAlex Deucher 25181629cbaSAlex Deucher union drm_amdgpu_ctx { 25281629cbaSAlex Deucher struct drm_amdgpu_ctx_in in; 25381629cbaSAlex Deucher union drm_amdgpu_ctx_out out; 25481629cbaSAlex Deucher }; 25581629cbaSAlex Deucher 256cfbcacf4SChunming Zhou /* vm ioctl */ 257cfbcacf4SChunming Zhou #define AMDGPU_VM_OP_RESERVE_VMID 1 258cfbcacf4SChunming Zhou #define AMDGPU_VM_OP_UNRESERVE_VMID 2 259cfbcacf4SChunming Zhou 260cfbcacf4SChunming Zhou struct drm_amdgpu_vm_in { 261cfbcacf4SChunming Zhou /** AMDGPU_VM_OP_* */ 262cfbcacf4SChunming Zhou __u32 op; 263cfbcacf4SChunming Zhou __u32 flags; 264cfbcacf4SChunming Zhou }; 265cfbcacf4SChunming Zhou 266cfbcacf4SChunming Zhou struct drm_amdgpu_vm_out { 267cfbcacf4SChunming Zhou /** For future use, no flags defined so far */ 268cfbcacf4SChunming Zhou __u64 flags; 269cfbcacf4SChunming Zhou }; 270cfbcacf4SChunming Zhou 271cfbcacf4SChunming Zhou union drm_amdgpu_vm { 272cfbcacf4SChunming Zhou struct drm_amdgpu_vm_in in; 273cfbcacf4SChunming Zhou struct drm_amdgpu_vm_out out; 274cfbcacf4SChunming Zhou }; 275cfbcacf4SChunming Zhou 27652c6a62cSAndres Rodriguez /* sched ioctl */ 27752c6a62cSAndres Rodriguez #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 278b5bb37edSBas Nieuwenhuizen #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 27952c6a62cSAndres Rodriguez 28052c6a62cSAndres Rodriguez struct drm_amdgpu_sched_in { 28152c6a62cSAndres Rodriguez /* AMDGPU_SCHED_OP_* */ 28252c6a62cSAndres Rodriguez __u32 op; 28352c6a62cSAndres Rodriguez __u32 fd; 28452c6a62cSAndres Rodriguez __s32 priority; 285b5bb37edSBas Nieuwenhuizen __u32 ctx_id; 28652c6a62cSAndres Rodriguez }; 28752c6a62cSAndres Rodriguez 28852c6a62cSAndres Rodriguez union drm_amdgpu_sched { 28952c6a62cSAndres Rodriguez struct drm_amdgpu_sched_in in; 29052c6a62cSAndres Rodriguez }; 29152c6a62cSAndres Rodriguez 29281629cbaSAlex Deucher /* 29381629cbaSAlex Deucher * This is not a reliable API and you should expect it to fail for any 29481629cbaSAlex Deucher * number of reasons and have fallback path that do not use userptr to 29581629cbaSAlex Deucher * perform any operation. 29681629cbaSAlex Deucher */ 29781629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 29881629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 29981629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 30081629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 30181629cbaSAlex Deucher 30281629cbaSAlex Deucher struct drm_amdgpu_gem_userptr { 3032ce9dde0SMikko Rapeli __u64 addr; 3042ce9dde0SMikko Rapeli __u64 size; 305675da0ddSChristian König /* AMDGPU_GEM_USERPTR_* */ 3062ce9dde0SMikko Rapeli __u32 flags; 307675da0ddSChristian König /* Resulting GEM handle */ 3082ce9dde0SMikko Rapeli __u32 handle; 30981629cbaSAlex Deucher }; 31081629cbaSAlex Deucher 31100ac6f6bSAlex Deucher /* SI-CI-VI: */ 312fbd76d59SMarek Olšák /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 313fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 314fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 315fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 316fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 317fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 318fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 319fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 320fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 321fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 322fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 323fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 324fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 325fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 326fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 327fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 328fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 329fbd76d59SMarek Olšák 33000ac6f6bSAlex Deucher /* GFX9 and later: */ 33100ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 33200ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 333ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 334ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 335ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 336ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 337ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 338ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 33900ac6f6bSAlex Deucher 34000ac6f6bSAlex Deucher /* Set/Get helpers for tiling flags. */ 341fbd76d59SMarek Olšák #define AMDGPU_TILING_SET(field, value) \ 34200ac6f6bSAlex Deucher (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 343fbd76d59SMarek Olšák #define AMDGPU_TILING_GET(value, field) \ 34400ac6f6bSAlex Deucher (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 34581629cbaSAlex Deucher 34681629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 34781629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 34881629cbaSAlex Deucher 34981629cbaSAlex Deucher /** The same structure is shared for input/output */ 35081629cbaSAlex Deucher struct drm_amdgpu_gem_metadata { 351675da0ddSChristian König /** GEM Object handle */ 3522ce9dde0SMikko Rapeli __u32 handle; 353675da0ddSChristian König /** Do we want get or set metadata */ 3542ce9dde0SMikko Rapeli __u32 op; 35581629cbaSAlex Deucher struct { 356675da0ddSChristian König /** For future use, no flags defined so far */ 3572ce9dde0SMikko Rapeli __u64 flags; 358675da0ddSChristian König /** family specific tiling info */ 3592ce9dde0SMikko Rapeli __u64 tiling_info; 3602ce9dde0SMikko Rapeli __u32 data_size_bytes; 3612ce9dde0SMikko Rapeli __u32 data[64]; 36281629cbaSAlex Deucher } data; 36381629cbaSAlex Deucher }; 36481629cbaSAlex Deucher 36581629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in { 366675da0ddSChristian König /** the GEM object handle */ 3672ce9dde0SMikko Rapeli __u32 handle; 3682ce9dde0SMikko Rapeli __u32 _pad; 36981629cbaSAlex Deucher }; 37081629cbaSAlex Deucher 37181629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out { 372675da0ddSChristian König /** mmap offset from the vma offset manager */ 3732ce9dde0SMikko Rapeli __u64 addr_ptr; 37481629cbaSAlex Deucher }; 37581629cbaSAlex Deucher 37681629cbaSAlex Deucher union drm_amdgpu_gem_mmap { 37781629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in in; 37881629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out out; 37981629cbaSAlex Deucher }; 38081629cbaSAlex Deucher 38181629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in { 382675da0ddSChristian König /** GEM object handle */ 3832ce9dde0SMikko Rapeli __u32 handle; 384675da0ddSChristian König /** For future use, no flags defined so far */ 3852ce9dde0SMikko Rapeli __u32 flags; 386675da0ddSChristian König /** Absolute timeout to wait */ 3872ce9dde0SMikko Rapeli __u64 timeout; 38881629cbaSAlex Deucher }; 38981629cbaSAlex Deucher 39081629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out { 391675da0ddSChristian König /** BO status: 0 - BO is idle, 1 - BO is busy */ 3922ce9dde0SMikko Rapeli __u32 status; 393675da0ddSChristian König /** Returned current memory domain */ 3942ce9dde0SMikko Rapeli __u32 domain; 39581629cbaSAlex Deucher }; 39681629cbaSAlex Deucher 39781629cbaSAlex Deucher union drm_amdgpu_gem_wait_idle { 39881629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in in; 39981629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out out; 40081629cbaSAlex Deucher }; 40181629cbaSAlex Deucher 40281629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in { 403d7b1eeb2SMonk Liu /* Command submission handle 404d7b1eeb2SMonk Liu * handle equals 0 means none to wait for 405080b24ebSAlex Deucher * handle equals ~0ull means wait for the latest sequence number 406d7b1eeb2SMonk Liu */ 4072ce9dde0SMikko Rapeli __u64 handle; 408675da0ddSChristian König /** Absolute timeout to wait */ 4092ce9dde0SMikko Rapeli __u64 timeout; 4102ce9dde0SMikko Rapeli __u32 ip_type; 4112ce9dde0SMikko Rapeli __u32 ip_instance; 4122ce9dde0SMikko Rapeli __u32 ring; 4132ce9dde0SMikko Rapeli __u32 ctx_id; 41481629cbaSAlex Deucher }; 41581629cbaSAlex Deucher 41681629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out { 417675da0ddSChristian König /** CS status: 0 - CS completed, 1 - CS still busy */ 4182ce9dde0SMikko Rapeli __u64 status; 41981629cbaSAlex Deucher }; 42081629cbaSAlex Deucher 42181629cbaSAlex Deucher union drm_amdgpu_wait_cs { 42281629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in in; 42381629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out out; 42481629cbaSAlex Deucher }; 42581629cbaSAlex Deucher 426eef18a82SJunwei Zhang struct drm_amdgpu_fence { 427eef18a82SJunwei Zhang __u32 ctx_id; 428eef18a82SJunwei Zhang __u32 ip_type; 429eef18a82SJunwei Zhang __u32 ip_instance; 430eef18a82SJunwei Zhang __u32 ring; 431eef18a82SJunwei Zhang __u64 seq_no; 432eef18a82SJunwei Zhang }; 433eef18a82SJunwei Zhang 434eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in { 435eef18a82SJunwei Zhang /** This points to uint64_t * which points to fences */ 436eef18a82SJunwei Zhang __u64 fences; 437eef18a82SJunwei Zhang __u32 fence_count; 438eef18a82SJunwei Zhang __u32 wait_all; 439eef18a82SJunwei Zhang __u64 timeout_ns; 440eef18a82SJunwei Zhang }; 441eef18a82SJunwei Zhang 442eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out { 443eef18a82SJunwei Zhang __u32 status; 444eef18a82SJunwei Zhang __u32 first_signaled; 445eef18a82SJunwei Zhang }; 446eef18a82SJunwei Zhang 447eef18a82SJunwei Zhang union drm_amdgpu_wait_fences { 448eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in in; 449eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out out; 450eef18a82SJunwei Zhang }; 451eef18a82SJunwei Zhang 45281629cbaSAlex Deucher #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 453d8f65a23SMarek Olšák #define AMDGPU_GEM_OP_SET_PLACEMENT 1 45481629cbaSAlex Deucher 455675da0ddSChristian König /* Sets or returns a value associated with a buffer. */ 456675da0ddSChristian König struct drm_amdgpu_gem_op { 457675da0ddSChristian König /** GEM object handle */ 4582ce9dde0SMikko Rapeli __u32 handle; 459675da0ddSChristian König /** AMDGPU_GEM_OP_* */ 4602ce9dde0SMikko Rapeli __u32 op; 461675da0ddSChristian König /** Input or return value */ 4622ce9dde0SMikko Rapeli __u64 value; 463675da0ddSChristian König }; 464675da0ddSChristian König 46581629cbaSAlex Deucher #define AMDGPU_VA_OP_MAP 1 46681629cbaSAlex Deucher #define AMDGPU_VA_OP_UNMAP 2 467dc54d3d1SChristian König #define AMDGPU_VA_OP_CLEAR 3 46880f95c57SChristian König #define AMDGPU_VA_OP_REPLACE 4 46981629cbaSAlex Deucher 470fc220f65SChristian König /* Delay the page table update till the next CS */ 471fc220f65SChristian König #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 472fc220f65SChristian König 47381629cbaSAlex Deucher /* Mapping flags */ 47481629cbaSAlex Deucher /* readable mapping */ 47581629cbaSAlex Deucher #define AMDGPU_VM_PAGE_READABLE (1 << 1) 47681629cbaSAlex Deucher /* writable mapping */ 47781629cbaSAlex Deucher #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 47881629cbaSAlex Deucher /* executable mapping, new for VI */ 47981629cbaSAlex Deucher #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 480b85891bdSJunwei Zhang /* partially resident texture */ 481b85891bdSJunwei Zhang #define AMDGPU_VM_PAGE_PRT (1 << 4) 48266e02bc3SAlex Xie /* MTYPE flags use bit 5 to 8 */ 48366e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 48466e02bc3SAlex Xie /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 48566e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 48666e02bc3SAlex Xie /* Use NC MTYPE instead of default MTYPE */ 48766e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_NC (1 << 5) 48866e02bc3SAlex Xie /* Use WC MTYPE instead of default MTYPE */ 48966e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_WC (2 << 5) 49066e02bc3SAlex Xie /* Use CC MTYPE instead of default MTYPE */ 49166e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_CC (3 << 5) 49266e02bc3SAlex Xie /* Use UC MTYPE instead of default MTYPE */ 49366e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_UC (4 << 5) 49481629cbaSAlex Deucher 49534b5f6a6SChristian König struct drm_amdgpu_gem_va { 496675da0ddSChristian König /** GEM object handle */ 4972ce9dde0SMikko Rapeli __u32 handle; 4982ce9dde0SMikko Rapeli __u32 _pad; 499675da0ddSChristian König /** AMDGPU_VA_OP_* */ 5002ce9dde0SMikko Rapeli __u32 operation; 501675da0ddSChristian König /** AMDGPU_VM_PAGE_* */ 5022ce9dde0SMikko Rapeli __u32 flags; 503675da0ddSChristian König /** va address to assign . Must be correctly aligned.*/ 5042ce9dde0SMikko Rapeli __u64 va_address; 505675da0ddSChristian König /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 5062ce9dde0SMikko Rapeli __u64 offset_in_bo; 507675da0ddSChristian König /** Specify mapping size. Must be correctly aligned. */ 5082ce9dde0SMikko Rapeli __u64 map_size; 50981629cbaSAlex Deucher }; 51081629cbaSAlex Deucher 51181629cbaSAlex Deucher #define AMDGPU_HW_IP_GFX 0 51281629cbaSAlex Deucher #define AMDGPU_HW_IP_COMPUTE 1 51381629cbaSAlex Deucher #define AMDGPU_HW_IP_DMA 2 51481629cbaSAlex Deucher #define AMDGPU_HW_IP_UVD 3 51581629cbaSAlex Deucher #define AMDGPU_HW_IP_VCE 4 516a50798b6SLeo Liu #define AMDGPU_HW_IP_UVD_ENC 5 51766e236f1SLeo Liu #define AMDGPU_HW_IP_VCN_DEC 6 518fcfc5a90SLeo Liu #define AMDGPU_HW_IP_VCN_ENC 7 51981d35014SBoyuan Zhang #define AMDGPU_HW_IP_VCN_JPEG 8 52081d35014SBoyuan Zhang #define AMDGPU_HW_IP_NUM 9 52181629cbaSAlex Deucher 52281629cbaSAlex Deucher #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 52381629cbaSAlex Deucher 52481629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_IB 0x01 52581629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_FENCE 0x02 5262b48d323SChristian König #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 527660e8558SDave Airlie #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 528660e8558SDave Airlie #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 529964d0fbfSAndrey Grodzovsky #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 53067dd1a36SAndrey Grodzovsky #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 5312624dd15SChunming Zhou #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 5322624dd15SChunming Zhou #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 533675da0ddSChristian König 53481629cbaSAlex Deucher struct drm_amdgpu_cs_chunk { 5352ce9dde0SMikko Rapeli __u32 chunk_id; 5362ce9dde0SMikko Rapeli __u32 length_dw; 5372ce9dde0SMikko Rapeli __u64 chunk_data; 53881629cbaSAlex Deucher }; 53981629cbaSAlex Deucher 54081629cbaSAlex Deucher struct drm_amdgpu_cs_in { 54181629cbaSAlex Deucher /** Rendering context id */ 5422ce9dde0SMikko Rapeli __u32 ctx_id; 54381629cbaSAlex Deucher /** Handle of resource list associated with CS */ 5442ce9dde0SMikko Rapeli __u32 bo_list_handle; 5452ce9dde0SMikko Rapeli __u32 num_chunks; 5462ce9dde0SMikko Rapeli __u32 _pad; 5472ce9dde0SMikko Rapeli /** this points to __u64 * which point to cs chunks */ 5482ce9dde0SMikko Rapeli __u64 chunks; 54981629cbaSAlex Deucher }; 55081629cbaSAlex Deucher 55181629cbaSAlex Deucher struct drm_amdgpu_cs_out { 5522ce9dde0SMikko Rapeli __u64 handle; 55381629cbaSAlex Deucher }; 55481629cbaSAlex Deucher 55581629cbaSAlex Deucher union drm_amdgpu_cs { 55681629cbaSAlex Deucher struct drm_amdgpu_cs_in in; 55781629cbaSAlex Deucher struct drm_amdgpu_cs_out out; 55881629cbaSAlex Deucher }; 55981629cbaSAlex Deucher 56081629cbaSAlex Deucher /* Specify flags to be used for IB */ 56181629cbaSAlex Deucher 56281629cbaSAlex Deucher /* This IB should be submitted to CE */ 56381629cbaSAlex Deucher #define AMDGPU_IB_FLAG_CE (1<<0) 56481629cbaSAlex Deucher 565ed834af2SMonk Liu /* Preamble flag, which means the IB could be dropped if no context switch */ 566cab6d57cSJammy Zhou #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 567aa2bdb24SJammy Zhou 56871aec257SMonk Liu /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 56971aec257SMonk Liu #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 57071aec257SMonk Liu 571d240cd9eSMarek Olšák /* The IB fence should do the L2 writeback but not invalidate any shader 572d240cd9eSMarek Olšák * caches (L2/vL1/sL1/I$). */ 573d240cd9eSMarek Olšák #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 574d240cd9eSMarek Olšák 57541cca166SMarek Olšák /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 57641cca166SMarek Olšák * This will reset wave ID counters for the IB. 57741cca166SMarek Olšák */ 57841cca166SMarek Olšák #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 57941cca166SMarek Olšák 58081629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib { 5812ce9dde0SMikko Rapeli __u32 _pad; 582675da0ddSChristian König /** AMDGPU_IB_FLAG_* */ 5832ce9dde0SMikko Rapeli __u32 flags; 584675da0ddSChristian König /** Virtual address to begin IB execution */ 5852ce9dde0SMikko Rapeli __u64 va_start; 586675da0ddSChristian König /** Size of submission */ 5872ce9dde0SMikko Rapeli __u32 ib_bytes; 588675da0ddSChristian König /** HW IP to submit to */ 5892ce9dde0SMikko Rapeli __u32 ip_type; 590675da0ddSChristian König /** HW IP index of the same type to submit to */ 5912ce9dde0SMikko Rapeli __u32 ip_instance; 592675da0ddSChristian König /** Ring index to submit to */ 5932ce9dde0SMikko Rapeli __u32 ring; 59481629cbaSAlex Deucher }; 59581629cbaSAlex Deucher 5962b48d323SChristian König struct drm_amdgpu_cs_chunk_dep { 5972ce9dde0SMikko Rapeli __u32 ip_type; 5982ce9dde0SMikko Rapeli __u32 ip_instance; 5992ce9dde0SMikko Rapeli __u32 ring; 6002ce9dde0SMikko Rapeli __u32 ctx_id; 6012ce9dde0SMikko Rapeli __u64 handle; 6022b48d323SChristian König }; 6032b48d323SChristian König 60481629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence { 6052ce9dde0SMikko Rapeli __u32 handle; 6062ce9dde0SMikko Rapeli __u32 offset; 60781629cbaSAlex Deucher }; 60881629cbaSAlex Deucher 609660e8558SDave Airlie struct drm_amdgpu_cs_chunk_sem { 610660e8558SDave Airlie __u32 handle; 611660e8558SDave Airlie }; 612660e8558SDave Airlie 6132624dd15SChunming Zhou struct drm_amdgpu_cs_chunk_syncobj { 6142624dd15SChunming Zhou __u32 handle; 6152624dd15SChunming Zhou __u32 flags; 6162624dd15SChunming Zhou __u64 point; 6172624dd15SChunming Zhou }; 6182624dd15SChunming Zhou 6197ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 6207ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 6217ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 6227ca24cf2SMarek Olšák 6237ca24cf2SMarek Olšák union drm_amdgpu_fence_to_handle { 6247ca24cf2SMarek Olšák struct { 6257ca24cf2SMarek Olšák struct drm_amdgpu_fence fence; 6267ca24cf2SMarek Olšák __u32 what; 62756e0349fSDave Airlie __u32 pad; 6287ca24cf2SMarek Olšák } in; 6297ca24cf2SMarek Olšák struct { 6307ca24cf2SMarek Olšák __u32 handle; 6317ca24cf2SMarek Olšák } out; 6327ca24cf2SMarek Olšák }; 6337ca24cf2SMarek Olšák 63481629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_data { 63581629cbaSAlex Deucher union { 63681629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib ib_data; 63781629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence fence_data; 63881629cbaSAlex Deucher }; 63981629cbaSAlex Deucher }; 64081629cbaSAlex Deucher 64181629cbaSAlex Deucher /** 64281629cbaSAlex Deucher * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 64381629cbaSAlex Deucher * 64481629cbaSAlex Deucher */ 64581629cbaSAlex Deucher #define AMDGPU_IDS_FLAGS_FUSION 0x1 646aafcafa0SMonk Liu #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 64781629cbaSAlex Deucher 64881629cbaSAlex Deucher /* indicate if acceleration can be working */ 64981629cbaSAlex Deucher #define AMDGPU_INFO_ACCEL_WORKING 0x00 65081629cbaSAlex Deucher /* get the crtc_id from the mode object id? */ 65181629cbaSAlex Deucher #define AMDGPU_INFO_CRTC_FROM_ID 0x01 65281629cbaSAlex Deucher /* query hw IP info */ 65381629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_INFO 0x02 65481629cbaSAlex Deucher /* query hw IP instance count for the specified type */ 65581629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_COUNT 0x03 65681629cbaSAlex Deucher /* timestamp for GL_ARB_timer_query */ 65781629cbaSAlex Deucher #define AMDGPU_INFO_TIMESTAMP 0x05 65881629cbaSAlex Deucher /* Query the firmware version */ 65981629cbaSAlex Deucher #define AMDGPU_INFO_FW_VERSION 0x0e 66081629cbaSAlex Deucher /* Subquery id: Query VCE firmware version */ 66181629cbaSAlex Deucher #define AMDGPU_INFO_FW_VCE 0x1 66281629cbaSAlex Deucher /* Subquery id: Query UVD firmware version */ 66381629cbaSAlex Deucher #define AMDGPU_INFO_FW_UVD 0x2 66481629cbaSAlex Deucher /* Subquery id: Query GMC firmware version */ 66581629cbaSAlex Deucher #define AMDGPU_INFO_FW_GMC 0x03 66681629cbaSAlex Deucher /* Subquery id: Query GFX ME firmware version */ 66781629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_ME 0x04 66881629cbaSAlex Deucher /* Subquery id: Query GFX PFP firmware version */ 66981629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_PFP 0x05 67081629cbaSAlex Deucher /* Subquery id: Query GFX CE firmware version */ 67181629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_CE 0x06 67281629cbaSAlex Deucher /* Subquery id: Query GFX RLC firmware version */ 67381629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_RLC 0x07 67481629cbaSAlex Deucher /* Subquery id: Query GFX MEC firmware version */ 67581629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_MEC 0x08 67681629cbaSAlex Deucher /* Subquery id: Query SMC firmware version */ 67781629cbaSAlex Deucher #define AMDGPU_INFO_FW_SMC 0x0a 67881629cbaSAlex Deucher /* Subquery id: Query SDMA firmware version */ 67981629cbaSAlex Deucher #define AMDGPU_INFO_FW_SDMA 0x0b 6806a7ed07eSHuang Rui /* Subquery id: Query PSP SOS firmware version */ 6816a7ed07eSHuang Rui #define AMDGPU_INFO_FW_SOS 0x0c 6826a7ed07eSHuang Rui /* Subquery id: Query PSP ASD firmware version */ 6836a7ed07eSHuang Rui #define AMDGPU_INFO_FW_ASD 0x0d 6843ac952b1SAlex Deucher /* Subquery id: Query VCN firmware version */ 6853ac952b1SAlex Deucher #define AMDGPU_INFO_FW_VCN 0x0e 686621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLC firmware version */ 687621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 688621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLG firmware version */ 689621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 690621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLS firmware version */ 691621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 6924d11b4b2SDavid Francis /* Subquery id: Query DMCU firmware version */ 6934d11b4b2SDavid Francis #define AMDGPU_INFO_FW_DMCU 0x12 6949b9ca62dSxinhui pan #define AMDGPU_INFO_FW_TA 0x13 69581629cbaSAlex Deucher /* number of bytes moved for TTM migration */ 69681629cbaSAlex Deucher #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 69781629cbaSAlex Deucher /* the used VRAM size */ 69881629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_USAGE 0x10 69981629cbaSAlex Deucher /* the used GTT size */ 70081629cbaSAlex Deucher #define AMDGPU_INFO_GTT_USAGE 0x11 70181629cbaSAlex Deucher /* Information about GDS, etc. resource configuration */ 70281629cbaSAlex Deucher #define AMDGPU_INFO_GDS_CONFIG 0x13 70381629cbaSAlex Deucher /* Query information about VRAM and GTT domains */ 70481629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_GTT 0x14 70581629cbaSAlex Deucher /* Query information about register in MMR address space*/ 70681629cbaSAlex Deucher #define AMDGPU_INFO_READ_MMR_REG 0x15 70781629cbaSAlex Deucher /* Query information about device: rev id, family, etc. */ 70881629cbaSAlex Deucher #define AMDGPU_INFO_DEV_INFO 0x16 70981629cbaSAlex Deucher /* visible vram usage */ 71081629cbaSAlex Deucher #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 71183a59b63SMarek Olšák /* number of TTM buffer evictions */ 71283a59b63SMarek Olšák #define AMDGPU_INFO_NUM_EVICTIONS 0x18 713e0adf6c8SJunwei Zhang /* Query memory about VRAM and GTT domains */ 714e0adf6c8SJunwei Zhang #define AMDGPU_INFO_MEMORY 0x19 715bbe87974SAlex Deucher /* Query vce clock table */ 716bbe87974SAlex Deucher #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 71740ee5888SEvan Quan /* Query vbios related information */ 71840ee5888SEvan Quan #define AMDGPU_INFO_VBIOS 0x1B 71940ee5888SEvan Quan /* Subquery id: Query vbios size */ 72040ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_SIZE 0x1 72140ee5888SEvan Quan /* Subquery id: Query vbios image */ 72240ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_IMAGE 0x2 72344879b62SArindam Nath /* Query UVD handles */ 72444879b62SArindam Nath #define AMDGPU_INFO_NUM_HANDLES 0x1C 7255ebbac4bSAlex Deucher /* Query sensor related information */ 7265ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR 0x1D 7275ebbac4bSAlex Deucher /* Subquery id: Query GPU shader clock */ 7285ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 7295ebbac4bSAlex Deucher /* Subquery id: Query GPU memory clock */ 7305ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 7315ebbac4bSAlex Deucher /* Subquery id: Query GPU temperature */ 7325ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 7335ebbac4bSAlex Deucher /* Subquery id: Query GPU load */ 7345ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 7355ebbac4bSAlex Deucher /* Subquery id: Query average GPU power */ 7365ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 7375ebbac4bSAlex Deucher /* Subquery id: Query northbridge voltage */ 7385ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDNB 0x6 7395ebbac4bSAlex Deucher /* Subquery id: Query graphics voltage */ 7405ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 74160bbade2SRex Zhu /* Subquery id: Query GPU stable pstate shader clock */ 74260bbade2SRex Zhu #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 74360bbade2SRex Zhu /* Subquery id: Query GPU stable pstate memory clock */ 74460bbade2SRex Zhu #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 74568e2c5ffSMarek Olšák /* Number of VRAM page faults on CPU access. */ 74668e2c5ffSMarek Olšák #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 7471f7251b7SChristian König #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 7485cb77114Sxinhui pan /* query ras mask of enabled features*/ 7495cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 7505cb77114Sxinhui pan 7515cb77114Sxinhui pan /* RAS MASK: UMC (VRAM) */ 7525cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 7535cb77114Sxinhui pan /* RAS MASK: SDMA */ 7545cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 7555cb77114Sxinhui pan /* RAS MASK: GFX */ 7565cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 7575cb77114Sxinhui pan /* RAS MASK: MMHUB */ 7585cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 7595cb77114Sxinhui pan /* RAS MASK: ATHUB */ 7605cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 7615cb77114Sxinhui pan /* RAS MASK: PCIE */ 7625cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 7635cb77114Sxinhui pan /* RAS MASK: HDP */ 7645cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 7655cb77114Sxinhui pan /* RAS MASK: XGMI */ 7665cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 7675cb77114Sxinhui pan /* RAS MASK: DF */ 7685cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 7695cb77114Sxinhui pan /* RAS MASK: SMN */ 7705cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 7715cb77114Sxinhui pan /* RAS MASK: SEM */ 7725cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 7735cb77114Sxinhui pan /* RAS MASK: MP0 */ 7745cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 7755cb77114Sxinhui pan /* RAS MASK: MP1 */ 7765cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 7775cb77114Sxinhui pan /* RAS MASK: FUSE */ 7785cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 77981629cbaSAlex Deucher 78081629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 78181629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 78281629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 78381629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 78481629cbaSAlex Deucher 785000cab9aSHuang Rui struct drm_amdgpu_query_fw { 786000cab9aSHuang Rui /** AMDGPU_INFO_FW_* */ 787000cab9aSHuang Rui __u32 fw_type; 788000cab9aSHuang Rui /** 789000cab9aSHuang Rui * Index of the IP if there are more IPs of 790000cab9aSHuang Rui * the same type. 791000cab9aSHuang Rui */ 792000cab9aSHuang Rui __u32 ip_instance; 793000cab9aSHuang Rui /** 794000cab9aSHuang Rui * Index of the engine. Whether this is used depends 795000cab9aSHuang Rui * on the firmware type. (e.g. MEC, SDMA) 796000cab9aSHuang Rui */ 797000cab9aSHuang Rui __u32 index; 798000cab9aSHuang Rui __u32 _pad; 799000cab9aSHuang Rui }; 800000cab9aSHuang Rui 80181629cbaSAlex Deucher /* Input structure for the INFO ioctl */ 80281629cbaSAlex Deucher struct drm_amdgpu_info { 80381629cbaSAlex Deucher /* Where the return value will be stored */ 8042ce9dde0SMikko Rapeli __u64 return_pointer; 80581629cbaSAlex Deucher /* The size of the return value. Just like "size" in "snprintf", 80681629cbaSAlex Deucher * it limits how many bytes the kernel can write. */ 8072ce9dde0SMikko Rapeli __u32 return_size; 80881629cbaSAlex Deucher /* The query request id. */ 8092ce9dde0SMikko Rapeli __u32 query; 81081629cbaSAlex Deucher 81181629cbaSAlex Deucher union { 81281629cbaSAlex Deucher struct { 8132ce9dde0SMikko Rapeli __u32 id; 8142ce9dde0SMikko Rapeli __u32 _pad; 81581629cbaSAlex Deucher } mode_crtc; 81681629cbaSAlex Deucher 81781629cbaSAlex Deucher struct { 81881629cbaSAlex Deucher /** AMDGPU_HW_IP_* */ 8192ce9dde0SMikko Rapeli __u32 type; 82081629cbaSAlex Deucher /** 821675da0ddSChristian König * Index of the IP if there are more IPs of the same 822675da0ddSChristian König * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 82381629cbaSAlex Deucher */ 8242ce9dde0SMikko Rapeli __u32 ip_instance; 82581629cbaSAlex Deucher } query_hw_ip; 82681629cbaSAlex Deucher 82781629cbaSAlex Deucher struct { 8282ce9dde0SMikko Rapeli __u32 dword_offset; 829675da0ddSChristian König /** number of registers to read */ 8302ce9dde0SMikko Rapeli __u32 count; 8312ce9dde0SMikko Rapeli __u32 instance; 832675da0ddSChristian König /** For future use, no flags defined so far */ 8332ce9dde0SMikko Rapeli __u32 flags; 83481629cbaSAlex Deucher } read_mmr_reg; 83581629cbaSAlex Deucher 836000cab9aSHuang Rui struct drm_amdgpu_query_fw query_fw; 83740ee5888SEvan Quan 83840ee5888SEvan Quan struct { 83940ee5888SEvan Quan __u32 type; 84040ee5888SEvan Quan __u32 offset; 84140ee5888SEvan Quan } vbios_info; 8425ebbac4bSAlex Deucher 8435ebbac4bSAlex Deucher struct { 8445ebbac4bSAlex Deucher __u32 type; 8455ebbac4bSAlex Deucher } sensor_info; 84681629cbaSAlex Deucher }; 84781629cbaSAlex Deucher }; 84881629cbaSAlex Deucher 84981629cbaSAlex Deucher struct drm_amdgpu_info_gds { 85081629cbaSAlex Deucher /** GDS GFX partition size */ 8512ce9dde0SMikko Rapeli __u32 gds_gfx_partition_size; 85281629cbaSAlex Deucher /** GDS compute partition size */ 8532ce9dde0SMikko Rapeli __u32 compute_partition_size; 85481629cbaSAlex Deucher /** total GDS memory size */ 8552ce9dde0SMikko Rapeli __u32 gds_total_size; 85681629cbaSAlex Deucher /** GWS size per GFX partition */ 8572ce9dde0SMikko Rapeli __u32 gws_per_gfx_partition; 85881629cbaSAlex Deucher /** GSW size per compute partition */ 8592ce9dde0SMikko Rapeli __u32 gws_per_compute_partition; 86081629cbaSAlex Deucher /** OA size per GFX partition */ 8612ce9dde0SMikko Rapeli __u32 oa_per_gfx_partition; 86281629cbaSAlex Deucher /** OA size per compute partition */ 8632ce9dde0SMikko Rapeli __u32 oa_per_compute_partition; 8642ce9dde0SMikko Rapeli __u32 _pad; 86581629cbaSAlex Deucher }; 86681629cbaSAlex Deucher 86781629cbaSAlex Deucher struct drm_amdgpu_info_vram_gtt { 8682ce9dde0SMikko Rapeli __u64 vram_size; 8692ce9dde0SMikko Rapeli __u64 vram_cpu_accessible_size; 8702ce9dde0SMikko Rapeli __u64 gtt_size; 87181629cbaSAlex Deucher }; 87281629cbaSAlex Deucher 873e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info { 874e0adf6c8SJunwei Zhang /** max. physical memory */ 875e0adf6c8SJunwei Zhang __u64 total_heap_size; 876e0adf6c8SJunwei Zhang 877e0adf6c8SJunwei Zhang /** Theoretical max. available memory in the given heap */ 878e0adf6c8SJunwei Zhang __u64 usable_heap_size; 879e0adf6c8SJunwei Zhang 880e0adf6c8SJunwei Zhang /** 881e0adf6c8SJunwei Zhang * Number of bytes allocated in the heap. This includes all processes 882e0adf6c8SJunwei Zhang * and private allocations in the kernel. It changes when new buffers 883e0adf6c8SJunwei Zhang * are allocated, freed, and moved. It cannot be larger than 884e0adf6c8SJunwei Zhang * heap_size. 885e0adf6c8SJunwei Zhang */ 886e0adf6c8SJunwei Zhang __u64 heap_usage; 887e0adf6c8SJunwei Zhang 888e0adf6c8SJunwei Zhang /** 889e0adf6c8SJunwei Zhang * Theoretical possible max. size of buffer which 890e0adf6c8SJunwei Zhang * could be allocated in the given heap 891e0adf6c8SJunwei Zhang */ 892e0adf6c8SJunwei Zhang __u64 max_allocation; 8939f6163e7SJunwei Zhang }; 8949f6163e7SJunwei Zhang 895e0adf6c8SJunwei Zhang struct drm_amdgpu_memory_info { 896e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info vram; 897e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info cpu_accessible_vram; 898e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info gtt; 899cfa32556SJunwei Zhang }; 900cfa32556SJunwei Zhang 90181629cbaSAlex Deucher struct drm_amdgpu_info_firmware { 9022ce9dde0SMikko Rapeli __u32 ver; 9032ce9dde0SMikko Rapeli __u32 feature; 90481629cbaSAlex Deucher }; 90581629cbaSAlex Deucher 90681c59f54SKen Wang #define AMDGPU_VRAM_TYPE_UNKNOWN 0 90781c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR1 1 90881c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR2 2 90981c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR3 3 91081c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR4 4 91181c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR5 5 91281c59f54SKen Wang #define AMDGPU_VRAM_TYPE_HBM 6 91381c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR3 7 9141e09b053SHawking Zhang #define AMDGPU_VRAM_TYPE_DDR4 8 915d67383e6SHuang Rui #define AMDGPU_VRAM_TYPE_GDDR6 9 91681c59f54SKen Wang 91781629cbaSAlex Deucher struct drm_amdgpu_info_device { 91881629cbaSAlex Deucher /** PCI Device ID */ 9192ce9dde0SMikko Rapeli __u32 device_id; 92081629cbaSAlex Deucher /** Internal chip revision: A0, A1, etc.) */ 9212ce9dde0SMikko Rapeli __u32 chip_rev; 9222ce9dde0SMikko Rapeli __u32 external_rev; 92381629cbaSAlex Deucher /** Revision id in PCI Config space */ 9242ce9dde0SMikko Rapeli __u32 pci_rev; 9252ce9dde0SMikko Rapeli __u32 family; 9262ce9dde0SMikko Rapeli __u32 num_shader_engines; 9272ce9dde0SMikko Rapeli __u32 num_shader_arrays_per_engine; 928675da0ddSChristian König /* in KHz */ 9292ce9dde0SMikko Rapeli __u32 gpu_counter_freq; 9302ce9dde0SMikko Rapeli __u64 max_engine_clock; 9312ce9dde0SMikko Rapeli __u64 max_memory_clock; 93281629cbaSAlex Deucher /* cu information */ 9332ce9dde0SMikko Rapeli __u32 cu_active_number; 934dbfe85eaSFlora Cui /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 9352ce9dde0SMikko Rapeli __u32 cu_ao_mask; 9362ce9dde0SMikko Rapeli __u32 cu_bitmap[4][4]; 93781629cbaSAlex Deucher /** Render backend pipe mask. One render backend is CB+DB. */ 9382ce9dde0SMikko Rapeli __u32 enabled_rb_pipes_mask; 9392ce9dde0SMikko Rapeli __u32 num_rb_pipes; 9402ce9dde0SMikko Rapeli __u32 num_hw_gfx_contexts; 9412ce9dde0SMikko Rapeli __u32 _pad; 9422ce9dde0SMikko Rapeli __u64 ids_flags; 94381629cbaSAlex Deucher /** Starting virtual address for UMDs. */ 9442ce9dde0SMikko Rapeli __u64 virtual_address_offset; 94502b70c8cSJammy Zhou /** The maximum virtual address */ 9462ce9dde0SMikko Rapeli __u64 virtual_address_max; 94781629cbaSAlex Deucher /** Required alignment of virtual addresses. */ 9482ce9dde0SMikko Rapeli __u32 virtual_address_alignment; 94981629cbaSAlex Deucher /** Page table entry - fragment size */ 9502ce9dde0SMikko Rapeli __u32 pte_fragment_size; 9512ce9dde0SMikko Rapeli __u32 gart_page_size; 952a101a899SKen Wang /** constant engine ram size*/ 9532ce9dde0SMikko Rapeli __u32 ce_ram_size; 954cab6d57cSJammy Zhou /** video memory type info*/ 9552ce9dde0SMikko Rapeli __u32 vram_type; 95681c59f54SKen Wang /** video memory bit width*/ 9572ce9dde0SMikko Rapeli __u32 vram_bit_width; 958fa92754eSLeo Liu /* vce harvesting instance */ 9592ce9dde0SMikko Rapeli __u32 vce_harvest_config; 960df6e2c4aSJunwei Zhang /* gfx double offchip LDS buffers */ 961df6e2c4aSJunwei Zhang __u32 gc_double_offchip_lds_buf; 962bce23e00SAlex Deucher /* NGG Primitive Buffer */ 963bce23e00SAlex Deucher __u64 prim_buf_gpu_addr; 964bce23e00SAlex Deucher /* NGG Position Buffer */ 965bce23e00SAlex Deucher __u64 pos_buf_gpu_addr; 966bce23e00SAlex Deucher /* NGG Control Sideband */ 967bce23e00SAlex Deucher __u64 cntl_sb_buf_gpu_addr; 968bce23e00SAlex Deucher /* NGG Parameter Cache */ 969bce23e00SAlex Deucher __u64 param_buf_gpu_addr; 970408bfe7cSJunwei Zhang __u32 prim_buf_size; 971408bfe7cSJunwei Zhang __u32 pos_buf_size; 972408bfe7cSJunwei Zhang __u32 cntl_sb_buf_size; 973408bfe7cSJunwei Zhang __u32 param_buf_size; 974408bfe7cSJunwei Zhang /* wavefront size*/ 975408bfe7cSJunwei Zhang __u32 wave_front_size; 976408bfe7cSJunwei Zhang /* shader visible vgprs*/ 977408bfe7cSJunwei Zhang __u32 num_shader_visible_vgprs; 978408bfe7cSJunwei Zhang /* CU per shader array*/ 979408bfe7cSJunwei Zhang __u32 num_cu_per_sh; 980408bfe7cSJunwei Zhang /* number of tcc blocks*/ 981408bfe7cSJunwei Zhang __u32 num_tcc_blocks; 982408bfe7cSJunwei Zhang /* gs vgt table depth*/ 983408bfe7cSJunwei Zhang __u32 gs_vgt_table_depth; 984408bfe7cSJunwei Zhang /* gs primitive buffer depth*/ 985408bfe7cSJunwei Zhang __u32 gs_prim_buffer_depth; 986408bfe7cSJunwei Zhang /* max gs wavefront per vgt*/ 987408bfe7cSJunwei Zhang __u32 max_gs_waves_per_vgt; 988408bfe7cSJunwei Zhang __u32 _pad1; 989dbfe85eaSFlora Cui /* always on cu bitmap */ 990dbfe85eaSFlora Cui __u32 cu_ao_bitmap[4][4]; 9915b565e0eSChristian König /** Starting high virtual address for UMDs. */ 9925b565e0eSChristian König __u64 high_va_offset; 9935b565e0eSChristian König /** The maximum high virtual address */ 9945b565e0eSChristian König __u64 high_va_max; 99581629cbaSAlex Deucher }; 99681629cbaSAlex Deucher 99781629cbaSAlex Deucher struct drm_amdgpu_info_hw_ip { 99881629cbaSAlex Deucher /** Version of h/w IP */ 9992ce9dde0SMikko Rapeli __u32 hw_ip_version_major; 10002ce9dde0SMikko Rapeli __u32 hw_ip_version_minor; 100181629cbaSAlex Deucher /** Capabilities */ 10022ce9dde0SMikko Rapeli __u64 capabilities_flags; 100371062f43SKen Wang /** command buffer address start alignment*/ 10042ce9dde0SMikko Rapeli __u32 ib_start_alignment; 100571062f43SKen Wang /** command buffer size alignment*/ 10062ce9dde0SMikko Rapeli __u32 ib_size_alignment; 100781629cbaSAlex Deucher /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 10082ce9dde0SMikko Rapeli __u32 available_rings; 10092ce9dde0SMikko Rapeli __u32 _pad; 101081629cbaSAlex Deucher }; 101181629cbaSAlex Deucher 101244879b62SArindam Nath struct drm_amdgpu_info_num_handles { 101344879b62SArindam Nath /** Max handles as supported by firmware for UVD */ 101444879b62SArindam Nath __u32 uvd_max_handles; 101544879b62SArindam Nath /** Handles currently in use for UVD */ 101644879b62SArindam Nath __u32 uvd_used_handles; 101744879b62SArindam Nath }; 101844879b62SArindam Nath 1019bbe87974SAlex Deucher #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1020bbe87974SAlex Deucher 1021bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry { 1022bbe87974SAlex Deucher /** System clock */ 1023bbe87974SAlex Deucher __u32 sclk; 1024bbe87974SAlex Deucher /** Memory clock */ 1025bbe87974SAlex Deucher __u32 mclk; 1026bbe87974SAlex Deucher /** VCE clock */ 1027bbe87974SAlex Deucher __u32 eclk; 1028bbe87974SAlex Deucher __u32 pad; 1029bbe87974SAlex Deucher }; 1030bbe87974SAlex Deucher 1031bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table { 1032bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1033bbe87974SAlex Deucher __u32 num_valid_entries; 1034bbe87974SAlex Deucher __u32 pad; 1035bbe87974SAlex Deucher }; 1036bbe87974SAlex Deucher 103781629cbaSAlex Deucher /* 103881629cbaSAlex Deucher * Supported GPU families 103981629cbaSAlex Deucher */ 104081629cbaSAlex Deucher #define AMDGPU_FAMILY_UNKNOWN 0 1041295d0dafSKen Wang #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 104281629cbaSAlex Deucher #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 104381629cbaSAlex Deucher #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 104481629cbaSAlex Deucher #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 104539bb0c92SSamuel Li #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1046a8f1f1ceSAlex Deucher #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 10472ca8a5d2SChunming Zhou #define AMDGPU_FAMILY_RV 142 /* Raven */ 1048107c34bcSHuang Rui #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 104981629cbaSAlex Deucher 1050cfa7152fSEmil Velikov #if defined(__cplusplus) 1051cfa7152fSEmil Velikov } 1052cfa7152fSEmil Velikov #endif 1053cfa7152fSEmil Velikov 105481629cbaSAlex Deucher #endif 1055