181629cbaSAlex Deucher /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 281629cbaSAlex Deucher * 381629cbaSAlex Deucher * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 481629cbaSAlex Deucher * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 581629cbaSAlex Deucher * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 681629cbaSAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 781629cbaSAlex Deucher * 881629cbaSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 981629cbaSAlex Deucher * copy of this software and associated documentation files (the "Software"), 1081629cbaSAlex Deucher * to deal in the Software without restriction, including without limitation 1181629cbaSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1281629cbaSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1381629cbaSAlex Deucher * Software is furnished to do so, subject to the following conditions: 1481629cbaSAlex Deucher * 1581629cbaSAlex Deucher * The above copyright notice and this permission notice shall be included in 1681629cbaSAlex Deucher * all copies or substantial portions of the Software. 1781629cbaSAlex Deucher * 1881629cbaSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1981629cbaSAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2081629cbaSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2181629cbaSAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2281629cbaSAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2381629cbaSAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2481629cbaSAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2581629cbaSAlex Deucher * 2681629cbaSAlex Deucher * Authors: 2781629cbaSAlex Deucher * Kevin E. Martin <martin@valinux.com> 2881629cbaSAlex Deucher * Gareth Hughes <gareth@valinux.com> 2981629cbaSAlex Deucher * Keith Whitwell <keith@tungstengraphics.com> 3081629cbaSAlex Deucher */ 3181629cbaSAlex Deucher 3281629cbaSAlex Deucher #ifndef __AMDGPU_DRM_H__ 3381629cbaSAlex Deucher #define __AMDGPU_DRM_H__ 3481629cbaSAlex Deucher 35b3fcf36aSMichel Dänzer #include "drm.h" 3681629cbaSAlex Deucher 37cfa7152fSEmil Velikov #if defined(__cplusplus) 38cfa7152fSEmil Velikov extern "C" { 39cfa7152fSEmil Velikov #endif 40cfa7152fSEmil Velikov 4181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_CREATE 0x00 4281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_MMAP 0x01 4381629cbaSAlex Deucher #define DRM_AMDGPU_CTX 0x02 4481629cbaSAlex Deucher #define DRM_AMDGPU_BO_LIST 0x03 4581629cbaSAlex Deucher #define DRM_AMDGPU_CS 0x04 4681629cbaSAlex Deucher #define DRM_AMDGPU_INFO 0x05 4781629cbaSAlex Deucher #define DRM_AMDGPU_GEM_METADATA 0x06 4881629cbaSAlex Deucher #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 4981629cbaSAlex Deucher #define DRM_AMDGPU_GEM_VA 0x08 5081629cbaSAlex Deucher #define DRM_AMDGPU_WAIT_CS 0x09 5181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_OP 0x10 5281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_USERPTR 0x11 53eef18a82SJunwei Zhang #define DRM_AMDGPU_WAIT_FENCES 0x12 54cfbcacf4SChunming Zhou #define DRM_AMDGPU_VM 0x13 557ca24cf2SMarek Olšák #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 5652c6a62cSAndres Rodriguez #define DRM_AMDGPU_SCHED 0x15 5781629cbaSAlex Deucher 5881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 5981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 6081629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 6181629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 6281629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 6381629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 6481629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 6581629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 6634b5f6a6SChristian König #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 6781629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 6881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 6981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70eef18a82SJunwei Zhang #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71cfbcacf4SChunming Zhou #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 727ca24cf2SMarek Olšák #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 7352c6a62cSAndres Rodriguez #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 7481629cbaSAlex Deucher 75b646c1dcSSamuel Li /** 76b646c1dcSSamuel Li * DOC: memory domains 77b646c1dcSSamuel Li * 78b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79b646c1dcSSamuel Li * Memory in this pool could be swapped out to disk if there is pressure. 80b646c1dcSSamuel Li * 81b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82b646c1dcSSamuel Li * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83b646c1dcSSamuel Li * pages of system memory, allows GPU access system memory in a linezrized 84b646c1dcSSamuel Li * fashion. 85b646c1dcSSamuel Li * 86b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87b646c1dcSSamuel Li * carved out by the BIOS. 88b646c1dcSSamuel Li * 89b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90b646c1dcSSamuel Li * across shader threads. 91b646c1dcSSamuel Li * 92b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93b646c1dcSSamuel Li * execution of all the waves on a device. 94b646c1dcSSamuel Li * 95b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96b646c1dcSSamuel Li * for appending data. 97b646c1dcSSamuel Li */ 9881629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_CPU 0x1 9981629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GTT 0x2 10081629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_VRAM 0x4 10181629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GDS 0x8 10281629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GWS 0x10 10381629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_OA 0x20 1043f188453SChunming Zhou #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 1053f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GTT | \ 1063f188453SChunming Zhou AMDGPU_GEM_DOMAIN_VRAM | \ 1073f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GDS | \ 1083f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GWS | \ 1093f188453SChunming Zhou AMDGPU_GEM_DOMAIN_OA) 11081629cbaSAlex Deucher 11181629cbaSAlex Deucher /* Flag that CPU access will be required for the case of VRAM domain */ 11281629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 11381629cbaSAlex Deucher /* Flag that CPU access will not work, this VRAM domain is invisible */ 11481629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 11581629cbaSAlex Deucher /* Flag that USWC attributes should be used for GTT */ 11688671288SJammy Zhou #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 1174fea83ffSFlora Cui /* Flag that the memory should be in VRAM and cleared */ 1184fea83ffSFlora Cui #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119e7893c4bSChunming Zhou /* Flag that create shadow bo(GTT) while allocating vram bo */ 120e7893c4bSChunming Zhou #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 12103f48dd5SChristian König /* Flag that allocating the BO should use linear VRAM */ 12203f48dd5SChristian König #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 123e1eb899bSChristian König /* Flag that BO is always valid in this VM */ 124e1eb899bSChristian König #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 125177ae09bSAndres Rodriguez /* Flag that BO sharing will be explicitly synchronized */ 126177ae09bSAndres Rodriguez #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 127959a2091SYong Zhao /* Flag that indicates allocating MQD gart on GFX9, where the mtype 128959a2091SYong Zhao * for the second page onward should be set to NC. 129959a2091SYong Zhao */ 130959a2091SYong Zhao #define AMDGPU_GEM_CREATE_MQD_GFX9 (1 << 8) 13181629cbaSAlex Deucher 13281629cbaSAlex Deucher struct drm_amdgpu_gem_create_in { 13381629cbaSAlex Deucher /** the requested memory size */ 1342ce9dde0SMikko Rapeli __u64 bo_size; 13581629cbaSAlex Deucher /** physical start_addr alignment in bytes for some HW requirements */ 1362ce9dde0SMikko Rapeli __u64 alignment; 13781629cbaSAlex Deucher /** the requested memory domains */ 1382ce9dde0SMikko Rapeli __u64 domains; 13981629cbaSAlex Deucher /** allocation flags */ 1402ce9dde0SMikko Rapeli __u64 domain_flags; 14181629cbaSAlex Deucher }; 14281629cbaSAlex Deucher 14381629cbaSAlex Deucher struct drm_amdgpu_gem_create_out { 14481629cbaSAlex Deucher /** returned GEM object handle */ 1452ce9dde0SMikko Rapeli __u32 handle; 1462ce9dde0SMikko Rapeli __u32 _pad; 14781629cbaSAlex Deucher }; 14881629cbaSAlex Deucher 14981629cbaSAlex Deucher union drm_amdgpu_gem_create { 15081629cbaSAlex Deucher struct drm_amdgpu_gem_create_in in; 15181629cbaSAlex Deucher struct drm_amdgpu_gem_create_out out; 15281629cbaSAlex Deucher }; 15381629cbaSAlex Deucher 15481629cbaSAlex Deucher /** Opcode to create new residency list. */ 15581629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_CREATE 0 15681629cbaSAlex Deucher /** Opcode to destroy previously created residency list */ 15781629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_DESTROY 1 15881629cbaSAlex Deucher /** Opcode to update resource information in the list */ 15981629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_UPDATE 2 16081629cbaSAlex Deucher 16181629cbaSAlex Deucher struct drm_amdgpu_bo_list_in { 16281629cbaSAlex Deucher /** Type of operation */ 1632ce9dde0SMikko Rapeli __u32 operation; 16481629cbaSAlex Deucher /** Handle of list or 0 if we want to create one */ 1652ce9dde0SMikko Rapeli __u32 list_handle; 16681629cbaSAlex Deucher /** Number of BOs in list */ 1672ce9dde0SMikko Rapeli __u32 bo_number; 16881629cbaSAlex Deucher /** Size of each element describing BO */ 1692ce9dde0SMikko Rapeli __u32 bo_info_size; 17081629cbaSAlex Deucher /** Pointer to array describing BOs */ 1712ce9dde0SMikko Rapeli __u64 bo_info_ptr; 17281629cbaSAlex Deucher }; 17381629cbaSAlex Deucher 17481629cbaSAlex Deucher struct drm_amdgpu_bo_list_entry { 17581629cbaSAlex Deucher /** Handle of BO */ 1762ce9dde0SMikko Rapeli __u32 bo_handle; 17781629cbaSAlex Deucher /** New (if specified) BO priority to be used during migration */ 1782ce9dde0SMikko Rapeli __u32 bo_priority; 17981629cbaSAlex Deucher }; 18081629cbaSAlex Deucher 18181629cbaSAlex Deucher struct drm_amdgpu_bo_list_out { 18281629cbaSAlex Deucher /** Handle of resource list */ 1832ce9dde0SMikko Rapeli __u32 list_handle; 1842ce9dde0SMikko Rapeli __u32 _pad; 18581629cbaSAlex Deucher }; 18681629cbaSAlex Deucher 18781629cbaSAlex Deucher union drm_amdgpu_bo_list { 18881629cbaSAlex Deucher struct drm_amdgpu_bo_list_in in; 18981629cbaSAlex Deucher struct drm_amdgpu_bo_list_out out; 19081629cbaSAlex Deucher }; 19181629cbaSAlex Deucher 19281629cbaSAlex Deucher /* context related */ 19381629cbaSAlex Deucher #define AMDGPU_CTX_OP_ALLOC_CTX 1 19481629cbaSAlex Deucher #define AMDGPU_CTX_OP_FREE_CTX 2 19581629cbaSAlex Deucher #define AMDGPU_CTX_OP_QUERY_STATE 3 196bc1b1bf6SMonk Liu #define AMDGPU_CTX_OP_QUERY_STATE2 4 19781629cbaSAlex Deucher 198d94aed5aSMarek Olšák /* GPU reset status */ 199d94aed5aSMarek Olšák #define AMDGPU_CTX_NO_RESET 0 200675da0ddSChristian König /* this the context caused it */ 201675da0ddSChristian König #define AMDGPU_CTX_GUILTY_RESET 1 202675da0ddSChristian König /* some other context caused it */ 203675da0ddSChristian König #define AMDGPU_CTX_INNOCENT_RESET 2 204675da0ddSChristian König /* unknown cause */ 205675da0ddSChristian König #define AMDGPU_CTX_UNKNOWN_RESET 3 206d94aed5aSMarek Olšák 207bc1b1bf6SMonk Liu /* indicate gpu reset occured after ctx created */ 208bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 209bc1b1bf6SMonk Liu /* indicate vram lost occured after ctx created */ 210bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 211bc1b1bf6SMonk Liu /* indicate some job from this context once cause gpu hang */ 212bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 213bc1b1bf6SMonk Liu 214c2636dc5SAndres Rodriguez /* Context priority level */ 215f3d19bf8SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_UNSET -2048 2168bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 2178bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_LOW -512 218c2636dc5SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_NORMAL 0 219c2636dc5SAndres Rodriguez /* Selecting a priority above NORMAL requires CAP_SYS_NICE or DRM_MASTER */ 2208bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_HIGH 512 2218bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 222c2636dc5SAndres Rodriguez 22381629cbaSAlex Deucher struct drm_amdgpu_ctx_in { 224675da0ddSChristian König /** AMDGPU_CTX_OP_* */ 2252ce9dde0SMikko Rapeli __u32 op; 226675da0ddSChristian König /** For future use, no flags defined so far */ 2272ce9dde0SMikko Rapeli __u32 flags; 2282ce9dde0SMikko Rapeli __u32 ctx_id; 229c2636dc5SAndres Rodriguez __s32 priority; 23081629cbaSAlex Deucher }; 23181629cbaSAlex Deucher 23281629cbaSAlex Deucher union drm_amdgpu_ctx_out { 23381629cbaSAlex Deucher struct { 2342ce9dde0SMikko Rapeli __u32 ctx_id; 2352ce9dde0SMikko Rapeli __u32 _pad; 23681629cbaSAlex Deucher } alloc; 23781629cbaSAlex Deucher 23881629cbaSAlex Deucher struct { 239675da0ddSChristian König /** For future use, no flags defined so far */ 2402ce9dde0SMikko Rapeli __u64 flags; 241d94aed5aSMarek Olšák /** Number of resets caused by this context so far. */ 2422ce9dde0SMikko Rapeli __u32 hangs; 243d94aed5aSMarek Olšák /** Reset status since the last call of the ioctl. */ 2442ce9dde0SMikko Rapeli __u32 reset_status; 24581629cbaSAlex Deucher } state; 24681629cbaSAlex Deucher }; 24781629cbaSAlex Deucher 24881629cbaSAlex Deucher union drm_amdgpu_ctx { 24981629cbaSAlex Deucher struct drm_amdgpu_ctx_in in; 25081629cbaSAlex Deucher union drm_amdgpu_ctx_out out; 25181629cbaSAlex Deucher }; 25281629cbaSAlex Deucher 253cfbcacf4SChunming Zhou /* vm ioctl */ 254cfbcacf4SChunming Zhou #define AMDGPU_VM_OP_RESERVE_VMID 1 255cfbcacf4SChunming Zhou #define AMDGPU_VM_OP_UNRESERVE_VMID 2 256cfbcacf4SChunming Zhou 257cfbcacf4SChunming Zhou struct drm_amdgpu_vm_in { 258cfbcacf4SChunming Zhou /** AMDGPU_VM_OP_* */ 259cfbcacf4SChunming Zhou __u32 op; 260cfbcacf4SChunming Zhou __u32 flags; 261cfbcacf4SChunming Zhou }; 262cfbcacf4SChunming Zhou 263cfbcacf4SChunming Zhou struct drm_amdgpu_vm_out { 264cfbcacf4SChunming Zhou /** For future use, no flags defined so far */ 265cfbcacf4SChunming Zhou __u64 flags; 266cfbcacf4SChunming Zhou }; 267cfbcacf4SChunming Zhou 268cfbcacf4SChunming Zhou union drm_amdgpu_vm { 269cfbcacf4SChunming Zhou struct drm_amdgpu_vm_in in; 270cfbcacf4SChunming Zhou struct drm_amdgpu_vm_out out; 271cfbcacf4SChunming Zhou }; 272cfbcacf4SChunming Zhou 27352c6a62cSAndres Rodriguez /* sched ioctl */ 27452c6a62cSAndres Rodriguez #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 27552c6a62cSAndres Rodriguez 27652c6a62cSAndres Rodriguez struct drm_amdgpu_sched_in { 27752c6a62cSAndres Rodriguez /* AMDGPU_SCHED_OP_* */ 27852c6a62cSAndres Rodriguez __u32 op; 27952c6a62cSAndres Rodriguez __u32 fd; 28052c6a62cSAndres Rodriguez __s32 priority; 28152c6a62cSAndres Rodriguez __u32 flags; 28252c6a62cSAndres Rodriguez }; 28352c6a62cSAndres Rodriguez 28452c6a62cSAndres Rodriguez union drm_amdgpu_sched { 28552c6a62cSAndres Rodriguez struct drm_amdgpu_sched_in in; 28652c6a62cSAndres Rodriguez }; 28752c6a62cSAndres Rodriguez 28881629cbaSAlex Deucher /* 28981629cbaSAlex Deucher * This is not a reliable API and you should expect it to fail for any 29081629cbaSAlex Deucher * number of reasons and have fallback path that do not use userptr to 29181629cbaSAlex Deucher * perform any operation. 29281629cbaSAlex Deucher */ 29381629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 29481629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 29581629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 29681629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 29781629cbaSAlex Deucher 29881629cbaSAlex Deucher struct drm_amdgpu_gem_userptr { 2992ce9dde0SMikko Rapeli __u64 addr; 3002ce9dde0SMikko Rapeli __u64 size; 301675da0ddSChristian König /* AMDGPU_GEM_USERPTR_* */ 3022ce9dde0SMikko Rapeli __u32 flags; 303675da0ddSChristian König /* Resulting GEM handle */ 3042ce9dde0SMikko Rapeli __u32 handle; 30581629cbaSAlex Deucher }; 30681629cbaSAlex Deucher 30700ac6f6bSAlex Deucher /* SI-CI-VI: */ 308fbd76d59SMarek Olšák /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 309fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 310fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 311fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 312fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 313fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 314fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 315fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 316fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 317fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 318fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 319fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 320fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 321fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 322fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 323fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 324fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 325fbd76d59SMarek Olšák 32600ac6f6bSAlex Deucher /* GFX9 and later: */ 32700ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 32800ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 32900ac6f6bSAlex Deucher 33000ac6f6bSAlex Deucher /* Set/Get helpers for tiling flags. */ 331fbd76d59SMarek Olšák #define AMDGPU_TILING_SET(field, value) \ 33200ac6f6bSAlex Deucher (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 333fbd76d59SMarek Olšák #define AMDGPU_TILING_GET(value, field) \ 33400ac6f6bSAlex Deucher (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 33581629cbaSAlex Deucher 33681629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 33781629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 33881629cbaSAlex Deucher 33981629cbaSAlex Deucher /** The same structure is shared for input/output */ 34081629cbaSAlex Deucher struct drm_amdgpu_gem_metadata { 341675da0ddSChristian König /** GEM Object handle */ 3422ce9dde0SMikko Rapeli __u32 handle; 343675da0ddSChristian König /** Do we want get or set metadata */ 3442ce9dde0SMikko Rapeli __u32 op; 34581629cbaSAlex Deucher struct { 346675da0ddSChristian König /** For future use, no flags defined so far */ 3472ce9dde0SMikko Rapeli __u64 flags; 348675da0ddSChristian König /** family specific tiling info */ 3492ce9dde0SMikko Rapeli __u64 tiling_info; 3502ce9dde0SMikko Rapeli __u32 data_size_bytes; 3512ce9dde0SMikko Rapeli __u32 data[64]; 35281629cbaSAlex Deucher } data; 35381629cbaSAlex Deucher }; 35481629cbaSAlex Deucher 35581629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in { 356675da0ddSChristian König /** the GEM object handle */ 3572ce9dde0SMikko Rapeli __u32 handle; 3582ce9dde0SMikko Rapeli __u32 _pad; 35981629cbaSAlex Deucher }; 36081629cbaSAlex Deucher 36181629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out { 362675da0ddSChristian König /** mmap offset from the vma offset manager */ 3632ce9dde0SMikko Rapeli __u64 addr_ptr; 36481629cbaSAlex Deucher }; 36581629cbaSAlex Deucher 36681629cbaSAlex Deucher union drm_amdgpu_gem_mmap { 36781629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in in; 36881629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out out; 36981629cbaSAlex Deucher }; 37081629cbaSAlex Deucher 37181629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in { 372675da0ddSChristian König /** GEM object handle */ 3732ce9dde0SMikko Rapeli __u32 handle; 374675da0ddSChristian König /** For future use, no flags defined so far */ 3752ce9dde0SMikko Rapeli __u32 flags; 376675da0ddSChristian König /** Absolute timeout to wait */ 3772ce9dde0SMikko Rapeli __u64 timeout; 37881629cbaSAlex Deucher }; 37981629cbaSAlex Deucher 38081629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out { 381675da0ddSChristian König /** BO status: 0 - BO is idle, 1 - BO is busy */ 3822ce9dde0SMikko Rapeli __u32 status; 383675da0ddSChristian König /** Returned current memory domain */ 3842ce9dde0SMikko Rapeli __u32 domain; 38581629cbaSAlex Deucher }; 38681629cbaSAlex Deucher 38781629cbaSAlex Deucher union drm_amdgpu_gem_wait_idle { 38881629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in in; 38981629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out out; 39081629cbaSAlex Deucher }; 39181629cbaSAlex Deucher 39281629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in { 393d7b1eeb2SMonk Liu /* Command submission handle 394d7b1eeb2SMonk Liu * handle equals 0 means none to wait for 395080b24ebSAlex Deucher * handle equals ~0ull means wait for the latest sequence number 396d7b1eeb2SMonk Liu */ 3972ce9dde0SMikko Rapeli __u64 handle; 398675da0ddSChristian König /** Absolute timeout to wait */ 3992ce9dde0SMikko Rapeli __u64 timeout; 4002ce9dde0SMikko Rapeli __u32 ip_type; 4012ce9dde0SMikko Rapeli __u32 ip_instance; 4022ce9dde0SMikko Rapeli __u32 ring; 4032ce9dde0SMikko Rapeli __u32 ctx_id; 40481629cbaSAlex Deucher }; 40581629cbaSAlex Deucher 40681629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out { 407675da0ddSChristian König /** CS status: 0 - CS completed, 1 - CS still busy */ 4082ce9dde0SMikko Rapeli __u64 status; 40981629cbaSAlex Deucher }; 41081629cbaSAlex Deucher 41181629cbaSAlex Deucher union drm_amdgpu_wait_cs { 41281629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in in; 41381629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out out; 41481629cbaSAlex Deucher }; 41581629cbaSAlex Deucher 416eef18a82SJunwei Zhang struct drm_amdgpu_fence { 417eef18a82SJunwei Zhang __u32 ctx_id; 418eef18a82SJunwei Zhang __u32 ip_type; 419eef18a82SJunwei Zhang __u32 ip_instance; 420eef18a82SJunwei Zhang __u32 ring; 421eef18a82SJunwei Zhang __u64 seq_no; 422eef18a82SJunwei Zhang }; 423eef18a82SJunwei Zhang 424eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in { 425eef18a82SJunwei Zhang /** This points to uint64_t * which points to fences */ 426eef18a82SJunwei Zhang __u64 fences; 427eef18a82SJunwei Zhang __u32 fence_count; 428eef18a82SJunwei Zhang __u32 wait_all; 429eef18a82SJunwei Zhang __u64 timeout_ns; 430eef18a82SJunwei Zhang }; 431eef18a82SJunwei Zhang 432eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out { 433eef18a82SJunwei Zhang __u32 status; 434eef18a82SJunwei Zhang __u32 first_signaled; 435eef18a82SJunwei Zhang }; 436eef18a82SJunwei Zhang 437eef18a82SJunwei Zhang union drm_amdgpu_wait_fences { 438eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in in; 439eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out out; 440eef18a82SJunwei Zhang }; 441eef18a82SJunwei Zhang 44281629cbaSAlex Deucher #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 443d8f65a23SMarek Olšák #define AMDGPU_GEM_OP_SET_PLACEMENT 1 44481629cbaSAlex Deucher 445675da0ddSChristian König /* Sets or returns a value associated with a buffer. */ 446675da0ddSChristian König struct drm_amdgpu_gem_op { 447675da0ddSChristian König /** GEM object handle */ 4482ce9dde0SMikko Rapeli __u32 handle; 449675da0ddSChristian König /** AMDGPU_GEM_OP_* */ 4502ce9dde0SMikko Rapeli __u32 op; 451675da0ddSChristian König /** Input or return value */ 4522ce9dde0SMikko Rapeli __u64 value; 453675da0ddSChristian König }; 454675da0ddSChristian König 45581629cbaSAlex Deucher #define AMDGPU_VA_OP_MAP 1 45681629cbaSAlex Deucher #define AMDGPU_VA_OP_UNMAP 2 457dc54d3d1SChristian König #define AMDGPU_VA_OP_CLEAR 3 45880f95c57SChristian König #define AMDGPU_VA_OP_REPLACE 4 45981629cbaSAlex Deucher 460fc220f65SChristian König /* Delay the page table update till the next CS */ 461fc220f65SChristian König #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 462fc220f65SChristian König 46381629cbaSAlex Deucher /* Mapping flags */ 46481629cbaSAlex Deucher /* readable mapping */ 46581629cbaSAlex Deucher #define AMDGPU_VM_PAGE_READABLE (1 << 1) 46681629cbaSAlex Deucher /* writable mapping */ 46781629cbaSAlex Deucher #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 46881629cbaSAlex Deucher /* executable mapping, new for VI */ 46981629cbaSAlex Deucher #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 470b85891bdSJunwei Zhang /* partially resident texture */ 471b85891bdSJunwei Zhang #define AMDGPU_VM_PAGE_PRT (1 << 4) 47266e02bc3SAlex Xie /* MTYPE flags use bit 5 to 8 */ 47366e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 47466e02bc3SAlex Xie /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 47566e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 47666e02bc3SAlex Xie /* Use NC MTYPE instead of default MTYPE */ 47766e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_NC (1 << 5) 47866e02bc3SAlex Xie /* Use WC MTYPE instead of default MTYPE */ 47966e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_WC (2 << 5) 48066e02bc3SAlex Xie /* Use CC MTYPE instead of default MTYPE */ 48166e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_CC (3 << 5) 48266e02bc3SAlex Xie /* Use UC MTYPE instead of default MTYPE */ 48366e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_UC (4 << 5) 48481629cbaSAlex Deucher 48534b5f6a6SChristian König struct drm_amdgpu_gem_va { 486675da0ddSChristian König /** GEM object handle */ 4872ce9dde0SMikko Rapeli __u32 handle; 4882ce9dde0SMikko Rapeli __u32 _pad; 489675da0ddSChristian König /** AMDGPU_VA_OP_* */ 4902ce9dde0SMikko Rapeli __u32 operation; 491675da0ddSChristian König /** AMDGPU_VM_PAGE_* */ 4922ce9dde0SMikko Rapeli __u32 flags; 493675da0ddSChristian König /** va address to assign . Must be correctly aligned.*/ 4942ce9dde0SMikko Rapeli __u64 va_address; 495675da0ddSChristian König /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 4962ce9dde0SMikko Rapeli __u64 offset_in_bo; 497675da0ddSChristian König /** Specify mapping size. Must be correctly aligned. */ 4982ce9dde0SMikko Rapeli __u64 map_size; 49981629cbaSAlex Deucher }; 50081629cbaSAlex Deucher 50181629cbaSAlex Deucher #define AMDGPU_HW_IP_GFX 0 50281629cbaSAlex Deucher #define AMDGPU_HW_IP_COMPUTE 1 50381629cbaSAlex Deucher #define AMDGPU_HW_IP_DMA 2 50481629cbaSAlex Deucher #define AMDGPU_HW_IP_UVD 3 50581629cbaSAlex Deucher #define AMDGPU_HW_IP_VCE 4 506a50798b6SLeo Liu #define AMDGPU_HW_IP_UVD_ENC 5 50766e236f1SLeo Liu #define AMDGPU_HW_IP_VCN_DEC 6 508fcfc5a90SLeo Liu #define AMDGPU_HW_IP_VCN_ENC 7 50981d35014SBoyuan Zhang #define AMDGPU_HW_IP_VCN_JPEG 8 51081d35014SBoyuan Zhang #define AMDGPU_HW_IP_NUM 9 51181629cbaSAlex Deucher 51281629cbaSAlex Deucher #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 51381629cbaSAlex Deucher 51481629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_IB 0x01 51581629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_FENCE 0x02 5162b48d323SChristian König #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 517660e8558SDave Airlie #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 518660e8558SDave Airlie #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 519964d0fbfSAndrey Grodzovsky #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 520675da0ddSChristian König 52181629cbaSAlex Deucher struct drm_amdgpu_cs_chunk { 5222ce9dde0SMikko Rapeli __u32 chunk_id; 5232ce9dde0SMikko Rapeli __u32 length_dw; 5242ce9dde0SMikko Rapeli __u64 chunk_data; 52581629cbaSAlex Deucher }; 52681629cbaSAlex Deucher 52781629cbaSAlex Deucher struct drm_amdgpu_cs_in { 52881629cbaSAlex Deucher /** Rendering context id */ 5292ce9dde0SMikko Rapeli __u32 ctx_id; 53081629cbaSAlex Deucher /** Handle of resource list associated with CS */ 5312ce9dde0SMikko Rapeli __u32 bo_list_handle; 5322ce9dde0SMikko Rapeli __u32 num_chunks; 5332ce9dde0SMikko Rapeli __u32 _pad; 5342ce9dde0SMikko Rapeli /** this points to __u64 * which point to cs chunks */ 5352ce9dde0SMikko Rapeli __u64 chunks; 53681629cbaSAlex Deucher }; 53781629cbaSAlex Deucher 53881629cbaSAlex Deucher struct drm_amdgpu_cs_out { 5392ce9dde0SMikko Rapeli __u64 handle; 54081629cbaSAlex Deucher }; 54181629cbaSAlex Deucher 54281629cbaSAlex Deucher union drm_amdgpu_cs { 54381629cbaSAlex Deucher struct drm_amdgpu_cs_in in; 54481629cbaSAlex Deucher struct drm_amdgpu_cs_out out; 54581629cbaSAlex Deucher }; 54681629cbaSAlex Deucher 54781629cbaSAlex Deucher /* Specify flags to be used for IB */ 54881629cbaSAlex Deucher 54981629cbaSAlex Deucher /* This IB should be submitted to CE */ 55081629cbaSAlex Deucher #define AMDGPU_IB_FLAG_CE (1<<0) 55181629cbaSAlex Deucher 552ed834af2SMonk Liu /* Preamble flag, which means the IB could be dropped if no context switch */ 553cab6d57cSJammy Zhou #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 554aa2bdb24SJammy Zhou 55571aec257SMonk Liu /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 55671aec257SMonk Liu #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 55771aec257SMonk Liu 558d240cd9eSMarek Olšák /* The IB fence should do the L2 writeback but not invalidate any shader 559d240cd9eSMarek Olšák * caches (L2/vL1/sL1/I$). */ 560d240cd9eSMarek Olšák #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 561d240cd9eSMarek Olšák 56281629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib { 5632ce9dde0SMikko Rapeli __u32 _pad; 564675da0ddSChristian König /** AMDGPU_IB_FLAG_* */ 5652ce9dde0SMikko Rapeli __u32 flags; 566675da0ddSChristian König /** Virtual address to begin IB execution */ 5672ce9dde0SMikko Rapeli __u64 va_start; 568675da0ddSChristian König /** Size of submission */ 5692ce9dde0SMikko Rapeli __u32 ib_bytes; 570675da0ddSChristian König /** HW IP to submit to */ 5712ce9dde0SMikko Rapeli __u32 ip_type; 572675da0ddSChristian König /** HW IP index of the same type to submit to */ 5732ce9dde0SMikko Rapeli __u32 ip_instance; 574675da0ddSChristian König /** Ring index to submit to */ 5752ce9dde0SMikko Rapeli __u32 ring; 57681629cbaSAlex Deucher }; 57781629cbaSAlex Deucher 5782b48d323SChristian König struct drm_amdgpu_cs_chunk_dep { 5792ce9dde0SMikko Rapeli __u32 ip_type; 5802ce9dde0SMikko Rapeli __u32 ip_instance; 5812ce9dde0SMikko Rapeli __u32 ring; 5822ce9dde0SMikko Rapeli __u32 ctx_id; 5832ce9dde0SMikko Rapeli __u64 handle; 5842b48d323SChristian König }; 5852b48d323SChristian König 58681629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence { 5872ce9dde0SMikko Rapeli __u32 handle; 5882ce9dde0SMikko Rapeli __u32 offset; 58981629cbaSAlex Deucher }; 59081629cbaSAlex Deucher 591660e8558SDave Airlie struct drm_amdgpu_cs_chunk_sem { 592660e8558SDave Airlie __u32 handle; 593660e8558SDave Airlie }; 594660e8558SDave Airlie 5957ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 5967ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 5977ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 5987ca24cf2SMarek Olšák 5997ca24cf2SMarek Olšák union drm_amdgpu_fence_to_handle { 6007ca24cf2SMarek Olšák struct { 6017ca24cf2SMarek Olšák struct drm_amdgpu_fence fence; 6027ca24cf2SMarek Olšák __u32 what; 60356e0349fSDave Airlie __u32 pad; 6047ca24cf2SMarek Olšák } in; 6057ca24cf2SMarek Olšák struct { 6067ca24cf2SMarek Olšák __u32 handle; 6077ca24cf2SMarek Olšák } out; 6087ca24cf2SMarek Olšák }; 6097ca24cf2SMarek Olšák 61081629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_data { 61181629cbaSAlex Deucher union { 61281629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib ib_data; 61381629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence fence_data; 61481629cbaSAlex Deucher }; 61581629cbaSAlex Deucher }; 61681629cbaSAlex Deucher 61781629cbaSAlex Deucher /** 61881629cbaSAlex Deucher * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 61981629cbaSAlex Deucher * 62081629cbaSAlex Deucher */ 62181629cbaSAlex Deucher #define AMDGPU_IDS_FLAGS_FUSION 0x1 622aafcafa0SMonk Liu #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 62381629cbaSAlex Deucher 62481629cbaSAlex Deucher /* indicate if acceleration can be working */ 62581629cbaSAlex Deucher #define AMDGPU_INFO_ACCEL_WORKING 0x00 62681629cbaSAlex Deucher /* get the crtc_id from the mode object id? */ 62781629cbaSAlex Deucher #define AMDGPU_INFO_CRTC_FROM_ID 0x01 62881629cbaSAlex Deucher /* query hw IP info */ 62981629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_INFO 0x02 63081629cbaSAlex Deucher /* query hw IP instance count for the specified type */ 63181629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_COUNT 0x03 63281629cbaSAlex Deucher /* timestamp for GL_ARB_timer_query */ 63381629cbaSAlex Deucher #define AMDGPU_INFO_TIMESTAMP 0x05 63481629cbaSAlex Deucher /* Query the firmware version */ 63581629cbaSAlex Deucher #define AMDGPU_INFO_FW_VERSION 0x0e 63681629cbaSAlex Deucher /* Subquery id: Query VCE firmware version */ 63781629cbaSAlex Deucher #define AMDGPU_INFO_FW_VCE 0x1 63881629cbaSAlex Deucher /* Subquery id: Query UVD firmware version */ 63981629cbaSAlex Deucher #define AMDGPU_INFO_FW_UVD 0x2 64081629cbaSAlex Deucher /* Subquery id: Query GMC firmware version */ 64181629cbaSAlex Deucher #define AMDGPU_INFO_FW_GMC 0x03 64281629cbaSAlex Deucher /* Subquery id: Query GFX ME firmware version */ 64381629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_ME 0x04 64481629cbaSAlex Deucher /* Subquery id: Query GFX PFP firmware version */ 64581629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_PFP 0x05 64681629cbaSAlex Deucher /* Subquery id: Query GFX CE firmware version */ 64781629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_CE 0x06 64881629cbaSAlex Deucher /* Subquery id: Query GFX RLC firmware version */ 64981629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_RLC 0x07 65081629cbaSAlex Deucher /* Subquery id: Query GFX MEC firmware version */ 65181629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_MEC 0x08 65281629cbaSAlex Deucher /* Subquery id: Query SMC firmware version */ 65381629cbaSAlex Deucher #define AMDGPU_INFO_FW_SMC 0x0a 65481629cbaSAlex Deucher /* Subquery id: Query SDMA firmware version */ 65581629cbaSAlex Deucher #define AMDGPU_INFO_FW_SDMA 0x0b 6566a7ed07eSHuang Rui /* Subquery id: Query PSP SOS firmware version */ 6576a7ed07eSHuang Rui #define AMDGPU_INFO_FW_SOS 0x0c 6586a7ed07eSHuang Rui /* Subquery id: Query PSP ASD firmware version */ 6596a7ed07eSHuang Rui #define AMDGPU_INFO_FW_ASD 0x0d 6603ac952b1SAlex Deucher /* Subquery id: Query VCN firmware version */ 6613ac952b1SAlex Deucher #define AMDGPU_INFO_FW_VCN 0x0e 662621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLC firmware version */ 663621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 664621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLG firmware version */ 665621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 666621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLS firmware version */ 667621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 66881629cbaSAlex Deucher /* number of bytes moved for TTM migration */ 66981629cbaSAlex Deucher #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 67081629cbaSAlex Deucher /* the used VRAM size */ 67181629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_USAGE 0x10 67281629cbaSAlex Deucher /* the used GTT size */ 67381629cbaSAlex Deucher #define AMDGPU_INFO_GTT_USAGE 0x11 67481629cbaSAlex Deucher /* Information about GDS, etc. resource configuration */ 67581629cbaSAlex Deucher #define AMDGPU_INFO_GDS_CONFIG 0x13 67681629cbaSAlex Deucher /* Query information about VRAM and GTT domains */ 67781629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_GTT 0x14 67881629cbaSAlex Deucher /* Query information about register in MMR address space*/ 67981629cbaSAlex Deucher #define AMDGPU_INFO_READ_MMR_REG 0x15 68081629cbaSAlex Deucher /* Query information about device: rev id, family, etc. */ 68181629cbaSAlex Deucher #define AMDGPU_INFO_DEV_INFO 0x16 68281629cbaSAlex Deucher /* visible vram usage */ 68381629cbaSAlex Deucher #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 68483a59b63SMarek Olšák /* number of TTM buffer evictions */ 68583a59b63SMarek Olšák #define AMDGPU_INFO_NUM_EVICTIONS 0x18 686e0adf6c8SJunwei Zhang /* Query memory about VRAM and GTT domains */ 687e0adf6c8SJunwei Zhang #define AMDGPU_INFO_MEMORY 0x19 688bbe87974SAlex Deucher /* Query vce clock table */ 689bbe87974SAlex Deucher #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 69040ee5888SEvan Quan /* Query vbios related information */ 69140ee5888SEvan Quan #define AMDGPU_INFO_VBIOS 0x1B 69240ee5888SEvan Quan /* Subquery id: Query vbios size */ 69340ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_SIZE 0x1 69440ee5888SEvan Quan /* Subquery id: Query vbios image */ 69540ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_IMAGE 0x2 69644879b62SArindam Nath /* Query UVD handles */ 69744879b62SArindam Nath #define AMDGPU_INFO_NUM_HANDLES 0x1C 6985ebbac4bSAlex Deucher /* Query sensor related information */ 6995ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR 0x1D 7005ebbac4bSAlex Deucher /* Subquery id: Query GPU shader clock */ 7015ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 7025ebbac4bSAlex Deucher /* Subquery id: Query GPU memory clock */ 7035ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 7045ebbac4bSAlex Deucher /* Subquery id: Query GPU temperature */ 7055ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 7065ebbac4bSAlex Deucher /* Subquery id: Query GPU load */ 7075ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 7085ebbac4bSAlex Deucher /* Subquery id: Query average GPU power */ 7095ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 7105ebbac4bSAlex Deucher /* Subquery id: Query northbridge voltage */ 7115ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDNB 0x6 7125ebbac4bSAlex Deucher /* Subquery id: Query graphics voltage */ 7135ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 71460bbade2SRex Zhu /* Subquery id: Query GPU stable pstate shader clock */ 71560bbade2SRex Zhu #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 71660bbade2SRex Zhu /* Subquery id: Query GPU stable pstate memory clock */ 71760bbade2SRex Zhu #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 71868e2c5ffSMarek Olšák /* Number of VRAM page faults on CPU access. */ 71968e2c5ffSMarek Olšák #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 7201f7251b7SChristian König #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 72181629cbaSAlex Deucher 72281629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 72381629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 72481629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 72581629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 72681629cbaSAlex Deucher 727000cab9aSHuang Rui struct drm_amdgpu_query_fw { 728000cab9aSHuang Rui /** AMDGPU_INFO_FW_* */ 729000cab9aSHuang Rui __u32 fw_type; 730000cab9aSHuang Rui /** 731000cab9aSHuang Rui * Index of the IP if there are more IPs of 732000cab9aSHuang Rui * the same type. 733000cab9aSHuang Rui */ 734000cab9aSHuang Rui __u32 ip_instance; 735000cab9aSHuang Rui /** 736000cab9aSHuang Rui * Index of the engine. Whether this is used depends 737000cab9aSHuang Rui * on the firmware type. (e.g. MEC, SDMA) 738000cab9aSHuang Rui */ 739000cab9aSHuang Rui __u32 index; 740000cab9aSHuang Rui __u32 _pad; 741000cab9aSHuang Rui }; 742000cab9aSHuang Rui 74381629cbaSAlex Deucher /* Input structure for the INFO ioctl */ 74481629cbaSAlex Deucher struct drm_amdgpu_info { 74581629cbaSAlex Deucher /* Where the return value will be stored */ 7462ce9dde0SMikko Rapeli __u64 return_pointer; 74781629cbaSAlex Deucher /* The size of the return value. Just like "size" in "snprintf", 74881629cbaSAlex Deucher * it limits how many bytes the kernel can write. */ 7492ce9dde0SMikko Rapeli __u32 return_size; 75081629cbaSAlex Deucher /* The query request id. */ 7512ce9dde0SMikko Rapeli __u32 query; 75281629cbaSAlex Deucher 75381629cbaSAlex Deucher union { 75481629cbaSAlex Deucher struct { 7552ce9dde0SMikko Rapeli __u32 id; 7562ce9dde0SMikko Rapeli __u32 _pad; 75781629cbaSAlex Deucher } mode_crtc; 75881629cbaSAlex Deucher 75981629cbaSAlex Deucher struct { 76081629cbaSAlex Deucher /** AMDGPU_HW_IP_* */ 7612ce9dde0SMikko Rapeli __u32 type; 76281629cbaSAlex Deucher /** 763675da0ddSChristian König * Index of the IP if there are more IPs of the same 764675da0ddSChristian König * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 76581629cbaSAlex Deucher */ 7662ce9dde0SMikko Rapeli __u32 ip_instance; 76781629cbaSAlex Deucher } query_hw_ip; 76881629cbaSAlex Deucher 76981629cbaSAlex Deucher struct { 7702ce9dde0SMikko Rapeli __u32 dword_offset; 771675da0ddSChristian König /** number of registers to read */ 7722ce9dde0SMikko Rapeli __u32 count; 7732ce9dde0SMikko Rapeli __u32 instance; 774675da0ddSChristian König /** For future use, no flags defined so far */ 7752ce9dde0SMikko Rapeli __u32 flags; 77681629cbaSAlex Deucher } read_mmr_reg; 77781629cbaSAlex Deucher 778000cab9aSHuang Rui struct drm_amdgpu_query_fw query_fw; 77940ee5888SEvan Quan 78040ee5888SEvan Quan struct { 78140ee5888SEvan Quan __u32 type; 78240ee5888SEvan Quan __u32 offset; 78340ee5888SEvan Quan } vbios_info; 7845ebbac4bSAlex Deucher 7855ebbac4bSAlex Deucher struct { 7865ebbac4bSAlex Deucher __u32 type; 7875ebbac4bSAlex Deucher } sensor_info; 78881629cbaSAlex Deucher }; 78981629cbaSAlex Deucher }; 79081629cbaSAlex Deucher 79181629cbaSAlex Deucher struct drm_amdgpu_info_gds { 79281629cbaSAlex Deucher /** GDS GFX partition size */ 7932ce9dde0SMikko Rapeli __u32 gds_gfx_partition_size; 79481629cbaSAlex Deucher /** GDS compute partition size */ 7952ce9dde0SMikko Rapeli __u32 compute_partition_size; 79681629cbaSAlex Deucher /** total GDS memory size */ 7972ce9dde0SMikko Rapeli __u32 gds_total_size; 79881629cbaSAlex Deucher /** GWS size per GFX partition */ 7992ce9dde0SMikko Rapeli __u32 gws_per_gfx_partition; 80081629cbaSAlex Deucher /** GSW size per compute partition */ 8012ce9dde0SMikko Rapeli __u32 gws_per_compute_partition; 80281629cbaSAlex Deucher /** OA size per GFX partition */ 8032ce9dde0SMikko Rapeli __u32 oa_per_gfx_partition; 80481629cbaSAlex Deucher /** OA size per compute partition */ 8052ce9dde0SMikko Rapeli __u32 oa_per_compute_partition; 8062ce9dde0SMikko Rapeli __u32 _pad; 80781629cbaSAlex Deucher }; 80881629cbaSAlex Deucher 80981629cbaSAlex Deucher struct drm_amdgpu_info_vram_gtt { 8102ce9dde0SMikko Rapeli __u64 vram_size; 8112ce9dde0SMikko Rapeli __u64 vram_cpu_accessible_size; 8122ce9dde0SMikko Rapeli __u64 gtt_size; 81381629cbaSAlex Deucher }; 81481629cbaSAlex Deucher 815e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info { 816e0adf6c8SJunwei Zhang /** max. physical memory */ 817e0adf6c8SJunwei Zhang __u64 total_heap_size; 818e0adf6c8SJunwei Zhang 819e0adf6c8SJunwei Zhang /** Theoretical max. available memory in the given heap */ 820e0adf6c8SJunwei Zhang __u64 usable_heap_size; 821e0adf6c8SJunwei Zhang 822e0adf6c8SJunwei Zhang /** 823e0adf6c8SJunwei Zhang * Number of bytes allocated in the heap. This includes all processes 824e0adf6c8SJunwei Zhang * and private allocations in the kernel. It changes when new buffers 825e0adf6c8SJunwei Zhang * are allocated, freed, and moved. It cannot be larger than 826e0adf6c8SJunwei Zhang * heap_size. 827e0adf6c8SJunwei Zhang */ 828e0adf6c8SJunwei Zhang __u64 heap_usage; 829e0adf6c8SJunwei Zhang 830e0adf6c8SJunwei Zhang /** 831e0adf6c8SJunwei Zhang * Theoretical possible max. size of buffer which 832e0adf6c8SJunwei Zhang * could be allocated in the given heap 833e0adf6c8SJunwei Zhang */ 834e0adf6c8SJunwei Zhang __u64 max_allocation; 8359f6163e7SJunwei Zhang }; 8369f6163e7SJunwei Zhang 837e0adf6c8SJunwei Zhang struct drm_amdgpu_memory_info { 838e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info vram; 839e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info cpu_accessible_vram; 840e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info gtt; 841cfa32556SJunwei Zhang }; 842cfa32556SJunwei Zhang 84381629cbaSAlex Deucher struct drm_amdgpu_info_firmware { 8442ce9dde0SMikko Rapeli __u32 ver; 8452ce9dde0SMikko Rapeli __u32 feature; 84681629cbaSAlex Deucher }; 84781629cbaSAlex Deucher 84881c59f54SKen Wang #define AMDGPU_VRAM_TYPE_UNKNOWN 0 84981c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR1 1 85081c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR2 2 85181c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR3 3 85281c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR4 4 85381c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR5 5 85481c59f54SKen Wang #define AMDGPU_VRAM_TYPE_HBM 6 85581c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR3 7 8561e09b053SHawking Zhang #define AMDGPU_VRAM_TYPE_DDR4 8 85781c59f54SKen Wang 85881629cbaSAlex Deucher struct drm_amdgpu_info_device { 85981629cbaSAlex Deucher /** PCI Device ID */ 8602ce9dde0SMikko Rapeli __u32 device_id; 86181629cbaSAlex Deucher /** Internal chip revision: A0, A1, etc.) */ 8622ce9dde0SMikko Rapeli __u32 chip_rev; 8632ce9dde0SMikko Rapeli __u32 external_rev; 86481629cbaSAlex Deucher /** Revision id in PCI Config space */ 8652ce9dde0SMikko Rapeli __u32 pci_rev; 8662ce9dde0SMikko Rapeli __u32 family; 8672ce9dde0SMikko Rapeli __u32 num_shader_engines; 8682ce9dde0SMikko Rapeli __u32 num_shader_arrays_per_engine; 869675da0ddSChristian König /* in KHz */ 8702ce9dde0SMikko Rapeli __u32 gpu_counter_freq; 8712ce9dde0SMikko Rapeli __u64 max_engine_clock; 8722ce9dde0SMikko Rapeli __u64 max_memory_clock; 87381629cbaSAlex Deucher /* cu information */ 8742ce9dde0SMikko Rapeli __u32 cu_active_number; 875dbfe85eaSFlora Cui /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 8762ce9dde0SMikko Rapeli __u32 cu_ao_mask; 8772ce9dde0SMikko Rapeli __u32 cu_bitmap[4][4]; 87881629cbaSAlex Deucher /** Render backend pipe mask. One render backend is CB+DB. */ 8792ce9dde0SMikko Rapeli __u32 enabled_rb_pipes_mask; 8802ce9dde0SMikko Rapeli __u32 num_rb_pipes; 8812ce9dde0SMikko Rapeli __u32 num_hw_gfx_contexts; 8822ce9dde0SMikko Rapeli __u32 _pad; 8832ce9dde0SMikko Rapeli __u64 ids_flags; 88481629cbaSAlex Deucher /** Starting virtual address for UMDs. */ 8852ce9dde0SMikko Rapeli __u64 virtual_address_offset; 88602b70c8cSJammy Zhou /** The maximum virtual address */ 8872ce9dde0SMikko Rapeli __u64 virtual_address_max; 88881629cbaSAlex Deucher /** Required alignment of virtual addresses. */ 8892ce9dde0SMikko Rapeli __u32 virtual_address_alignment; 89081629cbaSAlex Deucher /** Page table entry - fragment size */ 8912ce9dde0SMikko Rapeli __u32 pte_fragment_size; 8922ce9dde0SMikko Rapeli __u32 gart_page_size; 893a101a899SKen Wang /** constant engine ram size*/ 8942ce9dde0SMikko Rapeli __u32 ce_ram_size; 895cab6d57cSJammy Zhou /** video memory type info*/ 8962ce9dde0SMikko Rapeli __u32 vram_type; 89781c59f54SKen Wang /** video memory bit width*/ 8982ce9dde0SMikko Rapeli __u32 vram_bit_width; 899fa92754eSLeo Liu /* vce harvesting instance */ 9002ce9dde0SMikko Rapeli __u32 vce_harvest_config; 901df6e2c4aSJunwei Zhang /* gfx double offchip LDS buffers */ 902df6e2c4aSJunwei Zhang __u32 gc_double_offchip_lds_buf; 903bce23e00SAlex Deucher /* NGG Primitive Buffer */ 904bce23e00SAlex Deucher __u64 prim_buf_gpu_addr; 905bce23e00SAlex Deucher /* NGG Position Buffer */ 906bce23e00SAlex Deucher __u64 pos_buf_gpu_addr; 907bce23e00SAlex Deucher /* NGG Control Sideband */ 908bce23e00SAlex Deucher __u64 cntl_sb_buf_gpu_addr; 909bce23e00SAlex Deucher /* NGG Parameter Cache */ 910bce23e00SAlex Deucher __u64 param_buf_gpu_addr; 911408bfe7cSJunwei Zhang __u32 prim_buf_size; 912408bfe7cSJunwei Zhang __u32 pos_buf_size; 913408bfe7cSJunwei Zhang __u32 cntl_sb_buf_size; 914408bfe7cSJunwei Zhang __u32 param_buf_size; 915408bfe7cSJunwei Zhang /* wavefront size*/ 916408bfe7cSJunwei Zhang __u32 wave_front_size; 917408bfe7cSJunwei Zhang /* shader visible vgprs*/ 918408bfe7cSJunwei Zhang __u32 num_shader_visible_vgprs; 919408bfe7cSJunwei Zhang /* CU per shader array*/ 920408bfe7cSJunwei Zhang __u32 num_cu_per_sh; 921408bfe7cSJunwei Zhang /* number of tcc blocks*/ 922408bfe7cSJunwei Zhang __u32 num_tcc_blocks; 923408bfe7cSJunwei Zhang /* gs vgt table depth*/ 924408bfe7cSJunwei Zhang __u32 gs_vgt_table_depth; 925408bfe7cSJunwei Zhang /* gs primitive buffer depth*/ 926408bfe7cSJunwei Zhang __u32 gs_prim_buffer_depth; 927408bfe7cSJunwei Zhang /* max gs wavefront per vgt*/ 928408bfe7cSJunwei Zhang __u32 max_gs_waves_per_vgt; 929408bfe7cSJunwei Zhang __u32 _pad1; 930dbfe85eaSFlora Cui /* always on cu bitmap */ 931dbfe85eaSFlora Cui __u32 cu_ao_bitmap[4][4]; 9325b565e0eSChristian König /** Starting high virtual address for UMDs. */ 9335b565e0eSChristian König __u64 high_va_offset; 9345b565e0eSChristian König /** The maximum high virtual address */ 9355b565e0eSChristian König __u64 high_va_max; 93681629cbaSAlex Deucher }; 93781629cbaSAlex Deucher 93881629cbaSAlex Deucher struct drm_amdgpu_info_hw_ip { 93981629cbaSAlex Deucher /** Version of h/w IP */ 9402ce9dde0SMikko Rapeli __u32 hw_ip_version_major; 9412ce9dde0SMikko Rapeli __u32 hw_ip_version_minor; 94281629cbaSAlex Deucher /** Capabilities */ 9432ce9dde0SMikko Rapeli __u64 capabilities_flags; 94471062f43SKen Wang /** command buffer address start alignment*/ 9452ce9dde0SMikko Rapeli __u32 ib_start_alignment; 94671062f43SKen Wang /** command buffer size alignment*/ 9472ce9dde0SMikko Rapeli __u32 ib_size_alignment; 94881629cbaSAlex Deucher /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 9492ce9dde0SMikko Rapeli __u32 available_rings; 9502ce9dde0SMikko Rapeli __u32 _pad; 95181629cbaSAlex Deucher }; 95281629cbaSAlex Deucher 95344879b62SArindam Nath struct drm_amdgpu_info_num_handles { 95444879b62SArindam Nath /** Max handles as supported by firmware for UVD */ 95544879b62SArindam Nath __u32 uvd_max_handles; 95644879b62SArindam Nath /** Handles currently in use for UVD */ 95744879b62SArindam Nath __u32 uvd_used_handles; 95844879b62SArindam Nath }; 95944879b62SArindam Nath 960bbe87974SAlex Deucher #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 961bbe87974SAlex Deucher 962bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry { 963bbe87974SAlex Deucher /** System clock */ 964bbe87974SAlex Deucher __u32 sclk; 965bbe87974SAlex Deucher /** Memory clock */ 966bbe87974SAlex Deucher __u32 mclk; 967bbe87974SAlex Deucher /** VCE clock */ 968bbe87974SAlex Deucher __u32 eclk; 969bbe87974SAlex Deucher __u32 pad; 970bbe87974SAlex Deucher }; 971bbe87974SAlex Deucher 972bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table { 973bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 974bbe87974SAlex Deucher __u32 num_valid_entries; 975bbe87974SAlex Deucher __u32 pad; 976bbe87974SAlex Deucher }; 977bbe87974SAlex Deucher 97881629cbaSAlex Deucher /* 97981629cbaSAlex Deucher * Supported GPU families 98081629cbaSAlex Deucher */ 98181629cbaSAlex Deucher #define AMDGPU_FAMILY_UNKNOWN 0 982295d0dafSKen Wang #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 98381629cbaSAlex Deucher #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 98481629cbaSAlex Deucher #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 98581629cbaSAlex Deucher #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 98639bb0c92SSamuel Li #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 987a8f1f1ceSAlex Deucher #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 9882ca8a5d2SChunming Zhou #define AMDGPU_FAMILY_RV 142 /* Raven */ 98981629cbaSAlex Deucher 990cfa7152fSEmil Velikov #if defined(__cplusplus) 991cfa7152fSEmil Velikov } 992cfa7152fSEmil Velikov #endif 993cfa7152fSEmil Velikov 99481629cbaSAlex Deucher #endif 995