181629cbaSAlex Deucher /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 281629cbaSAlex Deucher * 381629cbaSAlex Deucher * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 481629cbaSAlex Deucher * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 581629cbaSAlex Deucher * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 681629cbaSAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 781629cbaSAlex Deucher * 881629cbaSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 981629cbaSAlex Deucher * copy of this software and associated documentation files (the "Software"), 1081629cbaSAlex Deucher * to deal in the Software without restriction, including without limitation 1181629cbaSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1281629cbaSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1381629cbaSAlex Deucher * Software is furnished to do so, subject to the following conditions: 1481629cbaSAlex Deucher * 1581629cbaSAlex Deucher * The above copyright notice and this permission notice shall be included in 1681629cbaSAlex Deucher * all copies or substantial portions of the Software. 1781629cbaSAlex Deucher * 1881629cbaSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1981629cbaSAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2081629cbaSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2181629cbaSAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2281629cbaSAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2381629cbaSAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2481629cbaSAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2581629cbaSAlex Deucher * 2681629cbaSAlex Deucher * Authors: 2781629cbaSAlex Deucher * Kevin E. Martin <martin@valinux.com> 2881629cbaSAlex Deucher * Gareth Hughes <gareth@valinux.com> 2981629cbaSAlex Deucher * Keith Whitwell <keith@tungstengraphics.com> 3081629cbaSAlex Deucher */ 3181629cbaSAlex Deucher 3281629cbaSAlex Deucher #ifndef __AMDGPU_DRM_H__ 3381629cbaSAlex Deucher #define __AMDGPU_DRM_H__ 3481629cbaSAlex Deucher 35b3fcf36aSMichel Dänzer #include "drm.h" 3681629cbaSAlex Deucher 37cfa7152fSEmil Velikov #if defined(__cplusplus) 38cfa7152fSEmil Velikov extern "C" { 39cfa7152fSEmil Velikov #endif 40cfa7152fSEmil Velikov 4181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_CREATE 0x00 4281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_MMAP 0x01 4381629cbaSAlex Deucher #define DRM_AMDGPU_CTX 0x02 4481629cbaSAlex Deucher #define DRM_AMDGPU_BO_LIST 0x03 4581629cbaSAlex Deucher #define DRM_AMDGPU_CS 0x04 4681629cbaSAlex Deucher #define DRM_AMDGPU_INFO 0x05 4781629cbaSAlex Deucher #define DRM_AMDGPU_GEM_METADATA 0x06 4881629cbaSAlex Deucher #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 4981629cbaSAlex Deucher #define DRM_AMDGPU_GEM_VA 0x08 5081629cbaSAlex Deucher #define DRM_AMDGPU_WAIT_CS 0x09 5181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_OP 0x10 5281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_USERPTR 0x11 53eef18a82SJunwei Zhang #define DRM_AMDGPU_WAIT_FENCES 0x12 54cfbcacf4SChunming Zhou #define DRM_AMDGPU_VM 0x13 557ca24cf2SMarek Olšák #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 5652c6a62cSAndres Rodriguez #define DRM_AMDGPU_SCHED 0x15 5781629cbaSAlex Deucher 5881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 5981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 6081629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 6181629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 6281629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 6381629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 6481629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 6581629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 6634b5f6a6SChristian König #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 6781629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 6881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 6981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70eef18a82SJunwei Zhang #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71cfbcacf4SChunming Zhou #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 727ca24cf2SMarek Olšák #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 7352c6a62cSAndres Rodriguez #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 7481629cbaSAlex Deucher 75b646c1dcSSamuel Li /** 76b646c1dcSSamuel Li * DOC: memory domains 77b646c1dcSSamuel Li * 78b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79b646c1dcSSamuel Li * Memory in this pool could be swapped out to disk if there is pressure. 80b646c1dcSSamuel Li * 81b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82b646c1dcSSamuel Li * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83326db0dcSYann Dirson * pages of system memory, allows GPU access system memory in a linearized 84b646c1dcSSamuel Li * fashion. 85b646c1dcSSamuel Li * 86b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87b646c1dcSSamuel Li * carved out by the BIOS. 88b646c1dcSSamuel Li * 89b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90b646c1dcSSamuel Li * across shader threads. 91b646c1dcSSamuel Li * 92b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93b646c1dcSSamuel Li * execution of all the waves on a device. 94b646c1dcSSamuel Li * 95b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96b646c1dcSSamuel Li * for appending data. 97b646c1dcSSamuel Li */ 9881629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_CPU 0x1 9981629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GTT 0x2 10081629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_VRAM 0x4 10181629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GDS 0x8 10281629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GWS 0x10 10381629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_OA 0x20 1043f188453SChunming Zhou #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 1053f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GTT | \ 1063f188453SChunming Zhou AMDGPU_GEM_DOMAIN_VRAM | \ 1073f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GDS | \ 1083f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GWS | \ 1093f188453SChunming Zhou AMDGPU_GEM_DOMAIN_OA) 11081629cbaSAlex Deucher 11181629cbaSAlex Deucher /* Flag that CPU access will be required for the case of VRAM domain */ 11281629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 11381629cbaSAlex Deucher /* Flag that CPU access will not work, this VRAM domain is invisible */ 11481629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 11581629cbaSAlex Deucher /* Flag that USWC attributes should be used for GTT */ 11688671288SJammy Zhou #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 1174fea83ffSFlora Cui /* Flag that the memory should be in VRAM and cleared */ 1184fea83ffSFlora Cui #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 11903f48dd5SChristian König /* Flag that allocating the BO should use linear VRAM */ 12003f48dd5SChristian König #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 121e1eb899bSChristian König /* Flag that BO is always valid in this VM */ 122e1eb899bSChristian König #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 123177ae09bSAndres Rodriguez /* Flag that BO sharing will be explicitly synchronized */ 124177ae09bSAndres Rodriguez #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 125959a2091SYong Zhao /* Flag that indicates allocating MQD gart on GFX9, where the mtype 126fa5bde80SYong Zhao * for the second page onward should be set to NC. It should never 127fa5bde80SYong Zhao * be used by user space applications. 128959a2091SYong Zhao */ 129fa5bde80SYong Zhao #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 130d8f4981eSFelix Kuehling /* Flag that BO may contain sensitive data that must be wiped before 131d8f4981eSFelix Kuehling * releasing the memory 132d8f4981eSFelix Kuehling */ 133d8f4981eSFelix Kuehling #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 13435ce0060SAlex Deucher /* Flag that BO will be encrypted and that the TMZ bit should be 13535ce0060SAlex Deucher * set in the PTEs when mapping this buffer via GPUVM or 13635ce0060SAlex Deucher * accessing it with various hw blocks 13735ce0060SAlex Deucher */ 13835ce0060SAlex Deucher #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 139b453e42aSFelix Kuehling /* Flag that BO will be used only in preemptible context, which does 140b453e42aSFelix Kuehling * not require GTT memory accounting 141b453e42aSFelix Kuehling */ 142b453e42aSFelix Kuehling #define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11) 143fab2cc83SChristian König /* Flag that BO can be discarded under memory pressure without keeping the 144fab2cc83SChristian König * content. 145fab2cc83SChristian König */ 146fab2cc83SChristian König #define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12) 14781629cbaSAlex Deucher 14881629cbaSAlex Deucher struct drm_amdgpu_gem_create_in { 14981629cbaSAlex Deucher /** the requested memory size */ 1502ce9dde0SMikko Rapeli __u64 bo_size; 15181629cbaSAlex Deucher /** physical start_addr alignment in bytes for some HW requirements */ 1522ce9dde0SMikko Rapeli __u64 alignment; 15381629cbaSAlex Deucher /** the requested memory domains */ 1542ce9dde0SMikko Rapeli __u64 domains; 15581629cbaSAlex Deucher /** allocation flags */ 1562ce9dde0SMikko Rapeli __u64 domain_flags; 15781629cbaSAlex Deucher }; 15881629cbaSAlex Deucher 15981629cbaSAlex Deucher struct drm_amdgpu_gem_create_out { 16081629cbaSAlex Deucher /** returned GEM object handle */ 1612ce9dde0SMikko Rapeli __u32 handle; 1622ce9dde0SMikko Rapeli __u32 _pad; 16381629cbaSAlex Deucher }; 16481629cbaSAlex Deucher 16581629cbaSAlex Deucher union drm_amdgpu_gem_create { 16681629cbaSAlex Deucher struct drm_amdgpu_gem_create_in in; 16781629cbaSAlex Deucher struct drm_amdgpu_gem_create_out out; 16881629cbaSAlex Deucher }; 16981629cbaSAlex Deucher 17081629cbaSAlex Deucher /** Opcode to create new residency list. */ 17181629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_CREATE 0 17281629cbaSAlex Deucher /** Opcode to destroy previously created residency list */ 17381629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_DESTROY 1 17481629cbaSAlex Deucher /** Opcode to update resource information in the list */ 17581629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_UPDATE 2 17681629cbaSAlex Deucher 17781629cbaSAlex Deucher struct drm_amdgpu_bo_list_in { 17881629cbaSAlex Deucher /** Type of operation */ 1792ce9dde0SMikko Rapeli __u32 operation; 18081629cbaSAlex Deucher /** Handle of list or 0 if we want to create one */ 1812ce9dde0SMikko Rapeli __u32 list_handle; 18281629cbaSAlex Deucher /** Number of BOs in list */ 1832ce9dde0SMikko Rapeli __u32 bo_number; 18481629cbaSAlex Deucher /** Size of each element describing BO */ 1852ce9dde0SMikko Rapeli __u32 bo_info_size; 18681629cbaSAlex Deucher /** Pointer to array describing BOs */ 1872ce9dde0SMikko Rapeli __u64 bo_info_ptr; 18881629cbaSAlex Deucher }; 18981629cbaSAlex Deucher 19081629cbaSAlex Deucher struct drm_amdgpu_bo_list_entry { 19181629cbaSAlex Deucher /** Handle of BO */ 1922ce9dde0SMikko Rapeli __u32 bo_handle; 19381629cbaSAlex Deucher /** New (if specified) BO priority to be used during migration */ 1942ce9dde0SMikko Rapeli __u32 bo_priority; 19581629cbaSAlex Deucher }; 19681629cbaSAlex Deucher 19781629cbaSAlex Deucher struct drm_amdgpu_bo_list_out { 19881629cbaSAlex Deucher /** Handle of resource list */ 1992ce9dde0SMikko Rapeli __u32 list_handle; 2002ce9dde0SMikko Rapeli __u32 _pad; 20181629cbaSAlex Deucher }; 20281629cbaSAlex Deucher 20381629cbaSAlex Deucher union drm_amdgpu_bo_list { 20481629cbaSAlex Deucher struct drm_amdgpu_bo_list_in in; 20581629cbaSAlex Deucher struct drm_amdgpu_bo_list_out out; 20681629cbaSAlex Deucher }; 20781629cbaSAlex Deucher 20881629cbaSAlex Deucher /* context related */ 20981629cbaSAlex Deucher #define AMDGPU_CTX_OP_ALLOC_CTX 1 21081629cbaSAlex Deucher #define AMDGPU_CTX_OP_FREE_CTX 2 21181629cbaSAlex Deucher #define AMDGPU_CTX_OP_QUERY_STATE 3 212bc1b1bf6SMonk Liu #define AMDGPU_CTX_OP_QUERY_STATE2 4 2138cda7a4fSAlex Deucher #define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5 2148cda7a4fSAlex Deucher #define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6 21581629cbaSAlex Deucher 216d94aed5aSMarek Olšák /* GPU reset status */ 217d94aed5aSMarek Olšák #define AMDGPU_CTX_NO_RESET 0 218675da0ddSChristian König /* this the context caused it */ 219675da0ddSChristian König #define AMDGPU_CTX_GUILTY_RESET 1 220675da0ddSChristian König /* some other context caused it */ 221675da0ddSChristian König #define AMDGPU_CTX_INNOCENT_RESET 2 222675da0ddSChristian König /* unknown cause */ 223675da0ddSChristian König #define AMDGPU_CTX_UNKNOWN_RESET 3 224d94aed5aSMarek Olšák 225bc1b1bf6SMonk Liu /* indicate gpu reset occured after ctx created */ 226bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 227bc1b1bf6SMonk Liu /* indicate vram lost occured after ctx created */ 228bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 229bc1b1bf6SMonk Liu /* indicate some job from this context once cause gpu hang */ 230bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 231ae363a21Sxinhui pan /* indicate some errors are detected by RAS */ 232ae363a21Sxinhui pan #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 233ae363a21Sxinhui pan #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 234bc1b1bf6SMonk Liu 235c2636dc5SAndres Rodriguez /* Context priority level */ 236f3d19bf8SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_UNSET -2048 2378bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 2388bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_LOW -512 239c2636dc5SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_NORMAL 0 240cf034477SEmil Velikov /* 241cf034477SEmil Velikov * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 242cf034477SEmil Velikov * CAP_SYS_NICE or DRM_MASTER 243cf034477SEmil Velikov */ 2448bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_HIGH 512 2458bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 246c2636dc5SAndres Rodriguez 2478cda7a4fSAlex Deucher /* select a stable profiling pstate for perfmon tools */ 2488cda7a4fSAlex Deucher #define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf 2498cda7a4fSAlex Deucher #define AMDGPU_CTX_STABLE_PSTATE_NONE 0 2508cda7a4fSAlex Deucher #define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1 2518cda7a4fSAlex Deucher #define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2 2528cda7a4fSAlex Deucher #define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3 2538cda7a4fSAlex Deucher #define AMDGPU_CTX_STABLE_PSTATE_PEAK 4 2548cda7a4fSAlex Deucher 25581629cbaSAlex Deucher struct drm_amdgpu_ctx_in { 256675da0ddSChristian König /** AMDGPU_CTX_OP_* */ 2572ce9dde0SMikko Rapeli __u32 op; 2588cda7a4fSAlex Deucher /** Flags */ 2592ce9dde0SMikko Rapeli __u32 flags; 2602ce9dde0SMikko Rapeli __u32 ctx_id; 261cf034477SEmil Velikov /** AMDGPU_CTX_PRIORITY_* */ 262c2636dc5SAndres Rodriguez __s32 priority; 26381629cbaSAlex Deucher }; 26481629cbaSAlex Deucher 26581629cbaSAlex Deucher union drm_amdgpu_ctx_out { 26681629cbaSAlex Deucher struct { 2672ce9dde0SMikko Rapeli __u32 ctx_id; 2682ce9dde0SMikko Rapeli __u32 _pad; 26981629cbaSAlex Deucher } alloc; 27081629cbaSAlex Deucher 27181629cbaSAlex Deucher struct { 272675da0ddSChristian König /** For future use, no flags defined so far */ 2732ce9dde0SMikko Rapeli __u64 flags; 274d94aed5aSMarek Olšák /** Number of resets caused by this context so far. */ 2752ce9dde0SMikko Rapeli __u32 hangs; 276d94aed5aSMarek Olšák /** Reset status since the last call of the ioctl. */ 2772ce9dde0SMikko Rapeli __u32 reset_status; 27881629cbaSAlex Deucher } state; 2798cda7a4fSAlex Deucher 2808cda7a4fSAlex Deucher struct { 2818cda7a4fSAlex Deucher __u32 flags; 2828cda7a4fSAlex Deucher __u32 _pad; 2838cda7a4fSAlex Deucher } pstate; 28481629cbaSAlex Deucher }; 28581629cbaSAlex Deucher 28681629cbaSAlex Deucher union drm_amdgpu_ctx { 28781629cbaSAlex Deucher struct drm_amdgpu_ctx_in in; 28881629cbaSAlex Deucher union drm_amdgpu_ctx_out out; 28981629cbaSAlex Deucher }; 29081629cbaSAlex Deucher 291cfbcacf4SChunming Zhou /* vm ioctl */ 292cfbcacf4SChunming Zhou #define AMDGPU_VM_OP_RESERVE_VMID 1 293cfbcacf4SChunming Zhou #define AMDGPU_VM_OP_UNRESERVE_VMID 2 294cfbcacf4SChunming Zhou 295cfbcacf4SChunming Zhou struct drm_amdgpu_vm_in { 296cfbcacf4SChunming Zhou /** AMDGPU_VM_OP_* */ 297cfbcacf4SChunming Zhou __u32 op; 298cfbcacf4SChunming Zhou __u32 flags; 299cfbcacf4SChunming Zhou }; 300cfbcacf4SChunming Zhou 301cfbcacf4SChunming Zhou struct drm_amdgpu_vm_out { 302cfbcacf4SChunming Zhou /** For future use, no flags defined so far */ 303cfbcacf4SChunming Zhou __u64 flags; 304cfbcacf4SChunming Zhou }; 305cfbcacf4SChunming Zhou 306cfbcacf4SChunming Zhou union drm_amdgpu_vm { 307cfbcacf4SChunming Zhou struct drm_amdgpu_vm_in in; 308cfbcacf4SChunming Zhou struct drm_amdgpu_vm_out out; 309cfbcacf4SChunming Zhou }; 310cfbcacf4SChunming Zhou 31152c6a62cSAndres Rodriguez /* sched ioctl */ 31252c6a62cSAndres Rodriguez #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 313b5bb37edSBas Nieuwenhuizen #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 31452c6a62cSAndres Rodriguez 31552c6a62cSAndres Rodriguez struct drm_amdgpu_sched_in { 31652c6a62cSAndres Rodriguez /* AMDGPU_SCHED_OP_* */ 31752c6a62cSAndres Rodriguez __u32 op; 31852c6a62cSAndres Rodriguez __u32 fd; 319cf034477SEmil Velikov /** AMDGPU_CTX_PRIORITY_* */ 32052c6a62cSAndres Rodriguez __s32 priority; 321b5bb37edSBas Nieuwenhuizen __u32 ctx_id; 32252c6a62cSAndres Rodriguez }; 32352c6a62cSAndres Rodriguez 32452c6a62cSAndres Rodriguez union drm_amdgpu_sched { 32552c6a62cSAndres Rodriguez struct drm_amdgpu_sched_in in; 32652c6a62cSAndres Rodriguez }; 32752c6a62cSAndres Rodriguez 32881629cbaSAlex Deucher /* 32981629cbaSAlex Deucher * This is not a reliable API and you should expect it to fail for any 33081629cbaSAlex Deucher * number of reasons and have fallback path that do not use userptr to 33181629cbaSAlex Deucher * perform any operation. 33281629cbaSAlex Deucher */ 33381629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 33481629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 33581629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 33681629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 33781629cbaSAlex Deucher 33881629cbaSAlex Deucher struct drm_amdgpu_gem_userptr { 3392ce9dde0SMikko Rapeli __u64 addr; 3402ce9dde0SMikko Rapeli __u64 size; 341675da0ddSChristian König /* AMDGPU_GEM_USERPTR_* */ 3422ce9dde0SMikko Rapeli __u32 flags; 343675da0ddSChristian König /* Resulting GEM handle */ 3442ce9dde0SMikko Rapeli __u32 handle; 34581629cbaSAlex Deucher }; 34681629cbaSAlex Deucher 34700ac6f6bSAlex Deucher /* SI-CI-VI: */ 348fbd76d59SMarek Olšák /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 349fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 350fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 351fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 352fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 353fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 354fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 355fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 356fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 357fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 358fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 359fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 360fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 361fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 362fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 363fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 364fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 365fbd76d59SMarek Olšák 36600ac6f6bSAlex Deucher /* GFX9 and later: */ 36700ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 36800ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 369ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 370ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 371ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 372ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 373ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 374ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 375c5705372SMarek Olšák #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 376c5705372SMarek Olšák #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 377c5705372SMarek Olšák #define AMDGPU_TILING_SCANOUT_SHIFT 63 378c5705372SMarek Olšák #define AMDGPU_TILING_SCANOUT_MASK 0x1 37900ac6f6bSAlex Deucher 38000ac6f6bSAlex Deucher /* Set/Get helpers for tiling flags. */ 381fbd76d59SMarek Olšák #define AMDGPU_TILING_SET(field, value) \ 38200ac6f6bSAlex Deucher (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 383fbd76d59SMarek Olšák #define AMDGPU_TILING_GET(value, field) \ 38400ac6f6bSAlex Deucher (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 38581629cbaSAlex Deucher 38681629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 38781629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 38881629cbaSAlex Deucher 38981629cbaSAlex Deucher /** The same structure is shared for input/output */ 39081629cbaSAlex Deucher struct drm_amdgpu_gem_metadata { 391675da0ddSChristian König /** GEM Object handle */ 3922ce9dde0SMikko Rapeli __u32 handle; 393675da0ddSChristian König /** Do we want get or set metadata */ 3942ce9dde0SMikko Rapeli __u32 op; 39581629cbaSAlex Deucher struct { 396675da0ddSChristian König /** For future use, no flags defined so far */ 3972ce9dde0SMikko Rapeli __u64 flags; 398675da0ddSChristian König /** family specific tiling info */ 3992ce9dde0SMikko Rapeli __u64 tiling_info; 4002ce9dde0SMikko Rapeli __u32 data_size_bytes; 4012ce9dde0SMikko Rapeli __u32 data[64]; 40281629cbaSAlex Deucher } data; 40381629cbaSAlex Deucher }; 40481629cbaSAlex Deucher 40581629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in { 406675da0ddSChristian König /** the GEM object handle */ 4072ce9dde0SMikko Rapeli __u32 handle; 4082ce9dde0SMikko Rapeli __u32 _pad; 40981629cbaSAlex Deucher }; 41081629cbaSAlex Deucher 41181629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out { 412675da0ddSChristian König /** mmap offset from the vma offset manager */ 4132ce9dde0SMikko Rapeli __u64 addr_ptr; 41481629cbaSAlex Deucher }; 41581629cbaSAlex Deucher 41681629cbaSAlex Deucher union drm_amdgpu_gem_mmap { 41781629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in in; 41881629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out out; 41981629cbaSAlex Deucher }; 42081629cbaSAlex Deucher 42181629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in { 422675da0ddSChristian König /** GEM object handle */ 4232ce9dde0SMikko Rapeli __u32 handle; 424675da0ddSChristian König /** For future use, no flags defined so far */ 4252ce9dde0SMikko Rapeli __u32 flags; 426675da0ddSChristian König /** Absolute timeout to wait */ 4272ce9dde0SMikko Rapeli __u64 timeout; 42881629cbaSAlex Deucher }; 42981629cbaSAlex Deucher 43081629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out { 431675da0ddSChristian König /** BO status: 0 - BO is idle, 1 - BO is busy */ 4322ce9dde0SMikko Rapeli __u32 status; 433675da0ddSChristian König /** Returned current memory domain */ 4342ce9dde0SMikko Rapeli __u32 domain; 43581629cbaSAlex Deucher }; 43681629cbaSAlex Deucher 43781629cbaSAlex Deucher union drm_amdgpu_gem_wait_idle { 43881629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in in; 43981629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out out; 44081629cbaSAlex Deucher }; 44181629cbaSAlex Deucher 44281629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in { 443d7b1eeb2SMonk Liu /* Command submission handle 444d7b1eeb2SMonk Liu * handle equals 0 means none to wait for 445080b24ebSAlex Deucher * handle equals ~0ull means wait for the latest sequence number 446d7b1eeb2SMonk Liu */ 4472ce9dde0SMikko Rapeli __u64 handle; 448675da0ddSChristian König /** Absolute timeout to wait */ 4492ce9dde0SMikko Rapeli __u64 timeout; 4502ce9dde0SMikko Rapeli __u32 ip_type; 4512ce9dde0SMikko Rapeli __u32 ip_instance; 4522ce9dde0SMikko Rapeli __u32 ring; 4532ce9dde0SMikko Rapeli __u32 ctx_id; 45481629cbaSAlex Deucher }; 45581629cbaSAlex Deucher 45681629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out { 457675da0ddSChristian König /** CS status: 0 - CS completed, 1 - CS still busy */ 4582ce9dde0SMikko Rapeli __u64 status; 45981629cbaSAlex Deucher }; 46081629cbaSAlex Deucher 46181629cbaSAlex Deucher union drm_amdgpu_wait_cs { 46281629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in in; 46381629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out out; 46481629cbaSAlex Deucher }; 46581629cbaSAlex Deucher 466eef18a82SJunwei Zhang struct drm_amdgpu_fence { 467eef18a82SJunwei Zhang __u32 ctx_id; 468eef18a82SJunwei Zhang __u32 ip_type; 469eef18a82SJunwei Zhang __u32 ip_instance; 470eef18a82SJunwei Zhang __u32 ring; 471eef18a82SJunwei Zhang __u64 seq_no; 472eef18a82SJunwei Zhang }; 473eef18a82SJunwei Zhang 474eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in { 475eef18a82SJunwei Zhang /** This points to uint64_t * which points to fences */ 476eef18a82SJunwei Zhang __u64 fences; 477eef18a82SJunwei Zhang __u32 fence_count; 478eef18a82SJunwei Zhang __u32 wait_all; 479eef18a82SJunwei Zhang __u64 timeout_ns; 480eef18a82SJunwei Zhang }; 481eef18a82SJunwei Zhang 482eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out { 483eef18a82SJunwei Zhang __u32 status; 484eef18a82SJunwei Zhang __u32 first_signaled; 485eef18a82SJunwei Zhang }; 486eef18a82SJunwei Zhang 487eef18a82SJunwei Zhang union drm_amdgpu_wait_fences { 488eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in in; 489eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out out; 490eef18a82SJunwei Zhang }; 491eef18a82SJunwei Zhang 49281629cbaSAlex Deucher #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 493d8f65a23SMarek Olšák #define AMDGPU_GEM_OP_SET_PLACEMENT 1 49481629cbaSAlex Deucher 495675da0ddSChristian König /* Sets or returns a value associated with a buffer. */ 496675da0ddSChristian König struct drm_amdgpu_gem_op { 497675da0ddSChristian König /** GEM object handle */ 4982ce9dde0SMikko Rapeli __u32 handle; 499675da0ddSChristian König /** AMDGPU_GEM_OP_* */ 5002ce9dde0SMikko Rapeli __u32 op; 501675da0ddSChristian König /** Input or return value */ 5022ce9dde0SMikko Rapeli __u64 value; 503675da0ddSChristian König }; 504675da0ddSChristian König 50581629cbaSAlex Deucher #define AMDGPU_VA_OP_MAP 1 50681629cbaSAlex Deucher #define AMDGPU_VA_OP_UNMAP 2 507dc54d3d1SChristian König #define AMDGPU_VA_OP_CLEAR 3 50880f95c57SChristian König #define AMDGPU_VA_OP_REPLACE 4 50981629cbaSAlex Deucher 510fc220f65SChristian König /* Delay the page table update till the next CS */ 511fc220f65SChristian König #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 512fc220f65SChristian König 51381629cbaSAlex Deucher /* Mapping flags */ 51481629cbaSAlex Deucher /* readable mapping */ 51581629cbaSAlex Deucher #define AMDGPU_VM_PAGE_READABLE (1 << 1) 51681629cbaSAlex Deucher /* writable mapping */ 51781629cbaSAlex Deucher #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 51881629cbaSAlex Deucher /* executable mapping, new for VI */ 51981629cbaSAlex Deucher #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 520b85891bdSJunwei Zhang /* partially resident texture */ 521b85891bdSJunwei Zhang #define AMDGPU_VM_PAGE_PRT (1 << 4) 52266e02bc3SAlex Xie /* MTYPE flags use bit 5 to 8 */ 52366e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 52466e02bc3SAlex Xie /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 52566e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 526130c8893SYong Zhao /* Use Non Coherent MTYPE instead of default MTYPE */ 52766e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_NC (1 << 5) 528130c8893SYong Zhao /* Use Write Combine MTYPE instead of default MTYPE */ 52966e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_WC (2 << 5) 530130c8893SYong Zhao /* Use Cache Coherent MTYPE instead of default MTYPE */ 53166e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_CC (3 << 5) 532130c8893SYong Zhao /* Use UnCached MTYPE instead of default MTYPE */ 53366e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_UC (4 << 5) 534130c8893SYong Zhao /* Use Read Write MTYPE instead of default MTYPE */ 535484deaedSOak Zeng #define AMDGPU_VM_MTYPE_RW (5 << 5) 536b6c65a2cSChristian König /* don't allocate MALL */ 537b6c65a2cSChristian König #define AMDGPU_VM_PAGE_NOALLOC (1 << 9) 53881629cbaSAlex Deucher 53934b5f6a6SChristian König struct drm_amdgpu_gem_va { 540675da0ddSChristian König /** GEM object handle */ 5412ce9dde0SMikko Rapeli __u32 handle; 5422ce9dde0SMikko Rapeli __u32 _pad; 543675da0ddSChristian König /** AMDGPU_VA_OP_* */ 5442ce9dde0SMikko Rapeli __u32 operation; 545675da0ddSChristian König /** AMDGPU_VM_PAGE_* */ 5462ce9dde0SMikko Rapeli __u32 flags; 547675da0ddSChristian König /** va address to assign . Must be correctly aligned.*/ 5482ce9dde0SMikko Rapeli __u64 va_address; 549675da0ddSChristian König /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 5502ce9dde0SMikko Rapeli __u64 offset_in_bo; 551675da0ddSChristian König /** Specify mapping size. Must be correctly aligned. */ 5522ce9dde0SMikko Rapeli __u64 map_size; 55381629cbaSAlex Deucher }; 55481629cbaSAlex Deucher 55581629cbaSAlex Deucher #define AMDGPU_HW_IP_GFX 0 55681629cbaSAlex Deucher #define AMDGPU_HW_IP_COMPUTE 1 55781629cbaSAlex Deucher #define AMDGPU_HW_IP_DMA 2 55881629cbaSAlex Deucher #define AMDGPU_HW_IP_UVD 3 55981629cbaSAlex Deucher #define AMDGPU_HW_IP_VCE 4 560a50798b6SLeo Liu #define AMDGPU_HW_IP_UVD_ENC 5 56166e236f1SLeo Liu #define AMDGPU_HW_IP_VCN_DEC 6 562*4528c186SRuijing Dong /* 563*4528c186SRuijing Dong * From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support 564*4528c186SRuijing Dong * both encoding and decoding jobs. 565*4528c186SRuijing Dong */ 566fcfc5a90SLeo Liu #define AMDGPU_HW_IP_VCN_ENC 7 56781d35014SBoyuan Zhang #define AMDGPU_HW_IP_VCN_JPEG 8 56881d35014SBoyuan Zhang #define AMDGPU_HW_IP_NUM 9 56981629cbaSAlex Deucher 57081629cbaSAlex Deucher #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 57181629cbaSAlex Deucher 57281629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_IB 0x01 57381629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_FENCE 0x02 5742b48d323SChristian König #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 575660e8558SDave Airlie #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 576660e8558SDave Airlie #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 577964d0fbfSAndrey Grodzovsky #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 57867dd1a36SAndrey Grodzovsky #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 5792624dd15SChunming Zhou #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 5802624dd15SChunming Zhou #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 581675da0ddSChristian König 58281629cbaSAlex Deucher struct drm_amdgpu_cs_chunk { 5832ce9dde0SMikko Rapeli __u32 chunk_id; 5842ce9dde0SMikko Rapeli __u32 length_dw; 5852ce9dde0SMikko Rapeli __u64 chunk_data; 58681629cbaSAlex Deucher }; 58781629cbaSAlex Deucher 58881629cbaSAlex Deucher struct drm_amdgpu_cs_in { 58981629cbaSAlex Deucher /** Rendering context id */ 5902ce9dde0SMikko Rapeli __u32 ctx_id; 59181629cbaSAlex Deucher /** Handle of resource list associated with CS */ 5922ce9dde0SMikko Rapeli __u32 bo_list_handle; 5932ce9dde0SMikko Rapeli __u32 num_chunks; 594e90c2b21SLuben Tuikov __u32 flags; 5952ce9dde0SMikko Rapeli /** this points to __u64 * which point to cs chunks */ 5962ce9dde0SMikko Rapeli __u64 chunks; 59781629cbaSAlex Deucher }; 59881629cbaSAlex Deucher 59981629cbaSAlex Deucher struct drm_amdgpu_cs_out { 6002ce9dde0SMikko Rapeli __u64 handle; 60181629cbaSAlex Deucher }; 60281629cbaSAlex Deucher 60381629cbaSAlex Deucher union drm_amdgpu_cs { 60481629cbaSAlex Deucher struct drm_amdgpu_cs_in in; 60581629cbaSAlex Deucher struct drm_amdgpu_cs_out out; 60681629cbaSAlex Deucher }; 60781629cbaSAlex Deucher 60881629cbaSAlex Deucher /* Specify flags to be used for IB */ 60981629cbaSAlex Deucher 61081629cbaSAlex Deucher /* This IB should be submitted to CE */ 61181629cbaSAlex Deucher #define AMDGPU_IB_FLAG_CE (1<<0) 61281629cbaSAlex Deucher 613ed834af2SMonk Liu /* Preamble flag, which means the IB could be dropped if no context switch */ 614cab6d57cSJammy Zhou #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 615aa2bdb24SJammy Zhou 61671aec257SMonk Liu /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 61771aec257SMonk Liu #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 61871aec257SMonk Liu 619d240cd9eSMarek Olšák /* The IB fence should do the L2 writeback but not invalidate any shader 620d240cd9eSMarek Olšák * caches (L2/vL1/sL1/I$). */ 621d240cd9eSMarek Olšák #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 622d240cd9eSMarek Olšák 62341cca166SMarek Olšák /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 62441cca166SMarek Olšák * This will reset wave ID counters for the IB. 62541cca166SMarek Olšák */ 62641cca166SMarek Olšák #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 62741cca166SMarek Olšák 6280bb5d5b0SLuben Tuikov /* Flag the IB as secure (TMZ) 6290bb5d5b0SLuben Tuikov */ 6300bb5d5b0SLuben Tuikov #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 6310bb5d5b0SLuben Tuikov 63243c8546bSAndrey Grodzovsky /* Tell KMD to flush and invalidate caches 63343c8546bSAndrey Grodzovsky */ 63443c8546bSAndrey Grodzovsky #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 63543c8546bSAndrey Grodzovsky 63681629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib { 6372ce9dde0SMikko Rapeli __u32 _pad; 638675da0ddSChristian König /** AMDGPU_IB_FLAG_* */ 6392ce9dde0SMikko Rapeli __u32 flags; 640675da0ddSChristian König /** Virtual address to begin IB execution */ 6412ce9dde0SMikko Rapeli __u64 va_start; 642675da0ddSChristian König /** Size of submission */ 6432ce9dde0SMikko Rapeli __u32 ib_bytes; 644675da0ddSChristian König /** HW IP to submit to */ 6452ce9dde0SMikko Rapeli __u32 ip_type; 646675da0ddSChristian König /** HW IP index of the same type to submit to */ 6472ce9dde0SMikko Rapeli __u32 ip_instance; 648675da0ddSChristian König /** Ring index to submit to */ 6492ce9dde0SMikko Rapeli __u32 ring; 65081629cbaSAlex Deucher }; 65181629cbaSAlex Deucher 6522b48d323SChristian König struct drm_amdgpu_cs_chunk_dep { 6532ce9dde0SMikko Rapeli __u32 ip_type; 6542ce9dde0SMikko Rapeli __u32 ip_instance; 6552ce9dde0SMikko Rapeli __u32 ring; 6562ce9dde0SMikko Rapeli __u32 ctx_id; 6572ce9dde0SMikko Rapeli __u64 handle; 6582b48d323SChristian König }; 6592b48d323SChristian König 66081629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence { 6612ce9dde0SMikko Rapeli __u32 handle; 6622ce9dde0SMikko Rapeli __u32 offset; 66381629cbaSAlex Deucher }; 66481629cbaSAlex Deucher 665660e8558SDave Airlie struct drm_amdgpu_cs_chunk_sem { 666660e8558SDave Airlie __u32 handle; 667660e8558SDave Airlie }; 668660e8558SDave Airlie 6692624dd15SChunming Zhou struct drm_amdgpu_cs_chunk_syncobj { 6702624dd15SChunming Zhou __u32 handle; 6712624dd15SChunming Zhou __u32 flags; 6722624dd15SChunming Zhou __u64 point; 6732624dd15SChunming Zhou }; 6742624dd15SChunming Zhou 6757ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 6767ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 6777ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 6787ca24cf2SMarek Olšák 6797ca24cf2SMarek Olšák union drm_amdgpu_fence_to_handle { 6807ca24cf2SMarek Olšák struct { 6817ca24cf2SMarek Olšák struct drm_amdgpu_fence fence; 6827ca24cf2SMarek Olšák __u32 what; 68356e0349fSDave Airlie __u32 pad; 6847ca24cf2SMarek Olšák } in; 6857ca24cf2SMarek Olšák struct { 6867ca24cf2SMarek Olšák __u32 handle; 6877ca24cf2SMarek Olšák } out; 6887ca24cf2SMarek Olšák }; 6897ca24cf2SMarek Olšák 69081629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_data { 69181629cbaSAlex Deucher union { 69281629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib ib_data; 69381629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence fence_data; 69481629cbaSAlex Deucher }; 69581629cbaSAlex Deucher }; 69681629cbaSAlex Deucher 697c45dd3bdSMauro Carvalho Chehab /* 69881629cbaSAlex Deucher * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 69981629cbaSAlex Deucher * 70081629cbaSAlex Deucher */ 70181629cbaSAlex Deucher #define AMDGPU_IDS_FLAGS_FUSION 0x1 702aafcafa0SMonk Liu #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 70316c642ecSPierre-Eric Pelloux-Prayer #define AMDGPU_IDS_FLAGS_TMZ 0x4 70481629cbaSAlex Deucher 70581629cbaSAlex Deucher /* indicate if acceleration can be working */ 70681629cbaSAlex Deucher #define AMDGPU_INFO_ACCEL_WORKING 0x00 70781629cbaSAlex Deucher /* get the crtc_id from the mode object id? */ 70881629cbaSAlex Deucher #define AMDGPU_INFO_CRTC_FROM_ID 0x01 70981629cbaSAlex Deucher /* query hw IP info */ 71081629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_INFO 0x02 71181629cbaSAlex Deucher /* query hw IP instance count for the specified type */ 71281629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_COUNT 0x03 71381629cbaSAlex Deucher /* timestamp for GL_ARB_timer_query */ 71481629cbaSAlex Deucher #define AMDGPU_INFO_TIMESTAMP 0x05 71581629cbaSAlex Deucher /* Query the firmware version */ 71681629cbaSAlex Deucher #define AMDGPU_INFO_FW_VERSION 0x0e 71781629cbaSAlex Deucher /* Subquery id: Query VCE firmware version */ 71881629cbaSAlex Deucher #define AMDGPU_INFO_FW_VCE 0x1 71981629cbaSAlex Deucher /* Subquery id: Query UVD firmware version */ 72081629cbaSAlex Deucher #define AMDGPU_INFO_FW_UVD 0x2 72181629cbaSAlex Deucher /* Subquery id: Query GMC firmware version */ 72281629cbaSAlex Deucher #define AMDGPU_INFO_FW_GMC 0x03 72381629cbaSAlex Deucher /* Subquery id: Query GFX ME firmware version */ 72481629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_ME 0x04 72581629cbaSAlex Deucher /* Subquery id: Query GFX PFP firmware version */ 72681629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_PFP 0x05 72781629cbaSAlex Deucher /* Subquery id: Query GFX CE firmware version */ 72881629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_CE 0x06 72981629cbaSAlex Deucher /* Subquery id: Query GFX RLC firmware version */ 73081629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_RLC 0x07 73181629cbaSAlex Deucher /* Subquery id: Query GFX MEC firmware version */ 73281629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_MEC 0x08 73381629cbaSAlex Deucher /* Subquery id: Query SMC firmware version */ 73481629cbaSAlex Deucher #define AMDGPU_INFO_FW_SMC 0x0a 73581629cbaSAlex Deucher /* Subquery id: Query SDMA firmware version */ 73681629cbaSAlex Deucher #define AMDGPU_INFO_FW_SDMA 0x0b 7376a7ed07eSHuang Rui /* Subquery id: Query PSP SOS firmware version */ 7386a7ed07eSHuang Rui #define AMDGPU_INFO_FW_SOS 0x0c 7396a7ed07eSHuang Rui /* Subquery id: Query PSP ASD firmware version */ 7406a7ed07eSHuang Rui #define AMDGPU_INFO_FW_ASD 0x0d 7413ac952b1SAlex Deucher /* Subquery id: Query VCN firmware version */ 7423ac952b1SAlex Deucher #define AMDGPU_INFO_FW_VCN 0x0e 743621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLC firmware version */ 744621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 745621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLG firmware version */ 746621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 747621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLS firmware version */ 748621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 7494d11b4b2SDavid Francis /* Subquery id: Query DMCU firmware version */ 7504d11b4b2SDavid Francis #define AMDGPU_INFO_FW_DMCU 0x12 7519b9ca62dSxinhui pan #define AMDGPU_INFO_FW_TA 0x13 752976e51a7SNicholas Kazlauskas /* Subquery id: Query DMCUB firmware version */ 753976e51a7SNicholas Kazlauskas #define AMDGPU_INFO_FW_DMCUB 0x14 7546fbcb00cSHuang Rui /* Subquery id: Query TOC firmware version */ 7556fbcb00cSHuang Rui #define AMDGPU_INFO_FW_TOC 0x15 756c4381d0eSBokun Zhang /* Subquery id: Query CAP firmware version */ 757c4381d0eSBokun Zhang #define AMDGPU_INFO_FW_CAP 0x16 758976e51a7SNicholas Kazlauskas 75981629cbaSAlex Deucher /* number of bytes moved for TTM migration */ 76081629cbaSAlex Deucher #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 76181629cbaSAlex Deucher /* the used VRAM size */ 76281629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_USAGE 0x10 76381629cbaSAlex Deucher /* the used GTT size */ 76481629cbaSAlex Deucher #define AMDGPU_INFO_GTT_USAGE 0x11 76581629cbaSAlex Deucher /* Information about GDS, etc. resource configuration */ 76681629cbaSAlex Deucher #define AMDGPU_INFO_GDS_CONFIG 0x13 76781629cbaSAlex Deucher /* Query information about VRAM and GTT domains */ 76881629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_GTT 0x14 76981629cbaSAlex Deucher /* Query information about register in MMR address space*/ 77081629cbaSAlex Deucher #define AMDGPU_INFO_READ_MMR_REG 0x15 77181629cbaSAlex Deucher /* Query information about device: rev id, family, etc. */ 77281629cbaSAlex Deucher #define AMDGPU_INFO_DEV_INFO 0x16 77381629cbaSAlex Deucher /* visible vram usage */ 77481629cbaSAlex Deucher #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 77583a59b63SMarek Olšák /* number of TTM buffer evictions */ 77683a59b63SMarek Olšák #define AMDGPU_INFO_NUM_EVICTIONS 0x18 777e0adf6c8SJunwei Zhang /* Query memory about VRAM and GTT domains */ 778e0adf6c8SJunwei Zhang #define AMDGPU_INFO_MEMORY 0x19 779bbe87974SAlex Deucher /* Query vce clock table */ 780bbe87974SAlex Deucher #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 78140ee5888SEvan Quan /* Query vbios related information */ 78240ee5888SEvan Quan #define AMDGPU_INFO_VBIOS 0x1B 78340ee5888SEvan Quan /* Subquery id: Query vbios size */ 78440ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_SIZE 0x1 78540ee5888SEvan Quan /* Subquery id: Query vbios image */ 78640ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_IMAGE 0x2 78729b4c589SJiawei Gu /* Subquery id: Query vbios info */ 78829b4c589SJiawei Gu #define AMDGPU_INFO_VBIOS_INFO 0x3 78944879b62SArindam Nath /* Query UVD handles */ 79044879b62SArindam Nath #define AMDGPU_INFO_NUM_HANDLES 0x1C 7915ebbac4bSAlex Deucher /* Query sensor related information */ 7925ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR 0x1D 7935ebbac4bSAlex Deucher /* Subquery id: Query GPU shader clock */ 7945ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 7955ebbac4bSAlex Deucher /* Subquery id: Query GPU memory clock */ 7965ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 7975ebbac4bSAlex Deucher /* Subquery id: Query GPU temperature */ 7985ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 7995ebbac4bSAlex Deucher /* Subquery id: Query GPU load */ 8005ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 8015ebbac4bSAlex Deucher /* Subquery id: Query average GPU power */ 8025ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 8035ebbac4bSAlex Deucher /* Subquery id: Query northbridge voltage */ 8045ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDNB 0x6 8055ebbac4bSAlex Deucher /* Subquery id: Query graphics voltage */ 8065ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 80760bbade2SRex Zhu /* Subquery id: Query GPU stable pstate shader clock */ 80860bbade2SRex Zhu #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 80960bbade2SRex Zhu /* Subquery id: Query GPU stable pstate memory clock */ 81060bbade2SRex Zhu #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 81168e2c5ffSMarek Olšák /* Number of VRAM page faults on CPU access. */ 81268e2c5ffSMarek Olšák #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 8131f7251b7SChristian König #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 8145cb77114Sxinhui pan /* query ras mask of enabled features*/ 8155cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 8165cb77114Sxinhui pan /* RAS MASK: UMC (VRAM) */ 8175cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 8185cb77114Sxinhui pan /* RAS MASK: SDMA */ 8195cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 8205cb77114Sxinhui pan /* RAS MASK: GFX */ 8215cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 8225cb77114Sxinhui pan /* RAS MASK: MMHUB */ 8235cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 8245cb77114Sxinhui pan /* RAS MASK: ATHUB */ 8255cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 8265cb77114Sxinhui pan /* RAS MASK: PCIE */ 8275cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 8285cb77114Sxinhui pan /* RAS MASK: HDP */ 8295cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 8305cb77114Sxinhui pan /* RAS MASK: XGMI */ 8315cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 8325cb77114Sxinhui pan /* RAS MASK: DF */ 8335cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 8345cb77114Sxinhui pan /* RAS MASK: SMN */ 8355cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 8365cb77114Sxinhui pan /* RAS MASK: SEM */ 8375cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 8385cb77114Sxinhui pan /* RAS MASK: MP0 */ 8395cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 8405cb77114Sxinhui pan /* RAS MASK: MP1 */ 8415cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 8425cb77114Sxinhui pan /* RAS MASK: FUSE */ 8435cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 84472f4c9d5SAlex Deucher /* query video encode/decode caps */ 84572f4c9d5SAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS 0x21 84672f4c9d5SAlex Deucher /* Subquery id: Decode */ 84772f4c9d5SAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_DECODE 0 84872f4c9d5SAlex Deucher /* Subquery id: Encode */ 84972f4c9d5SAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1 85081629cbaSAlex Deucher 85181629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 85281629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 85381629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 85481629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 85581629cbaSAlex Deucher 856000cab9aSHuang Rui struct drm_amdgpu_query_fw { 857000cab9aSHuang Rui /** AMDGPU_INFO_FW_* */ 858000cab9aSHuang Rui __u32 fw_type; 859000cab9aSHuang Rui /** 860000cab9aSHuang Rui * Index of the IP if there are more IPs of 861000cab9aSHuang Rui * the same type. 862000cab9aSHuang Rui */ 863000cab9aSHuang Rui __u32 ip_instance; 864000cab9aSHuang Rui /** 865000cab9aSHuang Rui * Index of the engine. Whether this is used depends 866000cab9aSHuang Rui * on the firmware type. (e.g. MEC, SDMA) 867000cab9aSHuang Rui */ 868000cab9aSHuang Rui __u32 index; 869000cab9aSHuang Rui __u32 _pad; 870000cab9aSHuang Rui }; 871000cab9aSHuang Rui 87281629cbaSAlex Deucher /* Input structure for the INFO ioctl */ 87381629cbaSAlex Deucher struct drm_amdgpu_info { 87481629cbaSAlex Deucher /* Where the return value will be stored */ 8752ce9dde0SMikko Rapeli __u64 return_pointer; 87681629cbaSAlex Deucher /* The size of the return value. Just like "size" in "snprintf", 87781629cbaSAlex Deucher * it limits how many bytes the kernel can write. */ 8782ce9dde0SMikko Rapeli __u32 return_size; 87981629cbaSAlex Deucher /* The query request id. */ 8802ce9dde0SMikko Rapeli __u32 query; 88181629cbaSAlex Deucher 88281629cbaSAlex Deucher union { 88381629cbaSAlex Deucher struct { 8842ce9dde0SMikko Rapeli __u32 id; 8852ce9dde0SMikko Rapeli __u32 _pad; 88681629cbaSAlex Deucher } mode_crtc; 88781629cbaSAlex Deucher 88881629cbaSAlex Deucher struct { 88981629cbaSAlex Deucher /** AMDGPU_HW_IP_* */ 8902ce9dde0SMikko Rapeli __u32 type; 89181629cbaSAlex Deucher /** 892675da0ddSChristian König * Index of the IP if there are more IPs of the same 893675da0ddSChristian König * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 89481629cbaSAlex Deucher */ 8952ce9dde0SMikko Rapeli __u32 ip_instance; 89681629cbaSAlex Deucher } query_hw_ip; 89781629cbaSAlex Deucher 89881629cbaSAlex Deucher struct { 8992ce9dde0SMikko Rapeli __u32 dword_offset; 900675da0ddSChristian König /** number of registers to read */ 9012ce9dde0SMikko Rapeli __u32 count; 9022ce9dde0SMikko Rapeli __u32 instance; 903675da0ddSChristian König /** For future use, no flags defined so far */ 9042ce9dde0SMikko Rapeli __u32 flags; 90581629cbaSAlex Deucher } read_mmr_reg; 90681629cbaSAlex Deucher 907000cab9aSHuang Rui struct drm_amdgpu_query_fw query_fw; 90840ee5888SEvan Quan 90940ee5888SEvan Quan struct { 91040ee5888SEvan Quan __u32 type; 91140ee5888SEvan Quan __u32 offset; 91240ee5888SEvan Quan } vbios_info; 9135ebbac4bSAlex Deucher 9145ebbac4bSAlex Deucher struct { 9155ebbac4bSAlex Deucher __u32 type; 9165ebbac4bSAlex Deucher } sensor_info; 917f35e9bdbSAlex Deucher 918f35e9bdbSAlex Deucher struct { 919f35e9bdbSAlex Deucher __u32 type; 920f35e9bdbSAlex Deucher } video_cap; 92181629cbaSAlex Deucher }; 92281629cbaSAlex Deucher }; 92381629cbaSAlex Deucher 92481629cbaSAlex Deucher struct drm_amdgpu_info_gds { 92581629cbaSAlex Deucher /** GDS GFX partition size */ 9262ce9dde0SMikko Rapeli __u32 gds_gfx_partition_size; 92781629cbaSAlex Deucher /** GDS compute partition size */ 9282ce9dde0SMikko Rapeli __u32 compute_partition_size; 92981629cbaSAlex Deucher /** total GDS memory size */ 9302ce9dde0SMikko Rapeli __u32 gds_total_size; 93181629cbaSAlex Deucher /** GWS size per GFX partition */ 9322ce9dde0SMikko Rapeli __u32 gws_per_gfx_partition; 93381629cbaSAlex Deucher /** GSW size per compute partition */ 9342ce9dde0SMikko Rapeli __u32 gws_per_compute_partition; 93581629cbaSAlex Deucher /** OA size per GFX partition */ 9362ce9dde0SMikko Rapeli __u32 oa_per_gfx_partition; 93781629cbaSAlex Deucher /** OA size per compute partition */ 9382ce9dde0SMikko Rapeli __u32 oa_per_compute_partition; 9392ce9dde0SMikko Rapeli __u32 _pad; 94081629cbaSAlex Deucher }; 94181629cbaSAlex Deucher 94281629cbaSAlex Deucher struct drm_amdgpu_info_vram_gtt { 9432ce9dde0SMikko Rapeli __u64 vram_size; 9442ce9dde0SMikko Rapeli __u64 vram_cpu_accessible_size; 9452ce9dde0SMikko Rapeli __u64 gtt_size; 94681629cbaSAlex Deucher }; 94781629cbaSAlex Deucher 948e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info { 949e0adf6c8SJunwei Zhang /** max. physical memory */ 950e0adf6c8SJunwei Zhang __u64 total_heap_size; 951e0adf6c8SJunwei Zhang 952e0adf6c8SJunwei Zhang /** Theoretical max. available memory in the given heap */ 953e0adf6c8SJunwei Zhang __u64 usable_heap_size; 954e0adf6c8SJunwei Zhang 955e0adf6c8SJunwei Zhang /** 956e0adf6c8SJunwei Zhang * Number of bytes allocated in the heap. This includes all processes 957e0adf6c8SJunwei Zhang * and private allocations in the kernel. It changes when new buffers 958e0adf6c8SJunwei Zhang * are allocated, freed, and moved. It cannot be larger than 959e0adf6c8SJunwei Zhang * heap_size. 960e0adf6c8SJunwei Zhang */ 961e0adf6c8SJunwei Zhang __u64 heap_usage; 962e0adf6c8SJunwei Zhang 963e0adf6c8SJunwei Zhang /** 964e0adf6c8SJunwei Zhang * Theoretical possible max. size of buffer which 965e0adf6c8SJunwei Zhang * could be allocated in the given heap 966e0adf6c8SJunwei Zhang */ 967e0adf6c8SJunwei Zhang __u64 max_allocation; 9689f6163e7SJunwei Zhang }; 9699f6163e7SJunwei Zhang 970e0adf6c8SJunwei Zhang struct drm_amdgpu_memory_info { 971e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info vram; 972e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info cpu_accessible_vram; 973e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info gtt; 974cfa32556SJunwei Zhang }; 975cfa32556SJunwei Zhang 97681629cbaSAlex Deucher struct drm_amdgpu_info_firmware { 9772ce9dde0SMikko Rapeli __u32 ver; 9782ce9dde0SMikko Rapeli __u32 feature; 97981629cbaSAlex Deucher }; 98081629cbaSAlex Deucher 98129b4c589SJiawei Gu struct drm_amdgpu_info_vbios { 98229b4c589SJiawei Gu __u8 name[64]; 98329b4c589SJiawei Gu __u8 vbios_pn[64]; 98429b4c589SJiawei Gu __u32 version; 98529b4c589SJiawei Gu __u32 pad; 98629b4c589SJiawei Gu __u8 vbios_ver_str[32]; 98729b4c589SJiawei Gu __u8 date[32]; 98829b4c589SJiawei Gu }; 98929b4c589SJiawei Gu 99081c59f54SKen Wang #define AMDGPU_VRAM_TYPE_UNKNOWN 0 99181c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR1 1 99281c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR2 2 99381c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR3 3 99481c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR4 4 99581c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR5 5 99681c59f54SKen Wang #define AMDGPU_VRAM_TYPE_HBM 6 99781c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR3 7 9981e09b053SHawking Zhang #define AMDGPU_VRAM_TYPE_DDR4 8 999d67383e6SHuang Rui #define AMDGPU_VRAM_TYPE_GDDR6 9 10001e483203SHuang Rui #define AMDGPU_VRAM_TYPE_DDR5 10 1001d534ca71SAlex Deucher #define AMDGPU_VRAM_TYPE_LPDDR4 11 1002d534ca71SAlex Deucher #define AMDGPU_VRAM_TYPE_LPDDR5 12 100381c59f54SKen Wang 100481629cbaSAlex Deucher struct drm_amdgpu_info_device { 100581629cbaSAlex Deucher /** PCI Device ID */ 10062ce9dde0SMikko Rapeli __u32 device_id; 100781629cbaSAlex Deucher /** Internal chip revision: A0, A1, etc.) */ 10082ce9dde0SMikko Rapeli __u32 chip_rev; 10092ce9dde0SMikko Rapeli __u32 external_rev; 101081629cbaSAlex Deucher /** Revision id in PCI Config space */ 10112ce9dde0SMikko Rapeli __u32 pci_rev; 10122ce9dde0SMikko Rapeli __u32 family; 10132ce9dde0SMikko Rapeli __u32 num_shader_engines; 10142ce9dde0SMikko Rapeli __u32 num_shader_arrays_per_engine; 1015675da0ddSChristian König /* in KHz */ 10162ce9dde0SMikko Rapeli __u32 gpu_counter_freq; 10172ce9dde0SMikko Rapeli __u64 max_engine_clock; 10182ce9dde0SMikko Rapeli __u64 max_memory_clock; 101981629cbaSAlex Deucher /* cu information */ 10202ce9dde0SMikko Rapeli __u32 cu_active_number; 1021dbfe85eaSFlora Cui /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 10222ce9dde0SMikko Rapeli __u32 cu_ao_mask; 10232ce9dde0SMikko Rapeli __u32 cu_bitmap[4][4]; 102481629cbaSAlex Deucher /** Render backend pipe mask. One render backend is CB+DB. */ 10252ce9dde0SMikko Rapeli __u32 enabled_rb_pipes_mask; 10262ce9dde0SMikko Rapeli __u32 num_rb_pipes; 10272ce9dde0SMikko Rapeli __u32 num_hw_gfx_contexts; 10282ce9dde0SMikko Rapeli __u32 _pad; 10292ce9dde0SMikko Rapeli __u64 ids_flags; 103081629cbaSAlex Deucher /** Starting virtual address for UMDs. */ 10312ce9dde0SMikko Rapeli __u64 virtual_address_offset; 103202b70c8cSJammy Zhou /** The maximum virtual address */ 10332ce9dde0SMikko Rapeli __u64 virtual_address_max; 103481629cbaSAlex Deucher /** Required alignment of virtual addresses. */ 10352ce9dde0SMikko Rapeli __u32 virtual_address_alignment; 103681629cbaSAlex Deucher /** Page table entry - fragment size */ 10372ce9dde0SMikko Rapeli __u32 pte_fragment_size; 10382ce9dde0SMikko Rapeli __u32 gart_page_size; 1039a101a899SKen Wang /** constant engine ram size*/ 10402ce9dde0SMikko Rapeli __u32 ce_ram_size; 1041cab6d57cSJammy Zhou /** video memory type info*/ 10422ce9dde0SMikko Rapeli __u32 vram_type; 104381c59f54SKen Wang /** video memory bit width*/ 10442ce9dde0SMikko Rapeli __u32 vram_bit_width; 1045fa92754eSLeo Liu /* vce harvesting instance */ 10462ce9dde0SMikko Rapeli __u32 vce_harvest_config; 1047df6e2c4aSJunwei Zhang /* gfx double offchip LDS buffers */ 1048df6e2c4aSJunwei Zhang __u32 gc_double_offchip_lds_buf; 1049bce23e00SAlex Deucher /* NGG Primitive Buffer */ 1050bce23e00SAlex Deucher __u64 prim_buf_gpu_addr; 1051bce23e00SAlex Deucher /* NGG Position Buffer */ 1052bce23e00SAlex Deucher __u64 pos_buf_gpu_addr; 1053bce23e00SAlex Deucher /* NGG Control Sideband */ 1054bce23e00SAlex Deucher __u64 cntl_sb_buf_gpu_addr; 1055bce23e00SAlex Deucher /* NGG Parameter Cache */ 1056bce23e00SAlex Deucher __u64 param_buf_gpu_addr; 1057408bfe7cSJunwei Zhang __u32 prim_buf_size; 1058408bfe7cSJunwei Zhang __u32 pos_buf_size; 1059408bfe7cSJunwei Zhang __u32 cntl_sb_buf_size; 1060408bfe7cSJunwei Zhang __u32 param_buf_size; 1061408bfe7cSJunwei Zhang /* wavefront size*/ 1062408bfe7cSJunwei Zhang __u32 wave_front_size; 1063408bfe7cSJunwei Zhang /* shader visible vgprs*/ 1064408bfe7cSJunwei Zhang __u32 num_shader_visible_vgprs; 1065408bfe7cSJunwei Zhang /* CU per shader array*/ 1066408bfe7cSJunwei Zhang __u32 num_cu_per_sh; 1067408bfe7cSJunwei Zhang /* number of tcc blocks*/ 1068408bfe7cSJunwei Zhang __u32 num_tcc_blocks; 1069408bfe7cSJunwei Zhang /* gs vgt table depth*/ 1070408bfe7cSJunwei Zhang __u32 gs_vgt_table_depth; 1071408bfe7cSJunwei Zhang /* gs primitive buffer depth*/ 1072408bfe7cSJunwei Zhang __u32 gs_prim_buffer_depth; 1073408bfe7cSJunwei Zhang /* max gs wavefront per vgt*/ 1074408bfe7cSJunwei Zhang __u32 max_gs_waves_per_vgt; 1075408bfe7cSJunwei Zhang __u32 _pad1; 1076dbfe85eaSFlora Cui /* always on cu bitmap */ 1077dbfe85eaSFlora Cui __u32 cu_ao_bitmap[4][4]; 10785b565e0eSChristian König /** Starting high virtual address for UMDs. */ 10795b565e0eSChristian König __u64 high_va_offset; 10805b565e0eSChristian König /** The maximum high virtual address */ 10815b565e0eSChristian König __u64 high_va_max; 108222e96fa6SHawking Zhang /* gfx10 pa_sc_tile_steering_override */ 108322e96fa6SHawking Zhang __u32 pa_sc_tile_steering_override; 1084cf21e76aSMarek Olšák /* disabled TCCs */ 1085cf21e76aSMarek Olšák __u64 tcc_disabled_mask; 108681629cbaSAlex Deucher }; 108781629cbaSAlex Deucher 108881629cbaSAlex Deucher struct drm_amdgpu_info_hw_ip { 108981629cbaSAlex Deucher /** Version of h/w IP */ 10902ce9dde0SMikko Rapeli __u32 hw_ip_version_major; 10912ce9dde0SMikko Rapeli __u32 hw_ip_version_minor; 109281629cbaSAlex Deucher /** Capabilities */ 10932ce9dde0SMikko Rapeli __u64 capabilities_flags; 109471062f43SKen Wang /** command buffer address start alignment*/ 10952ce9dde0SMikko Rapeli __u32 ib_start_alignment; 109671062f43SKen Wang /** command buffer size alignment*/ 10972ce9dde0SMikko Rapeli __u32 ib_size_alignment; 109881629cbaSAlex Deucher /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 10992ce9dde0SMikko Rapeli __u32 available_rings; 11002ce9dde0SMikko Rapeli __u32 _pad; 110181629cbaSAlex Deucher }; 110281629cbaSAlex Deucher 110344879b62SArindam Nath struct drm_amdgpu_info_num_handles { 110444879b62SArindam Nath /** Max handles as supported by firmware for UVD */ 110544879b62SArindam Nath __u32 uvd_max_handles; 110644879b62SArindam Nath /** Handles currently in use for UVD */ 110744879b62SArindam Nath __u32 uvd_used_handles; 110844879b62SArindam Nath }; 110944879b62SArindam Nath 1110bbe87974SAlex Deucher #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1111bbe87974SAlex Deucher 1112bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry { 1113bbe87974SAlex Deucher /** System clock */ 1114bbe87974SAlex Deucher __u32 sclk; 1115bbe87974SAlex Deucher /** Memory clock */ 1116bbe87974SAlex Deucher __u32 mclk; 1117bbe87974SAlex Deucher /** VCE clock */ 1118bbe87974SAlex Deucher __u32 eclk; 1119bbe87974SAlex Deucher __u32 pad; 1120bbe87974SAlex Deucher }; 1121bbe87974SAlex Deucher 1122bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table { 1123bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1124bbe87974SAlex Deucher __u32 num_valid_entries; 1125bbe87974SAlex Deucher __u32 pad; 1126bbe87974SAlex Deucher }; 1127bbe87974SAlex Deucher 1128f35e9bdbSAlex Deucher /* query video encode/decode caps */ 1129f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0 1130f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1 1131f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2 1132f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3 1133f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4 1134f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5 1135f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6 1136f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7 1137f35e9bdbSAlex Deucher #define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8 1138f35e9bdbSAlex Deucher 1139f35e9bdbSAlex Deucher struct drm_amdgpu_info_video_codec_info { 1140f35e9bdbSAlex Deucher __u32 valid; 1141f35e9bdbSAlex Deucher __u32 max_width; 1142f35e9bdbSAlex Deucher __u32 max_height; 1143f35e9bdbSAlex Deucher __u32 max_pixels_per_frame; 1144f35e9bdbSAlex Deucher __u32 max_level; 1145f35e9bdbSAlex Deucher __u32 pad; 1146f35e9bdbSAlex Deucher }; 1147f35e9bdbSAlex Deucher 1148f35e9bdbSAlex Deucher struct drm_amdgpu_info_video_caps { 1149f35e9bdbSAlex Deucher struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT]; 1150f35e9bdbSAlex Deucher }; 1151f35e9bdbSAlex Deucher 115281629cbaSAlex Deucher /* 115381629cbaSAlex Deucher * Supported GPU families 115481629cbaSAlex Deucher */ 115581629cbaSAlex Deucher #define AMDGPU_FAMILY_UNKNOWN 0 1156295d0dafSKen Wang #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 115781629cbaSAlex Deucher #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 115881629cbaSAlex Deucher #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 115981629cbaSAlex Deucher #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 116039bb0c92SSamuel Li #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1161a8f1f1ceSAlex Deucher #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 11622ca8a5d2SChunming Zhou #define AMDGPU_FAMILY_RV 142 /* Raven */ 1163107c34bcSHuang Rui #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1164f7b2cdb2SHuang Rui #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 11655eca8379SHawking Zhang #define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */ 116690a187d2SAaron Liu #define AMDGPU_FAMILY_YC 146 /* Yellow Carp */ 1167cbe757ecSHuang Rui #define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */ 1168874bfdfaSYifan Zhang #define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */ 1169a65dbf7cSPrike Liang #define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */ 117081629cbaSAlex Deucher 1171cfa7152fSEmil Velikov #if defined(__cplusplus) 1172cfa7152fSEmil Velikov } 1173cfa7152fSEmil Velikov #endif 1174cfa7152fSEmil Velikov 117581629cbaSAlex Deucher #endif 1176