181629cbaSAlex Deucher /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- 281629cbaSAlex Deucher * 381629cbaSAlex Deucher * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 481629cbaSAlex Deucher * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 581629cbaSAlex Deucher * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 681629cbaSAlex Deucher * Copyright 2014 Advanced Micro Devices, Inc. 781629cbaSAlex Deucher * 881629cbaSAlex Deucher * Permission is hereby granted, free of charge, to any person obtaining a 981629cbaSAlex Deucher * copy of this software and associated documentation files (the "Software"), 1081629cbaSAlex Deucher * to deal in the Software without restriction, including without limitation 1181629cbaSAlex Deucher * the rights to use, copy, modify, merge, publish, distribute, sublicense, 1281629cbaSAlex Deucher * and/or sell copies of the Software, and to permit persons to whom the 1381629cbaSAlex Deucher * Software is furnished to do so, subject to the following conditions: 1481629cbaSAlex Deucher * 1581629cbaSAlex Deucher * The above copyright notice and this permission notice shall be included in 1681629cbaSAlex Deucher * all copies or substantial portions of the Software. 1781629cbaSAlex Deucher * 1881629cbaSAlex Deucher * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 1981629cbaSAlex Deucher * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 2081629cbaSAlex Deucher * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 2181629cbaSAlex Deucher * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 2281629cbaSAlex Deucher * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 2381629cbaSAlex Deucher * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 2481629cbaSAlex Deucher * OTHER DEALINGS IN THE SOFTWARE. 2581629cbaSAlex Deucher * 2681629cbaSAlex Deucher * Authors: 2781629cbaSAlex Deucher * Kevin E. Martin <martin@valinux.com> 2881629cbaSAlex Deucher * Gareth Hughes <gareth@valinux.com> 2981629cbaSAlex Deucher * Keith Whitwell <keith@tungstengraphics.com> 3081629cbaSAlex Deucher */ 3181629cbaSAlex Deucher 3281629cbaSAlex Deucher #ifndef __AMDGPU_DRM_H__ 3381629cbaSAlex Deucher #define __AMDGPU_DRM_H__ 3481629cbaSAlex Deucher 35b3fcf36aSMichel Dänzer #include "drm.h" 3681629cbaSAlex Deucher 37cfa7152fSEmil Velikov #if defined(__cplusplus) 38cfa7152fSEmil Velikov extern "C" { 39cfa7152fSEmil Velikov #endif 40cfa7152fSEmil Velikov 4181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_CREATE 0x00 4281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_MMAP 0x01 4381629cbaSAlex Deucher #define DRM_AMDGPU_CTX 0x02 4481629cbaSAlex Deucher #define DRM_AMDGPU_BO_LIST 0x03 4581629cbaSAlex Deucher #define DRM_AMDGPU_CS 0x04 4681629cbaSAlex Deucher #define DRM_AMDGPU_INFO 0x05 4781629cbaSAlex Deucher #define DRM_AMDGPU_GEM_METADATA 0x06 4881629cbaSAlex Deucher #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 4981629cbaSAlex Deucher #define DRM_AMDGPU_GEM_VA 0x08 5081629cbaSAlex Deucher #define DRM_AMDGPU_WAIT_CS 0x09 5181629cbaSAlex Deucher #define DRM_AMDGPU_GEM_OP 0x10 5281629cbaSAlex Deucher #define DRM_AMDGPU_GEM_USERPTR 0x11 53eef18a82SJunwei Zhang #define DRM_AMDGPU_WAIT_FENCES 0x12 54cfbcacf4SChunming Zhou #define DRM_AMDGPU_VM 0x13 557ca24cf2SMarek Olšák #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 5652c6a62cSAndres Rodriguez #define DRM_AMDGPU_SCHED 0x15 5781629cbaSAlex Deucher 5881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) 5981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) 6081629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) 6181629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) 6281629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) 6381629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) 6481629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) 6581629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) 6634b5f6a6SChristian König #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) 6781629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) 6881629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) 6981629cbaSAlex Deucher #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) 70eef18a82SJunwei Zhang #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) 71cfbcacf4SChunming Zhou #define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm) 727ca24cf2SMarek Olšák #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) 7352c6a62cSAndres Rodriguez #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) 7481629cbaSAlex Deucher 75b646c1dcSSamuel Li /** 76b646c1dcSSamuel Li * DOC: memory domains 77b646c1dcSSamuel Li * 78b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_CPU System memory that is not GPU accessible. 79b646c1dcSSamuel Li * Memory in this pool could be swapped out to disk if there is pressure. 80b646c1dcSSamuel Li * 81b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the 82b646c1dcSSamuel Li * GPU's virtual address space via gart. Gart memory linearizes non-contiguous 83b646c1dcSSamuel Li * pages of system memory, allows GPU access system memory in a linezrized 84b646c1dcSSamuel Li * fashion. 85b646c1dcSSamuel Li * 86b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory 87b646c1dcSSamuel Li * carved out by the BIOS. 88b646c1dcSSamuel Li * 89b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GDS Global on-chip data storage used to share data 90b646c1dcSSamuel Li * across shader threads. 91b646c1dcSSamuel Li * 92b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_GWS Global wave sync, used to synchronize the 93b646c1dcSSamuel Li * execution of all the waves on a device. 94b646c1dcSSamuel Li * 95b646c1dcSSamuel Li * %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines 96b646c1dcSSamuel Li * for appending data. 97b646c1dcSSamuel Li */ 9881629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_CPU 0x1 9981629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GTT 0x2 10081629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_VRAM 0x4 10181629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GDS 0x8 10281629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_GWS 0x10 10381629cbaSAlex Deucher #define AMDGPU_GEM_DOMAIN_OA 0x20 1043f188453SChunming Zhou #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ 1053f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GTT | \ 1063f188453SChunming Zhou AMDGPU_GEM_DOMAIN_VRAM | \ 1073f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GDS | \ 1083f188453SChunming Zhou AMDGPU_GEM_DOMAIN_GWS | \ 1093f188453SChunming Zhou AMDGPU_GEM_DOMAIN_OA) 11081629cbaSAlex Deucher 11181629cbaSAlex Deucher /* Flag that CPU access will be required for the case of VRAM domain */ 11281629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) 11381629cbaSAlex Deucher /* Flag that CPU access will not work, this VRAM domain is invisible */ 11481629cbaSAlex Deucher #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) 11581629cbaSAlex Deucher /* Flag that USWC attributes should be used for GTT */ 11688671288SJammy Zhou #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) 1174fea83ffSFlora Cui /* Flag that the memory should be in VRAM and cleared */ 1184fea83ffSFlora Cui #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) 119e7893c4bSChunming Zhou /* Flag that create shadow bo(GTT) while allocating vram bo */ 120e7893c4bSChunming Zhou #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) 12103f48dd5SChristian König /* Flag that allocating the BO should use linear VRAM */ 12203f48dd5SChristian König #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) 123e1eb899bSChristian König /* Flag that BO is always valid in this VM */ 124e1eb899bSChristian König #define AMDGPU_GEM_CREATE_VM_ALWAYS_VALID (1 << 6) 125177ae09bSAndres Rodriguez /* Flag that BO sharing will be explicitly synchronized */ 126177ae09bSAndres Rodriguez #define AMDGPU_GEM_CREATE_EXPLICIT_SYNC (1 << 7) 127959a2091SYong Zhao /* Flag that indicates allocating MQD gart on GFX9, where the mtype 128fa5bde80SYong Zhao * for the second page onward should be set to NC. It should never 129fa5bde80SYong Zhao * be used by user space applications. 130959a2091SYong Zhao */ 131fa5bde80SYong Zhao #define AMDGPU_GEM_CREATE_CP_MQD_GFX9 (1 << 8) 132d8f4981eSFelix Kuehling /* Flag that BO may contain sensitive data that must be wiped before 133d8f4981eSFelix Kuehling * releasing the memory 134d8f4981eSFelix Kuehling */ 135d8f4981eSFelix Kuehling #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) 13635ce0060SAlex Deucher /* Flag that BO will be encrypted and that the TMZ bit should be 13735ce0060SAlex Deucher * set in the PTEs when mapping this buffer via GPUVM or 13835ce0060SAlex Deucher * accessing it with various hw blocks 13935ce0060SAlex Deucher */ 14035ce0060SAlex Deucher #define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) 14181629cbaSAlex Deucher 14281629cbaSAlex Deucher struct drm_amdgpu_gem_create_in { 14381629cbaSAlex Deucher /** the requested memory size */ 1442ce9dde0SMikko Rapeli __u64 bo_size; 14581629cbaSAlex Deucher /** physical start_addr alignment in bytes for some HW requirements */ 1462ce9dde0SMikko Rapeli __u64 alignment; 14781629cbaSAlex Deucher /** the requested memory domains */ 1482ce9dde0SMikko Rapeli __u64 domains; 14981629cbaSAlex Deucher /** allocation flags */ 1502ce9dde0SMikko Rapeli __u64 domain_flags; 15181629cbaSAlex Deucher }; 15281629cbaSAlex Deucher 15381629cbaSAlex Deucher struct drm_amdgpu_gem_create_out { 15481629cbaSAlex Deucher /** returned GEM object handle */ 1552ce9dde0SMikko Rapeli __u32 handle; 1562ce9dde0SMikko Rapeli __u32 _pad; 15781629cbaSAlex Deucher }; 15881629cbaSAlex Deucher 15981629cbaSAlex Deucher union drm_amdgpu_gem_create { 16081629cbaSAlex Deucher struct drm_amdgpu_gem_create_in in; 16181629cbaSAlex Deucher struct drm_amdgpu_gem_create_out out; 16281629cbaSAlex Deucher }; 16381629cbaSAlex Deucher 16481629cbaSAlex Deucher /** Opcode to create new residency list. */ 16581629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_CREATE 0 16681629cbaSAlex Deucher /** Opcode to destroy previously created residency list */ 16781629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_DESTROY 1 16881629cbaSAlex Deucher /** Opcode to update resource information in the list */ 16981629cbaSAlex Deucher #define AMDGPU_BO_LIST_OP_UPDATE 2 17081629cbaSAlex Deucher 17181629cbaSAlex Deucher struct drm_amdgpu_bo_list_in { 17281629cbaSAlex Deucher /** Type of operation */ 1732ce9dde0SMikko Rapeli __u32 operation; 17481629cbaSAlex Deucher /** Handle of list or 0 if we want to create one */ 1752ce9dde0SMikko Rapeli __u32 list_handle; 17681629cbaSAlex Deucher /** Number of BOs in list */ 1772ce9dde0SMikko Rapeli __u32 bo_number; 17881629cbaSAlex Deucher /** Size of each element describing BO */ 1792ce9dde0SMikko Rapeli __u32 bo_info_size; 18081629cbaSAlex Deucher /** Pointer to array describing BOs */ 1812ce9dde0SMikko Rapeli __u64 bo_info_ptr; 18281629cbaSAlex Deucher }; 18381629cbaSAlex Deucher 18481629cbaSAlex Deucher struct drm_amdgpu_bo_list_entry { 18581629cbaSAlex Deucher /** Handle of BO */ 1862ce9dde0SMikko Rapeli __u32 bo_handle; 18781629cbaSAlex Deucher /** New (if specified) BO priority to be used during migration */ 1882ce9dde0SMikko Rapeli __u32 bo_priority; 18981629cbaSAlex Deucher }; 19081629cbaSAlex Deucher 19181629cbaSAlex Deucher struct drm_amdgpu_bo_list_out { 19281629cbaSAlex Deucher /** Handle of resource list */ 1932ce9dde0SMikko Rapeli __u32 list_handle; 1942ce9dde0SMikko Rapeli __u32 _pad; 19581629cbaSAlex Deucher }; 19681629cbaSAlex Deucher 19781629cbaSAlex Deucher union drm_amdgpu_bo_list { 19881629cbaSAlex Deucher struct drm_amdgpu_bo_list_in in; 19981629cbaSAlex Deucher struct drm_amdgpu_bo_list_out out; 20081629cbaSAlex Deucher }; 20181629cbaSAlex Deucher 20281629cbaSAlex Deucher /* context related */ 20381629cbaSAlex Deucher #define AMDGPU_CTX_OP_ALLOC_CTX 1 20481629cbaSAlex Deucher #define AMDGPU_CTX_OP_FREE_CTX 2 20581629cbaSAlex Deucher #define AMDGPU_CTX_OP_QUERY_STATE 3 206bc1b1bf6SMonk Liu #define AMDGPU_CTX_OP_QUERY_STATE2 4 20781629cbaSAlex Deucher 208d94aed5aSMarek Olšák /* GPU reset status */ 209d94aed5aSMarek Olšák #define AMDGPU_CTX_NO_RESET 0 210675da0ddSChristian König /* this the context caused it */ 211675da0ddSChristian König #define AMDGPU_CTX_GUILTY_RESET 1 212675da0ddSChristian König /* some other context caused it */ 213675da0ddSChristian König #define AMDGPU_CTX_INNOCENT_RESET 2 214675da0ddSChristian König /* unknown cause */ 215675da0ddSChristian König #define AMDGPU_CTX_UNKNOWN_RESET 3 216d94aed5aSMarek Olšák 217bc1b1bf6SMonk Liu /* indicate gpu reset occured after ctx created */ 218bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0) 219bc1b1bf6SMonk Liu /* indicate vram lost occured after ctx created */ 220bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1) 221bc1b1bf6SMonk Liu /* indicate some job from this context once cause gpu hang */ 222bc1b1bf6SMonk Liu #define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2) 223ae363a21Sxinhui pan /* indicate some errors are detected by RAS */ 224ae363a21Sxinhui pan #define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3) 225ae363a21Sxinhui pan #define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4) 226bc1b1bf6SMonk Liu 227c2636dc5SAndres Rodriguez /* Context priority level */ 228f3d19bf8SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_UNSET -2048 2298bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_VERY_LOW -1023 2308bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_LOW -512 231c2636dc5SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_NORMAL 0 232cf034477SEmil Velikov /* 233cf034477SEmil Velikov * When used in struct drm_amdgpu_ctx_in, a priority above NORMAL requires 234cf034477SEmil Velikov * CAP_SYS_NICE or DRM_MASTER 235cf034477SEmil Velikov */ 2368bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_HIGH 512 2378bc4c256SAndres Rodriguez #define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023 238c2636dc5SAndres Rodriguez 23981629cbaSAlex Deucher struct drm_amdgpu_ctx_in { 240675da0ddSChristian König /** AMDGPU_CTX_OP_* */ 2412ce9dde0SMikko Rapeli __u32 op; 242675da0ddSChristian König /** For future use, no flags defined so far */ 2432ce9dde0SMikko Rapeli __u32 flags; 2442ce9dde0SMikko Rapeli __u32 ctx_id; 245cf034477SEmil Velikov /** AMDGPU_CTX_PRIORITY_* */ 246c2636dc5SAndres Rodriguez __s32 priority; 24781629cbaSAlex Deucher }; 24881629cbaSAlex Deucher 24981629cbaSAlex Deucher union drm_amdgpu_ctx_out { 25081629cbaSAlex Deucher struct { 2512ce9dde0SMikko Rapeli __u32 ctx_id; 2522ce9dde0SMikko Rapeli __u32 _pad; 25381629cbaSAlex Deucher } alloc; 25481629cbaSAlex Deucher 25581629cbaSAlex Deucher struct { 256675da0ddSChristian König /** For future use, no flags defined so far */ 2572ce9dde0SMikko Rapeli __u64 flags; 258d94aed5aSMarek Olšák /** Number of resets caused by this context so far. */ 2592ce9dde0SMikko Rapeli __u32 hangs; 260d94aed5aSMarek Olšák /** Reset status since the last call of the ioctl. */ 2612ce9dde0SMikko Rapeli __u32 reset_status; 26281629cbaSAlex Deucher } state; 26381629cbaSAlex Deucher }; 26481629cbaSAlex Deucher 26581629cbaSAlex Deucher union drm_amdgpu_ctx { 26681629cbaSAlex Deucher struct drm_amdgpu_ctx_in in; 26781629cbaSAlex Deucher union drm_amdgpu_ctx_out out; 26881629cbaSAlex Deucher }; 26981629cbaSAlex Deucher 270cfbcacf4SChunming Zhou /* vm ioctl */ 271cfbcacf4SChunming Zhou #define AMDGPU_VM_OP_RESERVE_VMID 1 272cfbcacf4SChunming Zhou #define AMDGPU_VM_OP_UNRESERVE_VMID 2 273cfbcacf4SChunming Zhou 274cfbcacf4SChunming Zhou struct drm_amdgpu_vm_in { 275cfbcacf4SChunming Zhou /** AMDGPU_VM_OP_* */ 276cfbcacf4SChunming Zhou __u32 op; 277cfbcacf4SChunming Zhou __u32 flags; 278cfbcacf4SChunming Zhou }; 279cfbcacf4SChunming Zhou 280cfbcacf4SChunming Zhou struct drm_amdgpu_vm_out { 281cfbcacf4SChunming Zhou /** For future use, no flags defined so far */ 282cfbcacf4SChunming Zhou __u64 flags; 283cfbcacf4SChunming Zhou }; 284cfbcacf4SChunming Zhou 285cfbcacf4SChunming Zhou union drm_amdgpu_vm { 286cfbcacf4SChunming Zhou struct drm_amdgpu_vm_in in; 287cfbcacf4SChunming Zhou struct drm_amdgpu_vm_out out; 288cfbcacf4SChunming Zhou }; 289cfbcacf4SChunming Zhou 29052c6a62cSAndres Rodriguez /* sched ioctl */ 29152c6a62cSAndres Rodriguez #define AMDGPU_SCHED_OP_PROCESS_PRIORITY_OVERRIDE 1 292b5bb37edSBas Nieuwenhuizen #define AMDGPU_SCHED_OP_CONTEXT_PRIORITY_OVERRIDE 2 29352c6a62cSAndres Rodriguez 29452c6a62cSAndres Rodriguez struct drm_amdgpu_sched_in { 29552c6a62cSAndres Rodriguez /* AMDGPU_SCHED_OP_* */ 29652c6a62cSAndres Rodriguez __u32 op; 29752c6a62cSAndres Rodriguez __u32 fd; 298cf034477SEmil Velikov /** AMDGPU_CTX_PRIORITY_* */ 29952c6a62cSAndres Rodriguez __s32 priority; 300b5bb37edSBas Nieuwenhuizen __u32 ctx_id; 30152c6a62cSAndres Rodriguez }; 30252c6a62cSAndres Rodriguez 30352c6a62cSAndres Rodriguez union drm_amdgpu_sched { 30452c6a62cSAndres Rodriguez struct drm_amdgpu_sched_in in; 30552c6a62cSAndres Rodriguez }; 30652c6a62cSAndres Rodriguez 30781629cbaSAlex Deucher /* 30881629cbaSAlex Deucher * This is not a reliable API and you should expect it to fail for any 30981629cbaSAlex Deucher * number of reasons and have fallback path that do not use userptr to 31081629cbaSAlex Deucher * perform any operation. 31181629cbaSAlex Deucher */ 31281629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) 31381629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) 31481629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) 31581629cbaSAlex Deucher #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) 31681629cbaSAlex Deucher 31781629cbaSAlex Deucher struct drm_amdgpu_gem_userptr { 3182ce9dde0SMikko Rapeli __u64 addr; 3192ce9dde0SMikko Rapeli __u64 size; 320675da0ddSChristian König /* AMDGPU_GEM_USERPTR_* */ 3212ce9dde0SMikko Rapeli __u32 flags; 322675da0ddSChristian König /* Resulting GEM handle */ 3232ce9dde0SMikko Rapeli __u32 handle; 32481629cbaSAlex Deucher }; 32581629cbaSAlex Deucher 32600ac6f6bSAlex Deucher /* SI-CI-VI: */ 327fbd76d59SMarek Olšák /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ 328fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 329fbd76d59SMarek Olšák #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf 330fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 331fbd76d59SMarek Olšák #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f 332fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 333fbd76d59SMarek Olšák #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 334fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 335fbd76d59SMarek Olšák #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 336fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 337fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 338fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 339fbd76d59SMarek Olšák #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 340fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 341fbd76d59SMarek Olšák #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 342fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 343fbd76d59SMarek Olšák #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 344fbd76d59SMarek Olšák 34500ac6f6bSAlex Deucher /* GFX9 and later: */ 34600ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 34700ac6f6bSAlex Deucher #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f 348ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5 349ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_OFFSET_256B_MASK 0xFFFFFF 350ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_PITCH_MAX_SHIFT 29 351ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF 352ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43 353ce331f8fSNicholas Kazlauskas #define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1 354c5705372SMarek Olšák #define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44 355c5705372SMarek Olšák #define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1 356c5705372SMarek Olšák #define AMDGPU_TILING_SCANOUT_SHIFT 63 357c5705372SMarek Olšák #define AMDGPU_TILING_SCANOUT_MASK 0x1 35800ac6f6bSAlex Deucher 35900ac6f6bSAlex Deucher /* Set/Get helpers for tiling flags. */ 360fbd76d59SMarek Olšák #define AMDGPU_TILING_SET(field, value) \ 36100ac6f6bSAlex Deucher (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) 362fbd76d59SMarek Olšák #define AMDGPU_TILING_GET(value, field) \ 36300ac6f6bSAlex Deucher (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) 36481629cbaSAlex Deucher 36581629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 36681629cbaSAlex Deucher #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 36781629cbaSAlex Deucher 36881629cbaSAlex Deucher /** The same structure is shared for input/output */ 36981629cbaSAlex Deucher struct drm_amdgpu_gem_metadata { 370675da0ddSChristian König /** GEM Object handle */ 3712ce9dde0SMikko Rapeli __u32 handle; 372675da0ddSChristian König /** Do we want get or set metadata */ 3732ce9dde0SMikko Rapeli __u32 op; 37481629cbaSAlex Deucher struct { 375675da0ddSChristian König /** For future use, no flags defined so far */ 3762ce9dde0SMikko Rapeli __u64 flags; 377675da0ddSChristian König /** family specific tiling info */ 3782ce9dde0SMikko Rapeli __u64 tiling_info; 3792ce9dde0SMikko Rapeli __u32 data_size_bytes; 3802ce9dde0SMikko Rapeli __u32 data[64]; 38181629cbaSAlex Deucher } data; 38281629cbaSAlex Deucher }; 38381629cbaSAlex Deucher 38481629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in { 385675da0ddSChristian König /** the GEM object handle */ 3862ce9dde0SMikko Rapeli __u32 handle; 3872ce9dde0SMikko Rapeli __u32 _pad; 38881629cbaSAlex Deucher }; 38981629cbaSAlex Deucher 39081629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out { 391675da0ddSChristian König /** mmap offset from the vma offset manager */ 3922ce9dde0SMikko Rapeli __u64 addr_ptr; 39381629cbaSAlex Deucher }; 39481629cbaSAlex Deucher 39581629cbaSAlex Deucher union drm_amdgpu_gem_mmap { 39681629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_in in; 39781629cbaSAlex Deucher struct drm_amdgpu_gem_mmap_out out; 39881629cbaSAlex Deucher }; 39981629cbaSAlex Deucher 40081629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in { 401675da0ddSChristian König /** GEM object handle */ 4022ce9dde0SMikko Rapeli __u32 handle; 403675da0ddSChristian König /** For future use, no flags defined so far */ 4042ce9dde0SMikko Rapeli __u32 flags; 405675da0ddSChristian König /** Absolute timeout to wait */ 4062ce9dde0SMikko Rapeli __u64 timeout; 40781629cbaSAlex Deucher }; 40881629cbaSAlex Deucher 40981629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out { 410675da0ddSChristian König /** BO status: 0 - BO is idle, 1 - BO is busy */ 4112ce9dde0SMikko Rapeli __u32 status; 412675da0ddSChristian König /** Returned current memory domain */ 4132ce9dde0SMikko Rapeli __u32 domain; 41481629cbaSAlex Deucher }; 41581629cbaSAlex Deucher 41681629cbaSAlex Deucher union drm_amdgpu_gem_wait_idle { 41781629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_in in; 41881629cbaSAlex Deucher struct drm_amdgpu_gem_wait_idle_out out; 41981629cbaSAlex Deucher }; 42081629cbaSAlex Deucher 42181629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in { 422d7b1eeb2SMonk Liu /* Command submission handle 423d7b1eeb2SMonk Liu * handle equals 0 means none to wait for 424080b24ebSAlex Deucher * handle equals ~0ull means wait for the latest sequence number 425d7b1eeb2SMonk Liu */ 4262ce9dde0SMikko Rapeli __u64 handle; 427675da0ddSChristian König /** Absolute timeout to wait */ 4282ce9dde0SMikko Rapeli __u64 timeout; 4292ce9dde0SMikko Rapeli __u32 ip_type; 4302ce9dde0SMikko Rapeli __u32 ip_instance; 4312ce9dde0SMikko Rapeli __u32 ring; 4322ce9dde0SMikko Rapeli __u32 ctx_id; 43381629cbaSAlex Deucher }; 43481629cbaSAlex Deucher 43581629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out { 436675da0ddSChristian König /** CS status: 0 - CS completed, 1 - CS still busy */ 4372ce9dde0SMikko Rapeli __u64 status; 43881629cbaSAlex Deucher }; 43981629cbaSAlex Deucher 44081629cbaSAlex Deucher union drm_amdgpu_wait_cs { 44181629cbaSAlex Deucher struct drm_amdgpu_wait_cs_in in; 44281629cbaSAlex Deucher struct drm_amdgpu_wait_cs_out out; 44381629cbaSAlex Deucher }; 44481629cbaSAlex Deucher 445eef18a82SJunwei Zhang struct drm_amdgpu_fence { 446eef18a82SJunwei Zhang __u32 ctx_id; 447eef18a82SJunwei Zhang __u32 ip_type; 448eef18a82SJunwei Zhang __u32 ip_instance; 449eef18a82SJunwei Zhang __u32 ring; 450eef18a82SJunwei Zhang __u64 seq_no; 451eef18a82SJunwei Zhang }; 452eef18a82SJunwei Zhang 453eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in { 454eef18a82SJunwei Zhang /** This points to uint64_t * which points to fences */ 455eef18a82SJunwei Zhang __u64 fences; 456eef18a82SJunwei Zhang __u32 fence_count; 457eef18a82SJunwei Zhang __u32 wait_all; 458eef18a82SJunwei Zhang __u64 timeout_ns; 459eef18a82SJunwei Zhang }; 460eef18a82SJunwei Zhang 461eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out { 462eef18a82SJunwei Zhang __u32 status; 463eef18a82SJunwei Zhang __u32 first_signaled; 464eef18a82SJunwei Zhang }; 465eef18a82SJunwei Zhang 466eef18a82SJunwei Zhang union drm_amdgpu_wait_fences { 467eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_in in; 468eef18a82SJunwei Zhang struct drm_amdgpu_wait_fences_out out; 469eef18a82SJunwei Zhang }; 470eef18a82SJunwei Zhang 47181629cbaSAlex Deucher #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 472d8f65a23SMarek Olšák #define AMDGPU_GEM_OP_SET_PLACEMENT 1 47381629cbaSAlex Deucher 474675da0ddSChristian König /* Sets or returns a value associated with a buffer. */ 475675da0ddSChristian König struct drm_amdgpu_gem_op { 476675da0ddSChristian König /** GEM object handle */ 4772ce9dde0SMikko Rapeli __u32 handle; 478675da0ddSChristian König /** AMDGPU_GEM_OP_* */ 4792ce9dde0SMikko Rapeli __u32 op; 480675da0ddSChristian König /** Input or return value */ 4812ce9dde0SMikko Rapeli __u64 value; 482675da0ddSChristian König }; 483675da0ddSChristian König 48481629cbaSAlex Deucher #define AMDGPU_VA_OP_MAP 1 48581629cbaSAlex Deucher #define AMDGPU_VA_OP_UNMAP 2 486dc54d3d1SChristian König #define AMDGPU_VA_OP_CLEAR 3 48780f95c57SChristian König #define AMDGPU_VA_OP_REPLACE 4 48881629cbaSAlex Deucher 489fc220f65SChristian König /* Delay the page table update till the next CS */ 490fc220f65SChristian König #define AMDGPU_VM_DELAY_UPDATE (1 << 0) 491fc220f65SChristian König 49281629cbaSAlex Deucher /* Mapping flags */ 49381629cbaSAlex Deucher /* readable mapping */ 49481629cbaSAlex Deucher #define AMDGPU_VM_PAGE_READABLE (1 << 1) 49581629cbaSAlex Deucher /* writable mapping */ 49681629cbaSAlex Deucher #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) 49781629cbaSAlex Deucher /* executable mapping, new for VI */ 49881629cbaSAlex Deucher #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) 499b85891bdSJunwei Zhang /* partially resident texture */ 500b85891bdSJunwei Zhang #define AMDGPU_VM_PAGE_PRT (1 << 4) 50166e02bc3SAlex Xie /* MTYPE flags use bit 5 to 8 */ 50266e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_MASK (0xf << 5) 50366e02bc3SAlex Xie /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ 50466e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) 505130c8893SYong Zhao /* Use Non Coherent MTYPE instead of default MTYPE */ 50666e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_NC (1 << 5) 507130c8893SYong Zhao /* Use Write Combine MTYPE instead of default MTYPE */ 50866e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_WC (2 << 5) 509130c8893SYong Zhao /* Use Cache Coherent MTYPE instead of default MTYPE */ 51066e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_CC (3 << 5) 511130c8893SYong Zhao /* Use UnCached MTYPE instead of default MTYPE */ 51266e02bc3SAlex Xie #define AMDGPU_VM_MTYPE_UC (4 << 5) 513130c8893SYong Zhao /* Use Read Write MTYPE instead of default MTYPE */ 514484deaedSOak Zeng #define AMDGPU_VM_MTYPE_RW (5 << 5) 51581629cbaSAlex Deucher 51634b5f6a6SChristian König struct drm_amdgpu_gem_va { 517675da0ddSChristian König /** GEM object handle */ 5182ce9dde0SMikko Rapeli __u32 handle; 5192ce9dde0SMikko Rapeli __u32 _pad; 520675da0ddSChristian König /** AMDGPU_VA_OP_* */ 5212ce9dde0SMikko Rapeli __u32 operation; 522675da0ddSChristian König /** AMDGPU_VM_PAGE_* */ 5232ce9dde0SMikko Rapeli __u32 flags; 524675da0ddSChristian König /** va address to assign . Must be correctly aligned.*/ 5252ce9dde0SMikko Rapeli __u64 va_address; 526675da0ddSChristian König /** Specify offset inside of BO to assign. Must be correctly aligned.*/ 5272ce9dde0SMikko Rapeli __u64 offset_in_bo; 528675da0ddSChristian König /** Specify mapping size. Must be correctly aligned. */ 5292ce9dde0SMikko Rapeli __u64 map_size; 53081629cbaSAlex Deucher }; 53181629cbaSAlex Deucher 53281629cbaSAlex Deucher #define AMDGPU_HW_IP_GFX 0 53381629cbaSAlex Deucher #define AMDGPU_HW_IP_COMPUTE 1 53481629cbaSAlex Deucher #define AMDGPU_HW_IP_DMA 2 53581629cbaSAlex Deucher #define AMDGPU_HW_IP_UVD 3 53681629cbaSAlex Deucher #define AMDGPU_HW_IP_VCE 4 537a50798b6SLeo Liu #define AMDGPU_HW_IP_UVD_ENC 5 53866e236f1SLeo Liu #define AMDGPU_HW_IP_VCN_DEC 6 539fcfc5a90SLeo Liu #define AMDGPU_HW_IP_VCN_ENC 7 54081d35014SBoyuan Zhang #define AMDGPU_HW_IP_VCN_JPEG 8 54181d35014SBoyuan Zhang #define AMDGPU_HW_IP_NUM 9 54281629cbaSAlex Deucher 54381629cbaSAlex Deucher #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 54481629cbaSAlex Deucher 54581629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_IB 0x01 54681629cbaSAlex Deucher #define AMDGPU_CHUNK_ID_FENCE 0x02 5472b48d323SChristian König #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 548660e8558SDave Airlie #define AMDGPU_CHUNK_ID_SYNCOBJ_IN 0x04 549660e8558SDave Airlie #define AMDGPU_CHUNK_ID_SYNCOBJ_OUT 0x05 550964d0fbfSAndrey Grodzovsky #define AMDGPU_CHUNK_ID_BO_HANDLES 0x06 55167dd1a36SAndrey Grodzovsky #define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07 5522624dd15SChunming Zhou #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08 5532624dd15SChunming Zhou #define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09 554675da0ddSChristian König 55581629cbaSAlex Deucher struct drm_amdgpu_cs_chunk { 5562ce9dde0SMikko Rapeli __u32 chunk_id; 5572ce9dde0SMikko Rapeli __u32 length_dw; 5582ce9dde0SMikko Rapeli __u64 chunk_data; 55981629cbaSAlex Deucher }; 56081629cbaSAlex Deucher 56181629cbaSAlex Deucher struct drm_amdgpu_cs_in { 56281629cbaSAlex Deucher /** Rendering context id */ 5632ce9dde0SMikko Rapeli __u32 ctx_id; 56481629cbaSAlex Deucher /** Handle of resource list associated with CS */ 5652ce9dde0SMikko Rapeli __u32 bo_list_handle; 5662ce9dde0SMikko Rapeli __u32 num_chunks; 567e90c2b21SLuben Tuikov __u32 flags; 5682ce9dde0SMikko Rapeli /** this points to __u64 * which point to cs chunks */ 5692ce9dde0SMikko Rapeli __u64 chunks; 57081629cbaSAlex Deucher }; 57181629cbaSAlex Deucher 57281629cbaSAlex Deucher struct drm_amdgpu_cs_out { 5732ce9dde0SMikko Rapeli __u64 handle; 57481629cbaSAlex Deucher }; 57581629cbaSAlex Deucher 57681629cbaSAlex Deucher union drm_amdgpu_cs { 57781629cbaSAlex Deucher struct drm_amdgpu_cs_in in; 57881629cbaSAlex Deucher struct drm_amdgpu_cs_out out; 57981629cbaSAlex Deucher }; 58081629cbaSAlex Deucher 58181629cbaSAlex Deucher /* Specify flags to be used for IB */ 58281629cbaSAlex Deucher 58381629cbaSAlex Deucher /* This IB should be submitted to CE */ 58481629cbaSAlex Deucher #define AMDGPU_IB_FLAG_CE (1<<0) 58581629cbaSAlex Deucher 586ed834af2SMonk Liu /* Preamble flag, which means the IB could be dropped if no context switch */ 587cab6d57cSJammy Zhou #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) 588aa2bdb24SJammy Zhou 58971aec257SMonk Liu /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ 59071aec257SMonk Liu #define AMDGPU_IB_FLAG_PREEMPT (1<<2) 59171aec257SMonk Liu 592d240cd9eSMarek Olšák /* The IB fence should do the L2 writeback but not invalidate any shader 593d240cd9eSMarek Olšák * caches (L2/vL1/sL1/I$). */ 594d240cd9eSMarek Olšák #define AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE (1 << 3) 595d240cd9eSMarek Olšák 59641cca166SMarek Olšák /* Set GDS_COMPUTE_MAX_WAVE_ID = DEFAULT before PACKET3_INDIRECT_BUFFER. 59741cca166SMarek Olšák * This will reset wave ID counters for the IB. 59841cca166SMarek Olšák */ 59941cca166SMarek Olšák #define AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID (1 << 4) 60041cca166SMarek Olšák 6010bb5d5b0SLuben Tuikov /* Flag the IB as secure (TMZ) 6020bb5d5b0SLuben Tuikov */ 6030bb5d5b0SLuben Tuikov #define AMDGPU_IB_FLAGS_SECURE (1 << 5) 6040bb5d5b0SLuben Tuikov 60543c8546bSAndrey Grodzovsky /* Tell KMD to flush and invalidate caches 60643c8546bSAndrey Grodzovsky */ 60743c8546bSAndrey Grodzovsky #define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6) 60843c8546bSAndrey Grodzovsky 60981629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib { 6102ce9dde0SMikko Rapeli __u32 _pad; 611675da0ddSChristian König /** AMDGPU_IB_FLAG_* */ 6122ce9dde0SMikko Rapeli __u32 flags; 613675da0ddSChristian König /** Virtual address to begin IB execution */ 6142ce9dde0SMikko Rapeli __u64 va_start; 615675da0ddSChristian König /** Size of submission */ 6162ce9dde0SMikko Rapeli __u32 ib_bytes; 617675da0ddSChristian König /** HW IP to submit to */ 6182ce9dde0SMikko Rapeli __u32 ip_type; 619675da0ddSChristian König /** HW IP index of the same type to submit to */ 6202ce9dde0SMikko Rapeli __u32 ip_instance; 621675da0ddSChristian König /** Ring index to submit to */ 6222ce9dde0SMikko Rapeli __u32 ring; 62381629cbaSAlex Deucher }; 62481629cbaSAlex Deucher 6252b48d323SChristian König struct drm_amdgpu_cs_chunk_dep { 6262ce9dde0SMikko Rapeli __u32 ip_type; 6272ce9dde0SMikko Rapeli __u32 ip_instance; 6282ce9dde0SMikko Rapeli __u32 ring; 6292ce9dde0SMikko Rapeli __u32 ctx_id; 6302ce9dde0SMikko Rapeli __u64 handle; 6312b48d323SChristian König }; 6322b48d323SChristian König 63381629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence { 6342ce9dde0SMikko Rapeli __u32 handle; 6352ce9dde0SMikko Rapeli __u32 offset; 63681629cbaSAlex Deucher }; 63781629cbaSAlex Deucher 638660e8558SDave Airlie struct drm_amdgpu_cs_chunk_sem { 639660e8558SDave Airlie __u32 handle; 640660e8558SDave Airlie }; 641660e8558SDave Airlie 6422624dd15SChunming Zhou struct drm_amdgpu_cs_chunk_syncobj { 6432624dd15SChunming Zhou __u32 handle; 6442624dd15SChunming Zhou __u32 flags; 6452624dd15SChunming Zhou __u64 point; 6462624dd15SChunming Zhou }; 6472624dd15SChunming Zhou 6487ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ 0 6497ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD 1 6507ca24cf2SMarek Olšák #define AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD 2 6517ca24cf2SMarek Olšák 6527ca24cf2SMarek Olšák union drm_amdgpu_fence_to_handle { 6537ca24cf2SMarek Olšák struct { 6547ca24cf2SMarek Olšák struct drm_amdgpu_fence fence; 6557ca24cf2SMarek Olšák __u32 what; 65656e0349fSDave Airlie __u32 pad; 6577ca24cf2SMarek Olšák } in; 6587ca24cf2SMarek Olšák struct { 6597ca24cf2SMarek Olšák __u32 handle; 6607ca24cf2SMarek Olšák } out; 6617ca24cf2SMarek Olšák }; 6627ca24cf2SMarek Olšák 66381629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_data { 66481629cbaSAlex Deucher union { 66581629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_ib ib_data; 66681629cbaSAlex Deucher struct drm_amdgpu_cs_chunk_fence fence_data; 66781629cbaSAlex Deucher }; 66881629cbaSAlex Deucher }; 66981629cbaSAlex Deucher 67081629cbaSAlex Deucher /** 67181629cbaSAlex Deucher * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU 67281629cbaSAlex Deucher * 67381629cbaSAlex Deucher */ 67481629cbaSAlex Deucher #define AMDGPU_IDS_FLAGS_FUSION 0x1 675aafcafa0SMonk Liu #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 67616c642ecSPierre-Eric Pelloux-Prayer #define AMDGPU_IDS_FLAGS_TMZ 0x4 67781629cbaSAlex Deucher 67881629cbaSAlex Deucher /* indicate if acceleration can be working */ 67981629cbaSAlex Deucher #define AMDGPU_INFO_ACCEL_WORKING 0x00 68081629cbaSAlex Deucher /* get the crtc_id from the mode object id? */ 68181629cbaSAlex Deucher #define AMDGPU_INFO_CRTC_FROM_ID 0x01 68281629cbaSAlex Deucher /* query hw IP info */ 68381629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_INFO 0x02 68481629cbaSAlex Deucher /* query hw IP instance count for the specified type */ 68581629cbaSAlex Deucher #define AMDGPU_INFO_HW_IP_COUNT 0x03 68681629cbaSAlex Deucher /* timestamp for GL_ARB_timer_query */ 68781629cbaSAlex Deucher #define AMDGPU_INFO_TIMESTAMP 0x05 68881629cbaSAlex Deucher /* Query the firmware version */ 68981629cbaSAlex Deucher #define AMDGPU_INFO_FW_VERSION 0x0e 69081629cbaSAlex Deucher /* Subquery id: Query VCE firmware version */ 69181629cbaSAlex Deucher #define AMDGPU_INFO_FW_VCE 0x1 69281629cbaSAlex Deucher /* Subquery id: Query UVD firmware version */ 69381629cbaSAlex Deucher #define AMDGPU_INFO_FW_UVD 0x2 69481629cbaSAlex Deucher /* Subquery id: Query GMC firmware version */ 69581629cbaSAlex Deucher #define AMDGPU_INFO_FW_GMC 0x03 69681629cbaSAlex Deucher /* Subquery id: Query GFX ME firmware version */ 69781629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_ME 0x04 69881629cbaSAlex Deucher /* Subquery id: Query GFX PFP firmware version */ 69981629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_PFP 0x05 70081629cbaSAlex Deucher /* Subquery id: Query GFX CE firmware version */ 70181629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_CE 0x06 70281629cbaSAlex Deucher /* Subquery id: Query GFX RLC firmware version */ 70381629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_RLC 0x07 70481629cbaSAlex Deucher /* Subquery id: Query GFX MEC firmware version */ 70581629cbaSAlex Deucher #define AMDGPU_INFO_FW_GFX_MEC 0x08 70681629cbaSAlex Deucher /* Subquery id: Query SMC firmware version */ 70781629cbaSAlex Deucher #define AMDGPU_INFO_FW_SMC 0x0a 70881629cbaSAlex Deucher /* Subquery id: Query SDMA firmware version */ 70981629cbaSAlex Deucher #define AMDGPU_INFO_FW_SDMA 0x0b 7106a7ed07eSHuang Rui /* Subquery id: Query PSP SOS firmware version */ 7116a7ed07eSHuang Rui #define AMDGPU_INFO_FW_SOS 0x0c 7126a7ed07eSHuang Rui /* Subquery id: Query PSP ASD firmware version */ 7136a7ed07eSHuang Rui #define AMDGPU_INFO_FW_ASD 0x0d 7143ac952b1SAlex Deucher /* Subquery id: Query VCN firmware version */ 7153ac952b1SAlex Deucher #define AMDGPU_INFO_FW_VCN 0x0e 716621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLC firmware version */ 717621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL 0x0f 718621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLG firmware version */ 719621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM 0x10 720621a6318SHuang Rui /* Subquery id: Query GFX RLC SRLS firmware version */ 721621a6318SHuang Rui #define AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM 0x11 7224d11b4b2SDavid Francis /* Subquery id: Query DMCU firmware version */ 7234d11b4b2SDavid Francis #define AMDGPU_INFO_FW_DMCU 0x12 7249b9ca62dSxinhui pan #define AMDGPU_INFO_FW_TA 0x13 725976e51a7SNicholas Kazlauskas /* Subquery id: Query DMCUB firmware version */ 726976e51a7SNicholas Kazlauskas #define AMDGPU_INFO_FW_DMCUB 0x14 727976e51a7SNicholas Kazlauskas 72881629cbaSAlex Deucher /* number of bytes moved for TTM migration */ 72981629cbaSAlex Deucher #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f 73081629cbaSAlex Deucher /* the used VRAM size */ 73181629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_USAGE 0x10 73281629cbaSAlex Deucher /* the used GTT size */ 73381629cbaSAlex Deucher #define AMDGPU_INFO_GTT_USAGE 0x11 73481629cbaSAlex Deucher /* Information about GDS, etc. resource configuration */ 73581629cbaSAlex Deucher #define AMDGPU_INFO_GDS_CONFIG 0x13 73681629cbaSAlex Deucher /* Query information about VRAM and GTT domains */ 73781629cbaSAlex Deucher #define AMDGPU_INFO_VRAM_GTT 0x14 73881629cbaSAlex Deucher /* Query information about register in MMR address space*/ 73981629cbaSAlex Deucher #define AMDGPU_INFO_READ_MMR_REG 0x15 74081629cbaSAlex Deucher /* Query information about device: rev id, family, etc. */ 74181629cbaSAlex Deucher #define AMDGPU_INFO_DEV_INFO 0x16 74281629cbaSAlex Deucher /* visible vram usage */ 74381629cbaSAlex Deucher #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 74483a59b63SMarek Olšák /* number of TTM buffer evictions */ 74583a59b63SMarek Olšák #define AMDGPU_INFO_NUM_EVICTIONS 0x18 746e0adf6c8SJunwei Zhang /* Query memory about VRAM and GTT domains */ 747e0adf6c8SJunwei Zhang #define AMDGPU_INFO_MEMORY 0x19 748bbe87974SAlex Deucher /* Query vce clock table */ 749bbe87974SAlex Deucher #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A 75040ee5888SEvan Quan /* Query vbios related information */ 75140ee5888SEvan Quan #define AMDGPU_INFO_VBIOS 0x1B 75240ee5888SEvan Quan /* Subquery id: Query vbios size */ 75340ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_SIZE 0x1 75440ee5888SEvan Quan /* Subquery id: Query vbios image */ 75540ee5888SEvan Quan #define AMDGPU_INFO_VBIOS_IMAGE 0x2 75644879b62SArindam Nath /* Query UVD handles */ 75744879b62SArindam Nath #define AMDGPU_INFO_NUM_HANDLES 0x1C 7585ebbac4bSAlex Deucher /* Query sensor related information */ 7595ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR 0x1D 7605ebbac4bSAlex Deucher /* Subquery id: Query GPU shader clock */ 7615ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 7625ebbac4bSAlex Deucher /* Subquery id: Query GPU memory clock */ 7635ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 7645ebbac4bSAlex Deucher /* Subquery id: Query GPU temperature */ 7655ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 7665ebbac4bSAlex Deucher /* Subquery id: Query GPU load */ 7675ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 7685ebbac4bSAlex Deucher /* Subquery id: Query average GPU power */ 7695ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 7705ebbac4bSAlex Deucher /* Subquery id: Query northbridge voltage */ 7715ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDNB 0x6 7725ebbac4bSAlex Deucher /* Subquery id: Query graphics voltage */ 7735ebbac4bSAlex Deucher #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 77460bbade2SRex Zhu /* Subquery id: Query GPU stable pstate shader clock */ 77560bbade2SRex Zhu #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8 77660bbade2SRex Zhu /* Subquery id: Query GPU stable pstate memory clock */ 77760bbade2SRex Zhu #define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9 77868e2c5ffSMarek Olšák /* Number of VRAM page faults on CPU access. */ 77968e2c5ffSMarek Olšák #define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E 7801f7251b7SChristian König #define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F 7815cb77114Sxinhui pan /* query ras mask of enabled features*/ 7825cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20 7835cb77114Sxinhui pan 7845cb77114Sxinhui pan /* RAS MASK: UMC (VRAM) */ 7855cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0) 7865cb77114Sxinhui pan /* RAS MASK: SDMA */ 7875cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SDMA (1 << 1) 7885cb77114Sxinhui pan /* RAS MASK: GFX */ 7895cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_GFX (1 << 2) 7905cb77114Sxinhui pan /* RAS MASK: MMHUB */ 7915cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MMHUB (1 << 3) 7925cb77114Sxinhui pan /* RAS MASK: ATHUB */ 7935cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_ATHUB (1 << 4) 7945cb77114Sxinhui pan /* RAS MASK: PCIE */ 7955cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_PCIE (1 << 5) 7965cb77114Sxinhui pan /* RAS MASK: HDP */ 7975cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_HDP (1 << 6) 7985cb77114Sxinhui pan /* RAS MASK: XGMI */ 7995cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_XGMI (1 << 7) 8005cb77114Sxinhui pan /* RAS MASK: DF */ 8015cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_DF (1 << 8) 8025cb77114Sxinhui pan /* RAS MASK: SMN */ 8035cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SMN (1 << 9) 8045cb77114Sxinhui pan /* RAS MASK: SEM */ 8055cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_SEM (1 << 10) 8065cb77114Sxinhui pan /* RAS MASK: MP0 */ 8075cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MP0 (1 << 11) 8085cb77114Sxinhui pan /* RAS MASK: MP1 */ 8095cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12) 8105cb77114Sxinhui pan /* RAS MASK: FUSE */ 8115cb77114Sxinhui pan #define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13) 81281629cbaSAlex Deucher 81381629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 81481629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff 81581629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 81681629cbaSAlex Deucher #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff 81781629cbaSAlex Deucher 818000cab9aSHuang Rui struct drm_amdgpu_query_fw { 819000cab9aSHuang Rui /** AMDGPU_INFO_FW_* */ 820000cab9aSHuang Rui __u32 fw_type; 821000cab9aSHuang Rui /** 822000cab9aSHuang Rui * Index of the IP if there are more IPs of 823000cab9aSHuang Rui * the same type. 824000cab9aSHuang Rui */ 825000cab9aSHuang Rui __u32 ip_instance; 826000cab9aSHuang Rui /** 827000cab9aSHuang Rui * Index of the engine. Whether this is used depends 828000cab9aSHuang Rui * on the firmware type. (e.g. MEC, SDMA) 829000cab9aSHuang Rui */ 830000cab9aSHuang Rui __u32 index; 831000cab9aSHuang Rui __u32 _pad; 832000cab9aSHuang Rui }; 833000cab9aSHuang Rui 83481629cbaSAlex Deucher /* Input structure for the INFO ioctl */ 83581629cbaSAlex Deucher struct drm_amdgpu_info { 83681629cbaSAlex Deucher /* Where the return value will be stored */ 8372ce9dde0SMikko Rapeli __u64 return_pointer; 83881629cbaSAlex Deucher /* The size of the return value. Just like "size" in "snprintf", 83981629cbaSAlex Deucher * it limits how many bytes the kernel can write. */ 8402ce9dde0SMikko Rapeli __u32 return_size; 84181629cbaSAlex Deucher /* The query request id. */ 8422ce9dde0SMikko Rapeli __u32 query; 84381629cbaSAlex Deucher 84481629cbaSAlex Deucher union { 84581629cbaSAlex Deucher struct { 8462ce9dde0SMikko Rapeli __u32 id; 8472ce9dde0SMikko Rapeli __u32 _pad; 84881629cbaSAlex Deucher } mode_crtc; 84981629cbaSAlex Deucher 85081629cbaSAlex Deucher struct { 85181629cbaSAlex Deucher /** AMDGPU_HW_IP_* */ 8522ce9dde0SMikko Rapeli __u32 type; 85381629cbaSAlex Deucher /** 854675da0ddSChristian König * Index of the IP if there are more IPs of the same 855675da0ddSChristian König * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. 85681629cbaSAlex Deucher */ 8572ce9dde0SMikko Rapeli __u32 ip_instance; 85881629cbaSAlex Deucher } query_hw_ip; 85981629cbaSAlex Deucher 86081629cbaSAlex Deucher struct { 8612ce9dde0SMikko Rapeli __u32 dword_offset; 862675da0ddSChristian König /** number of registers to read */ 8632ce9dde0SMikko Rapeli __u32 count; 8642ce9dde0SMikko Rapeli __u32 instance; 865675da0ddSChristian König /** For future use, no flags defined so far */ 8662ce9dde0SMikko Rapeli __u32 flags; 86781629cbaSAlex Deucher } read_mmr_reg; 86881629cbaSAlex Deucher 869000cab9aSHuang Rui struct drm_amdgpu_query_fw query_fw; 87040ee5888SEvan Quan 87140ee5888SEvan Quan struct { 87240ee5888SEvan Quan __u32 type; 87340ee5888SEvan Quan __u32 offset; 87440ee5888SEvan Quan } vbios_info; 8755ebbac4bSAlex Deucher 8765ebbac4bSAlex Deucher struct { 8775ebbac4bSAlex Deucher __u32 type; 8785ebbac4bSAlex Deucher } sensor_info; 87981629cbaSAlex Deucher }; 88081629cbaSAlex Deucher }; 88181629cbaSAlex Deucher 88281629cbaSAlex Deucher struct drm_amdgpu_info_gds { 88381629cbaSAlex Deucher /** GDS GFX partition size */ 8842ce9dde0SMikko Rapeli __u32 gds_gfx_partition_size; 88581629cbaSAlex Deucher /** GDS compute partition size */ 8862ce9dde0SMikko Rapeli __u32 compute_partition_size; 88781629cbaSAlex Deucher /** total GDS memory size */ 8882ce9dde0SMikko Rapeli __u32 gds_total_size; 88981629cbaSAlex Deucher /** GWS size per GFX partition */ 8902ce9dde0SMikko Rapeli __u32 gws_per_gfx_partition; 89181629cbaSAlex Deucher /** GSW size per compute partition */ 8922ce9dde0SMikko Rapeli __u32 gws_per_compute_partition; 89381629cbaSAlex Deucher /** OA size per GFX partition */ 8942ce9dde0SMikko Rapeli __u32 oa_per_gfx_partition; 89581629cbaSAlex Deucher /** OA size per compute partition */ 8962ce9dde0SMikko Rapeli __u32 oa_per_compute_partition; 8972ce9dde0SMikko Rapeli __u32 _pad; 89881629cbaSAlex Deucher }; 89981629cbaSAlex Deucher 90081629cbaSAlex Deucher struct drm_amdgpu_info_vram_gtt { 9012ce9dde0SMikko Rapeli __u64 vram_size; 9022ce9dde0SMikko Rapeli __u64 vram_cpu_accessible_size; 9032ce9dde0SMikko Rapeli __u64 gtt_size; 90481629cbaSAlex Deucher }; 90581629cbaSAlex Deucher 906e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info { 907e0adf6c8SJunwei Zhang /** max. physical memory */ 908e0adf6c8SJunwei Zhang __u64 total_heap_size; 909e0adf6c8SJunwei Zhang 910e0adf6c8SJunwei Zhang /** Theoretical max. available memory in the given heap */ 911e0adf6c8SJunwei Zhang __u64 usable_heap_size; 912e0adf6c8SJunwei Zhang 913e0adf6c8SJunwei Zhang /** 914e0adf6c8SJunwei Zhang * Number of bytes allocated in the heap. This includes all processes 915e0adf6c8SJunwei Zhang * and private allocations in the kernel. It changes when new buffers 916e0adf6c8SJunwei Zhang * are allocated, freed, and moved. It cannot be larger than 917e0adf6c8SJunwei Zhang * heap_size. 918e0adf6c8SJunwei Zhang */ 919e0adf6c8SJunwei Zhang __u64 heap_usage; 920e0adf6c8SJunwei Zhang 921e0adf6c8SJunwei Zhang /** 922e0adf6c8SJunwei Zhang * Theoretical possible max. size of buffer which 923e0adf6c8SJunwei Zhang * could be allocated in the given heap 924e0adf6c8SJunwei Zhang */ 925e0adf6c8SJunwei Zhang __u64 max_allocation; 9269f6163e7SJunwei Zhang }; 9279f6163e7SJunwei Zhang 928e0adf6c8SJunwei Zhang struct drm_amdgpu_memory_info { 929e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info vram; 930e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info cpu_accessible_vram; 931e0adf6c8SJunwei Zhang struct drm_amdgpu_heap_info gtt; 932cfa32556SJunwei Zhang }; 933cfa32556SJunwei Zhang 93481629cbaSAlex Deucher struct drm_amdgpu_info_firmware { 9352ce9dde0SMikko Rapeli __u32 ver; 9362ce9dde0SMikko Rapeli __u32 feature; 93781629cbaSAlex Deucher }; 93881629cbaSAlex Deucher 93981c59f54SKen Wang #define AMDGPU_VRAM_TYPE_UNKNOWN 0 94081c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR1 1 94181c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR2 2 94281c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR3 3 94381c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR4 4 94481c59f54SKen Wang #define AMDGPU_VRAM_TYPE_GDDR5 5 94581c59f54SKen Wang #define AMDGPU_VRAM_TYPE_HBM 6 94681c59f54SKen Wang #define AMDGPU_VRAM_TYPE_DDR3 7 9471e09b053SHawking Zhang #define AMDGPU_VRAM_TYPE_DDR4 8 948d67383e6SHuang Rui #define AMDGPU_VRAM_TYPE_GDDR6 9 949*1e483203SHuang Rui #define AMDGPU_VRAM_TYPE_DDR5 10 95081c59f54SKen Wang 95181629cbaSAlex Deucher struct drm_amdgpu_info_device { 95281629cbaSAlex Deucher /** PCI Device ID */ 9532ce9dde0SMikko Rapeli __u32 device_id; 95481629cbaSAlex Deucher /** Internal chip revision: A0, A1, etc.) */ 9552ce9dde0SMikko Rapeli __u32 chip_rev; 9562ce9dde0SMikko Rapeli __u32 external_rev; 95781629cbaSAlex Deucher /** Revision id in PCI Config space */ 9582ce9dde0SMikko Rapeli __u32 pci_rev; 9592ce9dde0SMikko Rapeli __u32 family; 9602ce9dde0SMikko Rapeli __u32 num_shader_engines; 9612ce9dde0SMikko Rapeli __u32 num_shader_arrays_per_engine; 962675da0ddSChristian König /* in KHz */ 9632ce9dde0SMikko Rapeli __u32 gpu_counter_freq; 9642ce9dde0SMikko Rapeli __u64 max_engine_clock; 9652ce9dde0SMikko Rapeli __u64 max_memory_clock; 96681629cbaSAlex Deucher /* cu information */ 9672ce9dde0SMikko Rapeli __u32 cu_active_number; 968dbfe85eaSFlora Cui /* NOTE: cu_ao_mask is INVALID, DON'T use it */ 9692ce9dde0SMikko Rapeli __u32 cu_ao_mask; 9702ce9dde0SMikko Rapeli __u32 cu_bitmap[4][4]; 97181629cbaSAlex Deucher /** Render backend pipe mask. One render backend is CB+DB. */ 9722ce9dde0SMikko Rapeli __u32 enabled_rb_pipes_mask; 9732ce9dde0SMikko Rapeli __u32 num_rb_pipes; 9742ce9dde0SMikko Rapeli __u32 num_hw_gfx_contexts; 9752ce9dde0SMikko Rapeli __u32 _pad; 9762ce9dde0SMikko Rapeli __u64 ids_flags; 97781629cbaSAlex Deucher /** Starting virtual address for UMDs. */ 9782ce9dde0SMikko Rapeli __u64 virtual_address_offset; 97902b70c8cSJammy Zhou /** The maximum virtual address */ 9802ce9dde0SMikko Rapeli __u64 virtual_address_max; 98181629cbaSAlex Deucher /** Required alignment of virtual addresses. */ 9822ce9dde0SMikko Rapeli __u32 virtual_address_alignment; 98381629cbaSAlex Deucher /** Page table entry - fragment size */ 9842ce9dde0SMikko Rapeli __u32 pte_fragment_size; 9852ce9dde0SMikko Rapeli __u32 gart_page_size; 986a101a899SKen Wang /** constant engine ram size*/ 9872ce9dde0SMikko Rapeli __u32 ce_ram_size; 988cab6d57cSJammy Zhou /** video memory type info*/ 9892ce9dde0SMikko Rapeli __u32 vram_type; 99081c59f54SKen Wang /** video memory bit width*/ 9912ce9dde0SMikko Rapeli __u32 vram_bit_width; 992fa92754eSLeo Liu /* vce harvesting instance */ 9932ce9dde0SMikko Rapeli __u32 vce_harvest_config; 994df6e2c4aSJunwei Zhang /* gfx double offchip LDS buffers */ 995df6e2c4aSJunwei Zhang __u32 gc_double_offchip_lds_buf; 996bce23e00SAlex Deucher /* NGG Primitive Buffer */ 997bce23e00SAlex Deucher __u64 prim_buf_gpu_addr; 998bce23e00SAlex Deucher /* NGG Position Buffer */ 999bce23e00SAlex Deucher __u64 pos_buf_gpu_addr; 1000bce23e00SAlex Deucher /* NGG Control Sideband */ 1001bce23e00SAlex Deucher __u64 cntl_sb_buf_gpu_addr; 1002bce23e00SAlex Deucher /* NGG Parameter Cache */ 1003bce23e00SAlex Deucher __u64 param_buf_gpu_addr; 1004408bfe7cSJunwei Zhang __u32 prim_buf_size; 1005408bfe7cSJunwei Zhang __u32 pos_buf_size; 1006408bfe7cSJunwei Zhang __u32 cntl_sb_buf_size; 1007408bfe7cSJunwei Zhang __u32 param_buf_size; 1008408bfe7cSJunwei Zhang /* wavefront size*/ 1009408bfe7cSJunwei Zhang __u32 wave_front_size; 1010408bfe7cSJunwei Zhang /* shader visible vgprs*/ 1011408bfe7cSJunwei Zhang __u32 num_shader_visible_vgprs; 1012408bfe7cSJunwei Zhang /* CU per shader array*/ 1013408bfe7cSJunwei Zhang __u32 num_cu_per_sh; 1014408bfe7cSJunwei Zhang /* number of tcc blocks*/ 1015408bfe7cSJunwei Zhang __u32 num_tcc_blocks; 1016408bfe7cSJunwei Zhang /* gs vgt table depth*/ 1017408bfe7cSJunwei Zhang __u32 gs_vgt_table_depth; 1018408bfe7cSJunwei Zhang /* gs primitive buffer depth*/ 1019408bfe7cSJunwei Zhang __u32 gs_prim_buffer_depth; 1020408bfe7cSJunwei Zhang /* max gs wavefront per vgt*/ 1021408bfe7cSJunwei Zhang __u32 max_gs_waves_per_vgt; 1022408bfe7cSJunwei Zhang __u32 _pad1; 1023dbfe85eaSFlora Cui /* always on cu bitmap */ 1024dbfe85eaSFlora Cui __u32 cu_ao_bitmap[4][4]; 10255b565e0eSChristian König /** Starting high virtual address for UMDs. */ 10265b565e0eSChristian König __u64 high_va_offset; 10275b565e0eSChristian König /** The maximum high virtual address */ 10285b565e0eSChristian König __u64 high_va_max; 102922e96fa6SHawking Zhang /* gfx10 pa_sc_tile_steering_override */ 103022e96fa6SHawking Zhang __u32 pa_sc_tile_steering_override; 1031cf21e76aSMarek Olšák /* disabled TCCs */ 1032cf21e76aSMarek Olšák __u64 tcc_disabled_mask; 103381629cbaSAlex Deucher }; 103481629cbaSAlex Deucher 103581629cbaSAlex Deucher struct drm_amdgpu_info_hw_ip { 103681629cbaSAlex Deucher /** Version of h/w IP */ 10372ce9dde0SMikko Rapeli __u32 hw_ip_version_major; 10382ce9dde0SMikko Rapeli __u32 hw_ip_version_minor; 103981629cbaSAlex Deucher /** Capabilities */ 10402ce9dde0SMikko Rapeli __u64 capabilities_flags; 104171062f43SKen Wang /** command buffer address start alignment*/ 10422ce9dde0SMikko Rapeli __u32 ib_start_alignment; 104371062f43SKen Wang /** command buffer size alignment*/ 10442ce9dde0SMikko Rapeli __u32 ib_size_alignment; 104581629cbaSAlex Deucher /** Bitmask of available rings. Bit 0 means ring 0, etc. */ 10462ce9dde0SMikko Rapeli __u32 available_rings; 10472ce9dde0SMikko Rapeli __u32 _pad; 104881629cbaSAlex Deucher }; 104981629cbaSAlex Deucher 105044879b62SArindam Nath struct drm_amdgpu_info_num_handles { 105144879b62SArindam Nath /** Max handles as supported by firmware for UVD */ 105244879b62SArindam Nath __u32 uvd_max_handles; 105344879b62SArindam Nath /** Handles currently in use for UVD */ 105444879b62SArindam Nath __u32 uvd_used_handles; 105544879b62SArindam Nath }; 105644879b62SArindam Nath 1057bbe87974SAlex Deucher #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 1058bbe87974SAlex Deucher 1059bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry { 1060bbe87974SAlex Deucher /** System clock */ 1061bbe87974SAlex Deucher __u32 sclk; 1062bbe87974SAlex Deucher /** Memory clock */ 1063bbe87974SAlex Deucher __u32 mclk; 1064bbe87974SAlex Deucher /** VCE clock */ 1065bbe87974SAlex Deucher __u32 eclk; 1066bbe87974SAlex Deucher __u32 pad; 1067bbe87974SAlex Deucher }; 1068bbe87974SAlex Deucher 1069bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table { 1070bbe87974SAlex Deucher struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; 1071bbe87974SAlex Deucher __u32 num_valid_entries; 1072bbe87974SAlex Deucher __u32 pad; 1073bbe87974SAlex Deucher }; 1074bbe87974SAlex Deucher 107581629cbaSAlex Deucher /* 107681629cbaSAlex Deucher * Supported GPU families 107781629cbaSAlex Deucher */ 107881629cbaSAlex Deucher #define AMDGPU_FAMILY_UNKNOWN 0 1079295d0dafSKen Wang #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ 108081629cbaSAlex Deucher #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ 108181629cbaSAlex Deucher #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ 108281629cbaSAlex Deucher #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ 108339bb0c92SSamuel Li #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ 1084a8f1f1ceSAlex Deucher #define AMDGPU_FAMILY_AI 141 /* Vega10 */ 10852ca8a5d2SChunming Zhou #define AMDGPU_FAMILY_RV 142 /* Raven */ 1086107c34bcSHuang Rui #define AMDGPU_FAMILY_NV 143 /* Navi10 */ 1087f7b2cdb2SHuang Rui #define AMDGPU_FAMILY_VGH 144 /* Van Gogh */ 108881629cbaSAlex Deucher 1089cfa7152fSEmil Velikov #if defined(__cplusplus) 1090cfa7152fSEmil Velikov } 1091cfa7152fSEmil Velikov #endif 1092cfa7152fSEmil Velikov 109381629cbaSAlex Deucher #endif 1094