1 /******************************************************************************* 2 3 Header file for stmmac platform data 4 5 Copyright (C) 2009 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 *******************************************************************************/ 25 26 #ifndef __STMMAC_PLATFORM_DATA 27 #define __STMMAC_PLATFORM_DATA 28 29 #include <linux/platform_device.h> 30 31 #define STMMAC_RX_COE_NONE 0 32 #define STMMAC_RX_COE_TYPE1 1 33 #define STMMAC_RX_COE_TYPE2 2 34 35 /* Define the macros for CSR clock range parameters to be passed by 36 * platform code. 37 * This could also be configured at run time using CPU freq framework. */ 38 39 /* MDC Clock Selection define*/ 40 #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ 41 #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ 42 #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ 43 #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ 44 #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ 45 #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ 46 47 /* The MDC clock could be set higher than the IEEE 802.3 48 * specified frequency limit 0f 2.5 MHz, by programming a clock divider 49 * of value different than the above defined values. The resultant MDIO 50 * clock frequency of 12.5 MHz is applicable for the interfacing chips 51 * supporting higher MDC clocks. 52 * The MDC clock selection macros need to be defined for MDC clock rate 53 * of 12.5 MHz, corresponding to the following selection. 54 */ 55 #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ 56 #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ 57 #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ 58 #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ 59 #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ 60 #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ 61 #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ 62 #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ 63 64 /* AXI DMA Burst length supported */ 65 #define DMA_AXI_BLEN_4 (1 << 1) 66 #define DMA_AXI_BLEN_8 (1 << 2) 67 #define DMA_AXI_BLEN_16 (1 << 3) 68 #define DMA_AXI_BLEN_32 (1 << 4) 69 #define DMA_AXI_BLEN_64 (1 << 5) 70 #define DMA_AXI_BLEN_128 (1 << 6) 71 #define DMA_AXI_BLEN_256 (1 << 7) 72 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \ 73 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ 74 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) 75 76 /* Platfrom data for platform device structure's platform_data field */ 77 78 struct stmmac_mdio_bus_data { 79 int (*phy_reset)(void *priv); 80 unsigned int phy_mask; 81 int *irqs; 82 int probed_phy_irq; 83 #ifdef CONFIG_OF 84 int reset_gpio, active_low; 85 u32 delays[3]; 86 #endif 87 }; 88 89 struct stmmac_dma_cfg { 90 int pbl; 91 int txpbl; 92 int rxpbl; 93 bool pblx8; 94 int fixed_burst; 95 int mixed_burst; 96 bool aal; 97 }; 98 99 #define AXI_BLEN 7 100 struct stmmac_axi { 101 bool axi_lpi_en; 102 bool axi_xit_frm; 103 u32 axi_wr_osr_lmt; 104 u32 axi_rd_osr_lmt; 105 bool axi_kbbe; 106 bool axi_axi_all; 107 u32 axi_blen[AXI_BLEN]; 108 bool axi_fb; 109 bool axi_mb; 110 bool axi_rb; 111 }; 112 113 struct plat_stmmacenet_data { 114 int bus_id; 115 int phy_addr; 116 int interface; 117 struct stmmac_mdio_bus_data *mdio_bus_data; 118 struct device_node *phy_node; 119 struct device_node *mdio_node; 120 struct stmmac_dma_cfg *dma_cfg; 121 int clk_csr; 122 int has_gmac; 123 int enh_desc; 124 int tx_coe; 125 int rx_coe; 126 int bugged_jumbo; 127 int pmt; 128 int force_sf_dma_mode; 129 int force_thresh_dma_mode; 130 int riwt_off; 131 int max_speed; 132 int maxmtu; 133 int multicast_filter_bins; 134 int unicast_filter_entries; 135 int tx_fifo_size; 136 int rx_fifo_size; 137 void (*fix_mac_speed)(void *priv, unsigned int speed); 138 void (*bus_setup)(void __iomem *ioaddr); 139 int (*init)(struct platform_device *pdev, void *priv); 140 void (*exit)(struct platform_device *pdev, void *priv); 141 void *bsp_priv; 142 struct stmmac_axi *axi; 143 int has_gmac4; 144 bool tso_en; 145 int mac_port_sel_speed; 146 }; 147 #endif 148