1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 4 Header file for stmmac platform data 5 6 Copyright (C) 2009 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 *******************************************************************************/ 11 12 #ifndef __STMMAC_PLATFORM_DATA 13 #define __STMMAC_PLATFORM_DATA 14 15 #include <linux/platform_device.h> 16 17 #define MTL_MAX_RX_QUEUES 8 18 #define MTL_MAX_TX_QUEUES 8 19 #define STMMAC_CH_MAX 8 20 21 #define STMMAC_RX_COE_NONE 0 22 #define STMMAC_RX_COE_TYPE1 1 23 #define STMMAC_RX_COE_TYPE2 2 24 25 /* Define the macros for CSR clock range parameters to be passed by 26 * platform code. 27 * This could also be configured at run time using CPU freq framework. */ 28 29 /* MDC Clock Selection define*/ 30 #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ 31 #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ 32 #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ 33 #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ 34 #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ 35 #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ 36 37 /* MTL algorithms identifiers */ 38 #define MTL_TX_ALGORITHM_WRR 0x0 39 #define MTL_TX_ALGORITHM_WFQ 0x1 40 #define MTL_TX_ALGORITHM_DWRR 0x2 41 #define MTL_TX_ALGORITHM_SP 0x3 42 #define MTL_RX_ALGORITHM_SP 0x4 43 #define MTL_RX_ALGORITHM_WSP 0x5 44 45 /* RX/TX Queue Mode */ 46 #define MTL_QUEUE_AVB 0x0 47 #define MTL_QUEUE_DCB 0x1 48 49 /* The MDC clock could be set higher than the IEEE 802.3 50 * specified frequency limit 0f 2.5 MHz, by programming a clock divider 51 * of value different than the above defined values. The resultant MDIO 52 * clock frequency of 12.5 MHz is applicable for the interfacing chips 53 * supporting higher MDC clocks. 54 * The MDC clock selection macros need to be defined for MDC clock rate 55 * of 12.5 MHz, corresponding to the following selection. 56 */ 57 #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ 58 #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ 59 #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ 60 #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ 61 #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ 62 #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ 63 #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ 64 #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ 65 66 /* AXI DMA Burst length supported */ 67 #define DMA_AXI_BLEN_4 (1 << 1) 68 #define DMA_AXI_BLEN_8 (1 << 2) 69 #define DMA_AXI_BLEN_16 (1 << 3) 70 #define DMA_AXI_BLEN_32 (1 << 4) 71 #define DMA_AXI_BLEN_64 (1 << 5) 72 #define DMA_AXI_BLEN_128 (1 << 6) 73 #define DMA_AXI_BLEN_256 (1 << 7) 74 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \ 75 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ 76 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) 77 78 /* Platfrom data for platform device structure's platform_data field */ 79 80 struct stmmac_mdio_bus_data { 81 unsigned int phy_mask; 82 int *irqs; 83 int probed_phy_irq; 84 }; 85 86 struct stmmac_dma_cfg { 87 int pbl; 88 int txpbl; 89 int rxpbl; 90 bool pblx8; 91 int fixed_burst; 92 int mixed_burst; 93 bool aal; 94 }; 95 96 #define AXI_BLEN 7 97 struct stmmac_axi { 98 bool axi_lpi_en; 99 bool axi_xit_frm; 100 u32 axi_wr_osr_lmt; 101 u32 axi_rd_osr_lmt; 102 bool axi_kbbe; 103 u32 axi_blen[AXI_BLEN]; 104 bool axi_fb; 105 bool axi_mb; 106 bool axi_rb; 107 }; 108 109 struct stmmac_rxq_cfg { 110 u8 mode_to_use; 111 u32 chan; 112 u8 pkt_route; 113 bool use_prio; 114 u32 prio; 115 }; 116 117 struct stmmac_txq_cfg { 118 u32 weight; 119 u8 mode_to_use; 120 /* Credit Base Shaper parameters */ 121 u32 send_slope; 122 u32 idle_slope; 123 u32 high_credit; 124 u32 low_credit; 125 bool use_prio; 126 u32 prio; 127 }; 128 129 struct plat_stmmacenet_data { 130 int bus_id; 131 int phy_addr; 132 int interface; 133 struct stmmac_mdio_bus_data *mdio_bus_data; 134 struct device_node *phy_node; 135 struct device_node *phylink_node; 136 struct device_node *mdio_node; 137 struct stmmac_dma_cfg *dma_cfg; 138 int clk_csr; 139 int has_gmac; 140 int enh_desc; 141 int tx_coe; 142 int rx_coe; 143 int bugged_jumbo; 144 int pmt; 145 int force_sf_dma_mode; 146 int force_thresh_dma_mode; 147 int riwt_off; 148 int max_speed; 149 int maxmtu; 150 int multicast_filter_bins; 151 int unicast_filter_entries; 152 int tx_fifo_size; 153 int rx_fifo_size; 154 u32 rx_queues_to_use; 155 u32 tx_queues_to_use; 156 u8 rx_sched_algorithm; 157 u8 tx_sched_algorithm; 158 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; 159 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; 160 void (*fix_mac_speed)(void *priv, unsigned int speed); 161 int (*init)(struct platform_device *pdev, void *priv); 162 void (*exit)(struct platform_device *pdev, void *priv); 163 struct mac_device_info *(*setup)(void *priv); 164 void *bsp_priv; 165 struct clk *stmmac_clk; 166 struct clk *pclk; 167 struct clk *clk_ptp_ref; 168 unsigned int clk_ptp_rate; 169 unsigned int clk_ref_rate; 170 struct reset_control *stmmac_rst; 171 struct stmmac_axi *axi; 172 int has_gmac4; 173 bool has_sun8i; 174 bool tso_en; 175 int mac_port_sel_speed; 176 bool en_tx_lpi_clockgating; 177 int has_xgmac; 178 }; 179 #endif 180