1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /******************************************************************************* 3 4 Header file for stmmac platform data 5 6 Copyright (C) 2009 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 *******************************************************************************/ 11 12 #ifndef __STMMAC_PLATFORM_DATA 13 #define __STMMAC_PLATFORM_DATA 14 15 #include <linux/platform_device.h> 16 #include <linux/phy.h> 17 18 #define MTL_MAX_RX_QUEUES 8 19 #define MTL_MAX_TX_QUEUES 8 20 #define STMMAC_CH_MAX 8 21 22 #define STMMAC_RX_COE_NONE 0 23 #define STMMAC_RX_COE_TYPE1 1 24 #define STMMAC_RX_COE_TYPE2 2 25 26 /* Define the macros for CSR clock range parameters to be passed by 27 * platform code. 28 * This could also be configured at run time using CPU freq framework. */ 29 30 /* MDC Clock Selection define*/ 31 #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ 32 #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ 33 #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ 34 #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ 35 #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ 36 #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ 37 38 /* MTL algorithms identifiers */ 39 #define MTL_TX_ALGORITHM_WRR 0x0 40 #define MTL_TX_ALGORITHM_WFQ 0x1 41 #define MTL_TX_ALGORITHM_DWRR 0x2 42 #define MTL_TX_ALGORITHM_SP 0x3 43 #define MTL_RX_ALGORITHM_SP 0x4 44 #define MTL_RX_ALGORITHM_WSP 0x5 45 46 /* RX/TX Queue Mode */ 47 #define MTL_QUEUE_AVB 0x0 48 #define MTL_QUEUE_DCB 0x1 49 50 /* The MDC clock could be set higher than the IEEE 802.3 51 * specified frequency limit 0f 2.5 MHz, by programming a clock divider 52 * of value different than the above defined values. The resultant MDIO 53 * clock frequency of 12.5 MHz is applicable for the interfacing chips 54 * supporting higher MDC clocks. 55 * The MDC clock selection macros need to be defined for MDC clock rate 56 * of 12.5 MHz, corresponding to the following selection. 57 */ 58 #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ 59 #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ 60 #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ 61 #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ 62 #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ 63 #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ 64 #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ 65 #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ 66 67 /* AXI DMA Burst length supported */ 68 #define DMA_AXI_BLEN_4 (1 << 1) 69 #define DMA_AXI_BLEN_8 (1 << 2) 70 #define DMA_AXI_BLEN_16 (1 << 3) 71 #define DMA_AXI_BLEN_32 (1 << 4) 72 #define DMA_AXI_BLEN_64 (1 << 5) 73 #define DMA_AXI_BLEN_128 (1 << 6) 74 #define DMA_AXI_BLEN_256 (1 << 7) 75 #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \ 76 | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ 77 | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) 78 79 /* Platfrom data for platform device structure's platform_data field */ 80 81 struct stmmac_mdio_bus_data { 82 unsigned int phy_mask; 83 int *irqs; 84 int probed_phy_irq; 85 bool needs_reset; 86 }; 87 88 struct stmmac_dma_cfg { 89 int pbl; 90 int txpbl; 91 int rxpbl; 92 bool pblx8; 93 int fixed_burst; 94 int mixed_burst; 95 bool aal; 96 bool eame; 97 }; 98 99 #define AXI_BLEN 7 100 struct stmmac_axi { 101 bool axi_lpi_en; 102 bool axi_xit_frm; 103 u32 axi_wr_osr_lmt; 104 u32 axi_rd_osr_lmt; 105 bool axi_kbbe; 106 u32 axi_blen[AXI_BLEN]; 107 bool axi_fb; 108 bool axi_mb; 109 bool axi_rb; 110 }; 111 112 #define EST_GCL 1024 113 struct stmmac_est { 114 int enable; 115 u32 btr_offset[2]; 116 u32 btr[2]; 117 u32 ctr[2]; 118 u32 ter; 119 u32 gcl_unaligned[EST_GCL]; 120 u32 gcl[EST_GCL]; 121 u32 gcl_size; 122 }; 123 124 struct stmmac_rxq_cfg { 125 u8 mode_to_use; 126 u32 chan; 127 u8 pkt_route; 128 bool use_prio; 129 u32 prio; 130 }; 131 132 struct stmmac_txq_cfg { 133 u32 weight; 134 u8 mode_to_use; 135 /* Credit Base Shaper parameters */ 136 u32 send_slope; 137 u32 idle_slope; 138 u32 high_credit; 139 u32 low_credit; 140 bool use_prio; 141 u32 prio; 142 int tbs_en; 143 }; 144 145 struct plat_stmmacenet_data { 146 int bus_id; 147 int phy_addr; 148 int interface; 149 phy_interface_t phy_interface; 150 struct stmmac_mdio_bus_data *mdio_bus_data; 151 struct device_node *phy_node; 152 struct device_node *phylink_node; 153 struct device_node *mdio_node; 154 struct stmmac_dma_cfg *dma_cfg; 155 struct stmmac_est *est; 156 int clk_csr; 157 int has_gmac; 158 int enh_desc; 159 int tx_coe; 160 int rx_coe; 161 int bugged_jumbo; 162 int pmt; 163 int force_sf_dma_mode; 164 int force_thresh_dma_mode; 165 int riwt_off; 166 int max_speed; 167 int maxmtu; 168 int multicast_filter_bins; 169 int unicast_filter_entries; 170 int tx_fifo_size; 171 int rx_fifo_size; 172 u32 rx_queues_to_use; 173 u32 tx_queues_to_use; 174 u8 rx_sched_algorithm; 175 u8 tx_sched_algorithm; 176 struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; 177 struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; 178 void (*fix_mac_speed)(void *priv, unsigned int speed); 179 int (*init)(struct platform_device *pdev, void *priv); 180 void (*exit)(struct platform_device *pdev, void *priv); 181 struct mac_device_info *(*setup)(void *priv); 182 void *bsp_priv; 183 struct clk *stmmac_clk; 184 struct clk *pclk; 185 struct clk *clk_ptp_ref; 186 unsigned int clk_ptp_rate; 187 unsigned int clk_ref_rate; 188 s32 ptp_max_adj; 189 struct reset_control *stmmac_rst; 190 struct stmmac_axi *axi; 191 int has_gmac4; 192 bool has_sun8i; 193 bool tso_en; 194 int rss_en; 195 int mac_port_sel_speed; 196 bool en_tx_lpi_clockgating; 197 int has_xgmac; 198 }; 199 #endif 200