1b2441318SGreg Kroah-Hartman /* SPDX-License-Identifier: GPL-2.0 */ 21d15cb9cSThierry Reding /* 31d15cb9cSThierry Reding * This header provides constants for binding nvidia,tegra210-car. 41d15cb9cSThierry Reding * 51d15cb9cSThierry Reding * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB 61d15cb9cSThierry Reding * registers. These IDs often match those in the CAR's RST_DEVICES registers, 71d15cb9cSThierry Reding * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In 81d15cb9cSThierry Reding * this case, those clocks are assigned IDs above 224 in order to highlight 91d15cb9cSThierry Reding * this issue. Implementations that interpret these clock IDs as bit values 101d15cb9cSThierry Reding * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to 111d15cb9cSThierry Reding * explicitly handle these special cases. 121d15cb9cSThierry Reding * 131d15cb9cSThierry Reding * The balance of the clocks controlled by the CAR are assigned IDs of 224 and 141d15cb9cSThierry Reding * above. 151d15cb9cSThierry Reding */ 161d15cb9cSThierry Reding 171d15cb9cSThierry Reding #ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H 181d15cb9cSThierry Reding #define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H 191d15cb9cSThierry Reding 201d15cb9cSThierry Reding /* 0 */ 211d15cb9cSThierry Reding /* 1 */ 221d15cb9cSThierry Reding /* 2 */ 231d15cb9cSThierry Reding #define TEGRA210_CLK_ISPB 3 241d15cb9cSThierry Reding #define TEGRA210_CLK_RTC 4 251d15cb9cSThierry Reding #define TEGRA210_CLK_TIMER 5 261d15cb9cSThierry Reding #define TEGRA210_CLK_UARTA 6 271d15cb9cSThierry Reding /* 7 (register bit affects uartb and vfir) */ 281d15cb9cSThierry Reding #define TEGRA210_CLK_GPIO 8 291d15cb9cSThierry Reding #define TEGRA210_CLK_SDMMC2 9 301d15cb9cSThierry Reding /* 10 (register bit affects spdif_in and spdif_out) */ 311d15cb9cSThierry Reding #define TEGRA210_CLK_I2S1 11 321d15cb9cSThierry Reding #define TEGRA210_CLK_I2C1 12 331d15cb9cSThierry Reding /* 13 */ 341d15cb9cSThierry Reding #define TEGRA210_CLK_SDMMC1 14 351d15cb9cSThierry Reding #define TEGRA210_CLK_SDMMC4 15 361d15cb9cSThierry Reding /* 16 */ 371d15cb9cSThierry Reding #define TEGRA210_CLK_PWM 17 381d15cb9cSThierry Reding #define TEGRA210_CLK_I2S2 18 391d15cb9cSThierry Reding /* 19 */ 401d15cb9cSThierry Reding /* 20 (register bit affects vi and vi_sensor) */ 411d15cb9cSThierry Reding /* 21 */ 421d15cb9cSThierry Reding #define TEGRA210_CLK_USBD 22 4334ac2c27SPeter De Schrijver #define TEGRA210_CLK_ISPA 23 441d15cb9cSThierry Reding /* 24 */ 451d15cb9cSThierry Reding /* 25 */ 461d15cb9cSThierry Reding #define TEGRA210_CLK_DISP2 26 471d15cb9cSThierry Reding #define TEGRA210_CLK_DISP1 27 481d15cb9cSThierry Reding #define TEGRA210_CLK_HOST1X 28 491d15cb9cSThierry Reding /* 29 */ 501d15cb9cSThierry Reding #define TEGRA210_CLK_I2S0 30 511d15cb9cSThierry Reding /* 31 */ 521d15cb9cSThierry Reding 531d15cb9cSThierry Reding #define TEGRA210_CLK_MC 32 541d15cb9cSThierry Reding #define TEGRA210_CLK_AHBDMA 33 551d15cb9cSThierry Reding #define TEGRA210_CLK_APBDMA 34 561d15cb9cSThierry Reding /* 35 */ 571d15cb9cSThierry Reding /* 36 */ 581d15cb9cSThierry Reding /* 37 */ 591d15cb9cSThierry Reding #define TEGRA210_CLK_PMC 38 601d15cb9cSThierry Reding /* 39 (register bit affects fuse and fuse_burn) */ 611d15cb9cSThierry Reding #define TEGRA210_CLK_KFUSE 40 621d15cb9cSThierry Reding #define TEGRA210_CLK_SBC1 41 631d15cb9cSThierry Reding /* 42 */ 641d15cb9cSThierry Reding /* 43 */ 651d15cb9cSThierry Reding #define TEGRA210_CLK_SBC2 44 661d15cb9cSThierry Reding /* 45 */ 671d15cb9cSThierry Reding #define TEGRA210_CLK_SBC3 46 681d15cb9cSThierry Reding #define TEGRA210_CLK_I2C5 47 691d15cb9cSThierry Reding #define TEGRA210_CLK_DSIA 48 701d15cb9cSThierry Reding /* 49 */ 711d15cb9cSThierry Reding /* 50 */ 721d15cb9cSThierry Reding /* 51 */ 731d15cb9cSThierry Reding #define TEGRA210_CLK_CSI 52 741d15cb9cSThierry Reding /* 53 */ 751d15cb9cSThierry Reding #define TEGRA210_CLK_I2C2 54 761d15cb9cSThierry Reding #define TEGRA210_CLK_UARTC 55 771d15cb9cSThierry Reding #define TEGRA210_CLK_MIPI_CAL 56 781d15cb9cSThierry Reding #define TEGRA210_CLK_EMC 57 791d15cb9cSThierry Reding #define TEGRA210_CLK_USB2 58 801d15cb9cSThierry Reding /* 59 */ 811d15cb9cSThierry Reding /* 60 */ 821d15cb9cSThierry Reding /* 61 */ 831d15cb9cSThierry Reding /* 62 */ 841d15cb9cSThierry Reding #define TEGRA210_CLK_BSEV 63 851d15cb9cSThierry Reding 861d15cb9cSThierry Reding /* 64 */ 871d15cb9cSThierry Reding #define TEGRA210_CLK_UARTD 65 881d15cb9cSThierry Reding /* 66 */ 891d15cb9cSThierry Reding #define TEGRA210_CLK_I2C3 67 901d15cb9cSThierry Reding #define TEGRA210_CLK_SBC4 68 911d15cb9cSThierry Reding #define TEGRA210_CLK_SDMMC3 69 921d15cb9cSThierry Reding #define TEGRA210_CLK_PCIE 70 931d15cb9cSThierry Reding #define TEGRA210_CLK_OWR 71 941d15cb9cSThierry Reding #define TEGRA210_CLK_AFI 72 951d15cb9cSThierry Reding #define TEGRA210_CLK_CSITE 73 961d15cb9cSThierry Reding /* 74 */ 971d15cb9cSThierry Reding /* 75 */ 9889e423c3SPeter De Schrijver #define TEGRA210_CLK_LA 76 991d15cb9cSThierry Reding /* 77 */ 1001d15cb9cSThierry Reding #define TEGRA210_CLK_SOC_THERM 78 1011d15cb9cSThierry Reding #define TEGRA210_CLK_DTV 79 1021d15cb9cSThierry Reding /* 80 */ 1031d15cb9cSThierry Reding #define TEGRA210_CLK_I2CSLOW 81 1041d15cb9cSThierry Reding #define TEGRA210_CLK_DSIB 82 1051d15cb9cSThierry Reding #define TEGRA210_CLK_TSEC 83 1061d15cb9cSThierry Reding /* 84 */ 1071d15cb9cSThierry Reding /* 85 */ 1081d15cb9cSThierry Reding /* 86 */ 1091d15cb9cSThierry Reding /* 87 */ 1101d15cb9cSThierry Reding /* 88 */ 1111d15cb9cSThierry Reding #define TEGRA210_CLK_XUSB_HOST 89 1121d15cb9cSThierry Reding /* 90 */ 1131d15cb9cSThierry Reding /* 91 */ 1141d15cb9cSThierry Reding #define TEGRA210_CLK_CSUS 92 1151d15cb9cSThierry Reding /* 93 */ 1161d15cb9cSThierry Reding /* 94 */ 1171d15cb9cSThierry Reding /* 95 (bit affects xusb_dev and xusb_dev_src) */ 1181d15cb9cSThierry Reding 1191d15cb9cSThierry Reding /* 96 */ 1201d15cb9cSThierry Reding /* 97 */ 1211d15cb9cSThierry Reding /* 98 */ 1221d15cb9cSThierry Reding #define TEGRA210_CLK_MSELECT 99 1231d15cb9cSThierry Reding #define TEGRA210_CLK_TSENSOR 100 1241d15cb9cSThierry Reding #define TEGRA210_CLK_I2S3 101 1251d15cb9cSThierry Reding #define TEGRA210_CLK_I2S4 102 1261d15cb9cSThierry Reding #define TEGRA210_CLK_I2C4 103 1271d15cb9cSThierry Reding /* 104 */ 1281d15cb9cSThierry Reding /* 105 */ 1291d15cb9cSThierry Reding #define TEGRA210_CLK_D_AUDIO 106 13029569941SJon Hunter #define TEGRA210_CLK_APB2APE 107 1311d15cb9cSThierry Reding /* 108 */ 1321d15cb9cSThierry Reding /* 109 */ 1331d15cb9cSThierry Reding /* 110 */ 1341d15cb9cSThierry Reding #define TEGRA210_CLK_HDA2CODEC_2X 111 1351d15cb9cSThierry Reding /* 112 */ 1361d15cb9cSThierry Reding /* 113 */ 1371d15cb9cSThierry Reding /* 114 */ 1381d15cb9cSThierry Reding /* 115 */ 1391d15cb9cSThierry Reding /* 116 */ 1401d15cb9cSThierry Reding /* 117 */ 1411d15cb9cSThierry Reding #define TEGRA210_CLK_SPDIF_2X 118 1421d15cb9cSThierry Reding #define TEGRA210_CLK_ACTMON 119 1431d15cb9cSThierry Reding #define TEGRA210_CLK_EXTERN1 120 1441d15cb9cSThierry Reding #define TEGRA210_CLK_EXTERN2 121 1451d15cb9cSThierry Reding #define TEGRA210_CLK_EXTERN3 122 1461d15cb9cSThierry Reding #define TEGRA210_CLK_SATA_OOB 123 1471d15cb9cSThierry Reding #define TEGRA210_CLK_SATA 124 1481d15cb9cSThierry Reding #define TEGRA210_CLK_HDA 125 1491d15cb9cSThierry Reding /* 126 */ 1501d15cb9cSThierry Reding /* 127 */ 1511d15cb9cSThierry Reding 1521d15cb9cSThierry Reding #define TEGRA210_CLK_HDA2HDMI 128 1531d15cb9cSThierry Reding /* 129 */ 1541d15cb9cSThierry Reding /* 130 */ 1551d15cb9cSThierry Reding /* 131 */ 1561d15cb9cSThierry Reding /* 132 */ 1571d15cb9cSThierry Reding /* 133 */ 1581d15cb9cSThierry Reding /* 134 */ 1591d15cb9cSThierry Reding /* 135 */ 160bfa34832SPeter De Schrijver #define TEGRA210_CLK_CEC 136 1611d15cb9cSThierry Reding /* 137 */ 1621d15cb9cSThierry Reding /* 138 */ 1631d15cb9cSThierry Reding /* 139 */ 1641d15cb9cSThierry Reding /* 140 */ 1651d15cb9cSThierry Reding /* 141 */ 1661d15cb9cSThierry Reding /* 142 */ 1671d15cb9cSThierry Reding /* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */ 1681d15cb9cSThierry Reding #define TEGRA210_CLK_XUSB_GATE 143 1691d15cb9cSThierry Reding #define TEGRA210_CLK_CILAB 144 1701d15cb9cSThierry Reding #define TEGRA210_CLK_CILCD 145 1711d15cb9cSThierry Reding #define TEGRA210_CLK_CILE 146 1721d15cb9cSThierry Reding #define TEGRA210_CLK_DSIALP 147 1731d15cb9cSThierry Reding #define TEGRA210_CLK_DSIBLP 148 1741d15cb9cSThierry Reding #define TEGRA210_CLK_ENTROPY 149 1751d15cb9cSThierry Reding /* 150 */ 1761d15cb9cSThierry Reding /* 151 */ 17788da44c5SPeter De Schrijver #define TEGRA210_CLK_DP2 152 1781d15cb9cSThierry Reding /* 153 */ 1791d15cb9cSThierry Reding /* 154 */ 1801d15cb9cSThierry Reding /* 155 (bit affects dfll_ref and dfll_soc) */ 1811d15cb9cSThierry Reding #define TEGRA210_CLK_XUSB_SS 156 1821d15cb9cSThierry Reding /* 157 */ 1831d15cb9cSThierry Reding /* 158 */ 1841d15cb9cSThierry Reding /* 159 */ 1851d15cb9cSThierry Reding 1861d15cb9cSThierry Reding /* 160 */ 1871d15cb9cSThierry Reding #define TEGRA210_CLK_DMIC1 161 1881d15cb9cSThierry Reding #define TEGRA210_CLK_DMIC2 162 1891d15cb9cSThierry Reding /* 163 */ 1901d15cb9cSThierry Reding /* 164 */ 1911d15cb9cSThierry Reding /* 165 */ 1921d15cb9cSThierry Reding #define TEGRA210_CLK_I2C6 166 1931d15cb9cSThierry Reding /* 167 */ 1941d15cb9cSThierry Reding /* 168 */ 1951d15cb9cSThierry Reding /* 169 */ 1961d15cb9cSThierry Reding /* 170 */ 1971d15cb9cSThierry Reding #define TEGRA210_CLK_VIM2_CLK 171 1981d15cb9cSThierry Reding /* 172 */ 1991d15cb9cSThierry Reding #define TEGRA210_CLK_MIPIBIF 173 2001d15cb9cSThierry Reding /* 174 */ 2011d15cb9cSThierry Reding /* 175 */ 2021d15cb9cSThierry Reding /* 176 */ 2031d15cb9cSThierry Reding #define TEGRA210_CLK_CLK72MHZ 177 2041d15cb9cSThierry Reding #define TEGRA210_CLK_VIC03 178 2051d15cb9cSThierry Reding /* 179 */ 2061d15cb9cSThierry Reding /* 180 */ 2071d15cb9cSThierry Reding #define TEGRA210_CLK_DPAUX 181 2081d15cb9cSThierry Reding #define TEGRA210_CLK_SOR0 182 2091d15cb9cSThierry Reding #define TEGRA210_CLK_SOR1 183 2101d15cb9cSThierry Reding #define TEGRA210_CLK_GPU 184 2111d15cb9cSThierry Reding #define TEGRA210_CLK_DBGAPB 185 2121d15cb9cSThierry Reding /* 186 */ 2131d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_P_OUT_ADSP 187 21488da44c5SPeter De Schrijver /* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/ 2151d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_G_REF 189 2161d15cb9cSThierry Reding /* 190 */ 2171d15cb9cSThierry Reding /* 191 */ 2181d15cb9cSThierry Reding 2191d15cb9cSThierry Reding /* 192 */ 2201d15cb9cSThierry Reding #define TEGRA210_CLK_SDMMC_LEGACY 193 2211d15cb9cSThierry Reding #define TEGRA210_CLK_NVDEC 194 2221d15cb9cSThierry Reding #define TEGRA210_CLK_NVJPG 195 2231d15cb9cSThierry Reding /* 196 */ 2241d15cb9cSThierry Reding #define TEGRA210_CLK_DMIC3 197 2251d15cb9cSThierry Reding #define TEGRA210_CLK_APE 198 22688da44c5SPeter De Schrijver #define TEGRA210_CLK_ADSP 199 2271d15cb9cSThierry Reding /* 200 */ 2281d15cb9cSThierry Reding /* 201 */ 2291d15cb9cSThierry Reding #define TEGRA210_CLK_MAUD 202 2301d15cb9cSThierry Reding /* 203 */ 2311d15cb9cSThierry Reding /* 204 */ 2321d15cb9cSThierry Reding /* 205 */ 2331d15cb9cSThierry Reding #define TEGRA210_CLK_TSECB 206 2341d15cb9cSThierry Reding #define TEGRA210_CLK_DPAUX1 207 2351d15cb9cSThierry Reding #define TEGRA210_CLK_VI_I2C 208 2361d15cb9cSThierry Reding #define TEGRA210_CLK_HSIC_TRK 209 2371d15cb9cSThierry Reding #define TEGRA210_CLK_USB2_TRK 210 2381d15cb9cSThierry Reding #define TEGRA210_CLK_QSPI 211 2391d15cb9cSThierry Reding #define TEGRA210_CLK_UARTAPE 212 2401d15cb9cSThierry Reding /* 213 */ 2411d15cb9cSThierry Reding /* 214 */ 2421d15cb9cSThierry Reding /* 215 */ 2431d15cb9cSThierry Reding /* 216 */ 2441d15cb9cSThierry Reding /* 217 */ 24588da44c5SPeter De Schrijver #define TEGRA210_CLK_ADSP_NEON 218 2461d15cb9cSThierry Reding #define TEGRA210_CLK_NVENC 219 24788da44c5SPeter De Schrijver #define TEGRA210_CLK_IQC2 220 24888da44c5SPeter De Schrijver #define TEGRA210_CLK_IQC1 221 2491d15cb9cSThierry Reding #define TEGRA210_CLK_SOR_SAFE 222 2501d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_P_OUT_CPU 223 2511d15cb9cSThierry Reding 2521d15cb9cSThierry Reding 2531d15cb9cSThierry Reding #define TEGRA210_CLK_UARTB 224 2541d15cb9cSThierry Reding #define TEGRA210_CLK_VFIR 225 2551d15cb9cSThierry Reding #define TEGRA210_CLK_SPDIF_IN 226 2561d15cb9cSThierry Reding #define TEGRA210_CLK_SPDIF_OUT 227 2571d15cb9cSThierry Reding #define TEGRA210_CLK_VI 228 2581d15cb9cSThierry Reding #define TEGRA210_CLK_VI_SENSOR 229 2591d15cb9cSThierry Reding #define TEGRA210_CLK_FUSE 230 2601d15cb9cSThierry Reding #define TEGRA210_CLK_FUSE_BURN 231 2611d15cb9cSThierry Reding #define TEGRA210_CLK_CLK_32K 232 2621d15cb9cSThierry Reding #define TEGRA210_CLK_CLK_M 233 2631d15cb9cSThierry Reding #define TEGRA210_CLK_CLK_M_DIV2 234 2641d15cb9cSThierry Reding #define TEGRA210_CLK_CLK_M_DIV4 235 265e5377ab2SSowjanya Komatineni #define TEGRA210_CLK_OSC_DIV2 234 266e5377ab2SSowjanya Komatineni #define TEGRA210_CLK_OSC_DIV4 235 2671d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_REF 236 2681d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_C 237 2691d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_C_OUT1 238 2701d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_C2 239 2711d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_C3 240 2721d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_M 241 2731d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_M_OUT1 242 2741d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_P 243 2751d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_P_OUT1 244 2761d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_P_OUT2 245 2771d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_P_OUT3 246 2781d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_P_OUT4 247 2791d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_A 248 2801d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_A_OUT0 249 2811d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_D 250 2821d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_D_OUT0 251 2831d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_D2 252 2841d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_D2_OUT0 253 2851d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_U 254 2861d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_U_480M 255 2871d15cb9cSThierry Reding 2881d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_U_60M 256 2891d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_U_48M 257 2901d15cb9cSThierry Reding /* 258 */ 2911d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_X 259 2921d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_X_OUT0 260 2931d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_RE_VCO 261 2941d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_RE_OUT 262 2951d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_E 263 2961d15cb9cSThierry Reding #define TEGRA210_CLK_SPDIF_IN_SYNC 264 2971d15cb9cSThierry Reding #define TEGRA210_CLK_I2S0_SYNC 265 2981d15cb9cSThierry Reding #define TEGRA210_CLK_I2S1_SYNC 266 2991d15cb9cSThierry Reding #define TEGRA210_CLK_I2S2_SYNC 267 3001d15cb9cSThierry Reding #define TEGRA210_CLK_I2S3_SYNC 268 3011d15cb9cSThierry Reding #define TEGRA210_CLK_I2S4_SYNC 269 3021d15cb9cSThierry Reding #define TEGRA210_CLK_VIMCLK_SYNC 270 3031d15cb9cSThierry Reding #define TEGRA210_CLK_AUDIO0 271 3041d15cb9cSThierry Reding #define TEGRA210_CLK_AUDIO1 272 3051d15cb9cSThierry Reding #define TEGRA210_CLK_AUDIO2 273 3061d15cb9cSThierry Reding #define TEGRA210_CLK_AUDIO3 274 3071d15cb9cSThierry Reding #define TEGRA210_CLK_AUDIO4 275 3081d15cb9cSThierry Reding #define TEGRA210_CLK_SPDIF 276 3091d15cb9cSThierry Reding #define TEGRA210_CLK_CLK_OUT_1 277 3101d15cb9cSThierry Reding #define TEGRA210_CLK_CLK_OUT_2 278 3111d15cb9cSThierry Reding #define TEGRA210_CLK_CLK_OUT_3 279 3121d15cb9cSThierry Reding #define TEGRA210_CLK_BLINK 280 31305308d7eSThierry Reding #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */ 31405308d7eSThierry Reding #define TEGRA210_CLK_SOR0_OUT 281 3154d1dc401SThierry Reding #define TEGRA210_CLK_SOR1_OUT 282 3161d15cb9cSThierry Reding /* 283 */ 3171d15cb9cSThierry Reding #define TEGRA210_CLK_XUSB_HOST_SRC 284 3181d15cb9cSThierry Reding #define TEGRA210_CLK_XUSB_FALCON_SRC 285 3191d15cb9cSThierry Reding #define TEGRA210_CLK_XUSB_FS_SRC 286 3201d15cb9cSThierry Reding #define TEGRA210_CLK_XUSB_SS_SRC 287 3211d15cb9cSThierry Reding 3221d15cb9cSThierry Reding #define TEGRA210_CLK_XUSB_DEV_SRC 288 3231d15cb9cSThierry Reding #define TEGRA210_CLK_XUSB_DEV 289 3241d15cb9cSThierry Reding #define TEGRA210_CLK_XUSB_HS_SRC 290 3251d15cb9cSThierry Reding #define TEGRA210_CLK_SCLK 291 3261d15cb9cSThierry Reding #define TEGRA210_CLK_HCLK 292 3271d15cb9cSThierry Reding #define TEGRA210_CLK_PCLK 293 3281d15cb9cSThierry Reding #define TEGRA210_CLK_CCLK_G 294 3291d15cb9cSThierry Reding #define TEGRA210_CLK_CCLK_LP 295 3301d15cb9cSThierry Reding #define TEGRA210_CLK_DFLL_REF 296 3311d15cb9cSThierry Reding #define TEGRA210_CLK_DFLL_SOC 297 3321d15cb9cSThierry Reding #define TEGRA210_CLK_VI_SENSOR2 298 3331d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_P_OUT5 299 3341d15cb9cSThierry Reding #define TEGRA210_CLK_CML0 300 3351d15cb9cSThierry Reding #define TEGRA210_CLK_CML1 301 3361d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_C4 302 3371d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_DP 303 3381d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_E_MUX 304 3391d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_MB 305 3401d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_A1 306 3411d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_D_DSI_OUT 307 3421d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_C4_OUT0 308 3431d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_C4_OUT1 309 3441d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_C4_OUT2 310 3451d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_C4_OUT3 311 3461d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_U_OUT 312 3471d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_U_OUT1 313 3481d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_U_OUT2 314 3491d15cb9cSThierry Reding #define TEGRA210_CLK_USB2_HSIC_TRK 315 3501d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_P_OUT_HSIO 316 3511d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_P_OUT_XUSB 317 3521d15cb9cSThierry Reding #define TEGRA210_CLK_XUSB_SSP_SRC 318 353926655f9SRhyland Klein #define TEGRA210_CLK_PLL_RE_OUT1 319 3541d15cb9cSThierry Reding /* 320 */ 3551d15cb9cSThierry Reding /* 321 */ 35634ac2c27SPeter De Schrijver #define TEGRA210_CLK_ISP 322 35788da44c5SPeter De Schrijver #define TEGRA210_CLK_PLL_A_OUT_ADSP 323 35888da44c5SPeter De Schrijver #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324 3591d15cb9cSThierry Reding /* 325 */ 360e5377ab2SSowjanya Komatineni #define TEGRA210_CLK_OSC 326 3611d15cb9cSThierry Reding /* 327 */ 3621d15cb9cSThierry Reding /* 328 */ 3631d15cb9cSThierry Reding /* 329 */ 3641d15cb9cSThierry Reding /* 330 */ 3651d15cb9cSThierry Reding /* 331 */ 3661d15cb9cSThierry Reding /* 332 */ 3671d15cb9cSThierry Reding /* 333 */ 3681d15cb9cSThierry Reding /* 334 */ 3691d15cb9cSThierry Reding /* 335 */ 3701d15cb9cSThierry Reding /* 336 */ 3711d15cb9cSThierry Reding /* 337 */ 3721d15cb9cSThierry Reding /* 338 */ 3731d15cb9cSThierry Reding /* 339 */ 3741d15cb9cSThierry Reding /* 340 */ 3751d15cb9cSThierry Reding /* 341 */ 3761d15cb9cSThierry Reding /* 342 */ 3771d15cb9cSThierry Reding /* 343 */ 3781d15cb9cSThierry Reding /* 344 */ 3791d15cb9cSThierry Reding /* 345 */ 3801d15cb9cSThierry Reding /* 346 */ 3811d15cb9cSThierry Reding /* 347 */ 3821d15cb9cSThierry Reding /* 348 */ 3831d15cb9cSThierry Reding /* 349 */ 3841d15cb9cSThierry Reding 3851d15cb9cSThierry Reding #define TEGRA210_CLK_AUDIO0_MUX 350 3861d15cb9cSThierry Reding #define TEGRA210_CLK_AUDIO1_MUX 351 3871d15cb9cSThierry Reding #define TEGRA210_CLK_AUDIO2_MUX 352 3881d15cb9cSThierry Reding #define TEGRA210_CLK_AUDIO3_MUX 353 3891d15cb9cSThierry Reding #define TEGRA210_CLK_AUDIO4_MUX 354 3901d15cb9cSThierry Reding #define TEGRA210_CLK_SPDIF_MUX 355 3911d15cb9cSThierry Reding #define TEGRA210_CLK_CLK_OUT_1_MUX 356 3921d15cb9cSThierry Reding #define TEGRA210_CLK_CLK_OUT_2_MUX 357 3931d15cb9cSThierry Reding #define TEGRA210_CLK_CLK_OUT_3_MUX 358 3941d15cb9cSThierry Reding #define TEGRA210_CLK_DSIA_MUX 359 3951d15cb9cSThierry Reding #define TEGRA210_CLK_DSIB_MUX 360 39605308d7eSThierry Reding /* 361 */ 3971d15cb9cSThierry Reding #define TEGRA210_CLK_XUSB_SS_DIV2 362 3981d15cb9cSThierry Reding 3991d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_M_UD 363 4001d15cb9cSThierry Reding #define TEGRA210_CLK_PLL_C_UD 364 4011d15cb9cSThierry Reding #define TEGRA210_CLK_SCLK_MUX 365 4021d15cb9cSThierry Reding 40324c3ebefSPeter De Schrijver #define TEGRA210_CLK_ACLK 370 40424c3ebefSPeter De Schrijver 405319af797SPeter De Schrijver #define TEGRA210_CLK_DMIC1_SYNC_CLK 388 406319af797SPeter De Schrijver #define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389 407319af797SPeter De Schrijver #define TEGRA210_CLK_DMIC2_SYNC_CLK 390 408319af797SPeter De Schrijver #define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391 409319af797SPeter De Schrijver #define TEGRA210_CLK_DMIC3_SYNC_CLK 392 410319af797SPeter De Schrijver #define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393 411319af797SPeter De Schrijver 412319af797SPeter De Schrijver #define TEGRA210_CLK_CLK_MAX 394 4131d15cb9cSThierry Reding 4141d15cb9cSThierry Reding #endif /* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */ 415