1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Universal Flash Storage Host controller PCI glue driver 4 * 5 * Copyright (C) 2011-2013 Samsung India Software Operations 6 * 7 * Authors: 8 * Santosh Yaraganavi <santosh.sy@samsung.com> 9 * Vinayak Holikatti <h.vinayak@samsung.com> 10 */ 11 12 #include <ufs/ufshcd.h> 13 #include <linux/delay.h> 14 #include <linux/module.h> 15 #include <linux/pci.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/pm_qos.h> 18 #include <linux/debugfs.h> 19 #include <linux/uuid.h> 20 #include <linux/acpi.h> 21 #include <linux/gpio/consumer.h> 22 23 struct ufs_host { 24 void (*late_init)(struct ufs_hba *hba); 25 }; 26 27 enum { 28 INTEL_DSM_FNS = 0, 29 INTEL_DSM_RESET = 1, 30 }; 31 32 struct intel_host { 33 struct ufs_host ufs_host; 34 u32 dsm_fns; 35 u32 active_ltr; 36 u32 idle_ltr; 37 struct dentry *debugfs_root; 38 struct gpio_desc *reset_gpio; 39 }; 40 41 static const guid_t intel_dsm_guid = 42 GUID_INIT(0x1A4832A0, 0x7D03, 0x43CA, 43 0xB0, 0x20, 0xF6, 0xDC, 0xD1, 0x2A, 0x19, 0x50); 44 45 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 46 unsigned int fn, u32 *result) 47 { 48 union acpi_object *obj; 49 int err = 0; 50 size_t len; 51 52 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 53 if (!obj) 54 return -EOPNOTSUPP; 55 56 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 57 err = -EINVAL; 58 goto out; 59 } 60 61 len = min_t(size_t, obj->buffer.length, 4); 62 63 *result = 0; 64 memcpy(result, obj->buffer.pointer, len); 65 out: 66 ACPI_FREE(obj); 67 68 return err; 69 } 70 71 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 72 unsigned int fn, u32 *result) 73 { 74 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 75 return -EOPNOTSUPP; 76 77 return __intel_dsm(intel_host, dev, fn, result); 78 } 79 80 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev) 81 { 82 int err; 83 84 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 85 dev_dbg(dev, "DSM fns %#x, error %d\n", intel_host->dsm_fns, err); 86 } 87 88 static int ufs_intel_hce_enable_notify(struct ufs_hba *hba, 89 enum ufs_notify_change_status status) 90 { 91 /* Cannot enable ICE until after HC enable */ 92 if (status == POST_CHANGE && hba->caps & UFSHCD_CAP_CRYPTO) { 93 u32 hce = ufshcd_readl(hba, REG_CONTROLLER_ENABLE); 94 95 hce |= CRYPTO_GENERAL_ENABLE; 96 ufshcd_writel(hba, hce, REG_CONTROLLER_ENABLE); 97 } 98 99 return 0; 100 } 101 102 static int ufs_intel_disable_lcc(struct ufs_hba *hba) 103 { 104 u32 attr = UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE); 105 u32 lcc_enable = 0; 106 107 ufshcd_dme_get(hba, attr, &lcc_enable); 108 if (lcc_enable) 109 ufshcd_disable_host_tx_lcc(hba); 110 111 return 0; 112 } 113 114 static int ufs_intel_link_startup_notify(struct ufs_hba *hba, 115 enum ufs_notify_change_status status) 116 { 117 int err = 0; 118 119 switch (status) { 120 case PRE_CHANGE: 121 err = ufs_intel_disable_lcc(hba); 122 break; 123 case POST_CHANGE: 124 break; 125 default: 126 break; 127 } 128 129 return err; 130 } 131 132 static int ufs_intel_set_lanes(struct ufs_hba *hba, u32 lanes) 133 { 134 struct ufs_pa_layer_attr pwr_info = hba->pwr_info; 135 int ret; 136 137 pwr_info.lane_rx = lanes; 138 pwr_info.lane_tx = lanes; 139 ret = ufshcd_config_pwr_mode(hba, &pwr_info); 140 if (ret) 141 dev_err(hba->dev, "%s: Setting %u lanes, err = %d\n", 142 __func__, lanes, ret); 143 return ret; 144 } 145 146 static int ufs_intel_lkf_pwr_change_notify(struct ufs_hba *hba, 147 enum ufs_notify_change_status status, 148 struct ufs_pa_layer_attr *dev_max_params, 149 struct ufs_pa_layer_attr *dev_req_params) 150 { 151 int err = 0; 152 153 switch (status) { 154 case PRE_CHANGE: 155 if (ufshcd_is_hs_mode(dev_max_params) && 156 (hba->pwr_info.lane_rx != 2 || hba->pwr_info.lane_tx != 2)) 157 ufs_intel_set_lanes(hba, 2); 158 memcpy(dev_req_params, dev_max_params, sizeof(*dev_req_params)); 159 break; 160 case POST_CHANGE: 161 if (ufshcd_is_hs_mode(dev_req_params)) { 162 u32 peer_granularity; 163 164 usleep_range(1000, 1250); 165 err = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), 166 &peer_granularity); 167 } 168 break; 169 default: 170 break; 171 } 172 173 return err; 174 } 175 176 static int ufs_intel_lkf_apply_dev_quirks(struct ufs_hba *hba) 177 { 178 u32 granularity, peer_granularity; 179 u32 pa_tactivate, peer_pa_tactivate; 180 int ret; 181 182 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY), &granularity); 183 if (ret) 184 goto out; 185 186 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_GRANULARITY), &peer_granularity); 187 if (ret) 188 goto out; 189 190 ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &pa_tactivate); 191 if (ret) 192 goto out; 193 194 ret = ufshcd_dme_peer_get(hba, UIC_ARG_MIB(PA_TACTIVATE), &peer_pa_tactivate); 195 if (ret) 196 goto out; 197 198 if (granularity == peer_granularity) { 199 u32 new_peer_pa_tactivate = pa_tactivate + 2; 200 201 ret = ufshcd_dme_peer_set(hba, UIC_ARG_MIB(PA_TACTIVATE), new_peer_pa_tactivate); 202 } 203 out: 204 return ret; 205 } 206 207 #define INTEL_ACTIVELTR 0x804 208 #define INTEL_IDLELTR 0x808 209 210 #define INTEL_LTR_REQ BIT(15) 211 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10) 212 #define INTEL_LTR_SCALE_1US (2 << 10) 213 #define INTEL_LTR_SCALE_32US (3 << 10) 214 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0) 215 216 static void intel_cache_ltr(struct ufs_hba *hba) 217 { 218 struct intel_host *host = ufshcd_get_variant(hba); 219 220 host->active_ltr = readl(hba->mmio_base + INTEL_ACTIVELTR); 221 host->idle_ltr = readl(hba->mmio_base + INTEL_IDLELTR); 222 } 223 224 static void intel_ltr_set(struct device *dev, s32 val) 225 { 226 struct ufs_hba *hba = dev_get_drvdata(dev); 227 struct intel_host *host = ufshcd_get_variant(hba); 228 u32 ltr; 229 230 pm_runtime_get_sync(dev); 231 232 /* 233 * Program latency tolerance (LTR) accordingly what has been asked 234 * by the PM QoS layer or disable it in case we were passed 235 * negative value or PM_QOS_LATENCY_ANY. 236 */ 237 ltr = readl(hba->mmio_base + INTEL_ACTIVELTR); 238 239 if (val == PM_QOS_LATENCY_ANY || val < 0) { 240 ltr &= ~INTEL_LTR_REQ; 241 } else { 242 ltr |= INTEL_LTR_REQ; 243 ltr &= ~INTEL_LTR_SCALE_MASK; 244 ltr &= ~INTEL_LTR_VALUE_MASK; 245 246 if (val > INTEL_LTR_VALUE_MASK) { 247 val >>= 5; 248 if (val > INTEL_LTR_VALUE_MASK) 249 val = INTEL_LTR_VALUE_MASK; 250 ltr |= INTEL_LTR_SCALE_32US | val; 251 } else { 252 ltr |= INTEL_LTR_SCALE_1US | val; 253 } 254 } 255 256 if (ltr == host->active_ltr) 257 goto out; 258 259 writel(ltr, hba->mmio_base + INTEL_ACTIVELTR); 260 writel(ltr, hba->mmio_base + INTEL_IDLELTR); 261 262 /* Cache the values into intel_host structure */ 263 intel_cache_ltr(hba); 264 out: 265 pm_runtime_put(dev); 266 } 267 268 static void intel_ltr_expose(struct device *dev) 269 { 270 dev->power.set_latency_tolerance = intel_ltr_set; 271 dev_pm_qos_expose_latency_tolerance(dev); 272 } 273 274 static void intel_ltr_hide(struct device *dev) 275 { 276 dev_pm_qos_hide_latency_tolerance(dev); 277 dev->power.set_latency_tolerance = NULL; 278 } 279 280 static void intel_add_debugfs(struct ufs_hba *hba) 281 { 282 struct dentry *dir = debugfs_create_dir(dev_name(hba->dev), NULL); 283 struct intel_host *host = ufshcd_get_variant(hba); 284 285 intel_cache_ltr(hba); 286 287 host->debugfs_root = dir; 288 debugfs_create_x32("active_ltr", 0444, dir, &host->active_ltr); 289 debugfs_create_x32("idle_ltr", 0444, dir, &host->idle_ltr); 290 } 291 292 static void intel_remove_debugfs(struct ufs_hba *hba) 293 { 294 struct intel_host *host = ufshcd_get_variant(hba); 295 296 debugfs_remove_recursive(host->debugfs_root); 297 } 298 299 static int ufs_intel_device_reset(struct ufs_hba *hba) 300 { 301 struct intel_host *host = ufshcd_get_variant(hba); 302 303 if (host->dsm_fns & INTEL_DSM_RESET) { 304 u32 result = 0; 305 int err; 306 307 err = intel_dsm(host, hba->dev, INTEL_DSM_RESET, &result); 308 if (!err && !result) 309 err = -EIO; 310 if (err) 311 dev_err(hba->dev, "%s: DSM error %d result %u\n", 312 __func__, err, result); 313 return err; 314 } 315 316 if (!host->reset_gpio) 317 return -EOPNOTSUPP; 318 319 gpiod_set_value_cansleep(host->reset_gpio, 1); 320 usleep_range(10, 15); 321 322 gpiod_set_value_cansleep(host->reset_gpio, 0); 323 usleep_range(10, 15); 324 325 return 0; 326 } 327 328 static struct gpio_desc *ufs_intel_get_reset_gpio(struct device *dev) 329 { 330 /* GPIO in _DSD has active low setting */ 331 return devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 332 } 333 334 static int ufs_intel_common_init(struct ufs_hba *hba) 335 { 336 struct intel_host *host; 337 338 hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND; 339 340 host = devm_kzalloc(hba->dev, sizeof(*host), GFP_KERNEL); 341 if (!host) 342 return -ENOMEM; 343 ufshcd_set_variant(hba, host); 344 intel_dsm_init(host, hba->dev); 345 if (host->dsm_fns & INTEL_DSM_RESET) { 346 if (hba->vops->device_reset) 347 hba->caps |= UFSHCD_CAP_DEEPSLEEP; 348 } else { 349 if (hba->vops->device_reset) 350 host->reset_gpio = ufs_intel_get_reset_gpio(hba->dev); 351 if (IS_ERR(host->reset_gpio)) { 352 dev_err(hba->dev, "%s: failed to get reset GPIO, error %ld\n", 353 __func__, PTR_ERR(host->reset_gpio)); 354 host->reset_gpio = NULL; 355 } 356 if (host->reset_gpio) { 357 gpiod_set_value_cansleep(host->reset_gpio, 0); 358 hba->caps |= UFSHCD_CAP_DEEPSLEEP; 359 } 360 } 361 intel_ltr_expose(hba->dev); 362 intel_add_debugfs(hba); 363 return 0; 364 } 365 366 static void ufs_intel_common_exit(struct ufs_hba *hba) 367 { 368 intel_remove_debugfs(hba); 369 intel_ltr_hide(hba->dev); 370 } 371 372 static int ufs_intel_resume(struct ufs_hba *hba, enum ufs_pm_op op) 373 { 374 if (ufshcd_is_link_hibern8(hba)) { 375 int ret = ufshcd_uic_hibern8_exit(hba); 376 377 if (!ret) { 378 ufshcd_set_link_active(hba); 379 } else { 380 dev_err(hba->dev, "%s: hibern8 exit failed %d\n", 381 __func__, ret); 382 /* 383 * Force reset and restore. Any other actions can lead 384 * to an unrecoverable state. 385 */ 386 ufshcd_set_link_off(hba); 387 } 388 } 389 390 return 0; 391 } 392 393 static int ufs_intel_ehl_init(struct ufs_hba *hba) 394 { 395 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8; 396 return ufs_intel_common_init(hba); 397 } 398 399 static void ufs_intel_lkf_late_init(struct ufs_hba *hba) 400 { 401 /* LKF always needs a full reset, so set PM accordingly */ 402 if (hba->caps & UFSHCD_CAP_DEEPSLEEP) { 403 hba->spm_lvl = UFS_PM_LVL_6; 404 hba->rpm_lvl = UFS_PM_LVL_6; 405 } else { 406 hba->spm_lvl = UFS_PM_LVL_5; 407 hba->rpm_lvl = UFS_PM_LVL_5; 408 } 409 } 410 411 static int ufs_intel_lkf_init(struct ufs_hba *hba) 412 { 413 struct ufs_host *ufs_host; 414 int err; 415 416 hba->nop_out_timeout = 200; 417 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8; 418 hba->caps |= UFSHCD_CAP_CRYPTO; 419 err = ufs_intel_common_init(hba); 420 ufs_host = ufshcd_get_variant(hba); 421 ufs_host->late_init = ufs_intel_lkf_late_init; 422 return err; 423 } 424 425 static int ufs_intel_adl_init(struct ufs_hba *hba) 426 { 427 hba->nop_out_timeout = 200; 428 hba->quirks |= UFSHCD_QUIRK_BROKEN_AUTO_HIBERN8; 429 hba->caps |= UFSHCD_CAP_WB_EN; 430 return ufs_intel_common_init(hba); 431 } 432 433 static int ufs_intel_mtl_init(struct ufs_hba *hba) 434 { 435 hba->caps |= UFSHCD_CAP_CRYPTO | UFSHCD_CAP_WB_EN; 436 return ufs_intel_common_init(hba); 437 } 438 439 static struct ufs_hba_variant_ops ufs_intel_cnl_hba_vops = { 440 .name = "intel-pci", 441 .init = ufs_intel_common_init, 442 .exit = ufs_intel_common_exit, 443 .link_startup_notify = ufs_intel_link_startup_notify, 444 .resume = ufs_intel_resume, 445 }; 446 447 static struct ufs_hba_variant_ops ufs_intel_ehl_hba_vops = { 448 .name = "intel-pci", 449 .init = ufs_intel_ehl_init, 450 .exit = ufs_intel_common_exit, 451 .link_startup_notify = ufs_intel_link_startup_notify, 452 .resume = ufs_intel_resume, 453 }; 454 455 static struct ufs_hba_variant_ops ufs_intel_lkf_hba_vops = { 456 .name = "intel-pci", 457 .init = ufs_intel_lkf_init, 458 .exit = ufs_intel_common_exit, 459 .hce_enable_notify = ufs_intel_hce_enable_notify, 460 .link_startup_notify = ufs_intel_link_startup_notify, 461 .pwr_change_notify = ufs_intel_lkf_pwr_change_notify, 462 .apply_dev_quirks = ufs_intel_lkf_apply_dev_quirks, 463 .resume = ufs_intel_resume, 464 .device_reset = ufs_intel_device_reset, 465 }; 466 467 static struct ufs_hba_variant_ops ufs_intel_adl_hba_vops = { 468 .name = "intel-pci", 469 .init = ufs_intel_adl_init, 470 .exit = ufs_intel_common_exit, 471 .link_startup_notify = ufs_intel_link_startup_notify, 472 .resume = ufs_intel_resume, 473 .device_reset = ufs_intel_device_reset, 474 }; 475 476 static struct ufs_hba_variant_ops ufs_intel_mtl_hba_vops = { 477 .name = "intel-pci", 478 .init = ufs_intel_mtl_init, 479 .exit = ufs_intel_common_exit, 480 .hce_enable_notify = ufs_intel_hce_enable_notify, 481 .link_startup_notify = ufs_intel_link_startup_notify, 482 .resume = ufs_intel_resume, 483 .device_reset = ufs_intel_device_reset, 484 }; 485 486 #ifdef CONFIG_PM_SLEEP 487 static int ufshcd_pci_restore(struct device *dev) 488 { 489 struct ufs_hba *hba = dev_get_drvdata(dev); 490 491 /* Force a full reset and restore */ 492 ufshcd_set_link_off(hba); 493 494 return ufshcd_system_resume(dev); 495 } 496 #endif 497 498 /** 499 * ufshcd_pci_shutdown - main function to put the controller in reset state 500 * @pdev: pointer to PCI device handle 501 */ 502 static void ufshcd_pci_shutdown(struct pci_dev *pdev) 503 { 504 ufshcd_shutdown((struct ufs_hba *)pci_get_drvdata(pdev)); 505 } 506 507 /** 508 * ufshcd_pci_remove - de-allocate PCI/SCSI host and host memory space 509 * data structure memory 510 * @pdev: pointer to PCI handle 511 */ 512 static void ufshcd_pci_remove(struct pci_dev *pdev) 513 { 514 struct ufs_hba *hba = pci_get_drvdata(pdev); 515 516 pm_runtime_forbid(&pdev->dev); 517 pm_runtime_get_noresume(&pdev->dev); 518 ufshcd_remove(hba); 519 ufshcd_dealloc_host(hba); 520 } 521 522 /** 523 * ufshcd_pci_probe - probe routine of the driver 524 * @pdev: pointer to PCI device handle 525 * @id: PCI device id 526 * 527 * Returns 0 on success, non-zero value on failure 528 */ 529 static int 530 ufshcd_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 531 { 532 struct ufs_host *ufs_host; 533 struct ufs_hba *hba; 534 void __iomem *mmio_base; 535 int err; 536 537 err = pcim_enable_device(pdev); 538 if (err) { 539 dev_err(&pdev->dev, "pcim_enable_device failed\n"); 540 return err; 541 } 542 543 pci_set_master(pdev); 544 545 err = pcim_iomap_regions(pdev, 1 << 0, UFSHCD); 546 if (err < 0) { 547 dev_err(&pdev->dev, "request and iomap failed\n"); 548 return err; 549 } 550 551 mmio_base = pcim_iomap_table(pdev)[0]; 552 553 err = ufshcd_alloc_host(&pdev->dev, &hba); 554 if (err) { 555 dev_err(&pdev->dev, "Allocation failed\n"); 556 return err; 557 } 558 559 hba->vops = (struct ufs_hba_variant_ops *)id->driver_data; 560 561 err = ufshcd_init(hba, mmio_base, pdev->irq); 562 if (err) { 563 dev_err(&pdev->dev, "Initialization failed\n"); 564 ufshcd_dealloc_host(hba); 565 return err; 566 } 567 568 ufs_host = ufshcd_get_variant(hba); 569 if (ufs_host && ufs_host->late_init) 570 ufs_host->late_init(hba); 571 572 pm_runtime_put_noidle(&pdev->dev); 573 pm_runtime_allow(&pdev->dev); 574 575 return 0; 576 } 577 578 static const struct dev_pm_ops ufshcd_pci_pm_ops = { 579 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL) 580 #ifdef CONFIG_PM_SLEEP 581 .suspend = ufshcd_system_suspend, 582 .resume = ufshcd_system_resume, 583 .freeze = ufshcd_system_suspend, 584 .thaw = ufshcd_system_resume, 585 .poweroff = ufshcd_system_suspend, 586 .restore = ufshcd_pci_restore, 587 .prepare = ufshcd_suspend_prepare, 588 .complete = ufshcd_resume_complete, 589 #endif 590 }; 591 592 static const struct pci_device_id ufshcd_pci_tbl[] = { 593 { PCI_VENDOR_ID_SAMSUNG, 0xC00C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, 594 { PCI_VDEVICE(INTEL, 0x9DFA), (kernel_ulong_t)&ufs_intel_cnl_hba_vops }, 595 { PCI_VDEVICE(INTEL, 0x4B41), (kernel_ulong_t)&ufs_intel_ehl_hba_vops }, 596 { PCI_VDEVICE(INTEL, 0x4B43), (kernel_ulong_t)&ufs_intel_ehl_hba_vops }, 597 { PCI_VDEVICE(INTEL, 0x98FA), (kernel_ulong_t)&ufs_intel_lkf_hba_vops }, 598 { PCI_VDEVICE(INTEL, 0x51FF), (kernel_ulong_t)&ufs_intel_adl_hba_vops }, 599 { PCI_VDEVICE(INTEL, 0x54FF), (kernel_ulong_t)&ufs_intel_adl_hba_vops }, 600 { PCI_VDEVICE(INTEL, 0x7E47), (kernel_ulong_t)&ufs_intel_mtl_hba_vops }, 601 { } /* terminate list */ 602 }; 603 604 MODULE_DEVICE_TABLE(pci, ufshcd_pci_tbl); 605 606 static struct pci_driver ufshcd_pci_driver = { 607 .name = UFSHCD, 608 .id_table = ufshcd_pci_tbl, 609 .probe = ufshcd_pci_probe, 610 .remove = ufshcd_pci_remove, 611 .shutdown = ufshcd_pci_shutdown, 612 .driver = { 613 .pm = &ufshcd_pci_pm_ops 614 }, 615 }; 616 617 module_pci_driver(ufshcd_pci_driver); 618 619 MODULE_AUTHOR("Santosh Yaragnavi <santosh.sy@samsung.com>"); 620 MODULE_AUTHOR("Vinayak Holikatti <h.vinayak@samsung.com>"); 621 MODULE_DESCRIPTION("UFS host controller PCI glue driver"); 622 MODULE_LICENSE("GPL"); 623