xref: /openbmc/linux/drivers/thermal/tegra/soctherm.c (revision 53f9cd5c)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2014 - 2018, NVIDIA CORPORATION.  All rights reserved.
4  *
5  * Author:
6  *	Mikko Perttunen <mperttunen@nvidia.com>
7  *
8  * This software is licensed under the terms of the GNU General Public
9  * License version 2, as published by the Free Software Foundation, and
10  * may be copied, distributed, and modified under those terms.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  */
18 
19 #include <linux/debugfs.h>
20 #include <linux/bitops.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/err.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/irq.h>
27 #include <linux/irqdomain.h>
28 #include <linux/module.h>
29 #include <linux/of.h>
30 #include <linux/platform_device.h>
31 #include <linux/reset.h>
32 #include <linux/thermal.h>
33 
34 #include <dt-bindings/thermal/tegra124-soctherm.h>
35 
36 #include "../thermal_core.h"
37 #include "soctherm.h"
38 
39 #define SENSOR_CONFIG0				0
40 #define SENSOR_CONFIG0_STOP			BIT(0)
41 #define SENSOR_CONFIG0_CPTR_OVER		BIT(2)
42 #define SENSOR_CONFIG0_OVER			BIT(3)
43 #define SENSOR_CONFIG0_TCALC_OVER		BIT(4)
44 #define SENSOR_CONFIG0_TALL_MASK		(0xfffff << 8)
45 #define SENSOR_CONFIG0_TALL_SHIFT		8
46 
47 #define SENSOR_CONFIG1				4
48 #define SENSOR_CONFIG1_TSAMPLE_MASK		0x3ff
49 #define SENSOR_CONFIG1_TSAMPLE_SHIFT		0
50 #define SENSOR_CONFIG1_TIDDQ_EN_MASK		(0x3f << 15)
51 #define SENSOR_CONFIG1_TIDDQ_EN_SHIFT		15
52 #define SENSOR_CONFIG1_TEN_COUNT_MASK		(0x3f << 24)
53 #define SENSOR_CONFIG1_TEN_COUNT_SHIFT		24
54 #define SENSOR_CONFIG1_TEMP_ENABLE		BIT(31)
55 
56 /*
57  * SENSOR_CONFIG2 is defined in soctherm.h
58  * because, it will be used by tegra_soctherm_fuse.c
59  */
60 
61 #define SENSOR_STATUS0				0xc
62 #define SENSOR_STATUS0_VALID_MASK		BIT(31)
63 #define SENSOR_STATUS0_CAPTURE_MASK		0xffff
64 
65 #define SENSOR_STATUS1				0x10
66 #define SENSOR_STATUS1_TEMP_VALID_MASK		BIT(31)
67 #define SENSOR_STATUS1_TEMP_MASK		0xffff
68 
69 #define READBACK_VALUE_MASK			0xff00
70 #define READBACK_VALUE_SHIFT			8
71 #define READBACK_ADD_HALF			BIT(7)
72 #define READBACK_NEGATE				BIT(0)
73 
74 /*
75  * THERMCTL_LEVEL0_GROUP_CPU is defined in soctherm.h
76  * because it will be used by tegraxxx_soctherm.c
77  */
78 #define THERMCTL_LVL0_CPU0_EN_MASK		BIT(8)
79 #define THERMCTL_LVL0_CPU0_CPU_THROT_MASK	(0x3 << 5)
80 #define THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT	0x1
81 #define THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY	0x2
82 #define THERMCTL_LVL0_CPU0_GPU_THROT_MASK	(0x3 << 3)
83 #define THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT	0x1
84 #define THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY	0x2
85 #define THERMCTL_LVL0_CPU0_MEM_THROT_MASK	BIT(2)
86 #define THERMCTL_LVL0_CPU0_STATUS_MASK		0x3
87 
88 #define THERMCTL_LVL0_UP_STATS			0x10
89 #define THERMCTL_LVL0_DN_STATS			0x14
90 
91 #define THERMCTL_INTR_STATUS			0x84
92 
93 #define TH_INTR_MD0_MASK			BIT(25)
94 #define TH_INTR_MU0_MASK			BIT(24)
95 #define TH_INTR_GD0_MASK			BIT(17)
96 #define TH_INTR_GU0_MASK			BIT(16)
97 #define TH_INTR_CD0_MASK			BIT(9)
98 #define TH_INTR_CU0_MASK			BIT(8)
99 #define TH_INTR_PD0_MASK			BIT(1)
100 #define TH_INTR_PU0_MASK			BIT(0)
101 #define TH_INTR_IGNORE_MASK			0xFCFCFCFC
102 
103 #define THERMCTL_STATS_CTL			0x94
104 #define STATS_CTL_CLR_DN			0x8
105 #define STATS_CTL_EN_DN				0x4
106 #define STATS_CTL_CLR_UP			0x2
107 #define STATS_CTL_EN_UP				0x1
108 
109 #define OC1_CFG					0x310
110 #define OC1_CFG_LONG_LATENCY_MASK		BIT(6)
111 #define OC1_CFG_HW_RESTORE_MASK			BIT(5)
112 #define OC1_CFG_PWR_GOOD_MASK_MASK		BIT(4)
113 #define OC1_CFG_THROTTLE_MODE_MASK		(0x3 << 2)
114 #define OC1_CFG_ALARM_POLARITY_MASK		BIT(1)
115 #define OC1_CFG_EN_THROTTLE_MASK		BIT(0)
116 
117 #define OC1_CNT_THRESHOLD			0x314
118 #define OC1_THROTTLE_PERIOD			0x318
119 #define OC1_ALARM_COUNT				0x31c
120 #define OC1_FILTER				0x320
121 #define OC1_STATS				0x3a8
122 
123 #define OC_INTR_STATUS				0x39c
124 #define OC_INTR_ENABLE				0x3a0
125 #define OC_INTR_DISABLE				0x3a4
126 #define OC_STATS_CTL				0x3c4
127 #define OC_STATS_CTL_CLR_ALL			0x2
128 #define OC_STATS_CTL_EN_ALL			0x1
129 
130 #define OC_INTR_OC1_MASK			BIT(0)
131 #define OC_INTR_OC2_MASK			BIT(1)
132 #define OC_INTR_OC3_MASK			BIT(2)
133 #define OC_INTR_OC4_MASK			BIT(3)
134 #define OC_INTR_OC5_MASK			BIT(4)
135 
136 #define THROT_GLOBAL_CFG			0x400
137 #define THROT_GLOBAL_ENB_MASK			BIT(0)
138 
139 #define CPU_PSKIP_STATUS			0x418
140 #define XPU_PSKIP_STATUS_M_MASK			(0xff << 12)
141 #define XPU_PSKIP_STATUS_N_MASK			(0xff << 4)
142 #define XPU_PSKIP_STATUS_SW_OVERRIDE_MASK	BIT(1)
143 #define XPU_PSKIP_STATUS_ENABLED_MASK		BIT(0)
144 
145 #define THROT_PRIORITY_LOCK			0x424
146 #define THROT_PRIORITY_LOCK_PRIORITY_MASK	0xff
147 
148 #define THROT_STATUS				0x428
149 #define THROT_STATUS_BREACH_MASK		BIT(12)
150 #define THROT_STATUS_STATE_MASK			(0xff << 4)
151 #define THROT_STATUS_ENABLED_MASK		BIT(0)
152 
153 #define THROT_PSKIP_CTRL_LITE_CPU		0x430
154 #define THROT_PSKIP_CTRL_ENABLE_MASK            BIT(31)
155 #define THROT_PSKIP_CTRL_DIVIDEND_MASK          (0xff << 8)
156 #define THROT_PSKIP_CTRL_DIVISOR_MASK           0xff
157 #define THROT_PSKIP_CTRL_VECT_GPU_MASK          (0x7 << 16)
158 #define THROT_PSKIP_CTRL_VECT_CPU_MASK          (0x7 << 8)
159 #define THROT_PSKIP_CTRL_VECT2_CPU_MASK         0x7
160 
161 #define THROT_VECT_NONE				0x0 /* 3'b000 */
162 #define THROT_VECT_LOW				0x1 /* 3'b001 */
163 #define THROT_VECT_MED				0x3 /* 3'b011 */
164 #define THROT_VECT_HIGH				0x7 /* 3'b111 */
165 
166 #define THROT_PSKIP_RAMP_LITE_CPU		0x434
167 #define THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK	BIT(31)
168 #define THROT_PSKIP_RAMP_DURATION_MASK		(0xffff << 8)
169 #define THROT_PSKIP_RAMP_STEP_MASK		0xff
170 
171 #define THROT_PRIORITY_LITE			0x444
172 #define THROT_PRIORITY_LITE_PRIO_MASK		0xff
173 
174 #define THROT_DELAY_LITE			0x448
175 #define THROT_DELAY_LITE_DELAY_MASK		0xff
176 
177 /* car register offsets needed for enabling HW throttling */
178 #define CAR_SUPER_CCLKG_DIVIDER			0x36c
179 #define CDIVG_USE_THERM_CONTROLS_MASK		BIT(30)
180 
181 /* ccroc register offsets needed for enabling HW throttling for Tegra132 */
182 #define CCROC_SUPER_CCLKG_DIVIDER		0x024
183 
184 #define CCROC_GLOBAL_CFG			0x148
185 
186 #define CCROC_THROT_PSKIP_RAMP_CPU		0x150
187 #define CCROC_THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK	BIT(31)
188 #define CCROC_THROT_PSKIP_RAMP_DURATION_MASK	(0xffff << 8)
189 #define CCROC_THROT_PSKIP_RAMP_STEP_MASK	0xff
190 
191 #define CCROC_THROT_PSKIP_CTRL_CPU		0x154
192 #define CCROC_THROT_PSKIP_CTRL_ENB_MASK		BIT(31)
193 #define CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK	(0xff << 8)
194 #define CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK	0xff
195 
196 /* get val from register(r) mask bits(m) */
197 #define REG_GET_MASK(r, m)	(((r) & (m)) >> (ffs(m) - 1))
198 /* set val(v) to mask bits(m) of register(r) */
199 #define REG_SET_MASK(r, m, v)	(((r) & ~(m)) | \
200 				 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1)))
201 
202 /* get dividend from the depth */
203 #define THROT_DEPTH_DIVIDEND(depth)	((256 * (100 - (depth)) / 100) - 1)
204 
205 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-soctherm.h
206  * level	vector
207  * NONE		3'b000
208  * LOW		3'b001
209  * MED		3'b011
210  * HIGH		3'b111
211  */
212 #define THROT_LEVEL_TO_DEPTH(level)	((0x1 << (level)) - 1)
213 
214 /* get THROT_PSKIP_xxx offset per LIGHT/HEAVY throt and CPU/GPU dev */
215 #define THROT_OFFSET			0x30
216 #define THROT_PSKIP_CTRL(throt, dev)	(THROT_PSKIP_CTRL_LITE_CPU + \
217 					(THROT_OFFSET * throt) + (8 * dev))
218 #define THROT_PSKIP_RAMP(throt, dev)	(THROT_PSKIP_RAMP_LITE_CPU + \
219 					(THROT_OFFSET * throt) + (8 * dev))
220 
221 /* get THROT_xxx_CTRL offset per LIGHT/HEAVY throt */
222 #define THROT_PRIORITY_CTRL(throt)	(THROT_PRIORITY_LITE + \
223 					(THROT_OFFSET * throt))
224 #define THROT_DELAY_CTRL(throt)		(THROT_DELAY_LITE + \
225 					(THROT_OFFSET * throt))
226 
227 #define ALARM_OFFSET			0x14
228 #define ALARM_CFG(throt)		(OC1_CFG + \
229 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
230 
231 #define ALARM_CNT_THRESHOLD(throt)	(OC1_CNT_THRESHOLD + \
232 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
233 
234 #define ALARM_THROTTLE_PERIOD(throt)	(OC1_THROTTLE_PERIOD + \
235 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
236 
237 #define ALARM_ALARM_COUNT(throt)	(OC1_ALARM_COUNT + \
238 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
239 
240 #define ALARM_FILTER(throt)		(OC1_FILTER + \
241 					(ALARM_OFFSET * (throt - THROTTLE_OC1)))
242 
243 #define ALARM_STATS(throt)		(OC1_STATS + \
244 					(4 * (throt - THROTTLE_OC1)))
245 
246 /* get CCROC_THROT_PSKIP_xxx offset per HIGH/MED/LOW vect*/
247 #define CCROC_THROT_OFFSET			0x0c
248 #define CCROC_THROT_PSKIP_CTRL_CPU_REG(vect)    (CCROC_THROT_PSKIP_CTRL_CPU + \
249 						(CCROC_THROT_OFFSET * vect))
250 #define CCROC_THROT_PSKIP_RAMP_CPU_REG(vect)    (CCROC_THROT_PSKIP_RAMP_CPU + \
251 						(CCROC_THROT_OFFSET * vect))
252 
253 /* get THERMCTL_LEVELx offset per CPU/GPU/MEM/TSENSE rg and LEVEL0~3 lv */
254 #define THERMCTL_LVL_REGS_SIZE		0x20
255 #define THERMCTL_LVL_REG(rg, lv)	((rg) + ((lv) * THERMCTL_LVL_REGS_SIZE))
256 
257 #define OC_THROTTLE_MODE_DISABLED	0
258 #define OC_THROTTLE_MODE_BRIEF		2
259 
260 static const int min_low_temp = -127000;
261 static const int max_high_temp = 127000;
262 
263 enum soctherm_throttle_id {
264 	THROTTLE_LIGHT = 0,
265 	THROTTLE_HEAVY,
266 	THROTTLE_OC1,
267 	THROTTLE_OC2,
268 	THROTTLE_OC3,
269 	THROTTLE_OC4,
270 	THROTTLE_OC5, /* OC5 is reserved */
271 	THROTTLE_SIZE,
272 };
273 
274 enum soctherm_oc_irq_id {
275 	TEGRA_SOC_OC_IRQ_1,
276 	TEGRA_SOC_OC_IRQ_2,
277 	TEGRA_SOC_OC_IRQ_3,
278 	TEGRA_SOC_OC_IRQ_4,
279 	TEGRA_SOC_OC_IRQ_5,
280 	TEGRA_SOC_OC_IRQ_MAX,
281 };
282 
283 enum soctherm_throttle_dev_id {
284 	THROTTLE_DEV_CPU = 0,
285 	THROTTLE_DEV_GPU,
286 	THROTTLE_DEV_SIZE,
287 };
288 
289 static const char *const throt_names[] = {
290 	[THROTTLE_LIGHT] = "light",
291 	[THROTTLE_HEAVY] = "heavy",
292 	[THROTTLE_OC1]   = "oc1",
293 	[THROTTLE_OC2]   = "oc2",
294 	[THROTTLE_OC3]   = "oc3",
295 	[THROTTLE_OC4]   = "oc4",
296 	[THROTTLE_OC5]   = "oc5",
297 };
298 
299 struct tegra_soctherm;
300 struct tegra_thermctl_zone {
301 	void __iomem *reg;
302 	struct device *dev;
303 	struct tegra_soctherm *ts;
304 	struct thermal_zone_device *tz;
305 	const struct tegra_tsensor_group *sg;
306 };
307 
308 struct soctherm_oc_cfg {
309 	u32 active_low;
310 	u32 throt_period;
311 	u32 alarm_cnt_thresh;
312 	u32 alarm_filter;
313 	u32 mode;
314 	bool intr_en;
315 };
316 
317 struct soctherm_throt_cfg {
318 	const char *name;
319 	unsigned int id;
320 	u8 priority;
321 	u8 cpu_throt_level;
322 	u32 cpu_throt_depth;
323 	u32 gpu_throt_level;
324 	struct soctherm_oc_cfg oc_cfg;
325 	struct thermal_cooling_device *cdev;
326 	bool init;
327 };
328 
329 struct tegra_soctherm {
330 	struct reset_control *reset;
331 	struct clk *clock_tsensor;
332 	struct clk *clock_soctherm;
333 	void __iomem *regs;
334 	void __iomem *clk_regs;
335 	void __iomem *ccroc_regs;
336 
337 	int thermal_irq;
338 	int edp_irq;
339 
340 	u32 *calib;
341 	struct thermal_zone_device **thermctl_tzs;
342 	struct tegra_soctherm_soc *soc;
343 
344 	struct soctherm_throt_cfg throt_cfgs[THROTTLE_SIZE];
345 
346 	struct dentry *debugfs_dir;
347 
348 	struct mutex thermctl_lock;
349 };
350 
351 struct soctherm_oc_irq_chip_data {
352 	struct mutex		irq_lock; /* serialize OC IRQs */
353 	struct irq_chip		irq_chip;
354 	struct irq_domain	*domain;
355 	int			irq_enable;
356 };
357 
358 static struct soctherm_oc_irq_chip_data soc_irq_cdata;
359 
360 /**
361  * ccroc_writel() - writes a value to a CCROC register
362  * @ts: pointer to a struct tegra_soctherm
363  * @value: the value to write
364  * @reg: the register offset
365  *
366  * Writes @v to @reg.  No return value.
367  */
368 static inline void ccroc_writel(struct tegra_soctherm *ts, u32 value, u32 reg)
369 {
370 	writel(value, (ts->ccroc_regs + reg));
371 }
372 
373 /**
374  * ccroc_readl() - reads specified register from CCROC IP block
375  * @ts: pointer to a struct tegra_soctherm
376  * @reg: register address to be read
377  *
378  * Return: the value of the register
379  */
380 static inline u32 ccroc_readl(struct tegra_soctherm *ts, u32 reg)
381 {
382 	return readl(ts->ccroc_regs + reg);
383 }
384 
385 static void enable_tsensor(struct tegra_soctherm *tegra, unsigned int i)
386 {
387 	const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i];
388 	void __iomem *base = tegra->regs + sensor->base;
389 	unsigned int val;
390 
391 	val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT;
392 	writel(val, base + SENSOR_CONFIG0);
393 
394 	val  = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT;
395 	val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT;
396 	val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT;
397 	val |= SENSOR_CONFIG1_TEMP_ENABLE;
398 	writel(val, base + SENSOR_CONFIG1);
399 
400 	writel(tegra->calib[i], base + SENSOR_CONFIG2);
401 }
402 
403 /*
404  * Translate from soctherm readback format to millicelsius.
405  * The soctherm readback format in bits is as follows:
406  *   TTTTTTTT H______N
407  * where T's contain the temperature in Celsius,
408  * H denotes an addition of 0.5 Celsius and N denotes negation
409  * of the final value.
410  */
411 static int translate_temp(u16 val)
412 {
413 	int t;
414 
415 	t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000;
416 	if (val & READBACK_ADD_HALF)
417 		t += 500;
418 	if (val & READBACK_NEGATE)
419 		t *= -1;
420 
421 	return t;
422 }
423 
424 static int tegra_thermctl_get_temp(void *data, int *out_temp)
425 {
426 	struct tegra_thermctl_zone *zone = data;
427 	u32 val;
428 
429 	val = readl(zone->reg);
430 	val = REG_GET_MASK(val, zone->sg->sensor_temp_mask);
431 	*out_temp = translate_temp(val);
432 
433 	return 0;
434 }
435 
436 /**
437  * enforce_temp_range() - check and enforce temperature range [min, max]
438  * @dev: struct device * of the SOC_THERM instance
439  * @trip_temp: the trip temperature to check
440  *
441  * Checks and enforces the permitted temperature range that SOC_THERM
442  * HW can support This is
443  * done while taking care of precision.
444  *
445  * Return: The precision adjusted capped temperature in millicelsius.
446  */
447 static int enforce_temp_range(struct device *dev, int trip_temp)
448 {
449 	int temp;
450 
451 	temp = clamp_val(trip_temp, min_low_temp, max_high_temp);
452 	if (temp != trip_temp)
453 		dev_dbg(dev, "soctherm: trip temperature %d forced to %d\n",
454 			trip_temp, temp);
455 	return temp;
456 }
457 
458 /**
459  * thermtrip_program() - Configures the hardware to shut down the
460  * system if a given sensor group reaches a given temperature
461  * @dev: ptr to the struct device for the SOC_THERM IP block
462  * @sg: pointer to the sensor group to set the thermtrip temperature for
463  * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
464  *
465  * Sets the thermal trip threshold of the given sensor group to be the
466  * @trip_temp.  If this threshold is crossed, the hardware will shut
467  * down.
468  *
469  * Note that, although @trip_temp is specified in millicelsius, the
470  * hardware is programmed in degrees Celsius.
471  *
472  * Return: 0 upon success, or %-EINVAL upon failure.
473  */
474 static int thermtrip_program(struct device *dev,
475 			     const struct tegra_tsensor_group *sg,
476 			     int trip_temp)
477 {
478 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
479 	int temp;
480 	u32 r;
481 
482 	if (!sg || !sg->thermtrip_threshold_mask)
483 		return -EINVAL;
484 
485 	temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;
486 
487 	r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);
488 	r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp);
489 	r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1);
490 	r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0);
491 	writel(r, ts->regs + THERMCTL_THERMTRIP_CTL);
492 
493 	return 0;
494 }
495 
496 /**
497  * throttrip_program() - Configures the hardware to throttle the
498  * pulse if a given sensor group reaches a given temperature
499  * @dev: ptr to the struct device for the SOC_THERM IP block
500  * @sg: pointer to the sensor group to set the thermtrip temperature for
501  * @stc: pointer to the throttle need to be triggered
502  * @trip_temp: the temperature in millicelsius to trigger the thermal trip at
503  *
504  * Sets the thermal trip threshold and throttle event of the given sensor
505  * group. If this threshold is crossed, the hardware will trigger the
506  * throttle.
507  *
508  * Note that, although @trip_temp is specified in millicelsius, the
509  * hardware is programmed in degrees Celsius.
510  *
511  * Return: 0 upon success, or %-EINVAL upon failure.
512  */
513 static int throttrip_program(struct device *dev,
514 			     const struct tegra_tsensor_group *sg,
515 			     struct soctherm_throt_cfg *stc,
516 			     int trip_temp)
517 {
518 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
519 	int temp, cpu_throt, gpu_throt;
520 	unsigned int throt;
521 	u32 r, reg_off;
522 
523 	if (!sg || !stc || !stc->init)
524 		return -EINVAL;
525 
526 	temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain;
527 
528 	/* Hardcode LIGHT on LEVEL1 and HEAVY on LEVEL2 */
529 	throt = stc->id;
530 	reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1);
531 
532 	if (throt == THROTTLE_LIGHT) {
533 		cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT;
534 		gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT;
535 	} else {
536 		cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY;
537 		gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY;
538 		if (throt != THROTTLE_HEAVY)
539 			dev_warn(dev,
540 				 "invalid throt id %d - assuming HEAVY",
541 				 throt);
542 	}
543 
544 	r = readl(ts->regs + reg_off);
545 	r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp);
546 	r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp);
547 	r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_CPU_THROT_MASK, cpu_throt);
548 	r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_GPU_THROT_MASK, gpu_throt);
549 	r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
550 	writel(r, ts->regs + reg_off);
551 
552 	return 0;
553 }
554 
555 static struct soctherm_throt_cfg *
556 find_throttle_cfg_by_name(struct tegra_soctherm *ts, const char *name)
557 {
558 	unsigned int i;
559 
560 	for (i = 0; ts->throt_cfgs[i].name; i++)
561 		if (!strcmp(ts->throt_cfgs[i].name, name))
562 			return &ts->throt_cfgs[i];
563 
564 	return NULL;
565 }
566 
567 static int tsensor_group_thermtrip_get(struct tegra_soctherm *ts, int id)
568 {
569 	int i, temp = min_low_temp;
570 	struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;
571 
572 	if (id >= TEGRA124_SOCTHERM_SENSOR_NUM)
573 		return temp;
574 
575 	if (tt) {
576 		for (i = 0; i < ts->soc->num_ttgs; i++) {
577 			if (tt[i].id == id)
578 				return tt[i].temp;
579 		}
580 	}
581 
582 	return temp;
583 }
584 
585 static int tegra_thermctl_set_trip_temp(void *data, int trip, int temp)
586 {
587 	struct tegra_thermctl_zone *zone = data;
588 	struct thermal_zone_device *tz = zone->tz;
589 	struct tegra_soctherm *ts = zone->ts;
590 	const struct tegra_tsensor_group *sg = zone->sg;
591 	struct device *dev = zone->dev;
592 	enum thermal_trip_type type;
593 	int ret;
594 
595 	if (!tz)
596 		return -EINVAL;
597 
598 	ret = tz->ops->get_trip_type(tz, trip, &type);
599 	if (ret)
600 		return ret;
601 
602 	if (type == THERMAL_TRIP_CRITICAL) {
603 		/*
604 		 * If thermtrips property is set in DT,
605 		 * doesn't need to program critical type trip to HW,
606 		 * if not, program critical trip to HW.
607 		 */
608 		if (min_low_temp == tsensor_group_thermtrip_get(ts, sg->id))
609 			return thermtrip_program(dev, sg, temp);
610 		else
611 			return 0;
612 
613 	} else if (type == THERMAL_TRIP_HOT) {
614 		int i;
615 
616 		for (i = 0; i < THROTTLE_SIZE; i++) {
617 			struct thermal_cooling_device *cdev;
618 			struct soctherm_throt_cfg *stc;
619 
620 			if (!ts->throt_cfgs[i].init)
621 				continue;
622 
623 			cdev = ts->throt_cfgs[i].cdev;
624 			if (get_thermal_instance(tz, cdev, trip))
625 				stc = find_throttle_cfg_by_name(ts, cdev->type);
626 			else
627 				continue;
628 
629 			return throttrip_program(dev, sg, stc, temp);
630 		}
631 	}
632 
633 	return 0;
634 }
635 
636 static void thermal_irq_enable(struct tegra_thermctl_zone *zn)
637 {
638 	u32 r;
639 
640 	/* multiple zones could be handling and setting trips at once */
641 	mutex_lock(&zn->ts->thermctl_lock);
642 	r = readl(zn->ts->regs + THERMCTL_INTR_ENABLE);
643 	r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN);
644 	writel(r, zn->ts->regs + THERMCTL_INTR_ENABLE);
645 	mutex_unlock(&zn->ts->thermctl_lock);
646 }
647 
648 static void thermal_irq_disable(struct tegra_thermctl_zone *zn)
649 {
650 	u32 r;
651 
652 	/* multiple zones could be handling and setting trips at once */
653 	mutex_lock(&zn->ts->thermctl_lock);
654 	r = readl(zn->ts->regs + THERMCTL_INTR_DISABLE);
655 	r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0);
656 	writel(r, zn->ts->regs + THERMCTL_INTR_DISABLE);
657 	mutex_unlock(&zn->ts->thermctl_lock);
658 }
659 
660 static int tegra_thermctl_set_trips(void *data, int lo, int hi)
661 {
662 	struct tegra_thermctl_zone *zone = data;
663 	u32 r;
664 
665 	thermal_irq_disable(zone);
666 
667 	r = readl(zone->ts->regs + zone->sg->thermctl_lvl0_offset);
668 	r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 0);
669 	writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
670 
671 	lo = enforce_temp_range(zone->dev, lo) / zone->ts->soc->thresh_grain;
672 	hi = enforce_temp_range(zone->dev, hi) / zone->ts->soc->thresh_grain;
673 	dev_dbg(zone->dev, "%s hi:%d, lo:%d\n", __func__, hi, lo);
674 
675 	r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi);
676 	r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo);
677 	r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1);
678 	writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset);
679 
680 	thermal_irq_enable(zone);
681 
682 	return 0;
683 }
684 
685 static const struct thermal_zone_of_device_ops tegra_of_thermal_ops = {
686 	.get_temp = tegra_thermctl_get_temp,
687 	.set_trip_temp = tegra_thermctl_set_trip_temp,
688 	.set_trips = tegra_thermctl_set_trips,
689 };
690 
691 static int get_hot_temp(struct thermal_zone_device *tz, int *trip, int *temp)
692 {
693 	int ntrips, i, ret;
694 	enum thermal_trip_type type;
695 
696 	ntrips = of_thermal_get_ntrips(tz);
697 	if (ntrips <= 0)
698 		return -EINVAL;
699 
700 	for (i = 0; i < ntrips; i++) {
701 		ret = tz->ops->get_trip_type(tz, i, &type);
702 		if (ret)
703 			return -EINVAL;
704 		if (type == THERMAL_TRIP_HOT) {
705 			ret = tz->ops->get_trip_temp(tz, i, temp);
706 			if (!ret)
707 				*trip = i;
708 
709 			return ret;
710 		}
711 	}
712 
713 	return -EINVAL;
714 }
715 
716 /**
717  * tegra_soctherm_set_hwtrips() - set HW trip point from DT data
718  * @dev: struct device * of the SOC_THERM instance
719  * @sg: pointer to the sensor group to set the thermtrip temperature for
720  * @tz: struct thermal_zone_device *
721  *
722  * Configure the SOC_THERM HW trip points, setting "THERMTRIP"
723  * "THROTTLE" trip points , using "thermtrips", "critical" or "hot"
724  * type trip_temp
725  * from thermal zone.
726  * After they have been configured, THERMTRIP or THROTTLE will take
727  * action when the configured SoC thermal sensor group reaches a
728  * certain temperature.
729  *
730  * Return: 0 upon success, or a negative error code on failure.
731  * "Success" does not mean that trips was enabled; it could also
732  * mean that no node was found in DT.
733  * THERMTRIP has been enabled successfully when a message similar to
734  * this one appears on the serial console:
735  * "thermtrip: will shut down when sensor group XXX reaches YYYYYY mC"
736  * THROTTLE has been enabled successfully when a message similar to
737  * this one appears on the serial console:
738  * ""throttrip: will throttle when sensor group XXX reaches YYYYYY mC"
739  */
740 static int tegra_soctherm_set_hwtrips(struct device *dev,
741 				      const struct tegra_tsensor_group *sg,
742 				      struct thermal_zone_device *tz)
743 {
744 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
745 	struct soctherm_throt_cfg *stc;
746 	int i, trip, temperature, ret;
747 
748 	/* Get thermtrips. If missing, try to get critical trips. */
749 	temperature = tsensor_group_thermtrip_get(ts, sg->id);
750 	if (min_low_temp == temperature)
751 		if (tz->ops->get_crit_temp(tz, &temperature))
752 			temperature = max_high_temp;
753 
754 	ret = thermtrip_program(dev, sg, temperature);
755 	if (ret) {
756 		dev_err(dev, "thermtrip: %s: error during enable\n", sg->name);
757 		return ret;
758 	}
759 
760 	dev_info(dev, "thermtrip: will shut down when %s reaches %d mC\n",
761 		 sg->name, temperature);
762 
763 	ret = get_hot_temp(tz, &trip, &temperature);
764 	if (ret) {
765 		dev_info(dev, "throttrip: %s: missing hot temperature\n",
766 			 sg->name);
767 		return 0;
768 	}
769 
770 	for (i = 0; i < THROTTLE_OC1; i++) {
771 		struct thermal_cooling_device *cdev;
772 
773 		if (!ts->throt_cfgs[i].init)
774 			continue;
775 
776 		cdev = ts->throt_cfgs[i].cdev;
777 		if (get_thermal_instance(tz, cdev, trip))
778 			stc = find_throttle_cfg_by_name(ts, cdev->type);
779 		else
780 			continue;
781 
782 		ret = throttrip_program(dev, sg, stc, temperature);
783 		if (ret) {
784 			dev_err(dev, "throttrip: %s: error during enable\n",
785 				sg->name);
786 			return ret;
787 		}
788 
789 		dev_info(dev,
790 			 "throttrip: will throttle when %s reaches %d mC\n",
791 			 sg->name, temperature);
792 		break;
793 	}
794 
795 	if (i == THROTTLE_SIZE)
796 		dev_info(dev, "throttrip: %s: missing throttle cdev\n",
797 			 sg->name);
798 
799 	return 0;
800 }
801 
802 static irqreturn_t soctherm_thermal_isr(int irq, void *dev_id)
803 {
804 	struct tegra_soctherm *ts = dev_id;
805 	u32 r;
806 
807 	/* Case for no lock:
808 	 * Although interrupts are enabled in set_trips, there is still no need
809 	 * to lock here because the interrupts are disabled before programming
810 	 * new trip points. Hence there cant be a interrupt on the same sensor.
811 	 * An interrupt can however occur on a sensor while trips are being
812 	 * programmed on a different one. This beign a LEVEL interrupt won't
813 	 * cause a new interrupt but this is taken care of by the re-reading of
814 	 * the STATUS register in the thread function.
815 	 */
816 	r = readl(ts->regs + THERMCTL_INTR_STATUS);
817 	writel(r, ts->regs + THERMCTL_INTR_DISABLE);
818 
819 	return IRQ_WAKE_THREAD;
820 }
821 
822 /**
823  * soctherm_thermal_isr_thread() - Handles a thermal interrupt request
824  * @irq:       The interrupt number being requested; not used
825  * @dev_id:    Opaque pointer to tegra_soctherm;
826  *
827  * Clears the interrupt status register if there are expected
828  * interrupt bits set.
829  * The interrupt(s) are then handled by updating the corresponding
830  * thermal zones.
831  *
832  * An error is logged if any unexpected interrupt bits are set.
833  *
834  * Disabled interrupts are re-enabled.
835  *
836  * Return: %IRQ_HANDLED. Interrupt was handled and no further processing
837  * is needed.
838  */
839 static irqreturn_t soctherm_thermal_isr_thread(int irq, void *dev_id)
840 {
841 	struct tegra_soctherm *ts = dev_id;
842 	struct thermal_zone_device *tz;
843 	u32 st, ex = 0, cp = 0, gp = 0, pl = 0, me = 0;
844 
845 	st = readl(ts->regs + THERMCTL_INTR_STATUS);
846 
847 	/* deliberately clear expected interrupts handled in SW */
848 	cp |= st & TH_INTR_CD0_MASK;
849 	cp |= st & TH_INTR_CU0_MASK;
850 
851 	gp |= st & TH_INTR_GD0_MASK;
852 	gp |= st & TH_INTR_GU0_MASK;
853 
854 	pl |= st & TH_INTR_PD0_MASK;
855 	pl |= st & TH_INTR_PU0_MASK;
856 
857 	me |= st & TH_INTR_MD0_MASK;
858 	me |= st & TH_INTR_MU0_MASK;
859 
860 	ex |= cp | gp | pl | me;
861 	if (ex) {
862 		writel(ex, ts->regs + THERMCTL_INTR_STATUS);
863 		st &= ~ex;
864 
865 		if (cp) {
866 			tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_CPU];
867 			thermal_zone_device_update(tz,
868 						   THERMAL_EVENT_UNSPECIFIED);
869 		}
870 
871 		if (gp) {
872 			tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_GPU];
873 			thermal_zone_device_update(tz,
874 						   THERMAL_EVENT_UNSPECIFIED);
875 		}
876 
877 		if (pl) {
878 			tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_PLLX];
879 			thermal_zone_device_update(tz,
880 						   THERMAL_EVENT_UNSPECIFIED);
881 		}
882 
883 		if (me) {
884 			tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_MEM];
885 			thermal_zone_device_update(tz,
886 						   THERMAL_EVENT_UNSPECIFIED);
887 		}
888 	}
889 
890 	/* deliberately ignore expected interrupts NOT handled in SW */
891 	ex |= TH_INTR_IGNORE_MASK;
892 	st &= ~ex;
893 
894 	if (st) {
895 		/* Whine about any other unexpected INTR bits still set */
896 		pr_err("soctherm: Ignored unexpected INTRs 0x%08x\n", st);
897 		writel(st, ts->regs + THERMCTL_INTR_STATUS);
898 	}
899 
900 	return IRQ_HANDLED;
901 }
902 
903 /**
904  * soctherm_oc_intr_enable() - Enables the soctherm over-current interrupt
905  * @ts:		pointer to a struct tegra_soctherm
906  * @alarm:		The soctherm throttle id
907  * @enable:		Flag indicating enable the soctherm over-current
908  *			interrupt or disable it
909  *
910  * Enables a specific over-current pins @alarm to raise an interrupt if the flag
911  * is set and the alarm corresponds to OC1, OC2, OC3, or OC4.
912  */
913 static void soctherm_oc_intr_enable(struct tegra_soctherm *ts,
914 				    enum soctherm_throttle_id alarm,
915 				    bool enable)
916 {
917 	u32 r;
918 
919 	if (!enable)
920 		return;
921 
922 	r = readl(ts->regs + OC_INTR_ENABLE);
923 	switch (alarm) {
924 	case THROTTLE_OC1:
925 		r = REG_SET_MASK(r, OC_INTR_OC1_MASK, 1);
926 		break;
927 	case THROTTLE_OC2:
928 		r = REG_SET_MASK(r, OC_INTR_OC2_MASK, 1);
929 		break;
930 	case THROTTLE_OC3:
931 		r = REG_SET_MASK(r, OC_INTR_OC3_MASK, 1);
932 		break;
933 	case THROTTLE_OC4:
934 		r = REG_SET_MASK(r, OC_INTR_OC4_MASK, 1);
935 		break;
936 	default:
937 		r = 0;
938 		break;
939 	}
940 	writel(r, ts->regs + OC_INTR_ENABLE);
941 }
942 
943 /**
944  * soctherm_handle_alarm() - Handles soctherm alarms
945  * @alarm:		The soctherm throttle id
946  *
947  * "Handles" over-current alarms (OC1, OC2, OC3, and OC4) by printing
948  * a warning or informative message.
949  *
950  * Return: -EINVAL for @alarm = THROTTLE_OC3, otherwise 0 (success).
951  */
952 static int soctherm_handle_alarm(enum soctherm_throttle_id alarm)
953 {
954 	int rv = -EINVAL;
955 
956 	switch (alarm) {
957 	case THROTTLE_OC1:
958 		pr_debug("soctherm: Successfully handled OC1 alarm\n");
959 		rv = 0;
960 		break;
961 
962 	case THROTTLE_OC2:
963 		pr_debug("soctherm: Successfully handled OC2 alarm\n");
964 		rv = 0;
965 		break;
966 
967 	case THROTTLE_OC3:
968 		pr_debug("soctherm: Successfully handled OC3 alarm\n");
969 		rv = 0;
970 		break;
971 
972 	case THROTTLE_OC4:
973 		pr_debug("soctherm: Successfully handled OC4 alarm\n");
974 		rv = 0;
975 		break;
976 
977 	default:
978 		break;
979 	}
980 
981 	if (rv)
982 		pr_err("soctherm: ERROR in handling %s alarm\n",
983 		       throt_names[alarm]);
984 
985 	return rv;
986 }
987 
988 /**
989  * soctherm_edp_isr_thread() - log an over-current interrupt request
990  * @irq:	OC irq number. Currently not being used. See description
991  * @arg:	a void pointer for callback, currently not being used
992  *
993  * Over-current events are handled in hardware. This function is called to log
994  * and handle any OC events that happened. Additionally, it checks every
995  * over-current interrupt registers for registers are set but
996  * was not expected (i.e. any discrepancy in interrupt status) by the function,
997  * the discrepancy will logged.
998  *
999  * Return: %IRQ_HANDLED
1000  */
1001 static irqreturn_t soctherm_edp_isr_thread(int irq, void *arg)
1002 {
1003 	struct tegra_soctherm *ts = arg;
1004 	u32 st, ex, oc1, oc2, oc3, oc4;
1005 
1006 	st = readl(ts->regs + OC_INTR_STATUS);
1007 
1008 	/* deliberately clear expected interrupts handled in SW */
1009 	oc1 = st & OC_INTR_OC1_MASK;
1010 	oc2 = st & OC_INTR_OC2_MASK;
1011 	oc3 = st & OC_INTR_OC3_MASK;
1012 	oc4 = st & OC_INTR_OC4_MASK;
1013 	ex = oc1 | oc2 | oc3 | oc4;
1014 
1015 	pr_err("soctherm: OC ALARM 0x%08x\n", ex);
1016 	if (ex) {
1017 		writel(st, ts->regs + OC_INTR_STATUS);
1018 		st &= ~ex;
1019 
1020 		if (oc1 && !soctherm_handle_alarm(THROTTLE_OC1))
1021 			soctherm_oc_intr_enable(ts, THROTTLE_OC1, true);
1022 
1023 		if (oc2 && !soctherm_handle_alarm(THROTTLE_OC2))
1024 			soctherm_oc_intr_enable(ts, THROTTLE_OC2, true);
1025 
1026 		if (oc3 && !soctherm_handle_alarm(THROTTLE_OC3))
1027 			soctherm_oc_intr_enable(ts, THROTTLE_OC3, true);
1028 
1029 		if (oc4 && !soctherm_handle_alarm(THROTTLE_OC4))
1030 			soctherm_oc_intr_enable(ts, THROTTLE_OC4, true);
1031 
1032 		if (oc1 && soc_irq_cdata.irq_enable & BIT(0))
1033 			handle_nested_irq(
1034 				irq_find_mapping(soc_irq_cdata.domain, 0));
1035 
1036 		if (oc2 && soc_irq_cdata.irq_enable & BIT(1))
1037 			handle_nested_irq(
1038 				irq_find_mapping(soc_irq_cdata.domain, 1));
1039 
1040 		if (oc3 && soc_irq_cdata.irq_enable & BIT(2))
1041 			handle_nested_irq(
1042 				irq_find_mapping(soc_irq_cdata.domain, 2));
1043 
1044 		if (oc4 && soc_irq_cdata.irq_enable & BIT(3))
1045 			handle_nested_irq(
1046 				irq_find_mapping(soc_irq_cdata.domain, 3));
1047 	}
1048 
1049 	if (st) {
1050 		pr_err("soctherm: Ignored unexpected OC ALARM 0x%08x\n", st);
1051 		writel(st, ts->regs + OC_INTR_STATUS);
1052 	}
1053 
1054 	return IRQ_HANDLED;
1055 }
1056 
1057 /**
1058  * soctherm_edp_isr() - Disables any active interrupts
1059  * @irq:	The interrupt request number
1060  * @arg:	Opaque pointer to an argument
1061  *
1062  * Writes to the OC_INTR_DISABLE register the over current interrupt status,
1063  * masking any asserted interrupts. Doing this prevents the same interrupts
1064  * from triggering this isr repeatedly. The thread woken by this isr will
1065  * handle asserted interrupts and subsequently unmask/re-enable them.
1066  *
1067  * The OC_INTR_DISABLE register indicates which OC interrupts
1068  * have been disabled.
1069  *
1070  * Return: %IRQ_WAKE_THREAD, handler requests to wake the handler thread
1071  */
1072 static irqreturn_t soctherm_edp_isr(int irq, void *arg)
1073 {
1074 	struct tegra_soctherm *ts = arg;
1075 	u32 r;
1076 
1077 	if (!ts)
1078 		return IRQ_NONE;
1079 
1080 	r = readl(ts->regs + OC_INTR_STATUS);
1081 	writel(r, ts->regs + OC_INTR_DISABLE);
1082 
1083 	return IRQ_WAKE_THREAD;
1084 }
1085 
1086 /**
1087  * soctherm_oc_irq_lock() - locks the over-current interrupt request
1088  * @data:	Interrupt request data
1089  *
1090  * Looks up the chip data from @data and locks the mutex associated with
1091  * a particular over-current interrupt request.
1092  */
1093 static void soctherm_oc_irq_lock(struct irq_data *data)
1094 {
1095 	struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
1096 
1097 	mutex_lock(&d->irq_lock);
1098 }
1099 
1100 /**
1101  * soctherm_oc_irq_sync_unlock() - Unlocks the OC interrupt request
1102  * @data:		Interrupt request data
1103  *
1104  * Looks up the interrupt request data @data and unlocks the mutex associated
1105  * with a particular over-current interrupt request.
1106  */
1107 static void soctherm_oc_irq_sync_unlock(struct irq_data *data)
1108 {
1109 	struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
1110 
1111 	mutex_unlock(&d->irq_lock);
1112 }
1113 
1114 /**
1115  * soctherm_oc_irq_enable() - Enables the SOC_THERM over-current interrupt queue
1116  * @data:       irq_data structure of the chip
1117  *
1118  * Sets the irq_enable bit of SOC_THERM allowing SOC_THERM
1119  * to respond to over-current interrupts.
1120  *
1121  */
1122 static void soctherm_oc_irq_enable(struct irq_data *data)
1123 {
1124 	struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
1125 
1126 	d->irq_enable |= BIT(data->hwirq);
1127 }
1128 
1129 /**
1130  * soctherm_oc_irq_disable() - Disables overcurrent interrupt requests
1131  * @data:	The interrupt request information
1132  *
1133  * Clears the interrupt request enable bit of the overcurrent
1134  * interrupt request chip data.
1135  *
1136  * Return: Nothing is returned (void)
1137  */
1138 static void soctherm_oc_irq_disable(struct irq_data *data)
1139 {
1140 	struct soctherm_oc_irq_chip_data *d = irq_data_get_irq_chip_data(data);
1141 
1142 	d->irq_enable &= ~BIT(data->hwirq);
1143 }
1144 
1145 static int soctherm_oc_irq_set_type(struct irq_data *data, unsigned int type)
1146 {
1147 	return 0;
1148 }
1149 
1150 /**
1151  * soctherm_oc_irq_map() - SOC_THERM interrupt request domain mapper
1152  * @h:		Interrupt request domain
1153  * @virq:	Virtual interrupt request number
1154  * @hw:		Hardware interrupt request number
1155  *
1156  * Mapping callback function for SOC_THERM's irq_domain. When a SOC_THERM
1157  * interrupt request is called, the irq_domain takes the request's virtual
1158  * request number (much like a virtual memory address) and maps it to a
1159  * physical hardware request number.
1160  *
1161  * When a mapping doesn't already exist for a virtual request number, the
1162  * irq_domain calls this function to associate the virtual request number with
1163  * a hardware request number.
1164  *
1165  * Return: 0
1166  */
1167 static int soctherm_oc_irq_map(struct irq_domain *h, unsigned int virq,
1168 		irq_hw_number_t hw)
1169 {
1170 	struct soctherm_oc_irq_chip_data *data = h->host_data;
1171 
1172 	irq_set_chip_data(virq, data);
1173 	irq_set_chip(virq, &data->irq_chip);
1174 	irq_set_nested_thread(virq, 1);
1175 	return 0;
1176 }
1177 
1178 /**
1179  * soctherm_irq_domain_xlate_twocell() - xlate for soctherm interrupts
1180  * @d:      Interrupt request domain
1181  * @ctrlr:      Controller device tree node
1182  * @intspec:    Array of u32s from DTs "interrupt" property
1183  * @intsize:    Number of values inside the intspec array
1184  * @out_hwirq:  HW IRQ value associated with this interrupt
1185  * @out_type:   The IRQ SENSE type for this interrupt.
1186  *
1187  * This Device Tree IRQ specifier translation function will translate a
1188  * specific "interrupt" as defined by 2 DT values where the cell values map
1189  * the hwirq number + 1 and linux irq flags. Since the output is the hwirq
1190  * number, this function will subtract 1 from the value listed in DT.
1191  *
1192  * Return: 0
1193  */
1194 static int soctherm_irq_domain_xlate_twocell(struct irq_domain *d,
1195 	struct device_node *ctrlr, const u32 *intspec, unsigned int intsize,
1196 	irq_hw_number_t *out_hwirq, unsigned int *out_type)
1197 {
1198 	if (WARN_ON(intsize < 2))
1199 		return -EINVAL;
1200 
1201 	/*
1202 	 * The HW value is 1 index less than the DT IRQ values.
1203 	 * i.e. OC4 goes to HW index 3.
1204 	 */
1205 	*out_hwirq = intspec[0] - 1;
1206 	*out_type = intspec[1] & IRQ_TYPE_SENSE_MASK;
1207 	return 0;
1208 }
1209 
1210 static const struct irq_domain_ops soctherm_oc_domain_ops = {
1211 	.map	= soctherm_oc_irq_map,
1212 	.xlate	= soctherm_irq_domain_xlate_twocell,
1213 };
1214 
1215 /**
1216  * soctherm_oc_int_init() - Initial enabling of the over
1217  * current interrupts
1218  * @np:	The devicetree node for soctherm
1219  * @num_irqs:	The number of new interrupt requests
1220  *
1221  * Sets the over current interrupt request chip data
1222  *
1223  * Return: 0 on success or if overcurrent interrupts are not enabled,
1224  * -ENOMEM (out of memory), or irq_base if the function failed to
1225  * allocate the irqs
1226  */
1227 static int soctherm_oc_int_init(struct device_node *np, int num_irqs)
1228 {
1229 	if (!num_irqs) {
1230 		pr_info("%s(): OC interrupts are not enabled\n", __func__);
1231 		return 0;
1232 	}
1233 
1234 	mutex_init(&soc_irq_cdata.irq_lock);
1235 	soc_irq_cdata.irq_enable = 0;
1236 
1237 	soc_irq_cdata.irq_chip.name = "soc_therm_oc";
1238 	soc_irq_cdata.irq_chip.irq_bus_lock = soctherm_oc_irq_lock;
1239 	soc_irq_cdata.irq_chip.irq_bus_sync_unlock =
1240 		soctherm_oc_irq_sync_unlock;
1241 	soc_irq_cdata.irq_chip.irq_disable = soctherm_oc_irq_disable;
1242 	soc_irq_cdata.irq_chip.irq_enable = soctherm_oc_irq_enable;
1243 	soc_irq_cdata.irq_chip.irq_set_type = soctherm_oc_irq_set_type;
1244 	soc_irq_cdata.irq_chip.irq_set_wake = NULL;
1245 
1246 	soc_irq_cdata.domain = irq_domain_add_linear(np, num_irqs,
1247 						     &soctherm_oc_domain_ops,
1248 						     &soc_irq_cdata);
1249 
1250 	if (!soc_irq_cdata.domain) {
1251 		pr_err("%s: Failed to create IRQ domain\n", __func__);
1252 		return -ENOMEM;
1253 	}
1254 
1255 	pr_debug("%s(): OC interrupts enabled successful\n", __func__);
1256 	return 0;
1257 }
1258 
1259 #ifdef CONFIG_DEBUG_FS
1260 static int regs_show(struct seq_file *s, void *data)
1261 {
1262 	struct platform_device *pdev = s->private;
1263 	struct tegra_soctherm *ts = platform_get_drvdata(pdev);
1264 	const struct tegra_tsensor *tsensors = ts->soc->tsensors;
1265 	const struct tegra_tsensor_group **ttgs = ts->soc->ttgs;
1266 	u32 r, state;
1267 	int i, level;
1268 
1269 	seq_puts(s, "-----TSENSE (convert HW)-----\n");
1270 
1271 	for (i = 0; i < ts->soc->num_tsensors; i++) {
1272 		r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1);
1273 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TEMP_ENABLE);
1274 
1275 		seq_printf(s, "%s: ", tsensors[i].name);
1276 		seq_printf(s, "En(%d) ", state);
1277 
1278 		if (!state) {
1279 			seq_puts(s, "\n");
1280 			continue;
1281 		}
1282 
1283 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TIDDQ_EN_MASK);
1284 		seq_printf(s, "tiddq(%d) ", state);
1285 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TEN_COUNT_MASK);
1286 		seq_printf(s, "ten_count(%d) ", state);
1287 		state = REG_GET_MASK(r, SENSOR_CONFIG1_TSAMPLE_MASK);
1288 		seq_printf(s, "tsample(%d) ", state + 1);
1289 
1290 		r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1);
1291 		state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_VALID_MASK);
1292 		seq_printf(s, "Temp(%d/", state);
1293 		state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_MASK);
1294 		seq_printf(s, "%d) ", translate_temp(state));
1295 
1296 		r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0);
1297 		state = REG_GET_MASK(r, SENSOR_STATUS0_VALID_MASK);
1298 		seq_printf(s, "Capture(%d/", state);
1299 		state = REG_GET_MASK(r, SENSOR_STATUS0_CAPTURE_MASK);
1300 		seq_printf(s, "%d) ", state);
1301 
1302 		r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0);
1303 		state = REG_GET_MASK(r, SENSOR_CONFIG0_STOP);
1304 		seq_printf(s, "Stop(%d) ", state);
1305 		state = REG_GET_MASK(r, SENSOR_CONFIG0_TALL_MASK);
1306 		seq_printf(s, "Tall(%d) ", state);
1307 		state = REG_GET_MASK(r, SENSOR_CONFIG0_TCALC_OVER);
1308 		seq_printf(s, "Over(%d/", state);
1309 		state = REG_GET_MASK(r, SENSOR_CONFIG0_OVER);
1310 		seq_printf(s, "%d/", state);
1311 		state = REG_GET_MASK(r, SENSOR_CONFIG0_CPTR_OVER);
1312 		seq_printf(s, "%d) ", state);
1313 
1314 		r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2);
1315 		state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMA_MASK);
1316 		seq_printf(s, "Therm_A/B(%d/", state);
1317 		state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMB_MASK);
1318 		seq_printf(s, "%d)\n", (s16)state);
1319 	}
1320 
1321 	r = readl(ts->regs + SENSOR_PDIV);
1322 	seq_printf(s, "PDIV: 0x%x\n", r);
1323 
1324 	r = readl(ts->regs + SENSOR_HOTSPOT_OFF);
1325 	seq_printf(s, "HOTSPOT: 0x%x\n", r);
1326 
1327 	seq_puts(s, "\n");
1328 	seq_puts(s, "-----SOC_THERM-----\n");
1329 
1330 	r = readl(ts->regs + SENSOR_TEMP1);
1331 	state = REG_GET_MASK(r, SENSOR_TEMP1_CPU_TEMP_MASK);
1332 	seq_printf(s, "Temperatures: CPU(%d) ", translate_temp(state));
1333 	state = REG_GET_MASK(r, SENSOR_TEMP1_GPU_TEMP_MASK);
1334 	seq_printf(s, " GPU(%d) ", translate_temp(state));
1335 	r = readl(ts->regs + SENSOR_TEMP2);
1336 	state = REG_GET_MASK(r, SENSOR_TEMP2_PLLX_TEMP_MASK);
1337 	seq_printf(s, " PLLX(%d) ", translate_temp(state));
1338 	state = REG_GET_MASK(r, SENSOR_TEMP2_MEM_TEMP_MASK);
1339 	seq_printf(s, " MEM(%d)\n", translate_temp(state));
1340 
1341 	for (i = 0; i < ts->soc->num_ttgs; i++) {
1342 		seq_printf(s, "%s:\n", ttgs[i]->name);
1343 		for (level = 0; level < 4; level++) {
1344 			s32 v;
1345 			u32 mask;
1346 			u16 off = ttgs[i]->thermctl_lvl0_offset;
1347 
1348 			r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
1349 
1350 			mask = ttgs[i]->thermctl_lvl0_up_thresh_mask;
1351 			state = REG_GET_MASK(r, mask);
1352 			v = sign_extend32(state, ts->soc->bptt - 1);
1353 			v *= ts->soc->thresh_grain;
1354 			seq_printf(s, "   %d: Up/Dn(%d /", level, v);
1355 
1356 			mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask;
1357 			state = REG_GET_MASK(r, mask);
1358 			v = sign_extend32(state, ts->soc->bptt - 1);
1359 			v *= ts->soc->thresh_grain;
1360 			seq_printf(s, "%d ) ", v);
1361 
1362 			mask = THERMCTL_LVL0_CPU0_EN_MASK;
1363 			state = REG_GET_MASK(r, mask);
1364 			seq_printf(s, "En(%d) ", state);
1365 
1366 			mask = THERMCTL_LVL0_CPU0_CPU_THROT_MASK;
1367 			state = REG_GET_MASK(r, mask);
1368 			seq_puts(s, "CPU Throt");
1369 			if (!state)
1370 				seq_printf(s, "(%s) ", "none");
1371 			else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT)
1372 				seq_printf(s, "(%s) ", "L");
1373 			else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY)
1374 				seq_printf(s, "(%s) ", "H");
1375 			else
1376 				seq_printf(s, "(%s) ", "H+L");
1377 
1378 			mask = THERMCTL_LVL0_CPU0_GPU_THROT_MASK;
1379 			state = REG_GET_MASK(r, mask);
1380 			seq_puts(s, "GPU Throt");
1381 			if (!state)
1382 				seq_printf(s, "(%s) ", "none");
1383 			else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT)
1384 				seq_printf(s, "(%s) ", "L");
1385 			else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY)
1386 				seq_printf(s, "(%s) ", "H");
1387 			else
1388 				seq_printf(s, "(%s) ", "H+L");
1389 
1390 			mask = THERMCTL_LVL0_CPU0_STATUS_MASK;
1391 			state = REG_GET_MASK(r, mask);
1392 			seq_printf(s, "Status(%s)\n",
1393 				   state == 0 ? "LO" :
1394 				   state == 1 ? "In" :
1395 				   state == 2 ? "Res" : "HI");
1396 		}
1397 	}
1398 
1399 	r = readl(ts->regs + THERMCTL_STATS_CTL);
1400 	seq_printf(s, "STATS: Up(%s) Dn(%s)\n",
1401 		   r & STATS_CTL_EN_UP ? "En" : "--",
1402 		   r & STATS_CTL_EN_DN ? "En" : "--");
1403 
1404 	for (level = 0; level < 4; level++) {
1405 		u16 off;
1406 
1407 		off = THERMCTL_LVL0_UP_STATS;
1408 		r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
1409 		seq_printf(s, "  Level_%d Up(%d) ", level, r);
1410 
1411 		off = THERMCTL_LVL0_DN_STATS;
1412 		r = readl(ts->regs + THERMCTL_LVL_REG(off, level));
1413 		seq_printf(s, "Dn(%d)\n", r);
1414 	}
1415 
1416 	r = readl(ts->regs + THERMCTL_THERMTRIP_CTL);
1417 	state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask);
1418 	seq_printf(s, "Thermtrip Any En(%d)\n", state);
1419 	for (i = 0; i < ts->soc->num_ttgs; i++) {
1420 		state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask);
1421 		seq_printf(s, "     %s En(%d) ", ttgs[i]->name, state);
1422 		state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask);
1423 		state *= ts->soc->thresh_grain;
1424 		seq_printf(s, "Thresh(%d)\n", state);
1425 	}
1426 
1427 	r = readl(ts->regs + THROT_GLOBAL_CFG);
1428 	seq_puts(s, "\n");
1429 	seq_printf(s, "GLOBAL THROTTLE CONFIG: 0x%08x\n", r);
1430 
1431 	seq_puts(s, "---------------------------------------------------\n");
1432 	r = readl(ts->regs + THROT_STATUS);
1433 	state = REG_GET_MASK(r, THROT_STATUS_BREACH_MASK);
1434 	seq_printf(s, "THROT STATUS: breach(%d) ", state);
1435 	state = REG_GET_MASK(r, THROT_STATUS_STATE_MASK);
1436 	seq_printf(s, "state(%d) ", state);
1437 	state = REG_GET_MASK(r, THROT_STATUS_ENABLED_MASK);
1438 	seq_printf(s, "enabled(%d)\n", state);
1439 
1440 	r = readl(ts->regs + CPU_PSKIP_STATUS);
1441 	if (ts->soc->use_ccroc) {
1442 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);
1443 		seq_printf(s, "CPU PSKIP STATUS: enabled(%d)\n", state);
1444 	} else {
1445 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_M_MASK);
1446 		seq_printf(s, "CPU PSKIP STATUS: M(%d) ", state);
1447 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_N_MASK);
1448 		seq_printf(s, "N(%d) ", state);
1449 		state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK);
1450 		seq_printf(s, "enabled(%d)\n", state);
1451 	}
1452 
1453 	return 0;
1454 }
1455 
1456 DEFINE_SHOW_ATTRIBUTE(regs);
1457 
1458 static void soctherm_debug_init(struct platform_device *pdev)
1459 {
1460 	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
1461 	struct dentry *root;
1462 
1463 	root = debugfs_create_dir("soctherm", NULL);
1464 
1465 	tegra->debugfs_dir = root;
1466 
1467 	debugfs_create_file("reg_contents", 0644, root, pdev, &regs_fops);
1468 }
1469 #else
1470 static inline void soctherm_debug_init(struct platform_device *pdev) {}
1471 #endif
1472 
1473 static int soctherm_clk_enable(struct platform_device *pdev, bool enable)
1474 {
1475 	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
1476 	int err;
1477 
1478 	if (!tegra->clock_soctherm || !tegra->clock_tsensor)
1479 		return -EINVAL;
1480 
1481 	reset_control_assert(tegra->reset);
1482 
1483 	if (enable) {
1484 		err = clk_prepare_enable(tegra->clock_soctherm);
1485 		if (err) {
1486 			reset_control_deassert(tegra->reset);
1487 			return err;
1488 		}
1489 
1490 		err = clk_prepare_enable(tegra->clock_tsensor);
1491 		if (err) {
1492 			clk_disable_unprepare(tegra->clock_soctherm);
1493 			reset_control_deassert(tegra->reset);
1494 			return err;
1495 		}
1496 	} else {
1497 		clk_disable_unprepare(tegra->clock_tsensor);
1498 		clk_disable_unprepare(tegra->clock_soctherm);
1499 	}
1500 
1501 	reset_control_deassert(tegra->reset);
1502 
1503 	return 0;
1504 }
1505 
1506 static int throt_get_cdev_max_state(struct thermal_cooling_device *cdev,
1507 				    unsigned long *max_state)
1508 {
1509 	*max_state = 1;
1510 	return 0;
1511 }
1512 
1513 static int throt_get_cdev_cur_state(struct thermal_cooling_device *cdev,
1514 				    unsigned long *cur_state)
1515 {
1516 	struct tegra_soctherm *ts = cdev->devdata;
1517 	u32 r;
1518 
1519 	r = readl(ts->regs + THROT_STATUS);
1520 	if (REG_GET_MASK(r, THROT_STATUS_STATE_MASK))
1521 		*cur_state = 1;
1522 	else
1523 		*cur_state = 0;
1524 
1525 	return 0;
1526 }
1527 
1528 static int throt_set_cdev_state(struct thermal_cooling_device *cdev,
1529 				unsigned long cur_state)
1530 {
1531 	return 0;
1532 }
1533 
1534 static const struct thermal_cooling_device_ops throt_cooling_ops = {
1535 	.get_max_state = throt_get_cdev_max_state,
1536 	.get_cur_state = throt_get_cdev_cur_state,
1537 	.set_cur_state = throt_set_cdev_state,
1538 };
1539 
1540 static int soctherm_thermtrips_parse(struct platform_device *pdev)
1541 {
1542 	struct device *dev = &pdev->dev;
1543 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
1544 	struct tsensor_group_thermtrips *tt = ts->soc->thermtrips;
1545 	const int max_num_prop = ts->soc->num_ttgs * 2;
1546 	u32 *tlb;
1547 	int i, j, n, ret;
1548 
1549 	if (!tt)
1550 		return -ENOMEM;
1551 
1552 	n = of_property_count_u32_elems(dev->of_node, "nvidia,thermtrips");
1553 	if (n <= 0) {
1554 		dev_info(dev,
1555 			 "missing thermtrips, will use critical trips as shut down temp\n");
1556 		return n;
1557 	}
1558 
1559 	n = min(max_num_prop, n);
1560 
1561 	tlb = devm_kcalloc(&pdev->dev, max_num_prop, sizeof(u32), GFP_KERNEL);
1562 	if (!tlb)
1563 		return -ENOMEM;
1564 	ret = of_property_read_u32_array(dev->of_node, "nvidia,thermtrips",
1565 					 tlb, n);
1566 	if (ret) {
1567 		dev_err(dev, "invalid num ele: thermtrips:%d\n", ret);
1568 		return ret;
1569 	}
1570 
1571 	i = 0;
1572 	for (j = 0; j < n; j = j + 2) {
1573 		if (tlb[j] >= TEGRA124_SOCTHERM_SENSOR_NUM)
1574 			continue;
1575 
1576 		tt[i].id = tlb[j];
1577 		tt[i].temp = tlb[j + 1];
1578 		i++;
1579 	}
1580 
1581 	return 0;
1582 }
1583 
1584 static void soctherm_oc_cfg_parse(struct device *dev,
1585 				struct device_node *np_oc,
1586 				struct soctherm_throt_cfg *stc)
1587 {
1588 	u32 val;
1589 
1590 	if (of_property_read_bool(np_oc, "nvidia,polarity-active-low"))
1591 		stc->oc_cfg.active_low = 1;
1592 	else
1593 		stc->oc_cfg.active_low = 0;
1594 
1595 	if (!of_property_read_u32(np_oc, "nvidia,count-threshold", &val)) {
1596 		stc->oc_cfg.intr_en = 1;
1597 		stc->oc_cfg.alarm_cnt_thresh = val;
1598 	}
1599 
1600 	if (!of_property_read_u32(np_oc, "nvidia,throttle-period-us", &val))
1601 		stc->oc_cfg.throt_period = val;
1602 
1603 	if (!of_property_read_u32(np_oc, "nvidia,alarm-filter", &val))
1604 		stc->oc_cfg.alarm_filter = val;
1605 
1606 	/* BRIEF throttling by default, do not support STICKY */
1607 	stc->oc_cfg.mode = OC_THROTTLE_MODE_BRIEF;
1608 }
1609 
1610 static int soctherm_throt_cfg_parse(struct device *dev,
1611 				    struct device_node *np,
1612 				    struct soctherm_throt_cfg *stc)
1613 {
1614 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
1615 	int ret;
1616 	u32 val;
1617 
1618 	ret = of_property_read_u32(np, "nvidia,priority", &val);
1619 	if (ret) {
1620 		dev_err(dev, "throttle-cfg: %s: invalid priority\n", stc->name);
1621 		return -EINVAL;
1622 	}
1623 	stc->priority = val;
1624 
1625 	ret = of_property_read_u32(np, ts->soc->use_ccroc ?
1626 				   "nvidia,cpu-throt-level" :
1627 				   "nvidia,cpu-throt-percent", &val);
1628 	if (!ret) {
1629 		if (ts->soc->use_ccroc &&
1630 		    val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
1631 			stc->cpu_throt_level = val;
1632 		else if (!ts->soc->use_ccroc && val <= 100)
1633 			stc->cpu_throt_depth = val;
1634 		else
1635 			goto err;
1636 	} else {
1637 		goto err;
1638 	}
1639 
1640 	ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val);
1641 	if (!ret && val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH)
1642 		stc->gpu_throt_level = val;
1643 	else
1644 		goto err;
1645 
1646 	return 0;
1647 
1648 err:
1649 	dev_err(dev, "throttle-cfg: %s: no throt prop or invalid prop\n",
1650 		stc->name);
1651 	return -EINVAL;
1652 }
1653 
1654 /**
1655  * soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations
1656  * and register them as cooling devices.
1657  * @pdev: Pointer to platform_device struct
1658  */
1659 static void soctherm_init_hw_throt_cdev(struct platform_device *pdev)
1660 {
1661 	struct device *dev = &pdev->dev;
1662 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
1663 	struct device_node *np_stc, *np_stcc;
1664 	const char *name;
1665 	int i;
1666 
1667 	for (i = 0; i < THROTTLE_SIZE; i++) {
1668 		ts->throt_cfgs[i].name = throt_names[i];
1669 		ts->throt_cfgs[i].id = i;
1670 		ts->throt_cfgs[i].init = false;
1671 	}
1672 
1673 	np_stc = of_get_child_by_name(dev->of_node, "throttle-cfgs");
1674 	if (!np_stc) {
1675 		dev_info(dev,
1676 			 "throttle-cfg: no throttle-cfgs - not enabling\n");
1677 		return;
1678 	}
1679 
1680 	for_each_child_of_node(np_stc, np_stcc) {
1681 		struct soctherm_throt_cfg *stc;
1682 		struct thermal_cooling_device *tcd;
1683 		int err;
1684 
1685 		name = np_stcc->name;
1686 		stc = find_throttle_cfg_by_name(ts, name);
1687 		if (!stc) {
1688 			dev_err(dev,
1689 				"throttle-cfg: could not find %s\n", name);
1690 			continue;
1691 		}
1692 
1693 		if (stc->init) {
1694 			dev_err(dev, "throttle-cfg: %s: redefined!\n", name);
1695 			of_node_put(np_stcc);
1696 			break;
1697 		}
1698 
1699 		err = soctherm_throt_cfg_parse(dev, np_stcc, stc);
1700 		if (err)
1701 			continue;
1702 
1703 		if (stc->id >= THROTTLE_OC1) {
1704 			soctherm_oc_cfg_parse(dev, np_stcc, stc);
1705 			stc->init = true;
1706 		} else {
1707 
1708 			tcd = thermal_of_cooling_device_register(np_stcc,
1709 							 (char *)name, ts,
1710 							 &throt_cooling_ops);
1711 			if (IS_ERR_OR_NULL(tcd)) {
1712 				dev_err(dev,
1713 					"throttle-cfg: %s: failed to register cooling device\n",
1714 					name);
1715 				continue;
1716 			}
1717 			stc->cdev = tcd;
1718 			stc->init = true;
1719 		}
1720 
1721 	}
1722 
1723 	of_node_put(np_stc);
1724 }
1725 
1726 /**
1727  * throttlectl_cpu_level_cfg() - programs CCROC NV_THERM level config
1728  * @ts: pointer to a struct tegra_soctherm
1729  * @level: describing the level LOW/MED/HIGH of throttling
1730  *
1731  * It's necessary to set up the CPU-local CCROC NV_THERM instance with
1732  * the M/N values desired for each level. This function does this.
1733  *
1734  * This function pre-programs the CCROC NV_THERM levels in terms of
1735  * pre-configured "Low", "Medium" or "Heavy" throttle levels which are
1736  * mapped to THROT_LEVEL_LOW, THROT_LEVEL_MED and THROT_LEVEL_HVY.
1737  */
1738 static void throttlectl_cpu_level_cfg(struct tegra_soctherm *ts, int level)
1739 {
1740 	u8 depth, dividend;
1741 	u32 r;
1742 
1743 	switch (level) {
1744 	case TEGRA_SOCTHERM_THROT_LEVEL_LOW:
1745 		depth = 50;
1746 		break;
1747 	case TEGRA_SOCTHERM_THROT_LEVEL_MED:
1748 		depth = 75;
1749 		break;
1750 	case TEGRA_SOCTHERM_THROT_LEVEL_HIGH:
1751 		depth = 80;
1752 		break;
1753 	case TEGRA_SOCTHERM_THROT_LEVEL_NONE:
1754 		return;
1755 	default:
1756 		return;
1757 	}
1758 
1759 	dividend = THROT_DEPTH_DIVIDEND(depth);
1760 
1761 	/* setup PSKIP in ccroc nv_therm registers */
1762 	r = ccroc_readl(ts, CCROC_THROT_PSKIP_RAMP_CPU_REG(level));
1763 	r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
1764 	r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_STEP_MASK, 0xf);
1765 	ccroc_writel(ts, r, CCROC_THROT_PSKIP_RAMP_CPU_REG(level));
1766 
1767 	r = ccroc_readl(ts, CCROC_THROT_PSKIP_CTRL_CPU_REG(level));
1768 	r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_ENB_MASK, 1);
1769 	r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
1770 	r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
1771 	ccroc_writel(ts, r, CCROC_THROT_PSKIP_CTRL_CPU_REG(level));
1772 }
1773 
1774 /**
1775  * throttlectl_cpu_level_select() - program CPU pulse skipper config
1776  * @ts: pointer to a struct tegra_soctherm
1777  * @throt: the LIGHT/HEAVY of throttle event id
1778  *
1779  * Pulse skippers are used to throttle clock frequencies.  This
1780  * function programs the pulse skippers based on @throt and platform
1781  * data.  This function is used on SoCs which have CPU-local pulse
1782  * skipper control, such as T13x. It programs soctherm's interface to
1783  * Denver:CCROC NV_THERM in terms of Low, Medium and HIGH throttling
1784  * vectors. PSKIP_BYPASS mode is set as required per HW spec.
1785  */
1786 static void throttlectl_cpu_level_select(struct tegra_soctherm *ts,
1787 					 enum soctherm_throttle_id throt)
1788 {
1789 	u32 r, throt_vect;
1790 
1791 	/* Denver:CCROC NV_THERM interface N:3 Mapping */
1792 	switch (ts->throt_cfgs[throt].cpu_throt_level) {
1793 	case TEGRA_SOCTHERM_THROT_LEVEL_LOW:
1794 		throt_vect = THROT_VECT_LOW;
1795 		break;
1796 	case TEGRA_SOCTHERM_THROT_LEVEL_MED:
1797 		throt_vect = THROT_VECT_MED;
1798 		break;
1799 	case TEGRA_SOCTHERM_THROT_LEVEL_HIGH:
1800 		throt_vect = THROT_VECT_HIGH;
1801 		break;
1802 	default:
1803 		throt_vect = THROT_VECT_NONE;
1804 		break;
1805 	}
1806 
1807 	r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1808 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1809 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_CPU_MASK, throt_vect);
1810 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT2_CPU_MASK, throt_vect);
1811 	writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1812 
1813 	/* bypass sequencer in soc_therm as it is programmed in ccroc */
1814 	r = REG_SET_MASK(0, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK, 1);
1815 	writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1816 }
1817 
1818 /**
1819  * throttlectl_cpu_mn() - program CPU pulse skipper configuration
1820  * @ts: pointer to a struct tegra_soctherm
1821  * @throt: the LIGHT/HEAVY of throttle event id
1822  *
1823  * Pulse skippers are used to throttle clock frequencies.  This
1824  * function programs the pulse skippers based on @throt and platform
1825  * data.  This function is used for CPUs that have "remote" pulse
1826  * skipper control, e.g., the CPU pulse skipper is controlled by the
1827  * SOC_THERM IP block.  (SOC_THERM is located outside the CPU
1828  * complex.)
1829  */
1830 static void throttlectl_cpu_mn(struct tegra_soctherm *ts,
1831 			       enum soctherm_throttle_id throt)
1832 {
1833 	u32 r;
1834 	int depth;
1835 	u8 dividend;
1836 
1837 	depth = ts->throt_cfgs[throt].cpu_throt_depth;
1838 	dividend = THROT_DEPTH_DIVIDEND(depth);
1839 
1840 	r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1841 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1842 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend);
1843 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff);
1844 	writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU));
1845 
1846 	r = readl(ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1847 	r = REG_SET_MASK(r, THROT_PSKIP_RAMP_DURATION_MASK, 0xff);
1848 	r = REG_SET_MASK(r, THROT_PSKIP_RAMP_STEP_MASK, 0xf);
1849 	writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU));
1850 }
1851 
1852 /**
1853  * throttlectl_gpu_level_select() - selects throttling level for GPU
1854  * @ts: pointer to a struct tegra_soctherm
1855  * @throt: the LIGHT/HEAVY of throttle event id
1856  *
1857  * This function programs soctherm's interface to GK20a NV_THERM to select
1858  * pre-configured "Low", "Medium" or "Heavy" throttle levels.
1859  *
1860  * Return: boolean true if HW was programmed
1861  */
1862 static void throttlectl_gpu_level_select(struct tegra_soctherm *ts,
1863 					 enum soctherm_throttle_id throt)
1864 {
1865 	u32 r, level, throt_vect;
1866 
1867 	level = ts->throt_cfgs[throt].gpu_throt_level;
1868 	throt_vect = THROT_LEVEL_TO_DEPTH(level);
1869 	r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
1870 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1);
1871 	r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_GPU_MASK, throt_vect);
1872 	writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU));
1873 }
1874 
1875 static int soctherm_oc_cfg_program(struct tegra_soctherm *ts,
1876 				      enum soctherm_throttle_id throt)
1877 {
1878 	u32 r;
1879 	struct soctherm_oc_cfg *oc = &ts->throt_cfgs[throt].oc_cfg;
1880 
1881 	if (oc->mode == OC_THROTTLE_MODE_DISABLED)
1882 		return -EINVAL;
1883 
1884 	r = REG_SET_MASK(0, OC1_CFG_HW_RESTORE_MASK, 1);
1885 	r = REG_SET_MASK(r, OC1_CFG_THROTTLE_MODE_MASK, oc->mode);
1886 	r = REG_SET_MASK(r, OC1_CFG_ALARM_POLARITY_MASK, oc->active_low);
1887 	r = REG_SET_MASK(r, OC1_CFG_EN_THROTTLE_MASK, 1);
1888 	writel(r, ts->regs + ALARM_CFG(throt));
1889 	writel(oc->throt_period, ts->regs + ALARM_THROTTLE_PERIOD(throt));
1890 	writel(oc->alarm_cnt_thresh, ts->regs + ALARM_CNT_THRESHOLD(throt));
1891 	writel(oc->alarm_filter, ts->regs + ALARM_FILTER(throt));
1892 	soctherm_oc_intr_enable(ts, throt, oc->intr_en);
1893 
1894 	return 0;
1895 }
1896 
1897 /**
1898  * soctherm_throttle_program() - programs pulse skippers' configuration
1899  * @ts: pointer to a struct tegra_soctherm
1900  * @throt: the LIGHT/HEAVY of the throttle event id.
1901  *
1902  * Pulse skippers are used to throttle clock frequencies.
1903  * This function programs the pulse skippers.
1904  */
1905 static void soctherm_throttle_program(struct tegra_soctherm *ts,
1906 				      enum soctherm_throttle_id throt)
1907 {
1908 	u32 r;
1909 	struct soctherm_throt_cfg stc = ts->throt_cfgs[throt];
1910 
1911 	if (!stc.init)
1912 		return;
1913 
1914 	if ((throt >= THROTTLE_OC1) && (soctherm_oc_cfg_program(ts, throt)))
1915 		return;
1916 
1917 	/* Setup PSKIP parameters */
1918 	if (ts->soc->use_ccroc)
1919 		throttlectl_cpu_level_select(ts, throt);
1920 	else
1921 		throttlectl_cpu_mn(ts, throt);
1922 
1923 	throttlectl_gpu_level_select(ts, throt);
1924 
1925 	r = REG_SET_MASK(0, THROT_PRIORITY_LITE_PRIO_MASK, stc.priority);
1926 	writel(r, ts->regs + THROT_PRIORITY_CTRL(throt));
1927 
1928 	r = REG_SET_MASK(0, THROT_DELAY_LITE_DELAY_MASK, 0);
1929 	writel(r, ts->regs + THROT_DELAY_CTRL(throt));
1930 
1931 	r = readl(ts->regs + THROT_PRIORITY_LOCK);
1932 	r = REG_GET_MASK(r, THROT_PRIORITY_LOCK_PRIORITY_MASK);
1933 	if (r >= stc.priority)
1934 		return;
1935 	r = REG_SET_MASK(0, THROT_PRIORITY_LOCK_PRIORITY_MASK,
1936 			 stc.priority);
1937 	writel(r, ts->regs + THROT_PRIORITY_LOCK);
1938 }
1939 
1940 static void tegra_soctherm_throttle(struct device *dev)
1941 {
1942 	struct tegra_soctherm *ts = dev_get_drvdata(dev);
1943 	u32 v;
1944 	int i;
1945 
1946 	/* configure LOW, MED and HIGH levels for CCROC NV_THERM */
1947 	if (ts->soc->use_ccroc) {
1948 		throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_LOW);
1949 		throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_MED);
1950 		throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_HIGH);
1951 	}
1952 
1953 	/* Thermal HW throttle programming */
1954 	for (i = 0; i < THROTTLE_SIZE; i++)
1955 		soctherm_throttle_program(ts, i);
1956 
1957 	v = REG_SET_MASK(0, THROT_GLOBAL_ENB_MASK, 1);
1958 	if (ts->soc->use_ccroc) {
1959 		ccroc_writel(ts, v, CCROC_GLOBAL_CFG);
1960 
1961 		v = ccroc_readl(ts, CCROC_SUPER_CCLKG_DIVIDER);
1962 		v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
1963 		ccroc_writel(ts, v, CCROC_SUPER_CCLKG_DIVIDER);
1964 	} else {
1965 		writel(v, ts->regs + THROT_GLOBAL_CFG);
1966 
1967 		v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
1968 		v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1);
1969 		writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER);
1970 	}
1971 
1972 	/* initialize stats collection */
1973 	v = STATS_CTL_CLR_DN | STATS_CTL_EN_DN |
1974 	    STATS_CTL_CLR_UP | STATS_CTL_EN_UP;
1975 	writel(v, ts->regs + THERMCTL_STATS_CTL);
1976 }
1977 
1978 static int soctherm_interrupts_init(struct platform_device *pdev,
1979 				    struct tegra_soctherm *tegra)
1980 {
1981 	struct device_node *np = pdev->dev.of_node;
1982 	int ret;
1983 
1984 	ret = soctherm_oc_int_init(np, TEGRA_SOC_OC_IRQ_MAX);
1985 	if (ret < 0) {
1986 		dev_err(&pdev->dev, "soctherm_oc_int_init failed\n");
1987 		return ret;
1988 	}
1989 
1990 	tegra->thermal_irq = platform_get_irq(pdev, 0);
1991 	if (tegra->thermal_irq < 0) {
1992 		dev_dbg(&pdev->dev, "get 'thermal_irq' failed.\n");
1993 		return 0;
1994 	}
1995 
1996 	tegra->edp_irq = platform_get_irq(pdev, 1);
1997 	if (tegra->edp_irq < 0) {
1998 		dev_dbg(&pdev->dev, "get 'edp_irq' failed.\n");
1999 		return 0;
2000 	}
2001 
2002 	ret = devm_request_threaded_irq(&pdev->dev,
2003 					tegra->thermal_irq,
2004 					soctherm_thermal_isr,
2005 					soctherm_thermal_isr_thread,
2006 					IRQF_ONESHOT,
2007 					dev_name(&pdev->dev),
2008 					tegra);
2009 	if (ret < 0) {
2010 		dev_err(&pdev->dev, "request_irq 'thermal_irq' failed.\n");
2011 		return ret;
2012 	}
2013 
2014 	ret = devm_request_threaded_irq(&pdev->dev,
2015 					tegra->edp_irq,
2016 					soctherm_edp_isr,
2017 					soctherm_edp_isr_thread,
2018 					IRQF_ONESHOT,
2019 					"soctherm_edp",
2020 					tegra);
2021 	if (ret < 0) {
2022 		dev_err(&pdev->dev, "request_irq 'edp_irq' failed.\n");
2023 		return ret;
2024 	}
2025 
2026 	return 0;
2027 }
2028 
2029 static void soctherm_init(struct platform_device *pdev)
2030 {
2031 	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
2032 	const struct tegra_tsensor_group **ttgs = tegra->soc->ttgs;
2033 	int i;
2034 	u32 pdiv, hotspot;
2035 
2036 	/* Initialize raw sensors */
2037 	for (i = 0; i < tegra->soc->num_tsensors; ++i)
2038 		enable_tsensor(tegra, i);
2039 
2040 	/* program pdiv and hotspot offsets per THERM */
2041 	pdiv = readl(tegra->regs + SENSOR_PDIV);
2042 	hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF);
2043 	for (i = 0; i < tegra->soc->num_ttgs; ++i) {
2044 		pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask,
2045 				    ttgs[i]->pdiv);
2046 		/* hotspot offset from PLLX, doesn't need to configure PLLX */
2047 		if (ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX)
2048 			continue;
2049 		hotspot =  REG_SET_MASK(hotspot,
2050 					ttgs[i]->pllx_hotspot_mask,
2051 					ttgs[i]->pllx_hotspot_diff);
2052 	}
2053 	writel(pdiv, tegra->regs + SENSOR_PDIV);
2054 	writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF);
2055 
2056 	/* Configure hw throttle */
2057 	tegra_soctherm_throttle(&pdev->dev);
2058 }
2059 
2060 static const struct of_device_id tegra_soctherm_of_match[] = {
2061 #ifdef CONFIG_ARCH_TEGRA_124_SOC
2062 	{
2063 		.compatible = "nvidia,tegra124-soctherm",
2064 		.data = &tegra124_soctherm,
2065 	},
2066 #endif
2067 #ifdef CONFIG_ARCH_TEGRA_132_SOC
2068 	{
2069 		.compatible = "nvidia,tegra132-soctherm",
2070 		.data = &tegra132_soctherm,
2071 	},
2072 #endif
2073 #ifdef CONFIG_ARCH_TEGRA_210_SOC
2074 	{
2075 		.compatible = "nvidia,tegra210-soctherm",
2076 		.data = &tegra210_soctherm,
2077 	},
2078 #endif
2079 	{ },
2080 };
2081 MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match);
2082 
2083 static int tegra_soctherm_probe(struct platform_device *pdev)
2084 {
2085 	const struct of_device_id *match;
2086 	struct tegra_soctherm *tegra;
2087 	struct thermal_zone_device *z;
2088 	struct tsensor_shared_calib shared_calib;
2089 	struct tegra_soctherm_soc *soc;
2090 	unsigned int i;
2091 	int err;
2092 
2093 	match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node);
2094 	if (!match)
2095 		return -ENODEV;
2096 
2097 	soc = (struct tegra_soctherm_soc *)match->data;
2098 	if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM)
2099 		return -EINVAL;
2100 
2101 	tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
2102 	if (!tegra)
2103 		return -ENOMEM;
2104 
2105 	mutex_init(&tegra->thermctl_lock);
2106 	dev_set_drvdata(&pdev->dev, tegra);
2107 
2108 	tegra->soc = soc;
2109 
2110 	tegra->regs = devm_platform_ioremap_resource_byname(pdev, "soctherm-reg");
2111 	if (IS_ERR(tegra->regs)) {
2112 		dev_err(&pdev->dev, "can't get soctherm registers");
2113 		return PTR_ERR(tegra->regs);
2114 	}
2115 
2116 	if (!tegra->soc->use_ccroc) {
2117 		tegra->clk_regs = devm_platform_ioremap_resource_byname(pdev, "car-reg");
2118 		if (IS_ERR(tegra->clk_regs)) {
2119 			dev_err(&pdev->dev, "can't get car clk registers");
2120 			return PTR_ERR(tegra->clk_regs);
2121 		}
2122 	} else {
2123 		tegra->ccroc_regs = devm_platform_ioremap_resource_byname(pdev, "ccroc-reg");
2124 		if (IS_ERR(tegra->ccroc_regs)) {
2125 			dev_err(&pdev->dev, "can't get ccroc registers");
2126 			return PTR_ERR(tegra->ccroc_regs);
2127 		}
2128 	}
2129 
2130 	tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm");
2131 	if (IS_ERR(tegra->reset)) {
2132 		dev_err(&pdev->dev, "can't get soctherm reset\n");
2133 		return PTR_ERR(tegra->reset);
2134 	}
2135 
2136 	tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor");
2137 	if (IS_ERR(tegra->clock_tsensor)) {
2138 		dev_err(&pdev->dev, "can't get tsensor clock\n");
2139 		return PTR_ERR(tegra->clock_tsensor);
2140 	}
2141 
2142 	tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm");
2143 	if (IS_ERR(tegra->clock_soctherm)) {
2144 		dev_err(&pdev->dev, "can't get soctherm clock\n");
2145 		return PTR_ERR(tegra->clock_soctherm);
2146 	}
2147 
2148 	tegra->calib = devm_kcalloc(&pdev->dev,
2149 				    soc->num_tsensors, sizeof(u32),
2150 				    GFP_KERNEL);
2151 	if (!tegra->calib)
2152 		return -ENOMEM;
2153 
2154 	/* calculate shared calibration data */
2155 	err = tegra_calc_shared_calib(soc->tfuse, &shared_calib);
2156 	if (err)
2157 		return err;
2158 
2159 	/* calculate tsensor calibration data */
2160 	for (i = 0; i < soc->num_tsensors; ++i) {
2161 		err = tegra_calc_tsensor_calib(&soc->tsensors[i],
2162 					       &shared_calib,
2163 					       &tegra->calib[i]);
2164 		if (err)
2165 			return err;
2166 	}
2167 
2168 	tegra->thermctl_tzs = devm_kcalloc(&pdev->dev,
2169 					   soc->num_ttgs, sizeof(z),
2170 					   GFP_KERNEL);
2171 	if (!tegra->thermctl_tzs)
2172 		return -ENOMEM;
2173 
2174 	err = soctherm_clk_enable(pdev, true);
2175 	if (err)
2176 		return err;
2177 
2178 	soctherm_thermtrips_parse(pdev);
2179 
2180 	soctherm_init_hw_throt_cdev(pdev);
2181 
2182 	soctherm_init(pdev);
2183 
2184 	for (i = 0; i < soc->num_ttgs; ++i) {
2185 		struct tegra_thermctl_zone *zone =
2186 			devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL);
2187 		if (!zone) {
2188 			err = -ENOMEM;
2189 			goto disable_clocks;
2190 		}
2191 
2192 		zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset;
2193 		zone->dev = &pdev->dev;
2194 		zone->sg = soc->ttgs[i];
2195 		zone->ts = tegra;
2196 
2197 		z = devm_thermal_zone_of_sensor_register(&pdev->dev,
2198 							 soc->ttgs[i]->id, zone,
2199 							 &tegra_of_thermal_ops);
2200 		if (IS_ERR(z)) {
2201 			err = PTR_ERR(z);
2202 			dev_err(&pdev->dev, "failed to register sensor: %d\n",
2203 				err);
2204 			goto disable_clocks;
2205 		}
2206 
2207 		zone->tz = z;
2208 		tegra->thermctl_tzs[soc->ttgs[i]->id] = z;
2209 
2210 		/* Configure hw trip points */
2211 		err = tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z);
2212 		if (err)
2213 			goto disable_clocks;
2214 	}
2215 
2216 	err = soctherm_interrupts_init(pdev, tegra);
2217 
2218 	soctherm_debug_init(pdev);
2219 
2220 	return 0;
2221 
2222 disable_clocks:
2223 	soctherm_clk_enable(pdev, false);
2224 
2225 	return err;
2226 }
2227 
2228 static int tegra_soctherm_remove(struct platform_device *pdev)
2229 {
2230 	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
2231 
2232 	debugfs_remove_recursive(tegra->debugfs_dir);
2233 
2234 	soctherm_clk_enable(pdev, false);
2235 
2236 	return 0;
2237 }
2238 
2239 static int __maybe_unused soctherm_suspend(struct device *dev)
2240 {
2241 	struct platform_device *pdev = to_platform_device(dev);
2242 
2243 	soctherm_clk_enable(pdev, false);
2244 
2245 	return 0;
2246 }
2247 
2248 static int __maybe_unused soctherm_resume(struct device *dev)
2249 {
2250 	struct platform_device *pdev = to_platform_device(dev);
2251 	struct tegra_soctherm *tegra = platform_get_drvdata(pdev);
2252 	struct tegra_soctherm_soc *soc = tegra->soc;
2253 	int err, i;
2254 
2255 	err = soctherm_clk_enable(pdev, true);
2256 	if (err) {
2257 		dev_err(&pdev->dev,
2258 			"Resume failed: enable clocks failed\n");
2259 		return err;
2260 	}
2261 
2262 	soctherm_init(pdev);
2263 
2264 	for (i = 0; i < soc->num_ttgs; ++i) {
2265 		struct thermal_zone_device *tz;
2266 
2267 		tz = tegra->thermctl_tzs[soc->ttgs[i]->id];
2268 		err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz);
2269 		if (err) {
2270 			dev_err(&pdev->dev,
2271 				"Resume failed: set hwtrips failed\n");
2272 			return err;
2273 		}
2274 	}
2275 
2276 	return 0;
2277 }
2278 
2279 static SIMPLE_DEV_PM_OPS(tegra_soctherm_pm, soctherm_suspend, soctherm_resume);
2280 
2281 static struct platform_driver tegra_soctherm_driver = {
2282 	.probe = tegra_soctherm_probe,
2283 	.remove = tegra_soctherm_remove,
2284 	.driver = {
2285 		.name = "tegra_soctherm",
2286 		.pm = &tegra_soctherm_pm,
2287 		.of_match_table = tegra_soctherm_of_match,
2288 	},
2289 };
2290 module_platform_driver(tegra_soctherm_driver);
2291 
2292 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>");
2293 MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver");
2294 MODULE_LICENSE("GPL v2");
2295