1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2012 - 2014 Allwinner Tech 4 * Pan Nan <pannan@allwinnertech.com> 5 * 6 * Copyright (C) 2014 Maxime Ripard 7 * Maxime Ripard <maxime.ripard@free-electrons.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/reset.h> 21 #include <linux/dmaengine.h> 22 23 #include <linux/spi/spi.h> 24 25 #define SUN6I_AUTOSUSPEND_TIMEOUT 2000 26 27 #define SUN6I_FIFO_DEPTH 128 28 #define SUN8I_FIFO_DEPTH 64 29 30 #define SUN6I_GBL_CTL_REG 0x04 31 #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) 32 #define SUN6I_GBL_CTL_MASTER BIT(1) 33 #define SUN6I_GBL_CTL_TP BIT(7) 34 #define SUN6I_GBL_CTL_RST BIT(31) 35 36 #define SUN6I_TFR_CTL_REG 0x08 37 #define SUN6I_TFR_CTL_CPHA BIT(0) 38 #define SUN6I_TFR_CTL_CPOL BIT(1) 39 #define SUN6I_TFR_CTL_SPOL BIT(2) 40 #define SUN6I_TFR_CTL_CS_MASK 0x30 41 #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) 42 #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) 43 #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) 44 #define SUN6I_TFR_CTL_DHB BIT(8) 45 #define SUN6I_TFR_CTL_SDC BIT(11) 46 #define SUN6I_TFR_CTL_FBS BIT(12) 47 #define SUN6I_TFR_CTL_SDM BIT(13) 48 #define SUN6I_TFR_CTL_XCH BIT(31) 49 50 #define SUN6I_INT_CTL_REG 0x10 51 #define SUN6I_INT_CTL_RF_RDY BIT(0) 52 #define SUN6I_INT_CTL_TF_ERQ BIT(4) 53 #define SUN6I_INT_CTL_RF_OVF BIT(8) 54 #define SUN6I_INT_CTL_TC BIT(12) 55 56 #define SUN6I_INT_STA_REG 0x14 57 58 #define SUN6I_FIFO_CTL_REG 0x18 59 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_MASK 0xff 60 #define SUN6I_FIFO_CTL_RF_DRQ_EN BIT(8) 61 #define SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS 0 62 #define SUN6I_FIFO_CTL_RF_RST BIT(15) 63 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_MASK 0xff 64 #define SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS 16 65 #define SUN6I_FIFO_CTL_TF_DRQ_EN BIT(24) 66 #define SUN6I_FIFO_CTL_TF_RST BIT(31) 67 68 #define SUN6I_FIFO_STA_REG 0x1c 69 #define SUN6I_FIFO_STA_RF_CNT_MASK GENMASK(7, 0) 70 #define SUN6I_FIFO_STA_TF_CNT_MASK GENMASK(23, 16) 71 72 #define SUN6I_CLK_CTL_REG 0x24 73 #define SUN6I_CLK_CTL_CDR2_MASK 0xff 74 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) 75 #define SUN6I_CLK_CTL_CDR1_MASK 0xf 76 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) 77 #define SUN6I_CLK_CTL_DRS BIT(12) 78 79 #define SUN6I_MAX_XFER_SIZE 0xffffff 80 81 #define SUN6I_BURST_CNT_REG 0x30 82 83 #define SUN6I_XMIT_CNT_REG 0x34 84 85 #define SUN6I_BURST_CTL_CNT_REG 0x38 86 87 #define SUN6I_TXDATA_REG 0x200 88 #define SUN6I_RXDATA_REG 0x300 89 90 struct sun6i_spi_cfg { 91 unsigned long fifo_depth; 92 bool has_clk_ctl; 93 }; 94 95 struct sun6i_spi { 96 struct spi_master *master; 97 void __iomem *base_addr; 98 dma_addr_t dma_addr_rx; 99 dma_addr_t dma_addr_tx; 100 struct clk *hclk; 101 struct clk *mclk; 102 struct reset_control *rstc; 103 104 struct completion done; 105 106 const u8 *tx_buf; 107 u8 *rx_buf; 108 int len; 109 const struct sun6i_spi_cfg *cfg; 110 }; 111 112 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) 113 { 114 return readl(sspi->base_addr + reg); 115 } 116 117 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) 118 { 119 writel(value, sspi->base_addr + reg); 120 } 121 122 static inline u32 sun6i_spi_get_rx_fifo_count(struct sun6i_spi *sspi) 123 { 124 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 125 126 return FIELD_GET(SUN6I_FIFO_STA_RF_CNT_MASK, reg); 127 } 128 129 static inline u32 sun6i_spi_get_tx_fifo_count(struct sun6i_spi *sspi) 130 { 131 u32 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 132 133 return FIELD_GET(SUN6I_FIFO_STA_TF_CNT_MASK, reg); 134 } 135 136 static inline void sun6i_spi_disable_interrupt(struct sun6i_spi *sspi, u32 mask) 137 { 138 u32 reg = sun6i_spi_read(sspi, SUN6I_INT_CTL_REG); 139 140 reg &= ~mask; 141 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); 142 } 143 144 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi) 145 { 146 u32 len; 147 u8 byte; 148 149 /* See how much data is available */ 150 len = sun6i_spi_get_rx_fifo_count(sspi); 151 152 while (len--) { 153 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); 154 if (sspi->rx_buf) 155 *sspi->rx_buf++ = byte; 156 } 157 } 158 159 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi) 160 { 161 u32 cnt; 162 int len; 163 u8 byte; 164 165 /* See how much data we can fit */ 166 cnt = sspi->cfg->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); 167 168 len = min((int)cnt, sspi->len); 169 170 while (len--) { 171 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; 172 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); 173 sspi->len--; 174 } 175 } 176 177 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) 178 { 179 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); 180 u32 reg; 181 182 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 183 reg &= ~SUN6I_TFR_CTL_CS_MASK; 184 reg |= SUN6I_TFR_CTL_CS(spi_get_chipselect(spi, 0)); 185 186 if (enable) 187 reg |= SUN6I_TFR_CTL_CS_LEVEL; 188 else 189 reg &= ~SUN6I_TFR_CTL_CS_LEVEL; 190 191 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 192 } 193 194 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) 195 { 196 return SUN6I_MAX_XFER_SIZE - 1; 197 } 198 199 static int sun6i_spi_prepare_dma(struct sun6i_spi *sspi, 200 struct spi_transfer *tfr) 201 { 202 struct dma_async_tx_descriptor *rxdesc, *txdesc; 203 struct spi_master *master = sspi->master; 204 205 rxdesc = NULL; 206 if (tfr->rx_buf) { 207 struct dma_slave_config rxconf = { 208 .direction = DMA_DEV_TO_MEM, 209 .src_addr = sspi->dma_addr_rx, 210 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 211 .src_maxburst = 8, 212 }; 213 214 dmaengine_slave_config(master->dma_rx, &rxconf); 215 216 rxdesc = dmaengine_prep_slave_sg(master->dma_rx, 217 tfr->rx_sg.sgl, 218 tfr->rx_sg.nents, 219 DMA_DEV_TO_MEM, 220 DMA_PREP_INTERRUPT); 221 if (!rxdesc) 222 return -EINVAL; 223 } 224 225 txdesc = NULL; 226 if (tfr->tx_buf) { 227 struct dma_slave_config txconf = { 228 .direction = DMA_MEM_TO_DEV, 229 .dst_addr = sspi->dma_addr_tx, 230 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES, 231 .dst_maxburst = 8, 232 }; 233 234 dmaengine_slave_config(master->dma_tx, &txconf); 235 236 txdesc = dmaengine_prep_slave_sg(master->dma_tx, 237 tfr->tx_sg.sgl, 238 tfr->tx_sg.nents, 239 DMA_MEM_TO_DEV, 240 DMA_PREP_INTERRUPT); 241 if (!txdesc) { 242 if (rxdesc) 243 dmaengine_terminate_sync(master->dma_rx); 244 return -EINVAL; 245 } 246 } 247 248 if (tfr->rx_buf) { 249 dmaengine_submit(rxdesc); 250 dma_async_issue_pending(master->dma_rx); 251 } 252 253 if (tfr->tx_buf) { 254 dmaengine_submit(txdesc); 255 dma_async_issue_pending(master->dma_tx); 256 } 257 258 return 0; 259 } 260 261 static int sun6i_spi_transfer_one(struct spi_master *master, 262 struct spi_device *spi, 263 struct spi_transfer *tfr) 264 { 265 struct sun6i_spi *sspi = spi_master_get_devdata(master); 266 unsigned int div, div_cdr1, div_cdr2, timeout; 267 unsigned int start, end, tx_time; 268 unsigned int trig_level; 269 unsigned int tx_len = 0, rx_len = 0; 270 bool use_dma; 271 int ret = 0; 272 u32 reg; 273 274 if (tfr->len > SUN6I_MAX_XFER_SIZE) 275 return -EINVAL; 276 277 reinit_completion(&sspi->done); 278 sspi->tx_buf = tfr->tx_buf; 279 sspi->rx_buf = tfr->rx_buf; 280 sspi->len = tfr->len; 281 use_dma = master->can_dma ? master->can_dma(master, spi, tfr) : false; 282 283 /* Clear pending interrupts */ 284 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0); 285 286 /* Reset FIFO */ 287 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, 288 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); 289 290 reg = 0; 291 292 if (!use_dma) { 293 /* 294 * Setup FIFO interrupt trigger level 295 * Here we choose 3/4 of the full fifo depth, as it's 296 * the hardcoded value used in old generation of Allwinner 297 * SPI controller. (See spi-sun4i.c) 298 */ 299 trig_level = sspi->cfg->fifo_depth / 4 * 3; 300 } else { 301 /* 302 * Setup FIFO DMA request trigger level 303 * We choose 1/2 of the full fifo depth, that value will 304 * be used as DMA burst length. 305 */ 306 trig_level = sspi->cfg->fifo_depth / 2; 307 308 if (tfr->tx_buf) 309 reg |= SUN6I_FIFO_CTL_TF_DRQ_EN; 310 if (tfr->rx_buf) 311 reg |= SUN6I_FIFO_CTL_RF_DRQ_EN; 312 } 313 314 reg |= (trig_level << SUN6I_FIFO_CTL_RF_RDY_TRIG_LEVEL_BITS) | 315 (trig_level << SUN6I_FIFO_CTL_TF_ERQ_TRIG_LEVEL_BITS); 316 317 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, reg); 318 319 /* 320 * Setup the transfer control register: Chip Select, 321 * polarities, etc. 322 */ 323 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 324 325 if (spi->mode & SPI_CPOL) 326 reg |= SUN6I_TFR_CTL_CPOL; 327 else 328 reg &= ~SUN6I_TFR_CTL_CPOL; 329 330 if (spi->mode & SPI_CPHA) 331 reg |= SUN6I_TFR_CTL_CPHA; 332 else 333 reg &= ~SUN6I_TFR_CTL_CPHA; 334 335 if (spi->mode & SPI_LSB_FIRST) 336 reg |= SUN6I_TFR_CTL_FBS; 337 else 338 reg &= ~SUN6I_TFR_CTL_FBS; 339 340 /* 341 * If it's a TX only transfer, we don't want to fill the RX 342 * FIFO with bogus data 343 */ 344 if (sspi->rx_buf) { 345 reg &= ~SUN6I_TFR_CTL_DHB; 346 rx_len = tfr->len; 347 } else { 348 reg |= SUN6I_TFR_CTL_DHB; 349 } 350 351 /* We want to control the chip select manually */ 352 reg |= SUN6I_TFR_CTL_CS_MANUAL; 353 354 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 355 356 if (sspi->cfg->has_clk_ctl) { 357 unsigned int mclk_rate = clk_get_rate(sspi->mclk); 358 359 /* Ensure that we have a parent clock fast enough */ 360 if (mclk_rate < (2 * tfr->speed_hz)) { 361 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); 362 mclk_rate = clk_get_rate(sspi->mclk); 363 } 364 365 /* 366 * Setup clock divider. 367 * 368 * We have two choices there. Either we can use the clock 369 * divide rate 1, which is calculated thanks to this formula: 370 * SPI_CLK = MOD_CLK / (2 ^ cdr) 371 * Or we can use CDR2, which is calculated with the formula: 372 * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) 373 * Wether we use the former or the latter is set through the 374 * DRS bit. 375 * 376 * First try CDR2, and if we can't reach the expected 377 * frequency, fall back to CDR1. 378 */ 379 div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); 380 div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); 381 if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { 382 reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; 383 tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); 384 } else { 385 div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); 386 reg = SUN6I_CLK_CTL_CDR1(div); 387 tfr->effective_speed_hz = mclk_rate / (1 << div); 388 } 389 390 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); 391 } else { 392 clk_set_rate(sspi->mclk, tfr->speed_hz); 393 tfr->effective_speed_hz = clk_get_rate(sspi->mclk); 394 395 /* 396 * Configure work mode. 397 * 398 * There are three work modes depending on the controller clock 399 * frequency: 400 * - normal sample mode : CLK <= 24MHz SDM=1 SDC=0 401 * - delay half-cycle sample mode : CLK <= 40MHz SDM=0 SDC=0 402 * - delay one-cycle sample mode : CLK >= 80MHz SDM=0 SDC=1 403 */ 404 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 405 reg &= ~(SUN6I_TFR_CTL_SDM | SUN6I_TFR_CTL_SDC); 406 407 if (tfr->effective_speed_hz <= 24000000) 408 reg |= SUN6I_TFR_CTL_SDM; 409 else if (tfr->effective_speed_hz >= 80000000) 410 reg |= SUN6I_TFR_CTL_SDC; 411 412 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 413 } 414 415 /* Finally enable the bus - doing so before might raise SCK to HIGH */ 416 reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG); 417 reg |= SUN6I_GBL_CTL_BUS_ENABLE; 418 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, reg); 419 420 /* Setup the transfer now... */ 421 if (sspi->tx_buf) 422 tx_len = tfr->len; 423 424 /* Setup the counters */ 425 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, tfr->len); 426 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, tx_len); 427 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, tx_len); 428 429 if (!use_dma) { 430 /* Fill the TX FIFO */ 431 sun6i_spi_fill_fifo(sspi); 432 } else { 433 ret = sun6i_spi_prepare_dma(sspi, tfr); 434 if (ret) { 435 dev_warn(&master->dev, 436 "%s: prepare DMA failed, ret=%d", 437 dev_name(&spi->dev), ret); 438 return ret; 439 } 440 } 441 442 /* Enable the interrupts */ 443 reg = SUN6I_INT_CTL_TC; 444 445 if (!use_dma) { 446 if (rx_len > sspi->cfg->fifo_depth) 447 reg |= SUN6I_INT_CTL_RF_RDY; 448 if (tx_len > sspi->cfg->fifo_depth) 449 reg |= SUN6I_INT_CTL_TF_ERQ; 450 } 451 452 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, reg); 453 454 /* Start the transfer */ 455 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 456 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); 457 458 tx_time = spi_controller_xfer_timeout(master, tfr); 459 start = jiffies; 460 timeout = wait_for_completion_timeout(&sspi->done, 461 msecs_to_jiffies(tx_time)); 462 end = jiffies; 463 if (!timeout) { 464 dev_warn(&master->dev, 465 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", 466 dev_name(&spi->dev), tfr->len, tfr->speed_hz, 467 jiffies_to_msecs(end - start), tx_time); 468 ret = -ETIMEDOUT; 469 } 470 471 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); 472 473 if (ret && use_dma) { 474 dmaengine_terminate_sync(master->dma_rx); 475 dmaengine_terminate_sync(master->dma_tx); 476 } 477 478 return ret; 479 } 480 481 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) 482 { 483 struct sun6i_spi *sspi = dev_id; 484 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG); 485 486 /* Transfer complete */ 487 if (status & SUN6I_INT_CTL_TC) { 488 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); 489 sun6i_spi_drain_fifo(sspi); 490 complete(&sspi->done); 491 return IRQ_HANDLED; 492 } 493 494 /* Receive FIFO 3/4 full */ 495 if (status & SUN6I_INT_CTL_RF_RDY) { 496 sun6i_spi_drain_fifo(sspi); 497 /* Only clear the interrupt _after_ draining the FIFO */ 498 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_RF_RDY); 499 return IRQ_HANDLED; 500 } 501 502 /* Transmit FIFO 3/4 empty */ 503 if (status & SUN6I_INT_CTL_TF_ERQ) { 504 sun6i_spi_fill_fifo(sspi); 505 506 if (!sspi->len) 507 /* nothing left to transmit */ 508 sun6i_spi_disable_interrupt(sspi, SUN6I_INT_CTL_TF_ERQ); 509 510 /* Only clear the interrupt _after_ re-seeding the FIFO */ 511 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TF_ERQ); 512 513 return IRQ_HANDLED; 514 } 515 516 return IRQ_NONE; 517 } 518 519 static int sun6i_spi_runtime_resume(struct device *dev) 520 { 521 struct spi_master *master = dev_get_drvdata(dev); 522 struct sun6i_spi *sspi = spi_master_get_devdata(master); 523 int ret; 524 525 ret = clk_prepare_enable(sspi->hclk); 526 if (ret) { 527 dev_err(dev, "Couldn't enable AHB clock\n"); 528 goto out; 529 } 530 531 ret = clk_prepare_enable(sspi->mclk); 532 if (ret) { 533 dev_err(dev, "Couldn't enable module clock\n"); 534 goto err; 535 } 536 537 ret = reset_control_deassert(sspi->rstc); 538 if (ret) { 539 dev_err(dev, "Couldn't deassert the device from reset\n"); 540 goto err2; 541 } 542 543 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, 544 SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); 545 546 return 0; 547 548 err2: 549 clk_disable_unprepare(sspi->mclk); 550 err: 551 clk_disable_unprepare(sspi->hclk); 552 out: 553 return ret; 554 } 555 556 static int sun6i_spi_runtime_suspend(struct device *dev) 557 { 558 struct spi_master *master = dev_get_drvdata(dev); 559 struct sun6i_spi *sspi = spi_master_get_devdata(master); 560 561 reset_control_assert(sspi->rstc); 562 clk_disable_unprepare(sspi->mclk); 563 clk_disable_unprepare(sspi->hclk); 564 565 return 0; 566 } 567 568 static bool sun6i_spi_can_dma(struct spi_master *master, 569 struct spi_device *spi, 570 struct spi_transfer *xfer) 571 { 572 struct sun6i_spi *sspi = spi_master_get_devdata(master); 573 574 /* 575 * If the number of spi words to transfer is less or equal than 576 * the fifo length we can just fill the fifo and wait for a single 577 * irq, so don't bother setting up dma 578 */ 579 return xfer->len > sspi->cfg->fifo_depth; 580 } 581 582 static int sun6i_spi_probe(struct platform_device *pdev) 583 { 584 struct spi_master *master; 585 struct sun6i_spi *sspi; 586 struct resource *mem; 587 int ret = 0, irq; 588 589 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); 590 if (!master) { 591 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 592 return -ENOMEM; 593 } 594 595 platform_set_drvdata(pdev, master); 596 sspi = spi_master_get_devdata(master); 597 598 sspi->base_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 599 if (IS_ERR(sspi->base_addr)) { 600 ret = PTR_ERR(sspi->base_addr); 601 goto err_free_master; 602 } 603 604 irq = platform_get_irq(pdev, 0); 605 if (irq < 0) { 606 ret = -ENXIO; 607 goto err_free_master; 608 } 609 610 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, 611 0, "sun6i-spi", sspi); 612 if (ret) { 613 dev_err(&pdev->dev, "Cannot request IRQ\n"); 614 goto err_free_master; 615 } 616 617 sspi->master = master; 618 sspi->cfg = of_device_get_match_data(&pdev->dev); 619 620 master->max_speed_hz = 100 * 1000 * 1000; 621 master->min_speed_hz = 3 * 1000; 622 master->use_gpio_descriptors = true; 623 master->set_cs = sun6i_spi_set_cs; 624 master->transfer_one = sun6i_spi_transfer_one; 625 master->num_chipselect = 4; 626 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 627 master->bits_per_word_mask = SPI_BPW_MASK(8); 628 master->dev.of_node = pdev->dev.of_node; 629 master->auto_runtime_pm = true; 630 master->max_transfer_size = sun6i_spi_max_transfer_size; 631 632 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); 633 if (IS_ERR(sspi->hclk)) { 634 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); 635 ret = PTR_ERR(sspi->hclk); 636 goto err_free_master; 637 } 638 639 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); 640 if (IS_ERR(sspi->mclk)) { 641 dev_err(&pdev->dev, "Unable to acquire module clock\n"); 642 ret = PTR_ERR(sspi->mclk); 643 goto err_free_master; 644 } 645 646 init_completion(&sspi->done); 647 648 sspi->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); 649 if (IS_ERR(sspi->rstc)) { 650 dev_err(&pdev->dev, "Couldn't get reset controller\n"); 651 ret = PTR_ERR(sspi->rstc); 652 goto err_free_master; 653 } 654 655 master->dma_tx = dma_request_chan(&pdev->dev, "tx"); 656 if (IS_ERR(master->dma_tx)) { 657 /* Check tx to see if we need defer probing driver */ 658 if (PTR_ERR(master->dma_tx) == -EPROBE_DEFER) { 659 ret = -EPROBE_DEFER; 660 goto err_free_master; 661 } 662 dev_warn(&pdev->dev, "Failed to request TX DMA channel\n"); 663 master->dma_tx = NULL; 664 } 665 666 master->dma_rx = dma_request_chan(&pdev->dev, "rx"); 667 if (IS_ERR(master->dma_rx)) { 668 if (PTR_ERR(master->dma_rx) == -EPROBE_DEFER) { 669 ret = -EPROBE_DEFER; 670 goto err_free_dma_tx; 671 } 672 dev_warn(&pdev->dev, "Failed to request RX DMA channel\n"); 673 master->dma_rx = NULL; 674 } 675 676 if (master->dma_tx && master->dma_rx) { 677 sspi->dma_addr_tx = mem->start + SUN6I_TXDATA_REG; 678 sspi->dma_addr_rx = mem->start + SUN6I_RXDATA_REG; 679 master->can_dma = sun6i_spi_can_dma; 680 } 681 682 /* 683 * This wake-up/shutdown pattern is to be able to have the 684 * device woken up, even if runtime_pm is disabled 685 */ 686 ret = sun6i_spi_runtime_resume(&pdev->dev); 687 if (ret) { 688 dev_err(&pdev->dev, "Couldn't resume the device\n"); 689 goto err_free_dma_rx; 690 } 691 692 pm_runtime_set_autosuspend_delay(&pdev->dev, SUN6I_AUTOSUSPEND_TIMEOUT); 693 pm_runtime_use_autosuspend(&pdev->dev); 694 pm_runtime_set_active(&pdev->dev); 695 pm_runtime_enable(&pdev->dev); 696 697 ret = devm_spi_register_master(&pdev->dev, master); 698 if (ret) { 699 dev_err(&pdev->dev, "cannot register SPI master\n"); 700 goto err_pm_disable; 701 } 702 703 return 0; 704 705 err_pm_disable: 706 pm_runtime_disable(&pdev->dev); 707 sun6i_spi_runtime_suspend(&pdev->dev); 708 err_free_dma_rx: 709 if (master->dma_rx) 710 dma_release_channel(master->dma_rx); 711 err_free_dma_tx: 712 if (master->dma_tx) 713 dma_release_channel(master->dma_tx); 714 err_free_master: 715 spi_master_put(master); 716 return ret; 717 } 718 719 static void sun6i_spi_remove(struct platform_device *pdev) 720 { 721 struct spi_master *master = platform_get_drvdata(pdev); 722 723 pm_runtime_force_suspend(&pdev->dev); 724 725 if (master->dma_tx) 726 dma_release_channel(master->dma_tx); 727 if (master->dma_rx) 728 dma_release_channel(master->dma_rx); 729 } 730 731 static const struct sun6i_spi_cfg sun6i_a31_spi_cfg = { 732 .fifo_depth = SUN6I_FIFO_DEPTH, 733 .has_clk_ctl = true, 734 }; 735 736 static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = { 737 .fifo_depth = SUN8I_FIFO_DEPTH, 738 .has_clk_ctl = true, 739 }; 740 741 static const struct sun6i_spi_cfg sun50i_r329_spi_cfg = { 742 .fifo_depth = SUN8I_FIFO_DEPTH, 743 }; 744 745 static const struct of_device_id sun6i_spi_match[] = { 746 { .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_cfg }, 747 { .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_cfg }, 748 { 749 .compatible = "allwinner,sun50i-r329-spi", 750 .data = &sun50i_r329_spi_cfg 751 }, 752 {} 753 }; 754 MODULE_DEVICE_TABLE(of, sun6i_spi_match); 755 756 static const struct dev_pm_ops sun6i_spi_pm_ops = { 757 .runtime_resume = sun6i_spi_runtime_resume, 758 .runtime_suspend = sun6i_spi_runtime_suspend, 759 }; 760 761 static struct platform_driver sun6i_spi_driver = { 762 .probe = sun6i_spi_probe, 763 .remove_new = sun6i_spi_remove, 764 .driver = { 765 .name = "sun6i-spi", 766 .of_match_table = sun6i_spi_match, 767 .pm = &sun6i_spi_pm_ops, 768 }, 769 }; 770 module_platform_driver(sun6i_spi_driver); 771 772 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); 773 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 774 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver"); 775 MODULE_LICENSE("GPL"); 776