1 /* 2 * Copyright (C) 2012 - 2014 Allwinner Tech 3 * Pan Nan <pannan@allwinnertech.com> 4 * 5 * Copyright (C) 2014 Maxime Ripard 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/reset.h> 23 24 #include <linux/spi/spi.h> 25 26 #define SUN6I_FIFO_DEPTH 128 27 28 #define SUN6I_GBL_CTL_REG 0x04 29 #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) 30 #define SUN6I_GBL_CTL_MASTER BIT(1) 31 #define SUN6I_GBL_CTL_TP BIT(7) 32 #define SUN6I_GBL_CTL_RST BIT(31) 33 34 #define SUN6I_TFR_CTL_REG 0x08 35 #define SUN6I_TFR_CTL_CPHA BIT(0) 36 #define SUN6I_TFR_CTL_CPOL BIT(1) 37 #define SUN6I_TFR_CTL_SPOL BIT(2) 38 #define SUN6I_TFR_CTL_CS_MASK 0x30 39 #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) 40 #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) 41 #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) 42 #define SUN6I_TFR_CTL_DHB BIT(8) 43 #define SUN6I_TFR_CTL_FBS BIT(12) 44 #define SUN6I_TFR_CTL_XCH BIT(31) 45 46 #define SUN6I_INT_CTL_REG 0x10 47 #define SUN6I_INT_CTL_RF_OVF BIT(8) 48 #define SUN6I_INT_CTL_TC BIT(12) 49 50 #define SUN6I_INT_STA_REG 0x14 51 52 #define SUN6I_FIFO_CTL_REG 0x18 53 #define SUN6I_FIFO_CTL_RF_RST BIT(15) 54 #define SUN6I_FIFO_CTL_TF_RST BIT(31) 55 56 #define SUN6I_FIFO_STA_REG 0x1c 57 #define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f 58 #define SUN6I_FIFO_STA_RF_CNT_BITS 0 59 #define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f 60 #define SUN6I_FIFO_STA_TF_CNT_BITS 16 61 62 #define SUN6I_CLK_CTL_REG 0x24 63 #define SUN6I_CLK_CTL_CDR2_MASK 0xff 64 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) 65 #define SUN6I_CLK_CTL_CDR1_MASK 0xf 66 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) 67 #define SUN6I_CLK_CTL_DRS BIT(12) 68 69 #define SUN6I_BURST_CNT_REG 0x30 70 #define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff) 71 72 #define SUN6I_XMIT_CNT_REG 0x34 73 #define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff) 74 75 #define SUN6I_BURST_CTL_CNT_REG 0x38 76 #define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff) 77 78 #define SUN6I_TXDATA_REG 0x200 79 #define SUN6I_RXDATA_REG 0x300 80 81 struct sun6i_spi { 82 struct spi_master *master; 83 void __iomem *base_addr; 84 struct clk *hclk; 85 struct clk *mclk; 86 struct reset_control *rstc; 87 88 struct completion done; 89 90 const u8 *tx_buf; 91 u8 *rx_buf; 92 int len; 93 }; 94 95 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) 96 { 97 return readl(sspi->base_addr + reg); 98 } 99 100 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) 101 { 102 writel(value, sspi->base_addr + reg); 103 } 104 105 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) 106 { 107 u32 reg, cnt; 108 u8 byte; 109 110 /* See how much data is available */ 111 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 112 reg &= SUN6I_FIFO_STA_RF_CNT_MASK; 113 cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS; 114 115 if (len > cnt) 116 len = cnt; 117 118 while (len--) { 119 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); 120 if (sspi->rx_buf) 121 *sspi->rx_buf++ = byte; 122 } 123 } 124 125 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len) 126 { 127 u8 byte; 128 129 if (len > sspi->len) 130 len = sspi->len; 131 132 while (len--) { 133 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; 134 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); 135 sspi->len--; 136 } 137 } 138 139 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) 140 { 141 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); 142 u32 reg; 143 144 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 145 reg &= ~SUN6I_TFR_CTL_CS_MASK; 146 reg |= SUN6I_TFR_CTL_CS(spi->chip_select); 147 148 if (enable) 149 reg |= SUN6I_TFR_CTL_CS_LEVEL; 150 else 151 reg &= ~SUN6I_TFR_CTL_CS_LEVEL; 152 153 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 154 } 155 156 static size_t sun6i_spi_max_transfer_size(struct spi_device *spi) 157 { 158 return SUN6I_FIFO_DEPTH - 1; 159 } 160 161 static int sun6i_spi_transfer_one(struct spi_master *master, 162 struct spi_device *spi, 163 struct spi_transfer *tfr) 164 { 165 struct sun6i_spi *sspi = spi_master_get_devdata(master); 166 unsigned int mclk_rate, div, timeout; 167 unsigned int start, end, tx_time; 168 unsigned int tx_len = 0; 169 int ret = 0; 170 u32 reg; 171 172 /* We don't support transfer larger than the FIFO */ 173 if (tfr->len > SUN6I_FIFO_DEPTH) 174 return -EINVAL; 175 176 reinit_completion(&sspi->done); 177 sspi->tx_buf = tfr->tx_buf; 178 sspi->rx_buf = tfr->rx_buf; 179 sspi->len = tfr->len; 180 181 /* Clear pending interrupts */ 182 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0); 183 184 /* Reset FIFO */ 185 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, 186 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); 187 188 /* 189 * Setup the transfer control register: Chip Select, 190 * polarities, etc. 191 */ 192 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 193 194 if (spi->mode & SPI_CPOL) 195 reg |= SUN6I_TFR_CTL_CPOL; 196 else 197 reg &= ~SUN6I_TFR_CTL_CPOL; 198 199 if (spi->mode & SPI_CPHA) 200 reg |= SUN6I_TFR_CTL_CPHA; 201 else 202 reg &= ~SUN6I_TFR_CTL_CPHA; 203 204 if (spi->mode & SPI_LSB_FIRST) 205 reg |= SUN6I_TFR_CTL_FBS; 206 else 207 reg &= ~SUN6I_TFR_CTL_FBS; 208 209 /* 210 * If it's a TX only transfer, we don't want to fill the RX 211 * FIFO with bogus data 212 */ 213 if (sspi->rx_buf) 214 reg &= ~SUN6I_TFR_CTL_DHB; 215 else 216 reg |= SUN6I_TFR_CTL_DHB; 217 218 /* We want to control the chip select manually */ 219 reg |= SUN6I_TFR_CTL_CS_MANUAL; 220 221 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 222 223 /* Ensure that we have a parent clock fast enough */ 224 mclk_rate = clk_get_rate(sspi->mclk); 225 if (mclk_rate < (2 * tfr->speed_hz)) { 226 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); 227 mclk_rate = clk_get_rate(sspi->mclk); 228 } 229 230 /* 231 * Setup clock divider. 232 * 233 * We have two choices there. Either we can use the clock 234 * divide rate 1, which is calculated thanks to this formula: 235 * SPI_CLK = MOD_CLK / (2 ^ cdr) 236 * Or we can use CDR2, which is calculated with the formula: 237 * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) 238 * Wether we use the former or the latter is set through the 239 * DRS bit. 240 * 241 * First try CDR2, and if we can't reach the expected 242 * frequency, fall back to CDR1. 243 */ 244 div = mclk_rate / (2 * tfr->speed_hz); 245 if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { 246 if (div > 0) 247 div--; 248 249 reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS; 250 } else { 251 div = ilog2(mclk_rate) - ilog2(tfr->speed_hz); 252 reg = SUN6I_CLK_CTL_CDR1(div); 253 } 254 255 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); 256 257 /* Setup the transfer now... */ 258 if (sspi->tx_buf) 259 tx_len = tfr->len; 260 261 /* Setup the counters */ 262 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len)); 263 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len)); 264 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, 265 SUN6I_BURST_CTL_CNT_STC(tx_len)); 266 267 /* Fill the TX FIFO */ 268 sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH); 269 270 /* Enable the interrupts */ 271 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); 272 273 /* Start the transfer */ 274 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 275 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); 276 277 tx_time = max(tfr->len * 8 * 2 / (tfr->speed_hz / 1000), 100U); 278 start = jiffies; 279 timeout = wait_for_completion_timeout(&sspi->done, 280 msecs_to_jiffies(tx_time)); 281 end = jiffies; 282 if (!timeout) { 283 dev_warn(&master->dev, 284 "%s: timeout transferring %u bytes@%iHz for %i(%i)ms", 285 dev_name(&spi->dev), tfr->len, tfr->speed_hz, 286 jiffies_to_msecs(end - start), tx_time); 287 ret = -ETIMEDOUT; 288 goto out; 289 } 290 291 sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); 292 293 out: 294 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); 295 296 return ret; 297 } 298 299 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) 300 { 301 struct sun6i_spi *sspi = dev_id; 302 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG); 303 304 /* Transfer complete */ 305 if (status & SUN6I_INT_CTL_TC) { 306 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); 307 complete(&sspi->done); 308 return IRQ_HANDLED; 309 } 310 311 return IRQ_NONE; 312 } 313 314 static int sun6i_spi_runtime_resume(struct device *dev) 315 { 316 struct spi_master *master = dev_get_drvdata(dev); 317 struct sun6i_spi *sspi = spi_master_get_devdata(master); 318 int ret; 319 320 ret = clk_prepare_enable(sspi->hclk); 321 if (ret) { 322 dev_err(dev, "Couldn't enable AHB clock\n"); 323 goto out; 324 } 325 326 ret = clk_prepare_enable(sspi->mclk); 327 if (ret) { 328 dev_err(dev, "Couldn't enable module clock\n"); 329 goto err; 330 } 331 332 ret = reset_control_deassert(sspi->rstc); 333 if (ret) { 334 dev_err(dev, "Couldn't deassert the device from reset\n"); 335 goto err2; 336 } 337 338 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, 339 SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); 340 341 return 0; 342 343 err2: 344 clk_disable_unprepare(sspi->mclk); 345 err: 346 clk_disable_unprepare(sspi->hclk); 347 out: 348 return ret; 349 } 350 351 static int sun6i_spi_runtime_suspend(struct device *dev) 352 { 353 struct spi_master *master = dev_get_drvdata(dev); 354 struct sun6i_spi *sspi = spi_master_get_devdata(master); 355 356 reset_control_assert(sspi->rstc); 357 clk_disable_unprepare(sspi->mclk); 358 clk_disable_unprepare(sspi->hclk); 359 360 return 0; 361 } 362 363 static int sun6i_spi_probe(struct platform_device *pdev) 364 { 365 struct spi_master *master; 366 struct sun6i_spi *sspi; 367 struct resource *res; 368 int ret = 0, irq; 369 370 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); 371 if (!master) { 372 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 373 return -ENOMEM; 374 } 375 376 platform_set_drvdata(pdev, master); 377 sspi = spi_master_get_devdata(master); 378 379 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 380 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res); 381 if (IS_ERR(sspi->base_addr)) { 382 ret = PTR_ERR(sspi->base_addr); 383 goto err_free_master; 384 } 385 386 irq = platform_get_irq(pdev, 0); 387 if (irq < 0) { 388 dev_err(&pdev->dev, "No spi IRQ specified\n"); 389 ret = -ENXIO; 390 goto err_free_master; 391 } 392 393 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, 394 0, "sun6i-spi", sspi); 395 if (ret) { 396 dev_err(&pdev->dev, "Cannot request IRQ\n"); 397 goto err_free_master; 398 } 399 400 sspi->master = master; 401 master->max_speed_hz = 100 * 1000 * 1000; 402 master->min_speed_hz = 3 * 1000; 403 master->set_cs = sun6i_spi_set_cs; 404 master->transfer_one = sun6i_spi_transfer_one; 405 master->num_chipselect = 4; 406 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 407 master->bits_per_word_mask = SPI_BPW_MASK(8); 408 master->dev.of_node = pdev->dev.of_node; 409 master->auto_runtime_pm = true; 410 master->max_transfer_size = sun6i_spi_max_transfer_size; 411 412 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); 413 if (IS_ERR(sspi->hclk)) { 414 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); 415 ret = PTR_ERR(sspi->hclk); 416 goto err_free_master; 417 } 418 419 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); 420 if (IS_ERR(sspi->mclk)) { 421 dev_err(&pdev->dev, "Unable to acquire module clock\n"); 422 ret = PTR_ERR(sspi->mclk); 423 goto err_free_master; 424 } 425 426 init_completion(&sspi->done); 427 428 sspi->rstc = devm_reset_control_get(&pdev->dev, NULL); 429 if (IS_ERR(sspi->rstc)) { 430 dev_err(&pdev->dev, "Couldn't get reset controller\n"); 431 ret = PTR_ERR(sspi->rstc); 432 goto err_free_master; 433 } 434 435 /* 436 * This wake-up/shutdown pattern is to be able to have the 437 * device woken up, even if runtime_pm is disabled 438 */ 439 ret = sun6i_spi_runtime_resume(&pdev->dev); 440 if (ret) { 441 dev_err(&pdev->dev, "Couldn't resume the device\n"); 442 goto err_free_master; 443 } 444 445 pm_runtime_set_active(&pdev->dev); 446 pm_runtime_enable(&pdev->dev); 447 pm_runtime_idle(&pdev->dev); 448 449 ret = devm_spi_register_master(&pdev->dev, master); 450 if (ret) { 451 dev_err(&pdev->dev, "cannot register SPI master\n"); 452 goto err_pm_disable; 453 } 454 455 return 0; 456 457 err_pm_disable: 458 pm_runtime_disable(&pdev->dev); 459 sun6i_spi_runtime_suspend(&pdev->dev); 460 err_free_master: 461 spi_master_put(master); 462 return ret; 463 } 464 465 static int sun6i_spi_remove(struct platform_device *pdev) 466 { 467 pm_runtime_disable(&pdev->dev); 468 469 return 0; 470 } 471 472 static const struct of_device_id sun6i_spi_match[] = { 473 { .compatible = "allwinner,sun6i-a31-spi", }, 474 {} 475 }; 476 MODULE_DEVICE_TABLE(of, sun6i_spi_match); 477 478 static const struct dev_pm_ops sun6i_spi_pm_ops = { 479 .runtime_resume = sun6i_spi_runtime_resume, 480 .runtime_suspend = sun6i_spi_runtime_suspend, 481 }; 482 483 static struct platform_driver sun6i_spi_driver = { 484 .probe = sun6i_spi_probe, 485 .remove = sun6i_spi_remove, 486 .driver = { 487 .name = "sun6i-spi", 488 .of_match_table = sun6i_spi_match, 489 .pm = &sun6i_spi_pm_ops, 490 }, 491 }; 492 module_platform_driver(sun6i_spi_driver); 493 494 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); 495 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 496 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver"); 497 MODULE_LICENSE("GPL"); 498