1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 7 #include <linux/vmalloc.h> 8 #include <linux/delay.h> 9 10 #include "qla_def.h" 11 #include "qla_gbl.h" 12 13 #define TIMEOUT_100_MS 100 14 15 static const uint32_t qla8044_reg_tbl[] = { 16 QLA8044_PEG_HALT_STATUS1, 17 QLA8044_PEG_HALT_STATUS2, 18 QLA8044_PEG_ALIVE_COUNTER, 19 QLA8044_CRB_DRV_ACTIVE, 20 QLA8044_CRB_DEV_STATE, 21 QLA8044_CRB_DRV_STATE, 22 QLA8044_CRB_DRV_SCRATCH, 23 QLA8044_CRB_DEV_PART_INFO1, 24 QLA8044_CRB_IDC_VER_MAJOR, 25 QLA8044_FW_VER_MAJOR, 26 QLA8044_FW_VER_MINOR, 27 QLA8044_FW_VER_SUB, 28 QLA8044_CMDPEG_STATE, 29 QLA8044_ASIC_TEMP, 30 }; 31 32 /* 8044 Flash Read/Write functions */ 33 uint32_t 34 qla8044_rd_reg(struct qla_hw_data *ha, ulong addr) 35 { 36 return readl((void __iomem *) (ha->nx_pcibase + addr)); 37 } 38 39 void 40 qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val) 41 { 42 writel(val, (void __iomem *)((ha)->nx_pcibase + addr)); 43 } 44 45 int 46 qla8044_rd_direct(struct scsi_qla_host *vha, 47 const uint32_t crb_reg) 48 { 49 struct qla_hw_data *ha = vha->hw; 50 51 if (crb_reg < CRB_REG_INDEX_MAX) 52 return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]); 53 else 54 return QLA_FUNCTION_FAILED; 55 } 56 57 void 58 qla8044_wr_direct(struct scsi_qla_host *vha, 59 const uint32_t crb_reg, 60 const uint32_t value) 61 { 62 struct qla_hw_data *ha = vha->hw; 63 64 if (crb_reg < CRB_REG_INDEX_MAX) 65 qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value); 66 } 67 68 static int 69 qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr) 70 { 71 uint32_t val; 72 int ret_val = QLA_SUCCESS; 73 struct qla_hw_data *ha = vha->hw; 74 75 qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr); 76 val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum)); 77 78 if (val != addr) { 79 ql_log(ql_log_warn, vha, 0xb087, 80 "%s: Failed to set register window : " 81 "addr written 0x%x, read 0x%x!\n", 82 __func__, addr, val); 83 ret_val = QLA_FUNCTION_FAILED; 84 } 85 return ret_val; 86 } 87 88 static int 89 qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) 90 { 91 int ret_val = QLA_SUCCESS; 92 struct qla_hw_data *ha = vha->hw; 93 94 ret_val = qla8044_set_win_base(vha, addr); 95 if (!ret_val) 96 *data = qla8044_rd_reg(ha, QLA8044_WILDCARD); 97 else 98 ql_log(ql_log_warn, vha, 0xb088, 99 "%s: failed read of addr 0x%x!\n", __func__, addr); 100 return ret_val; 101 } 102 103 static int 104 qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) 105 { 106 int ret_val = QLA_SUCCESS; 107 struct qla_hw_data *ha = vha->hw; 108 109 ret_val = qla8044_set_win_base(vha, addr); 110 if (!ret_val) 111 qla8044_wr_reg(ha, QLA8044_WILDCARD, data); 112 else 113 ql_log(ql_log_warn, vha, 0xb089, 114 "%s: failed wrt to addr 0x%x, data 0x%x\n", 115 __func__, addr, data); 116 return ret_val; 117 } 118 119 /* 120 * qla8044_read_write_crb_reg - Read from raddr and write value to waddr. 121 * 122 * @ha : Pointer to adapter structure 123 * @raddr : CRB address to read from 124 * @waddr : CRB address to write to 125 * 126 */ 127 static void 128 qla8044_read_write_crb_reg(struct scsi_qla_host *vha, 129 uint32_t raddr, uint32_t waddr) 130 { 131 uint32_t value; 132 133 qla8044_rd_reg_indirect(vha, raddr, &value); 134 qla8044_wr_reg_indirect(vha, waddr, value); 135 } 136 137 static int 138 qla8044_poll_wait_for_ready(struct scsi_qla_host *vha, uint32_t addr1, 139 uint32_t mask) 140 { 141 unsigned long timeout; 142 uint32_t temp = 0; 143 144 /* jiffies after 100ms */ 145 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); 146 do { 147 qla8044_rd_reg_indirect(vha, addr1, &temp); 148 if ((temp & mask) != 0) 149 break; 150 if (time_after_eq(jiffies, timeout)) { 151 ql_log(ql_log_warn, vha, 0xb151, 152 "Error in processing rdmdio entry\n"); 153 return -1; 154 } 155 } while (1); 156 157 return 0; 158 } 159 160 static uint32_t 161 qla8044_ipmdio_rd_reg(struct scsi_qla_host *vha, 162 uint32_t addr1, uint32_t addr3, uint32_t mask, uint32_t addr) 163 { 164 uint32_t temp; 165 int ret = 0; 166 167 ret = qla8044_poll_wait_for_ready(vha, addr1, mask); 168 if (ret == -1) 169 return -1; 170 171 temp = (0x40000000 | addr); 172 qla8044_wr_reg_indirect(vha, addr1, temp); 173 174 ret = qla8044_poll_wait_for_ready(vha, addr1, mask); 175 if (ret == -1) 176 return 0; 177 178 qla8044_rd_reg_indirect(vha, addr3, &ret); 179 180 return ret; 181 } 182 183 184 static int 185 qla8044_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *vha, 186 uint32_t addr1, uint32_t addr2, uint32_t addr3, uint32_t mask) 187 { 188 unsigned long timeout; 189 uint32_t temp; 190 191 /* jiffies after 100 msecs */ 192 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); 193 do { 194 temp = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr2); 195 if ((temp & 0x1) != 1) 196 break; 197 if (time_after_eq(jiffies, timeout)) { 198 ql_log(ql_log_warn, vha, 0xb152, 199 "Error in processing mdiobus idle\n"); 200 return -1; 201 } 202 } while (1); 203 204 return 0; 205 } 206 207 static int 208 qla8044_ipmdio_wr_reg(struct scsi_qla_host *vha, uint32_t addr1, 209 uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t value) 210 { 211 int ret = 0; 212 213 ret = qla8044_poll_wait_for_ready(vha, addr1, mask); 214 if (ret == -1) 215 return -1; 216 217 qla8044_wr_reg_indirect(vha, addr3, value); 218 qla8044_wr_reg_indirect(vha, addr1, addr); 219 220 ret = qla8044_poll_wait_for_ready(vha, addr1, mask); 221 if (ret == -1) 222 return -1; 223 224 return 0; 225 } 226 /* 227 * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask, 228 * Shift Left,Right/OR/XOR with values RMW header and write value to waddr. 229 * 230 * @vha : Pointer to adapter structure 231 * @raddr : CRB address to read from 232 * @waddr : CRB address to write to 233 * @p_rmw_hdr : header with shift/or/xor values. 234 * 235 */ 236 static void 237 qla8044_rmw_crb_reg(struct scsi_qla_host *vha, 238 uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr) 239 { 240 uint32_t value; 241 242 if (p_rmw_hdr->index_a) 243 value = vha->reset_tmplt.array[p_rmw_hdr->index_a]; 244 else 245 qla8044_rd_reg_indirect(vha, raddr, &value); 246 value &= p_rmw_hdr->test_mask; 247 value <<= p_rmw_hdr->shl; 248 value >>= p_rmw_hdr->shr; 249 value |= p_rmw_hdr->or_value; 250 value ^= p_rmw_hdr->xor_value; 251 qla8044_wr_reg_indirect(vha, waddr, value); 252 return; 253 } 254 255 static inline void 256 qla8044_set_qsnt_ready(struct scsi_qla_host *vha) 257 { 258 uint32_t qsnt_state; 259 struct qla_hw_data *ha = vha->hw; 260 261 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 262 qsnt_state |= (1 << ha->portnum); 263 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state); 264 ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n", 265 __func__, vha->host_no, qsnt_state); 266 } 267 268 void 269 qla8044_clear_qsnt_ready(struct scsi_qla_host *vha) 270 { 271 uint32_t qsnt_state; 272 struct qla_hw_data *ha = vha->hw; 273 274 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 275 qsnt_state &= ~(1 << ha->portnum); 276 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state); 277 ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n", 278 __func__, vha->host_no, qsnt_state); 279 } 280 281 /** 282 * qla8044_lock_recovery - Recovers the idc_lock. 283 * @vha : Pointer to adapter structure 284 * 285 * Lock Recovery Register 286 * 5-2 Lock recovery owner: Function ID of driver doing lock recovery, 287 * valid if bits 1..0 are set by driver doing lock recovery. 288 * 1-0 1 - Driver intends to force unlock the IDC lock. 289 * 2 - Driver is moving forward to unlock the IDC lock. Driver clears 290 * this field after force unlocking the IDC lock. 291 * 292 * Lock Recovery process 293 * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is 294 * greater than 0, then wait for the other driver to unlock otherwise 295 * move to the next step. 296 * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY 297 * register bits 1..0 and also set the function# in bits 5..2. 298 * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms. 299 * Wait for the other driver to perform lock recovery if the function 300 * number in bits 5..2 has changed, otherwise move to the next step. 301 * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0 302 * leaving your function# in bits 5..2. 303 * e. Force unlock using the DRIVER_UNLOCK register and immediately clear 304 * the IDC_LOCK_RECOVERY bits 5..0 by writing 0. 305 **/ 306 static int 307 qla8044_lock_recovery(struct scsi_qla_host *vha) 308 { 309 uint32_t lock = 0, lockid; 310 struct qla_hw_data *ha = vha->hw; 311 312 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY); 313 314 /* Check for other Recovery in progress, go wait */ 315 if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0) 316 return QLA_FUNCTION_FAILED; 317 318 /* Intent to Recover */ 319 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 320 (ha->portnum << 321 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER); 322 msleep(200); 323 324 /* Check Intent to Recover is advertised */ 325 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY); 326 if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum << 327 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS)) 328 return QLA_FUNCTION_FAILED; 329 330 ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n" 331 , __func__, ha->portnum); 332 333 /* Proceed to Recover */ 334 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 335 (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | 336 PROCEED_TO_RECOVER); 337 338 /* Force Unlock() */ 339 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF); 340 qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK); 341 342 /* Clear bits 0-5 in IDC_RECOVERY register*/ 343 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0); 344 345 /* Get lock() */ 346 lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK); 347 if (lock) { 348 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 349 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum; 350 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid); 351 return QLA_SUCCESS; 352 } else 353 return QLA_FUNCTION_FAILED; 354 } 355 356 int 357 qla8044_idc_lock(struct qla_hw_data *ha) 358 { 359 uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0; 360 uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0; 361 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 362 363 while (status == 0) { 364 /* acquire semaphore5 from PCI HW block */ 365 status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK); 366 367 if (status) { 368 /* Increment Counter (8-31) and update func_num (0-7) on 369 * getting a successful lock */ 370 lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 371 lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum; 372 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id); 373 break; 374 } 375 376 if (timeout == 0) 377 first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 378 379 if (++timeout >= 380 (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) { 381 tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 382 func_num = tmo_owner & 0xFF; 383 lock_cnt = tmo_owner >> 8; 384 ql_log(ql_log_warn, vha, 0xb114, 385 "%s: Lock by func %d failed after 2s, lock held " 386 "by func %d, lock count %d, first_owner %d\n", 387 __func__, ha->portnum, func_num, lock_cnt, 388 (first_owner & 0xFF)); 389 if (first_owner != tmo_owner) { 390 /* Some other driver got lock, 391 * OR same driver got lock again (counter 392 * value changed), when we were waiting for 393 * lock. Retry for another 2 sec */ 394 ql_dbg(ql_dbg_p3p, vha, 0xb115, 395 "%s: %d: IDC lock failed\n", 396 __func__, ha->portnum); 397 timeout = 0; 398 } else { 399 /* Same driver holding lock > 2sec. 400 * Force Recovery */ 401 if (qla8044_lock_recovery(vha) == QLA_SUCCESS) { 402 /* Recovered and got lock */ 403 ret_val = QLA_SUCCESS; 404 ql_dbg(ql_dbg_p3p, vha, 0xb116, 405 "%s:IDC lock Recovery by %d" 406 "successful...\n", __func__, 407 ha->portnum); 408 } 409 /* Recovery Failed, some other function 410 * has the lock, wait for 2secs 411 * and retry 412 */ 413 ql_dbg(ql_dbg_p3p, vha, 0xb08a, 414 "%s: IDC lock Recovery by %d " 415 "failed, Retrying timeout\n", __func__, 416 ha->portnum); 417 timeout = 0; 418 } 419 } 420 msleep(QLA8044_DRV_LOCK_MSLEEP); 421 } 422 return ret_val; 423 } 424 425 void 426 qla8044_idc_unlock(struct qla_hw_data *ha) 427 { 428 int id; 429 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 430 431 id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 432 433 if ((id & 0xFF) != ha->portnum) { 434 ql_log(ql_log_warn, vha, 0xb118, 435 "%s: IDC Unlock by %d failed, lock owner is %d!\n", 436 __func__, ha->portnum, (id & 0xFF)); 437 return; 438 } 439 440 /* Keep lock counter value, update the ha->func_num to 0xFF */ 441 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF)); 442 qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK); 443 } 444 445 /* 8044 Flash Lock/Unlock functions */ 446 static int 447 qla8044_flash_lock(scsi_qla_host_t *vha) 448 { 449 int lock_owner; 450 int timeout = 0; 451 uint32_t lock_status = 0; 452 int ret_val = QLA_SUCCESS; 453 struct qla_hw_data *ha = vha->hw; 454 455 while (lock_status == 0) { 456 lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK); 457 if (lock_status) 458 break; 459 460 if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) { 461 lock_owner = qla8044_rd_reg(ha, 462 QLA8044_FLASH_LOCK_ID); 463 ql_log(ql_log_warn, vha, 0xb113, 464 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d", 465 __func__, ha->portnum, lock_owner); 466 ret_val = QLA_FUNCTION_FAILED; 467 break; 468 } 469 msleep(20); 470 } 471 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum); 472 return ret_val; 473 } 474 475 static void 476 qla8044_flash_unlock(scsi_qla_host_t *vha) 477 { 478 struct qla_hw_data *ha = vha->hw; 479 480 /* Reading FLASH_UNLOCK register unlocks the Flash */ 481 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF); 482 qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK); 483 } 484 485 486 static 487 void qla8044_flash_lock_recovery(struct scsi_qla_host *vha) 488 { 489 490 if (qla8044_flash_lock(vha)) { 491 /* Someone else is holding the lock. */ 492 ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n"); 493 } 494 495 /* 496 * Either we got the lock, or someone 497 * else died while holding it. 498 * In either case, unlock. 499 */ 500 qla8044_flash_unlock(vha); 501 } 502 503 /* 504 * Address and length are byte address 505 */ 506 static int 507 qla8044_read_flash_data(scsi_qla_host_t *vha, uint8_t *p_data, 508 uint32_t flash_addr, int u32_word_count) 509 { 510 int i, ret_val = QLA_SUCCESS; 511 uint32_t u32_word; 512 513 if (qla8044_flash_lock(vha) != QLA_SUCCESS) { 514 ret_val = QLA_FUNCTION_FAILED; 515 goto exit_lock_error; 516 } 517 518 if (flash_addr & 0x03) { 519 ql_log(ql_log_warn, vha, 0xb117, 520 "%s: Illegal addr = 0x%x\n", __func__, flash_addr); 521 ret_val = QLA_FUNCTION_FAILED; 522 goto exit_flash_read; 523 } 524 525 for (i = 0; i < u32_word_count; i++) { 526 if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW, 527 (flash_addr & 0xFFFF0000))) { 528 ql_log(ql_log_warn, vha, 0xb119, 529 "%s: failed to write addr 0x%x to " 530 "FLASH_DIRECT_WINDOW\n! ", 531 __func__, flash_addr); 532 ret_val = QLA_FUNCTION_FAILED; 533 goto exit_flash_read; 534 } 535 536 ret_val = qla8044_rd_reg_indirect(vha, 537 QLA8044_FLASH_DIRECT_DATA(flash_addr), 538 &u32_word); 539 if (ret_val != QLA_SUCCESS) { 540 ql_log(ql_log_warn, vha, 0xb08c, 541 "%s: failed to read addr 0x%x!\n", 542 __func__, flash_addr); 543 goto exit_flash_read; 544 } 545 546 *(uint32_t *)p_data = u32_word; 547 p_data = p_data + 4; 548 flash_addr = flash_addr + 4; 549 } 550 551 exit_flash_read: 552 qla8044_flash_unlock(vha); 553 554 exit_lock_error: 555 return ret_val; 556 } 557 558 /* 559 * Address and length are byte address 560 */ 561 void * 562 qla8044_read_optrom_data(struct scsi_qla_host *vha, void *buf, 563 uint32_t offset, uint32_t length) 564 { 565 scsi_block_requests(vha->host); 566 if (qla8044_read_flash_data(vha, buf, offset, length / 4) 567 != QLA_SUCCESS) { 568 ql_log(ql_log_warn, vha, 0xb08d, 569 "%s: Failed to read from flash\n", 570 __func__); 571 } 572 scsi_unblock_requests(vha->host); 573 return buf; 574 } 575 576 static inline int 577 qla8044_need_reset(struct scsi_qla_host *vha) 578 { 579 uint32_t drv_state, drv_active; 580 int rval; 581 struct qla_hw_data *ha = vha->hw; 582 583 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 584 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 585 586 rval = drv_state & (1 << ha->portnum); 587 588 if (ha->flags.eeh_busy && drv_active) 589 rval = 1; 590 return rval; 591 } 592 593 /* 594 * qla8044_write_list - Write the value (p_entry->arg2) to address specified 595 * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between 596 * entries. 597 * 598 * @vha : Pointer to adapter structure 599 * @p_hdr : reset_entry header for WRITE_LIST opcode. 600 * 601 */ 602 static void 603 qla8044_write_list(struct scsi_qla_host *vha, 604 struct qla8044_reset_entry_hdr *p_hdr) 605 { 606 struct qla8044_entry *p_entry; 607 uint32_t i; 608 609 p_entry = (struct qla8044_entry *)((char *)p_hdr + 610 sizeof(struct qla8044_reset_entry_hdr)); 611 612 for (i = 0; i < p_hdr->count; i++, p_entry++) { 613 qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2); 614 if (p_hdr->delay) 615 udelay((uint32_t)(p_hdr->delay)); 616 } 617 } 618 619 /* 620 * qla8044_read_write_list - Read from address specified by p_entry->arg1, 621 * write value read to address specified by p_entry->arg2, for all entries in 622 * header with delay of p_hdr->delay between entries. 623 * 624 * @vha : Pointer to adapter structure 625 * @p_hdr : reset_entry header for READ_WRITE_LIST opcode. 626 * 627 */ 628 static void 629 qla8044_read_write_list(struct scsi_qla_host *vha, 630 struct qla8044_reset_entry_hdr *p_hdr) 631 { 632 struct qla8044_entry *p_entry; 633 uint32_t i; 634 635 p_entry = (struct qla8044_entry *)((char *)p_hdr + 636 sizeof(struct qla8044_reset_entry_hdr)); 637 638 for (i = 0; i < p_hdr->count; i++, p_entry++) { 639 qla8044_read_write_crb_reg(vha, p_entry->arg1, 640 p_entry->arg2); 641 if (p_hdr->delay) 642 udelay((uint32_t)(p_hdr->delay)); 643 } 644 } 645 646 /* 647 * qla8044_poll_reg - Poll the given CRB addr for duration msecs till 648 * value read ANDed with test_mask is equal to test_result. 649 * 650 * @ha : Pointer to adapter structure 651 * @addr : CRB register address 652 * @duration : Poll for total of "duration" msecs 653 * @test_mask : Mask value read with "test_mask" 654 * @test_result : Compare (value&test_mask) with test_result. 655 * 656 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 657 */ 658 static int 659 qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr, 660 int duration, uint32_t test_mask, uint32_t test_result) 661 { 662 uint32_t value = 0; 663 int timeout_error; 664 uint8_t retries; 665 int ret_val = QLA_SUCCESS; 666 667 ret_val = qla8044_rd_reg_indirect(vha, addr, &value); 668 if (ret_val == QLA_FUNCTION_FAILED) { 669 timeout_error = 1; 670 goto exit_poll_reg; 671 } 672 673 /* poll every 1/10 of the total duration */ 674 retries = duration/10; 675 676 do { 677 if ((value & test_mask) != test_result) { 678 timeout_error = 1; 679 msleep(duration/10); 680 ret_val = qla8044_rd_reg_indirect(vha, addr, &value); 681 if (ret_val == QLA_FUNCTION_FAILED) { 682 timeout_error = 1; 683 goto exit_poll_reg; 684 } 685 } else { 686 timeout_error = 0; 687 break; 688 } 689 } while (retries--); 690 691 exit_poll_reg: 692 if (timeout_error) { 693 vha->reset_tmplt.seq_error++; 694 ql_log(ql_log_fatal, vha, 0xb090, 695 "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n", 696 __func__, value, test_mask, test_result); 697 } 698 699 return timeout_error; 700 } 701 702 /* 703 * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB 704 * register specified by p_entry->arg1 and compare (value AND test_mask) with 705 * test_result to validate it. Wait for p_hdr->delay between processing entries. 706 * 707 * @ha : Pointer to adapter structure 708 * @p_hdr : reset_entry header for POLL_LIST opcode. 709 * 710 */ 711 static void 712 qla8044_poll_list(struct scsi_qla_host *vha, 713 struct qla8044_reset_entry_hdr *p_hdr) 714 { 715 long delay; 716 struct qla8044_entry *p_entry; 717 struct qla8044_poll *p_poll; 718 uint32_t i; 719 uint32_t value; 720 721 p_poll = (struct qla8044_poll *) 722 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr)); 723 724 /* Entries start after 8 byte qla8044_poll, poll header contains 725 * the test_mask, test_value. 726 */ 727 p_entry = (struct qla8044_entry *)((char *)p_poll + 728 sizeof(struct qla8044_poll)); 729 730 delay = (long)p_hdr->delay; 731 732 if (!delay) { 733 for (i = 0; i < p_hdr->count; i++, p_entry++) 734 qla8044_poll_reg(vha, p_entry->arg1, 735 delay, p_poll->test_mask, p_poll->test_value); 736 } else { 737 for (i = 0; i < p_hdr->count; i++, p_entry++) { 738 if (delay) { 739 if (qla8044_poll_reg(vha, 740 p_entry->arg1, delay, 741 p_poll->test_mask, 742 p_poll->test_value)) { 743 /*If 744 * (data_read&test_mask != test_value) 745 * read TIMEOUT_ADDR (arg1) and 746 * ADDR (arg2) registers 747 */ 748 qla8044_rd_reg_indirect(vha, 749 p_entry->arg1, &value); 750 qla8044_rd_reg_indirect(vha, 751 p_entry->arg2, &value); 752 } 753 } 754 } 755 } 756 } 757 758 /* 759 * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr, 760 * read ar_addr, if (value& test_mask != test_mask) re-read till timeout 761 * expires. 762 * 763 * @vha : Pointer to adapter structure 764 * @p_hdr : reset entry header for POLL_WRITE_LIST opcode. 765 * 766 */ 767 static void 768 qla8044_poll_write_list(struct scsi_qla_host *vha, 769 struct qla8044_reset_entry_hdr *p_hdr) 770 { 771 long delay; 772 struct qla8044_quad_entry *p_entry; 773 struct qla8044_poll *p_poll; 774 uint32_t i; 775 776 p_poll = (struct qla8044_poll *)((char *)p_hdr + 777 sizeof(struct qla8044_reset_entry_hdr)); 778 779 p_entry = (struct qla8044_quad_entry *)((char *)p_poll + 780 sizeof(struct qla8044_poll)); 781 782 delay = (long)p_hdr->delay; 783 784 for (i = 0; i < p_hdr->count; i++, p_entry++) { 785 qla8044_wr_reg_indirect(vha, 786 p_entry->dr_addr, p_entry->dr_value); 787 qla8044_wr_reg_indirect(vha, 788 p_entry->ar_addr, p_entry->ar_value); 789 if (delay) { 790 if (qla8044_poll_reg(vha, 791 p_entry->ar_addr, delay, 792 p_poll->test_mask, 793 p_poll->test_value)) { 794 ql_dbg(ql_dbg_p3p, vha, 0xb091, 795 "%s: Timeout Error: poll list, ", 796 __func__); 797 ql_dbg(ql_dbg_p3p, vha, 0xb092, 798 "item_num %d, entry_num %d\n", i, 799 vha->reset_tmplt.seq_index); 800 } 801 } 802 } 803 } 804 805 /* 806 * qla8044_read_modify_write - Read value from p_entry->arg1, modify the 807 * value, write value to p_entry->arg2. Process entries with p_hdr->delay 808 * between entries. 809 * 810 * @vha : Pointer to adapter structure 811 * @p_hdr : header with shift/or/xor values. 812 * 813 */ 814 static void 815 qla8044_read_modify_write(struct scsi_qla_host *vha, 816 struct qla8044_reset_entry_hdr *p_hdr) 817 { 818 struct qla8044_entry *p_entry; 819 struct qla8044_rmw *p_rmw_hdr; 820 uint32_t i; 821 822 p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr + 823 sizeof(struct qla8044_reset_entry_hdr)); 824 825 p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr + 826 sizeof(struct qla8044_rmw)); 827 828 for (i = 0; i < p_hdr->count; i++, p_entry++) { 829 qla8044_rmw_crb_reg(vha, p_entry->arg1, 830 p_entry->arg2, p_rmw_hdr); 831 if (p_hdr->delay) 832 udelay((uint32_t)(p_hdr->delay)); 833 } 834 } 835 836 /* 837 * qla8044_pause - Wait for p_hdr->delay msecs, called between processing 838 * two entries of a sequence. 839 * 840 * @vha : Pointer to adapter structure 841 * @p_hdr : Common reset entry header. 842 * 843 */ 844 static 845 void qla8044_pause(struct scsi_qla_host *vha, 846 struct qla8044_reset_entry_hdr *p_hdr) 847 { 848 if (p_hdr->delay) 849 mdelay((uint32_t)((long)p_hdr->delay)); 850 } 851 852 /* 853 * qla8044_template_end - Indicates end of reset sequence processing. 854 * 855 * @vha : Pointer to adapter structure 856 * @p_hdr : Common reset entry header. 857 * 858 */ 859 static void 860 qla8044_template_end(struct scsi_qla_host *vha, 861 struct qla8044_reset_entry_hdr *p_hdr) 862 { 863 vha->reset_tmplt.template_end = 1; 864 865 if (vha->reset_tmplt.seq_error == 0) { 866 ql_dbg(ql_dbg_p3p, vha, 0xb093, 867 "%s: Reset sequence completed SUCCESSFULLY.\n", __func__); 868 } else { 869 ql_log(ql_log_fatal, vha, 0xb094, 870 "%s: Reset sequence completed with some timeout " 871 "errors.\n", __func__); 872 } 873 } 874 875 /* 876 * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr, 877 * if (value & test_mask != test_value) re-read till timeout value expires, 878 * read dr_addr register and assign to reset_tmplt.array. 879 * 880 * @vha : Pointer to adapter structure 881 * @p_hdr : Common reset entry header. 882 * 883 */ 884 static void 885 qla8044_poll_read_list(struct scsi_qla_host *vha, 886 struct qla8044_reset_entry_hdr *p_hdr) 887 { 888 long delay; 889 int index; 890 struct qla8044_quad_entry *p_entry; 891 struct qla8044_poll *p_poll; 892 uint32_t i; 893 uint32_t value; 894 895 p_poll = (struct qla8044_poll *) 896 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr)); 897 898 p_entry = (struct qla8044_quad_entry *) 899 ((char *)p_poll + sizeof(struct qla8044_poll)); 900 901 delay = (long)p_hdr->delay; 902 903 for (i = 0; i < p_hdr->count; i++, p_entry++) { 904 qla8044_wr_reg_indirect(vha, p_entry->ar_addr, 905 p_entry->ar_value); 906 if (delay) { 907 if (qla8044_poll_reg(vha, p_entry->ar_addr, delay, 908 p_poll->test_mask, p_poll->test_value)) { 909 ql_dbg(ql_dbg_p3p, vha, 0xb095, 910 "%s: Timeout Error: poll " 911 "list, ", __func__); 912 ql_dbg(ql_dbg_p3p, vha, 0xb096, 913 "Item_num %d, " 914 "entry_num %d\n", i, 915 vha->reset_tmplt.seq_index); 916 } else { 917 index = vha->reset_tmplt.array_index; 918 qla8044_rd_reg_indirect(vha, 919 p_entry->dr_addr, &value); 920 vha->reset_tmplt.array[index++] = value; 921 if (index == QLA8044_MAX_RESET_SEQ_ENTRIES) 922 vha->reset_tmplt.array_index = 1; 923 } 924 } 925 } 926 } 927 928 /* 929 * qla8031_process_reset_template - Process all entries in reset template 930 * till entry with SEQ_END opcode, which indicates end of the reset template 931 * processing. Each entry has a Reset Entry header, entry opcode/command, with 932 * size of the entry, number of entries in sub-sequence and delay in microsecs 933 * or timeout in millisecs. 934 * 935 * @ha : Pointer to adapter structure 936 * @p_buff : Common reset entry header. 937 * 938 */ 939 static void 940 qla8044_process_reset_template(struct scsi_qla_host *vha, 941 char *p_buff) 942 { 943 int index, entries; 944 struct qla8044_reset_entry_hdr *p_hdr; 945 char *p_entry = p_buff; 946 947 vha->reset_tmplt.seq_end = 0; 948 vha->reset_tmplt.template_end = 0; 949 entries = vha->reset_tmplt.hdr->entries; 950 index = vha->reset_tmplt.seq_index; 951 952 for (; (!vha->reset_tmplt.seq_end) && (index < entries); index++) { 953 p_hdr = (struct qla8044_reset_entry_hdr *)p_entry; 954 switch (p_hdr->cmd) { 955 case OPCODE_NOP: 956 break; 957 case OPCODE_WRITE_LIST: 958 qla8044_write_list(vha, p_hdr); 959 break; 960 case OPCODE_READ_WRITE_LIST: 961 qla8044_read_write_list(vha, p_hdr); 962 break; 963 case OPCODE_POLL_LIST: 964 qla8044_poll_list(vha, p_hdr); 965 break; 966 case OPCODE_POLL_WRITE_LIST: 967 qla8044_poll_write_list(vha, p_hdr); 968 break; 969 case OPCODE_READ_MODIFY_WRITE: 970 qla8044_read_modify_write(vha, p_hdr); 971 break; 972 case OPCODE_SEQ_PAUSE: 973 qla8044_pause(vha, p_hdr); 974 break; 975 case OPCODE_SEQ_END: 976 vha->reset_tmplt.seq_end = 1; 977 break; 978 case OPCODE_TMPL_END: 979 qla8044_template_end(vha, p_hdr); 980 break; 981 case OPCODE_POLL_READ_LIST: 982 qla8044_poll_read_list(vha, p_hdr); 983 break; 984 default: 985 ql_log(ql_log_fatal, vha, 0xb097, 986 "%s: Unknown command ==> 0x%04x on " 987 "entry = %d\n", __func__, p_hdr->cmd, index); 988 break; 989 } 990 /* 991 *Set pointer to next entry in the sequence. 992 */ 993 p_entry += p_hdr->size; 994 } 995 vha->reset_tmplt.seq_index = index; 996 } 997 998 static void 999 qla8044_process_init_seq(struct scsi_qla_host *vha) 1000 { 1001 qla8044_process_reset_template(vha, 1002 vha->reset_tmplt.init_offset); 1003 if (vha->reset_tmplt.seq_end != 1) 1004 ql_log(ql_log_fatal, vha, 0xb098, 1005 "%s: Abrupt INIT Sub-Sequence end.\n", 1006 __func__); 1007 } 1008 1009 static void 1010 qla8044_process_stop_seq(struct scsi_qla_host *vha) 1011 { 1012 vha->reset_tmplt.seq_index = 0; 1013 qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset); 1014 if (vha->reset_tmplt.seq_end != 1) 1015 ql_log(ql_log_fatal, vha, 0xb099, 1016 "%s: Abrupt STOP Sub-Sequence end.\n", __func__); 1017 } 1018 1019 static void 1020 qla8044_process_start_seq(struct scsi_qla_host *vha) 1021 { 1022 qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset); 1023 if (vha->reset_tmplt.template_end != 1) 1024 ql_log(ql_log_fatal, vha, 0xb09a, 1025 "%s: Abrupt START Sub-Sequence end.\n", 1026 __func__); 1027 } 1028 1029 static int 1030 qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha, 1031 uint32_t flash_addr, uint8_t *p_data, int u32_word_count) 1032 { 1033 uint32_t i; 1034 uint32_t u32_word; 1035 uint32_t flash_offset; 1036 uint32_t addr = flash_addr; 1037 int ret_val = QLA_SUCCESS; 1038 1039 flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1); 1040 1041 if (addr & 0x3) { 1042 ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n", 1043 __func__, addr); 1044 ret_val = QLA_FUNCTION_FAILED; 1045 goto exit_lockless_read; 1046 } 1047 1048 ret_val = qla8044_wr_reg_indirect(vha, 1049 QLA8044_FLASH_DIRECT_WINDOW, (addr)); 1050 1051 if (ret_val != QLA_SUCCESS) { 1052 ql_log(ql_log_fatal, vha, 0xb09c, 1053 "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n", 1054 __func__, addr); 1055 goto exit_lockless_read; 1056 } 1057 1058 /* Check if data is spread across multiple sectors */ 1059 if ((flash_offset + (u32_word_count * sizeof(uint32_t))) > 1060 (QLA8044_FLASH_SECTOR_SIZE - 1)) { 1061 /* Multi sector read */ 1062 for (i = 0; i < u32_word_count; i++) { 1063 ret_val = qla8044_rd_reg_indirect(vha, 1064 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word); 1065 if (ret_val != QLA_SUCCESS) { 1066 ql_log(ql_log_fatal, vha, 0xb09d, 1067 "%s: failed to read addr 0x%x!\n", 1068 __func__, addr); 1069 goto exit_lockless_read; 1070 } 1071 *(uint32_t *)p_data = u32_word; 1072 p_data = p_data + 4; 1073 addr = addr + 4; 1074 flash_offset = flash_offset + 4; 1075 if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) { 1076 /* This write is needed once for each sector */ 1077 ret_val = qla8044_wr_reg_indirect(vha, 1078 QLA8044_FLASH_DIRECT_WINDOW, (addr)); 1079 if (ret_val != QLA_SUCCESS) { 1080 ql_log(ql_log_fatal, vha, 0xb09f, 1081 "%s: failed to write addr " 1082 "0x%x to FLASH_DIRECT_WINDOW!\n", 1083 __func__, addr); 1084 goto exit_lockless_read; 1085 } 1086 flash_offset = 0; 1087 } 1088 } 1089 } else { 1090 /* Single sector read */ 1091 for (i = 0; i < u32_word_count; i++) { 1092 ret_val = qla8044_rd_reg_indirect(vha, 1093 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word); 1094 if (ret_val != QLA_SUCCESS) { 1095 ql_log(ql_log_fatal, vha, 0xb0a0, 1096 "%s: failed to read addr 0x%x!\n", 1097 __func__, addr); 1098 goto exit_lockless_read; 1099 } 1100 *(uint32_t *)p_data = u32_word; 1101 p_data = p_data + 4; 1102 addr = addr + 4; 1103 } 1104 } 1105 1106 exit_lockless_read: 1107 return ret_val; 1108 } 1109 1110 /* 1111 * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory 1112 * 1113 * @vha : Pointer to adapter structure 1114 * addr : Flash address to write to 1115 * data : Data to be written 1116 * count : word_count to be written 1117 * 1118 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 1119 */ 1120 static int 1121 qla8044_ms_mem_write_128b(struct scsi_qla_host *vha, 1122 uint64_t addr, uint32_t *data, uint32_t count) 1123 { 1124 int i, j, ret_val = QLA_SUCCESS; 1125 uint32_t agt_ctrl; 1126 unsigned long flags; 1127 struct qla_hw_data *ha = vha->hw; 1128 1129 /* Only 128-bit aligned access */ 1130 if (addr & 0xF) { 1131 ret_val = QLA_FUNCTION_FAILED; 1132 goto exit_ms_mem_write; 1133 } 1134 write_lock_irqsave(&ha->hw_lock, flags); 1135 1136 /* Write address */ 1137 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0); 1138 if (ret_val == QLA_FUNCTION_FAILED) { 1139 ql_log(ql_log_fatal, vha, 0xb0a1, 1140 "%s: write to AGT_ADDR_HI failed!\n", __func__); 1141 goto exit_ms_mem_write_unlock; 1142 } 1143 1144 for (i = 0; i < count; i++, addr += 16) { 1145 if (!((addr_in_range(addr, QLA8044_ADDR_QDR_NET, 1146 QLA8044_ADDR_QDR_NET_MAX)) || 1147 (addr_in_range(addr, QLA8044_ADDR_DDR_NET, 1148 QLA8044_ADDR_DDR_NET_MAX)))) { 1149 ret_val = QLA_FUNCTION_FAILED; 1150 goto exit_ms_mem_write_unlock; 1151 } 1152 1153 ret_val = qla8044_wr_reg_indirect(vha, 1154 MD_MIU_TEST_AGT_ADDR_LO, addr); 1155 1156 /* Write data */ 1157 ret_val += qla8044_wr_reg_indirect(vha, 1158 MD_MIU_TEST_AGT_WRDATA_LO, *data++); 1159 ret_val += qla8044_wr_reg_indirect(vha, 1160 MD_MIU_TEST_AGT_WRDATA_HI, *data++); 1161 ret_val += qla8044_wr_reg_indirect(vha, 1162 MD_MIU_TEST_AGT_WRDATA_ULO, *data++); 1163 ret_val += qla8044_wr_reg_indirect(vha, 1164 MD_MIU_TEST_AGT_WRDATA_UHI, *data++); 1165 if (ret_val == QLA_FUNCTION_FAILED) { 1166 ql_log(ql_log_fatal, vha, 0xb0a2, 1167 "%s: write to AGT_WRDATA failed!\n", 1168 __func__); 1169 goto exit_ms_mem_write_unlock; 1170 } 1171 1172 /* Check write status */ 1173 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, 1174 MIU_TA_CTL_WRITE_ENABLE); 1175 ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, 1176 MIU_TA_CTL_WRITE_START); 1177 if (ret_val == QLA_FUNCTION_FAILED) { 1178 ql_log(ql_log_fatal, vha, 0xb0a3, 1179 "%s: write to AGT_CTRL failed!\n", __func__); 1180 goto exit_ms_mem_write_unlock; 1181 } 1182 1183 for (j = 0; j < MAX_CTL_CHECK; j++) { 1184 ret_val = qla8044_rd_reg_indirect(vha, 1185 MD_MIU_TEST_AGT_CTRL, &agt_ctrl); 1186 if (ret_val == QLA_FUNCTION_FAILED) { 1187 ql_log(ql_log_fatal, vha, 0xb0a4, 1188 "%s: failed to read " 1189 "MD_MIU_TEST_AGT_CTRL!\n", __func__); 1190 goto exit_ms_mem_write_unlock; 1191 } 1192 if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0) 1193 break; 1194 } 1195 1196 /* Status check failed */ 1197 if (j >= MAX_CTL_CHECK) { 1198 ql_log(ql_log_fatal, vha, 0xb0a5, 1199 "%s: MS memory write failed!\n", 1200 __func__); 1201 ret_val = QLA_FUNCTION_FAILED; 1202 goto exit_ms_mem_write_unlock; 1203 } 1204 } 1205 1206 exit_ms_mem_write_unlock: 1207 write_unlock_irqrestore(&ha->hw_lock, flags); 1208 1209 exit_ms_mem_write: 1210 return ret_val; 1211 } 1212 1213 static int 1214 qla8044_copy_bootloader(struct scsi_qla_host *vha) 1215 { 1216 uint8_t *p_cache; 1217 uint32_t src, count, size; 1218 uint64_t dest; 1219 int ret_val = QLA_SUCCESS; 1220 struct qla_hw_data *ha = vha->hw; 1221 1222 src = QLA8044_BOOTLOADER_FLASH_ADDR; 1223 dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR); 1224 size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE); 1225 1226 /* 128 bit alignment check */ 1227 if (size & 0xF) 1228 size = (size + 16) & ~0xF; 1229 1230 /* 16 byte count */ 1231 count = size/16; 1232 1233 p_cache = vmalloc(size); 1234 if (p_cache == NULL) { 1235 ql_log(ql_log_fatal, vha, 0xb0a6, 1236 "%s: Failed to allocate memory for " 1237 "boot loader cache\n", __func__); 1238 ret_val = QLA_FUNCTION_FAILED; 1239 goto exit_copy_bootloader; 1240 } 1241 1242 ret_val = qla8044_lockless_flash_read_u32(vha, src, 1243 p_cache, size/sizeof(uint32_t)); 1244 if (ret_val == QLA_FUNCTION_FAILED) { 1245 ql_log(ql_log_fatal, vha, 0xb0a7, 1246 "%s: Error reading F/W from flash!!!\n", __func__); 1247 goto exit_copy_error; 1248 } 1249 ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n", 1250 __func__); 1251 1252 /* 128 bit/16 byte write to MS memory */ 1253 ret_val = qla8044_ms_mem_write_128b(vha, dest, 1254 (uint32_t *)p_cache, count); 1255 if (ret_val == QLA_FUNCTION_FAILED) { 1256 ql_log(ql_log_fatal, vha, 0xb0a9, 1257 "%s: Error writing F/W to MS !!!\n", __func__); 1258 goto exit_copy_error; 1259 } 1260 ql_dbg(ql_dbg_p3p, vha, 0xb0aa, 1261 "%s: Wrote F/W (size %d) to MS !!!\n", 1262 __func__, size); 1263 1264 exit_copy_error: 1265 vfree(p_cache); 1266 1267 exit_copy_bootloader: 1268 return ret_val; 1269 } 1270 1271 static int 1272 qla8044_restart(struct scsi_qla_host *vha) 1273 { 1274 int ret_val = QLA_SUCCESS; 1275 struct qla_hw_data *ha = vha->hw; 1276 1277 qla8044_process_stop_seq(vha); 1278 1279 /* Collect minidump */ 1280 if (ql2xmdenable) 1281 qla8044_get_minidump(vha); 1282 else 1283 ql_log(ql_log_fatal, vha, 0xb14c, 1284 "Minidump disabled.\n"); 1285 1286 qla8044_process_init_seq(vha); 1287 1288 if (qla8044_copy_bootloader(vha)) { 1289 ql_log(ql_log_fatal, vha, 0xb0ab, 1290 "%s: Copy bootloader, firmware restart failed!\n", 1291 __func__); 1292 ret_val = QLA_FUNCTION_FAILED; 1293 goto exit_restart; 1294 } 1295 1296 /* 1297 * Loads F/W from flash 1298 */ 1299 qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH); 1300 1301 qla8044_process_start_seq(vha); 1302 1303 exit_restart: 1304 return ret_val; 1305 } 1306 1307 /* 1308 * qla8044_check_cmd_peg_status - Check peg status to see if Peg is 1309 * initialized. 1310 * 1311 * @ha : Pointer to adapter structure 1312 * 1313 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 1314 */ 1315 static int 1316 qla8044_check_cmd_peg_status(struct scsi_qla_host *vha) 1317 { 1318 uint32_t val, ret_val = QLA_FUNCTION_FAILED; 1319 int retries = CRB_CMDPEG_CHECK_RETRY_COUNT; 1320 struct qla_hw_data *ha = vha->hw; 1321 1322 do { 1323 val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE); 1324 if (val == PHAN_INITIALIZE_COMPLETE) { 1325 ql_dbg(ql_dbg_p3p, vha, 0xb0ac, 1326 "%s: Command Peg initialization " 1327 "complete! state=0x%x\n", __func__, val); 1328 ret_val = QLA_SUCCESS; 1329 break; 1330 } 1331 msleep(CRB_CMDPEG_CHECK_DELAY); 1332 } while (--retries); 1333 1334 return ret_val; 1335 } 1336 1337 static int 1338 qla8044_start_firmware(struct scsi_qla_host *vha) 1339 { 1340 int ret_val = QLA_SUCCESS; 1341 1342 if (qla8044_restart(vha)) { 1343 ql_log(ql_log_fatal, vha, 0xb0ad, 1344 "%s: Restart Error!!!, Need Reset!!!\n", 1345 __func__); 1346 ret_val = QLA_FUNCTION_FAILED; 1347 goto exit_start_fw; 1348 } else 1349 ql_dbg(ql_dbg_p3p, vha, 0xb0af, 1350 "%s: Restart done!\n", __func__); 1351 1352 ret_val = qla8044_check_cmd_peg_status(vha); 1353 if (ret_val) { 1354 ql_log(ql_log_fatal, vha, 0xb0b0, 1355 "%s: Peg not initialized!\n", __func__); 1356 ret_val = QLA_FUNCTION_FAILED; 1357 } 1358 1359 exit_start_fw: 1360 return ret_val; 1361 } 1362 1363 void 1364 qla8044_clear_drv_active(struct qla_hw_data *ha) 1365 { 1366 uint32_t drv_active; 1367 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev); 1368 1369 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 1370 drv_active &= ~(1 << (ha->portnum)); 1371 1372 ql_log(ql_log_info, vha, 0xb0b1, 1373 "%s(%ld): drv_active: 0x%08x\n", 1374 __func__, vha->host_no, drv_active); 1375 1376 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active); 1377 } 1378 1379 /* 1380 * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw 1381 * @ha: pointer to adapter structure 1382 * 1383 * Note: IDC lock must be held upon entry 1384 **/ 1385 static int 1386 qla8044_device_bootstrap(struct scsi_qla_host *vha) 1387 { 1388 int rval = QLA_FUNCTION_FAILED; 1389 int i; 1390 uint32_t old_count = 0, count = 0; 1391 int need_reset = 0; 1392 uint32_t idc_ctrl; 1393 struct qla_hw_data *ha = vha->hw; 1394 1395 need_reset = qla8044_need_reset(vha); 1396 1397 if (!need_reset) { 1398 old_count = qla8044_rd_direct(vha, 1399 QLA8044_PEG_ALIVE_COUNTER_INDEX); 1400 1401 for (i = 0; i < 10; i++) { 1402 msleep(200); 1403 1404 count = qla8044_rd_direct(vha, 1405 QLA8044_PEG_ALIVE_COUNTER_INDEX); 1406 if (count != old_count) { 1407 rval = QLA_SUCCESS; 1408 goto dev_ready; 1409 } 1410 } 1411 qla8044_flash_lock_recovery(vha); 1412 } else { 1413 /* We are trying to perform a recovery here. */ 1414 if (ha->flags.isp82xx_fw_hung) 1415 qla8044_flash_lock_recovery(vha); 1416 } 1417 1418 /* set to DEV_INITIALIZING */ 1419 ql_log(ql_log_info, vha, 0xb0b2, 1420 "%s: HW State: INITIALIZING\n", __func__); 1421 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 1422 QLA8XXX_DEV_INITIALIZING); 1423 1424 qla8044_idc_unlock(ha); 1425 rval = qla8044_start_firmware(vha); 1426 qla8044_idc_lock(ha); 1427 1428 if (rval != QLA_SUCCESS) { 1429 ql_log(ql_log_info, vha, 0xb0b3, 1430 "%s: HW State: FAILED\n", __func__); 1431 qla8044_clear_drv_active(ha); 1432 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 1433 QLA8XXX_DEV_FAILED); 1434 return rval; 1435 } 1436 1437 /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after 1438 * device goes to INIT state. */ 1439 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 1440 if (idc_ctrl & GRACEFUL_RESET_BIT1) { 1441 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, 1442 (idc_ctrl & ~GRACEFUL_RESET_BIT1)); 1443 ha->fw_dumped = false; 1444 } 1445 1446 dev_ready: 1447 ql_log(ql_log_info, vha, 0xb0b4, 1448 "%s: HW State: READY\n", __func__); 1449 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY); 1450 1451 return rval; 1452 } 1453 1454 /*-------------------------Reset Sequence Functions-----------------------*/ 1455 static void 1456 qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha) 1457 { 1458 u8 *phdr; 1459 1460 if (!vha->reset_tmplt.buff) { 1461 ql_log(ql_log_fatal, vha, 0xb0b5, 1462 "%s: Error Invalid reset_seq_template\n", __func__); 1463 return; 1464 } 1465 1466 phdr = vha->reset_tmplt.buff; 1467 ql_dbg(ql_dbg_p3p, vha, 0xb0b6, 1468 "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X" 1469 "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n" 1470 "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n", 1471 *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4), 1472 *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8), 1473 *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12), 1474 *(phdr+13), *(phdr+14), *(phdr+15)); 1475 } 1476 1477 /* 1478 * qla8044_reset_seq_checksum_test - Validate Reset Sequence template. 1479 * 1480 * @ha : Pointer to adapter structure 1481 * 1482 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 1483 */ 1484 static int 1485 qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha) 1486 { 1487 uint32_t sum = 0; 1488 uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff; 1489 int u16_count = vha->reset_tmplt.hdr->size / sizeof(uint16_t); 1490 1491 while (u16_count-- > 0) 1492 sum += *buff++; 1493 1494 while (sum >> 16) 1495 sum = (sum & 0xFFFF) + (sum >> 16); 1496 1497 /* checksum of 0 indicates a valid template */ 1498 if (~sum) { 1499 return QLA_SUCCESS; 1500 } else { 1501 ql_log(ql_log_fatal, vha, 0xb0b7, 1502 "%s: Reset seq checksum failed\n", __func__); 1503 return QLA_FUNCTION_FAILED; 1504 } 1505 } 1506 1507 /* 1508 * qla8044_read_reset_template - Read Reset Template from Flash, validate 1509 * the template and store offsets of stop/start/init offsets in ha->reset_tmplt. 1510 * 1511 * @ha : Pointer to adapter structure 1512 */ 1513 void 1514 qla8044_read_reset_template(struct scsi_qla_host *vha) 1515 { 1516 uint8_t *p_buff; 1517 uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size; 1518 1519 vha->reset_tmplt.seq_error = 0; 1520 vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE); 1521 if (vha->reset_tmplt.buff == NULL) { 1522 ql_log(ql_log_fatal, vha, 0xb0b8, 1523 "%s: Failed to allocate reset template resources\n", 1524 __func__); 1525 goto exit_read_reset_template; 1526 } 1527 1528 p_buff = vha->reset_tmplt.buff; 1529 addr = QLA8044_RESET_TEMPLATE_ADDR; 1530 1531 tmplt_hdr_def_size = 1532 sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t); 1533 1534 ql_dbg(ql_dbg_p3p, vha, 0xb0b9, 1535 "%s: Read template hdr size %d from Flash\n", 1536 __func__, tmplt_hdr_def_size); 1537 1538 /* Copy template header from flash */ 1539 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) { 1540 ql_log(ql_log_fatal, vha, 0xb0ba, 1541 "%s: Failed to read reset template\n", __func__); 1542 goto exit_read_template_error; 1543 } 1544 1545 vha->reset_tmplt.hdr = 1546 (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff; 1547 1548 /* Validate the template header size and signature */ 1549 tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t); 1550 if ((tmplt_hdr_size != tmplt_hdr_def_size) || 1551 (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) { 1552 ql_log(ql_log_fatal, vha, 0xb0bb, 1553 "%s: Template Header size invalid %d " 1554 "tmplt_hdr_def_size %d!!!\n", __func__, 1555 tmplt_hdr_size, tmplt_hdr_def_size); 1556 goto exit_read_template_error; 1557 } 1558 1559 addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size; 1560 p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size; 1561 tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size - 1562 vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t); 1563 1564 ql_dbg(ql_dbg_p3p, vha, 0xb0bc, 1565 "%s: Read rest of the template size %d\n", 1566 __func__, vha->reset_tmplt.hdr->size); 1567 1568 /* Copy rest of the template */ 1569 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) { 1570 ql_log(ql_log_fatal, vha, 0xb0bd, 1571 "%s: Failed to read reset template\n", __func__); 1572 goto exit_read_template_error; 1573 } 1574 1575 /* Integrity check */ 1576 if (qla8044_reset_seq_checksum_test(vha)) { 1577 ql_log(ql_log_fatal, vha, 0xb0be, 1578 "%s: Reset Seq checksum failed!\n", __func__); 1579 goto exit_read_template_error; 1580 } 1581 1582 ql_dbg(ql_dbg_p3p, vha, 0xb0bf, 1583 "%s: Reset Seq checksum passed! Get stop, " 1584 "start and init seq offsets\n", __func__); 1585 1586 /* Get STOP, START, INIT sequence offsets */ 1587 vha->reset_tmplt.init_offset = vha->reset_tmplt.buff + 1588 vha->reset_tmplt.hdr->init_seq_offset; 1589 1590 vha->reset_tmplt.start_offset = vha->reset_tmplt.buff + 1591 vha->reset_tmplt.hdr->start_seq_offset; 1592 1593 vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff + 1594 vha->reset_tmplt.hdr->hdr_size; 1595 1596 qla8044_dump_reset_seq_hdr(vha); 1597 1598 goto exit_read_reset_template; 1599 1600 exit_read_template_error: 1601 vfree(vha->reset_tmplt.buff); 1602 1603 exit_read_reset_template: 1604 return; 1605 } 1606 1607 void 1608 qla8044_set_idc_dontreset(struct scsi_qla_host *vha) 1609 { 1610 uint32_t idc_ctrl; 1611 struct qla_hw_data *ha = vha->hw; 1612 1613 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 1614 idc_ctrl |= DONTRESET_BIT0; 1615 ql_dbg(ql_dbg_p3p, vha, 0xb0c0, 1616 "%s: idc_ctrl = %d\n", __func__, idc_ctrl); 1617 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl); 1618 } 1619 1620 static inline void 1621 qla8044_set_rst_ready(struct scsi_qla_host *vha) 1622 { 1623 uint32_t drv_state; 1624 struct qla_hw_data *ha = vha->hw; 1625 1626 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 1627 1628 /* For ISP8044, drv_active register has 1 bit per function, 1629 * shift 1 by func_num to set a bit for the function.*/ 1630 drv_state |= (1 << ha->portnum); 1631 1632 ql_log(ql_log_info, vha, 0xb0c1, 1633 "%s(%ld): drv_state: 0x%08x\n", 1634 __func__, vha->host_no, drv_state); 1635 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state); 1636 } 1637 1638 /** 1639 * qla8044_need_reset_handler - Code to start reset sequence 1640 * @vha: pointer to adapter structure 1641 * 1642 * Note: IDC lock must be held upon entry 1643 */ 1644 static void 1645 qla8044_need_reset_handler(struct scsi_qla_host *vha) 1646 { 1647 uint32_t dev_state = 0, drv_state, drv_active; 1648 unsigned long reset_timeout; 1649 struct qla_hw_data *ha = vha->hw; 1650 1651 ql_log(ql_log_fatal, vha, 0xb0c2, 1652 "%s: Performing ISP error recovery\n", __func__); 1653 1654 if (vha->flags.online) { 1655 qla8044_idc_unlock(ha); 1656 qla2x00_abort_isp_cleanup(vha); 1657 ha->isp_ops->get_flash_version(vha, vha->req->ring); 1658 ha->isp_ops->nvram_config(vha); 1659 qla8044_idc_lock(ha); 1660 } 1661 1662 dev_state = qla8044_rd_direct(vha, 1663 QLA8044_CRB_DEV_STATE_INDEX); 1664 drv_state = qla8044_rd_direct(vha, 1665 QLA8044_CRB_DRV_STATE_INDEX); 1666 drv_active = qla8044_rd_direct(vha, 1667 QLA8044_CRB_DRV_ACTIVE_INDEX); 1668 1669 ql_log(ql_log_info, vha, 0xb0c5, 1670 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x dev_state = 0x%x\n", 1671 __func__, vha->host_no, drv_state, drv_active, dev_state); 1672 1673 qla8044_set_rst_ready(vha); 1674 1675 /* wait for 10 seconds for reset ack from all functions */ 1676 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 1677 1678 do { 1679 if (time_after_eq(jiffies, reset_timeout)) { 1680 ql_log(ql_log_info, vha, 0xb0c4, 1681 "%s: Function %d: Reset Ack Timeout!, drv_state: 0x%08x, drv_active: 0x%08x\n", 1682 __func__, ha->portnum, drv_state, drv_active); 1683 break; 1684 } 1685 1686 qla8044_idc_unlock(ha); 1687 msleep(1000); 1688 qla8044_idc_lock(ha); 1689 1690 dev_state = qla8044_rd_direct(vha, 1691 QLA8044_CRB_DEV_STATE_INDEX); 1692 drv_state = qla8044_rd_direct(vha, 1693 QLA8044_CRB_DRV_STATE_INDEX); 1694 drv_active = qla8044_rd_direct(vha, 1695 QLA8044_CRB_DRV_ACTIVE_INDEX); 1696 } while (((drv_state & drv_active) != drv_active) && 1697 (dev_state == QLA8XXX_DEV_NEED_RESET)); 1698 1699 /* Remove IDC participation of functions not acknowledging */ 1700 if (drv_state != drv_active) { 1701 ql_log(ql_log_info, vha, 0xb0c7, 1702 "%s(%ld): Function %d turning off drv_active of non-acking function 0x%x\n", 1703 __func__, vha->host_no, ha->portnum, 1704 (drv_active ^ drv_state)); 1705 drv_active = drv_active & drv_state; 1706 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, 1707 drv_active); 1708 } else { 1709 /* 1710 * Reset owner should execute reset recovery, 1711 * if all functions acknowledged 1712 */ 1713 if ((ha->flags.nic_core_reset_owner) && 1714 (dev_state == QLA8XXX_DEV_NEED_RESET)) { 1715 ha->flags.nic_core_reset_owner = 0; 1716 qla8044_device_bootstrap(vha); 1717 return; 1718 } 1719 } 1720 1721 /* Exit if non active function */ 1722 if (!(drv_active & (1 << ha->portnum))) { 1723 ha->flags.nic_core_reset_owner = 0; 1724 return; 1725 } 1726 1727 /* 1728 * Execute Reset Recovery if Reset Owner or Function 7 1729 * is the only active function 1730 */ 1731 if (ha->flags.nic_core_reset_owner || 1732 ((drv_state & drv_active) == QLA8044_FUN7_ACTIVE_INDEX)) { 1733 ha->flags.nic_core_reset_owner = 0; 1734 qla8044_device_bootstrap(vha); 1735 } 1736 } 1737 1738 static void 1739 qla8044_set_drv_active(struct scsi_qla_host *vha) 1740 { 1741 uint32_t drv_active; 1742 struct qla_hw_data *ha = vha->hw; 1743 1744 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 1745 1746 /* For ISP8044, drv_active register has 1 bit per function, 1747 * shift 1 by func_num to set a bit for the function.*/ 1748 drv_active |= (1 << ha->portnum); 1749 1750 ql_log(ql_log_info, vha, 0xb0c8, 1751 "%s(%ld): drv_active: 0x%08x\n", 1752 __func__, vha->host_no, drv_active); 1753 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active); 1754 } 1755 1756 static int 1757 qla8044_check_drv_active(struct scsi_qla_host *vha) 1758 { 1759 uint32_t drv_active; 1760 struct qla_hw_data *ha = vha->hw; 1761 1762 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 1763 if (drv_active & (1 << ha->portnum)) 1764 return QLA_SUCCESS; 1765 else 1766 return QLA_TEST_FAILED; 1767 } 1768 1769 static void 1770 qla8044_clear_idc_dontreset(struct scsi_qla_host *vha) 1771 { 1772 uint32_t idc_ctrl; 1773 struct qla_hw_data *ha = vha->hw; 1774 1775 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 1776 idc_ctrl &= ~DONTRESET_BIT0; 1777 ql_log(ql_log_info, vha, 0xb0c9, 1778 "%s: idc_ctrl = %d\n", __func__, 1779 idc_ctrl); 1780 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl); 1781 } 1782 1783 static int 1784 qla8044_set_idc_ver(struct scsi_qla_host *vha) 1785 { 1786 int idc_ver; 1787 uint32_t drv_active; 1788 int rval = QLA_SUCCESS; 1789 struct qla_hw_data *ha = vha->hw; 1790 1791 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 1792 if (drv_active == (1 << ha->portnum)) { 1793 idc_ver = qla8044_rd_direct(vha, 1794 QLA8044_CRB_DRV_IDC_VERSION_INDEX); 1795 idc_ver &= (~0xFF); 1796 idc_ver |= QLA8044_IDC_VER_MAJ_VALUE; 1797 qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX, 1798 idc_ver); 1799 ql_log(ql_log_info, vha, 0xb0ca, 1800 "%s: IDC version updated to %d\n", 1801 __func__, idc_ver); 1802 } else { 1803 idc_ver = qla8044_rd_direct(vha, 1804 QLA8044_CRB_DRV_IDC_VERSION_INDEX); 1805 idc_ver &= 0xFF; 1806 if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) { 1807 ql_log(ql_log_info, vha, 0xb0cb, 1808 "%s: qla4xxx driver IDC version %d " 1809 "is not compatible with IDC version %d " 1810 "of other drivers!\n", 1811 __func__, QLA8044_IDC_VER_MAJ_VALUE, 1812 idc_ver); 1813 rval = QLA_FUNCTION_FAILED; 1814 goto exit_set_idc_ver; 1815 } 1816 } 1817 1818 /* Update IDC_MINOR_VERSION */ 1819 idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR); 1820 idc_ver &= ~(0x03 << (ha->portnum * 2)); 1821 idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2)); 1822 qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver); 1823 1824 exit_set_idc_ver: 1825 return rval; 1826 } 1827 1828 static int 1829 qla8044_update_idc_reg(struct scsi_qla_host *vha) 1830 { 1831 uint32_t drv_active; 1832 int rval = QLA_SUCCESS; 1833 struct qla_hw_data *ha = vha->hw; 1834 1835 if (vha->flags.init_done) 1836 goto exit_update_idc_reg; 1837 1838 qla8044_idc_lock(ha); 1839 qla8044_set_drv_active(vha); 1840 1841 drv_active = qla8044_rd_direct(vha, 1842 QLA8044_CRB_DRV_ACTIVE_INDEX); 1843 1844 /* If we are the first driver to load and 1845 * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */ 1846 if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba) 1847 qla8044_clear_idc_dontreset(vha); 1848 1849 rval = qla8044_set_idc_ver(vha); 1850 if (rval == QLA_FUNCTION_FAILED) 1851 qla8044_clear_drv_active(ha); 1852 qla8044_idc_unlock(ha); 1853 1854 exit_update_idc_reg: 1855 return rval; 1856 } 1857 1858 /** 1859 * qla8044_need_qsnt_handler - Code to start qsnt 1860 * @vha: pointer to adapter structure 1861 */ 1862 static void 1863 qla8044_need_qsnt_handler(struct scsi_qla_host *vha) 1864 { 1865 unsigned long qsnt_timeout; 1866 uint32_t drv_state, drv_active, dev_state; 1867 struct qla_hw_data *ha = vha->hw; 1868 1869 if (vha->flags.online) 1870 qla2x00_quiesce_io(vha); 1871 else 1872 return; 1873 1874 qla8044_set_qsnt_ready(vha); 1875 1876 /* Wait for 30 secs for all functions to ack qsnt mode */ 1877 qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ); 1878 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 1879 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 1880 1881 /* Shift drv_active by 1 to match drv_state. As quiescent ready bit 1882 position is at bit 1 and drv active is at bit 0 */ 1883 drv_active = drv_active << 1; 1884 1885 while (drv_state != drv_active) { 1886 if (time_after_eq(jiffies, qsnt_timeout)) { 1887 /* Other functions did not ack, changing state to 1888 * DEV_READY 1889 */ 1890 clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 1891 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 1892 QLA8XXX_DEV_READY); 1893 qla8044_clear_qsnt_ready(vha); 1894 ql_log(ql_log_info, vha, 0xb0cc, 1895 "Timeout waiting for quiescent ack!!!\n"); 1896 return; 1897 } 1898 qla8044_idc_unlock(ha); 1899 msleep(1000); 1900 qla8044_idc_lock(ha); 1901 1902 drv_state = qla8044_rd_direct(vha, 1903 QLA8044_CRB_DRV_STATE_INDEX); 1904 drv_active = qla8044_rd_direct(vha, 1905 QLA8044_CRB_DRV_ACTIVE_INDEX); 1906 drv_active = drv_active << 1; 1907 } 1908 1909 /* All functions have Acked. Set quiescent state */ 1910 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 1911 1912 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 1913 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 1914 QLA8XXX_DEV_QUIESCENT); 1915 ql_log(ql_log_info, vha, 0xb0cd, 1916 "%s: HW State: QUIESCENT\n", __func__); 1917 } 1918 } 1919 1920 /* 1921 * qla8044_device_state_handler - Adapter state machine 1922 * @ha: pointer to host adapter structure. 1923 * 1924 * Note: IDC lock must be UNLOCKED upon entry 1925 **/ 1926 int 1927 qla8044_device_state_handler(struct scsi_qla_host *vha) 1928 { 1929 uint32_t dev_state; 1930 int rval = QLA_SUCCESS; 1931 unsigned long dev_init_timeout; 1932 struct qla_hw_data *ha = vha->hw; 1933 1934 rval = qla8044_update_idc_reg(vha); 1935 if (rval == QLA_FUNCTION_FAILED) 1936 goto exit_error; 1937 1938 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 1939 ql_dbg(ql_dbg_p3p, vha, 0xb0ce, 1940 "Device state is 0x%x = %s\n", 1941 dev_state, dev_state < MAX_STATES ? 1942 qdev_state(dev_state) : "Unknown"); 1943 1944 /* wait for 30 seconds for device to go ready */ 1945 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 1946 1947 qla8044_idc_lock(ha); 1948 1949 while (1) { 1950 if (time_after_eq(jiffies, dev_init_timeout)) { 1951 if (qla8044_check_drv_active(vha) == QLA_SUCCESS) { 1952 ql_log(ql_log_warn, vha, 0xb0cf, 1953 "%s: Device Init Failed 0x%x = %s\n", 1954 QLA2XXX_DRIVER_NAME, dev_state, 1955 dev_state < MAX_STATES ? 1956 qdev_state(dev_state) : "Unknown"); 1957 qla8044_wr_direct(vha, 1958 QLA8044_CRB_DEV_STATE_INDEX, 1959 QLA8XXX_DEV_FAILED); 1960 } 1961 } 1962 1963 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 1964 ql_log(ql_log_info, vha, 0xb0d0, 1965 "Device state is 0x%x = %s\n", 1966 dev_state, dev_state < MAX_STATES ? 1967 qdev_state(dev_state) : "Unknown"); 1968 1969 /* NOTE: Make sure idc unlocked upon exit of switch statement */ 1970 switch (dev_state) { 1971 case QLA8XXX_DEV_READY: 1972 ha->flags.nic_core_reset_owner = 0; 1973 goto exit; 1974 case QLA8XXX_DEV_COLD: 1975 rval = qla8044_device_bootstrap(vha); 1976 break; 1977 case QLA8XXX_DEV_INITIALIZING: 1978 qla8044_idc_unlock(ha); 1979 msleep(1000); 1980 qla8044_idc_lock(ha); 1981 break; 1982 case QLA8XXX_DEV_NEED_RESET: 1983 /* For ISP8044, if NEED_RESET is set by any driver, 1984 * it should be honored, irrespective of IDC_CTRL 1985 * DONTRESET_BIT0 */ 1986 qla8044_need_reset_handler(vha); 1987 break; 1988 case QLA8XXX_DEV_NEED_QUIESCENT: 1989 /* idc locked/unlocked in handler */ 1990 qla8044_need_qsnt_handler(vha); 1991 1992 /* Reset the init timeout after qsnt handler */ 1993 dev_init_timeout = jiffies + 1994 (ha->fcoe_reset_timeout * HZ); 1995 break; 1996 case QLA8XXX_DEV_QUIESCENT: 1997 ql_log(ql_log_info, vha, 0xb0d1, 1998 "HW State: QUIESCENT\n"); 1999 2000 qla8044_idc_unlock(ha); 2001 msleep(1000); 2002 qla8044_idc_lock(ha); 2003 2004 /* Reset the init timeout after qsnt handler */ 2005 dev_init_timeout = jiffies + 2006 (ha->fcoe_reset_timeout * HZ); 2007 break; 2008 case QLA8XXX_DEV_FAILED: 2009 ha->flags.nic_core_reset_owner = 0; 2010 qla8044_idc_unlock(ha); 2011 qla8xxx_dev_failed_handler(vha); 2012 rval = QLA_FUNCTION_FAILED; 2013 qla8044_idc_lock(ha); 2014 goto exit; 2015 default: 2016 qla8044_idc_unlock(ha); 2017 qla8xxx_dev_failed_handler(vha); 2018 rval = QLA_FUNCTION_FAILED; 2019 qla8044_idc_lock(ha); 2020 goto exit; 2021 } 2022 } 2023 exit: 2024 qla8044_idc_unlock(ha); 2025 2026 exit_error: 2027 return rval; 2028 } 2029 2030 /** 2031 * qla8044_check_temp - Check the ISP82XX temperature. 2032 * @vha: adapter block pointer. 2033 * 2034 * Note: The caller should not hold the idc lock. 2035 */ 2036 static int 2037 qla8044_check_temp(struct scsi_qla_host *vha) 2038 { 2039 uint32_t temp, temp_state, temp_val; 2040 int status = QLA_SUCCESS; 2041 2042 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX); 2043 temp_state = qla82xx_get_temp_state(temp); 2044 temp_val = qla82xx_get_temp_val(temp); 2045 2046 if (temp_state == QLA82XX_TEMP_PANIC) { 2047 ql_log(ql_log_warn, vha, 0xb0d2, 2048 "Device temperature %d degrees C" 2049 " exceeds maximum allowed. Hardware has been shut" 2050 " down\n", temp_val); 2051 status = QLA_FUNCTION_FAILED; 2052 return status; 2053 } else if (temp_state == QLA82XX_TEMP_WARN) { 2054 ql_log(ql_log_warn, vha, 0xb0d3, 2055 "Device temperature %d" 2056 " degrees C exceeds operating range." 2057 " Immediate action needed.\n", temp_val); 2058 } 2059 return 0; 2060 } 2061 2062 int qla8044_read_temperature(scsi_qla_host_t *vha) 2063 { 2064 uint32_t temp; 2065 2066 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX); 2067 return qla82xx_get_temp_val(temp); 2068 } 2069 2070 /** 2071 * qla8044_check_fw_alive - Check firmware health 2072 * @vha: Pointer to host adapter structure. 2073 * 2074 * Context: Interrupt 2075 */ 2076 int 2077 qla8044_check_fw_alive(struct scsi_qla_host *vha) 2078 { 2079 uint32_t fw_heartbeat_counter; 2080 uint32_t halt_status1, halt_status2; 2081 int status = QLA_SUCCESS; 2082 2083 fw_heartbeat_counter = qla8044_rd_direct(vha, 2084 QLA8044_PEG_ALIVE_COUNTER_INDEX); 2085 2086 /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */ 2087 if (fw_heartbeat_counter == 0xffffffff) { 2088 ql_dbg(ql_dbg_p3p, vha, 0xb0d4, 2089 "scsi%ld: %s: Device in frozen " 2090 "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n", 2091 vha->host_no, __func__); 2092 return status; 2093 } 2094 2095 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 2096 vha->seconds_since_last_heartbeat++; 2097 /* FW not alive after 2 seconds */ 2098 if (vha->seconds_since_last_heartbeat == 2) { 2099 vha->seconds_since_last_heartbeat = 0; 2100 halt_status1 = qla8044_rd_direct(vha, 2101 QLA8044_PEG_HALT_STATUS1_INDEX); 2102 halt_status2 = qla8044_rd_direct(vha, 2103 QLA8044_PEG_HALT_STATUS2_INDEX); 2104 2105 ql_log(ql_log_info, vha, 0xb0d5, 2106 "scsi(%ld): %s, ISP8044 " 2107 "Dumping hw/fw registers:\n" 2108 " PEG_HALT_STATUS1: 0x%x, " 2109 "PEG_HALT_STATUS2: 0x%x,\n", 2110 vha->host_no, __func__, halt_status1, 2111 halt_status2); 2112 status = QLA_FUNCTION_FAILED; 2113 } 2114 } else 2115 vha->seconds_since_last_heartbeat = 0; 2116 2117 vha->fw_heartbeat_counter = fw_heartbeat_counter; 2118 return status; 2119 } 2120 2121 void 2122 qla8044_watchdog(struct scsi_qla_host *vha) 2123 { 2124 uint32_t dev_state, halt_status; 2125 int halt_status_unrecoverable = 0; 2126 struct qla_hw_data *ha = vha->hw; 2127 2128 /* don't poll if reset is going on or FW hang in quiescent state */ 2129 if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) || 2130 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) { 2131 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 2132 2133 if (qla8044_check_fw_alive(vha)) { 2134 ha->flags.isp82xx_fw_hung = 1; 2135 ql_log(ql_log_warn, vha, 0xb10a, 2136 "Firmware hung.\n"); 2137 qla82xx_clear_pending_mbx(vha); 2138 } 2139 2140 if (qla8044_check_temp(vha)) { 2141 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 2142 ha->flags.isp82xx_fw_hung = 1; 2143 qla2xxx_wake_dpc(vha); 2144 } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 2145 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 2146 ql_log(ql_log_info, vha, 0xb0d6, 2147 "%s: HW State: NEED RESET!\n", 2148 __func__); 2149 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2150 qla2xxx_wake_dpc(vha); 2151 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 2152 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 2153 ql_log(ql_log_info, vha, 0xb0d7, 2154 "%s: HW State: NEED QUIES detected!\n", 2155 __func__); 2156 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 2157 qla2xxx_wake_dpc(vha); 2158 } else { 2159 /* Check firmware health */ 2160 if (ha->flags.isp82xx_fw_hung) { 2161 halt_status = qla8044_rd_direct(vha, 2162 QLA8044_PEG_HALT_STATUS1_INDEX); 2163 if (halt_status & 2164 QLA8044_HALT_STATUS_FW_RESET) { 2165 ql_log(ql_log_fatal, vha, 2166 0xb0d8, "%s: Firmware " 2167 "error detected device " 2168 "is being reset\n", 2169 __func__); 2170 } else if (halt_status & 2171 QLA8044_HALT_STATUS_UNRECOVERABLE) { 2172 halt_status_unrecoverable = 1; 2173 } 2174 2175 /* Since we cannot change dev_state in interrupt 2176 * context, set appropriate DPC flag then wakeup 2177 * DPC */ 2178 if (halt_status_unrecoverable) { 2179 set_bit(ISP_UNRECOVERABLE, 2180 &vha->dpc_flags); 2181 } else { 2182 if (dev_state == 2183 QLA8XXX_DEV_QUIESCENT) { 2184 set_bit(FCOE_CTX_RESET_NEEDED, 2185 &vha->dpc_flags); 2186 ql_log(ql_log_info, vha, 0xb0d9, 2187 "%s: FW CONTEXT Reset " 2188 "needed!\n", __func__); 2189 } else { 2190 ql_log(ql_log_info, vha, 2191 0xb0da, "%s: " 2192 "detect abort needed\n", 2193 __func__); 2194 set_bit(ISP_ABORT_NEEDED, 2195 &vha->dpc_flags); 2196 } 2197 } 2198 qla2xxx_wake_dpc(vha); 2199 } 2200 } 2201 2202 } 2203 } 2204 2205 static int 2206 qla8044_minidump_process_control(struct scsi_qla_host *vha, 2207 struct qla8044_minidump_entry_hdr *entry_hdr) 2208 { 2209 struct qla8044_minidump_entry_crb *crb_entry; 2210 uint32_t read_value, opcode, poll_time, addr, index; 2211 uint32_t crb_addr, rval = QLA_SUCCESS; 2212 unsigned long wtime; 2213 struct qla8044_minidump_template_hdr *tmplt_hdr; 2214 int i; 2215 struct qla_hw_data *ha = vha->hw; 2216 2217 ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__); 2218 tmplt_hdr = (struct qla8044_minidump_template_hdr *) 2219 ha->md_tmplt_hdr; 2220 crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr; 2221 2222 crb_addr = crb_entry->addr; 2223 for (i = 0; i < crb_entry->op_count; i++) { 2224 opcode = crb_entry->crb_ctrl.opcode; 2225 2226 if (opcode & QLA82XX_DBG_OPCODE_WR) { 2227 qla8044_wr_reg_indirect(vha, crb_addr, 2228 crb_entry->value_1); 2229 } 2230 2231 if (opcode & QLA82XX_DBG_OPCODE_RW) { 2232 qla8044_rd_reg_indirect(vha, crb_addr, &read_value); 2233 qla8044_wr_reg_indirect(vha, crb_addr, read_value); 2234 } 2235 2236 if (opcode & QLA82XX_DBG_OPCODE_AND) { 2237 qla8044_rd_reg_indirect(vha, crb_addr, &read_value); 2238 read_value &= crb_entry->value_2; 2239 if (opcode & QLA82XX_DBG_OPCODE_OR) { 2240 read_value |= crb_entry->value_3; 2241 opcode &= ~QLA82XX_DBG_OPCODE_OR; 2242 } 2243 qla8044_wr_reg_indirect(vha, crb_addr, read_value); 2244 } 2245 if (opcode & QLA82XX_DBG_OPCODE_OR) { 2246 qla8044_rd_reg_indirect(vha, crb_addr, &read_value); 2247 read_value |= crb_entry->value_3; 2248 qla8044_wr_reg_indirect(vha, crb_addr, read_value); 2249 } 2250 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 2251 poll_time = crb_entry->crb_strd.poll_timeout; 2252 wtime = jiffies + poll_time; 2253 qla8044_rd_reg_indirect(vha, crb_addr, &read_value); 2254 2255 do { 2256 if ((read_value & crb_entry->value_2) == 2257 crb_entry->value_1) { 2258 break; 2259 } else if (time_after_eq(jiffies, wtime)) { 2260 /* capturing dump failed */ 2261 rval = QLA_FUNCTION_FAILED; 2262 break; 2263 } else { 2264 qla8044_rd_reg_indirect(vha, 2265 crb_addr, &read_value); 2266 } 2267 } while (1); 2268 } 2269 2270 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 2271 if (crb_entry->crb_strd.state_index_a) { 2272 index = crb_entry->crb_strd.state_index_a; 2273 addr = tmplt_hdr->saved_state_array[index]; 2274 } else { 2275 addr = crb_addr; 2276 } 2277 2278 qla8044_rd_reg_indirect(vha, addr, &read_value); 2279 index = crb_entry->crb_ctrl.state_index_v; 2280 tmplt_hdr->saved_state_array[index] = read_value; 2281 } 2282 2283 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 2284 if (crb_entry->crb_strd.state_index_a) { 2285 index = crb_entry->crb_strd.state_index_a; 2286 addr = tmplt_hdr->saved_state_array[index]; 2287 } else { 2288 addr = crb_addr; 2289 } 2290 2291 if (crb_entry->crb_ctrl.state_index_v) { 2292 index = crb_entry->crb_ctrl.state_index_v; 2293 read_value = 2294 tmplt_hdr->saved_state_array[index]; 2295 } else { 2296 read_value = crb_entry->value_1; 2297 } 2298 2299 qla8044_wr_reg_indirect(vha, addr, read_value); 2300 } 2301 2302 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 2303 index = crb_entry->crb_ctrl.state_index_v; 2304 read_value = tmplt_hdr->saved_state_array[index]; 2305 read_value <<= crb_entry->crb_ctrl.shl; 2306 read_value >>= crb_entry->crb_ctrl.shr; 2307 if (crb_entry->value_2) 2308 read_value &= crb_entry->value_2; 2309 read_value |= crb_entry->value_3; 2310 read_value += crb_entry->value_1; 2311 tmplt_hdr->saved_state_array[index] = read_value; 2312 } 2313 crb_addr += crb_entry->crb_strd.addr_stride; 2314 } 2315 return rval; 2316 } 2317 2318 static void 2319 qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha, 2320 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2321 { 2322 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 2323 struct qla8044_minidump_entry_crb *crb_hdr; 2324 uint32_t *data_ptr = *d_ptr; 2325 2326 ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__); 2327 crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr; 2328 r_addr = crb_hdr->addr; 2329 r_stride = crb_hdr->crb_strd.addr_stride; 2330 loop_cnt = crb_hdr->op_count; 2331 2332 for (i = 0; i < loop_cnt; i++) { 2333 qla8044_rd_reg_indirect(vha, r_addr, &r_value); 2334 *data_ptr++ = r_addr; 2335 *data_ptr++ = r_value; 2336 r_addr += r_stride; 2337 } 2338 *d_ptr = data_ptr; 2339 } 2340 2341 static int 2342 qla8044_minidump_process_rdmem(struct scsi_qla_host *vha, 2343 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2344 { 2345 uint32_t r_addr, r_value, r_data; 2346 uint32_t i, j, loop_cnt; 2347 struct qla8044_minidump_entry_rdmem *m_hdr; 2348 unsigned long flags; 2349 uint32_t *data_ptr = *d_ptr; 2350 struct qla_hw_data *ha = vha->hw; 2351 2352 ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__); 2353 m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr; 2354 r_addr = m_hdr->read_addr; 2355 loop_cnt = m_hdr->read_data_size/16; 2356 2357 ql_dbg(ql_dbg_p3p, vha, 0xb0f0, 2358 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", 2359 __func__, r_addr, m_hdr->read_data_size); 2360 2361 if (r_addr & 0xf) { 2362 ql_dbg(ql_dbg_p3p, vha, 0xb0f1, 2363 "[%s]: Read addr 0x%x not 16 bytes aligned\n", 2364 __func__, r_addr); 2365 return QLA_FUNCTION_FAILED; 2366 } 2367 2368 if (m_hdr->read_data_size % 16) { 2369 ql_dbg(ql_dbg_p3p, vha, 0xb0f2, 2370 "[%s]: Read data[0x%x] not multiple of 16 bytes\n", 2371 __func__, m_hdr->read_data_size); 2372 return QLA_FUNCTION_FAILED; 2373 } 2374 2375 ql_dbg(ql_dbg_p3p, vha, 0xb0f3, 2376 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 2377 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 2378 2379 write_lock_irqsave(&ha->hw_lock, flags); 2380 for (i = 0; i < loop_cnt; i++) { 2381 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr); 2382 r_value = 0; 2383 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value); 2384 r_value = MIU_TA_CTL_ENABLE; 2385 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value); 2386 r_value = MIU_TA_CTL_START_ENABLE; 2387 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value); 2388 2389 for (j = 0; j < MAX_CTL_CHECK; j++) { 2390 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, 2391 &r_value); 2392 if ((r_value & MIU_TA_CTL_BUSY) == 0) 2393 break; 2394 } 2395 2396 if (j >= MAX_CTL_CHECK) { 2397 write_unlock_irqrestore(&ha->hw_lock, flags); 2398 return QLA_SUCCESS; 2399 } 2400 2401 for (j = 0; j < 4; j++) { 2402 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j], 2403 &r_data); 2404 *data_ptr++ = r_data; 2405 } 2406 2407 r_addr += 16; 2408 } 2409 write_unlock_irqrestore(&ha->hw_lock, flags); 2410 2411 ql_dbg(ql_dbg_p3p, vha, 0xb0f4, 2412 "Leaving fn: %s datacount: 0x%x\n", 2413 __func__, (loop_cnt * 16)); 2414 2415 *d_ptr = data_ptr; 2416 return QLA_SUCCESS; 2417 } 2418 2419 /* ISP83xx flash read for _RDROM _BOARD */ 2420 static uint32_t 2421 qla8044_minidump_process_rdrom(struct scsi_qla_host *vha, 2422 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2423 { 2424 uint32_t fl_addr, u32_count, rval; 2425 struct qla8044_minidump_entry_rdrom *rom_hdr; 2426 uint32_t *data_ptr = *d_ptr; 2427 2428 rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr; 2429 fl_addr = rom_hdr->read_addr; 2430 u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t); 2431 2432 ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n", 2433 __func__, fl_addr, u32_count); 2434 2435 rval = qla8044_lockless_flash_read_u32(vha, fl_addr, 2436 (u8 *)(data_ptr), u32_count); 2437 2438 if (rval != QLA_SUCCESS) { 2439 ql_log(ql_log_fatal, vha, 0xb0f6, 2440 "%s: Flash Read Error,Count=%d\n", __func__, u32_count); 2441 return QLA_FUNCTION_FAILED; 2442 } else { 2443 data_ptr += u32_count; 2444 *d_ptr = data_ptr; 2445 return QLA_SUCCESS; 2446 } 2447 } 2448 2449 static void 2450 qla8044_mark_entry_skipped(struct scsi_qla_host *vha, 2451 struct qla8044_minidump_entry_hdr *entry_hdr, int index) 2452 { 2453 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 2454 2455 ql_log(ql_log_info, vha, 0xb0f7, 2456 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", 2457 vha->host_no, index, entry_hdr->entry_type, 2458 entry_hdr->d_ctrl.entry_capture_mask); 2459 } 2460 2461 static int 2462 qla8044_minidump_process_l2tag(struct scsi_qla_host *vha, 2463 struct qla8044_minidump_entry_hdr *entry_hdr, 2464 uint32_t **d_ptr) 2465 { 2466 uint32_t addr, r_addr, c_addr, t_r_addr; 2467 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 2468 unsigned long p_wait, w_time, p_mask; 2469 uint32_t c_value_w, c_value_r; 2470 struct qla8044_minidump_entry_cache *cache_hdr; 2471 int rval = QLA_FUNCTION_FAILED; 2472 uint32_t *data_ptr = *d_ptr; 2473 2474 ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__); 2475 cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr; 2476 2477 loop_count = cache_hdr->op_count; 2478 r_addr = cache_hdr->read_addr; 2479 c_addr = cache_hdr->control_addr; 2480 c_value_w = cache_hdr->cache_ctrl.write_value; 2481 2482 t_r_addr = cache_hdr->tag_reg_addr; 2483 t_value = cache_hdr->addr_ctrl.init_tag_value; 2484 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 2485 p_wait = cache_hdr->cache_ctrl.poll_wait; 2486 p_mask = cache_hdr->cache_ctrl.poll_mask; 2487 2488 for (i = 0; i < loop_count; i++) { 2489 qla8044_wr_reg_indirect(vha, t_r_addr, t_value); 2490 if (c_value_w) 2491 qla8044_wr_reg_indirect(vha, c_addr, c_value_w); 2492 2493 if (p_mask) { 2494 w_time = jiffies + p_wait; 2495 do { 2496 qla8044_rd_reg_indirect(vha, c_addr, 2497 &c_value_r); 2498 if ((c_value_r & p_mask) == 0) { 2499 break; 2500 } else if (time_after_eq(jiffies, w_time)) { 2501 /* capturing dump failed */ 2502 return rval; 2503 } 2504 } while (1); 2505 } 2506 2507 addr = r_addr; 2508 for (k = 0; k < r_cnt; k++) { 2509 qla8044_rd_reg_indirect(vha, addr, &r_value); 2510 *data_ptr++ = r_value; 2511 addr += cache_hdr->read_ctrl.read_addr_stride; 2512 } 2513 t_value += cache_hdr->addr_ctrl.tag_value_stride; 2514 } 2515 *d_ptr = data_ptr; 2516 return QLA_SUCCESS; 2517 } 2518 2519 static void 2520 qla8044_minidump_process_l1cache(struct scsi_qla_host *vha, 2521 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2522 { 2523 uint32_t addr, r_addr, c_addr, t_r_addr; 2524 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 2525 uint32_t c_value_w; 2526 struct qla8044_minidump_entry_cache *cache_hdr; 2527 uint32_t *data_ptr = *d_ptr; 2528 2529 cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr; 2530 loop_count = cache_hdr->op_count; 2531 r_addr = cache_hdr->read_addr; 2532 c_addr = cache_hdr->control_addr; 2533 c_value_w = cache_hdr->cache_ctrl.write_value; 2534 2535 t_r_addr = cache_hdr->tag_reg_addr; 2536 t_value = cache_hdr->addr_ctrl.init_tag_value; 2537 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 2538 2539 for (i = 0; i < loop_count; i++) { 2540 qla8044_wr_reg_indirect(vha, t_r_addr, t_value); 2541 qla8044_wr_reg_indirect(vha, c_addr, c_value_w); 2542 addr = r_addr; 2543 for (k = 0; k < r_cnt; k++) { 2544 qla8044_rd_reg_indirect(vha, addr, &r_value); 2545 *data_ptr++ = r_value; 2546 addr += cache_hdr->read_ctrl.read_addr_stride; 2547 } 2548 t_value += cache_hdr->addr_ctrl.tag_value_stride; 2549 } 2550 *d_ptr = data_ptr; 2551 } 2552 2553 static void 2554 qla8044_minidump_process_rdocm(struct scsi_qla_host *vha, 2555 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2556 { 2557 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 2558 struct qla8044_minidump_entry_rdocm *ocm_hdr; 2559 uint32_t *data_ptr = *d_ptr; 2560 struct qla_hw_data *ha = vha->hw; 2561 2562 ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__); 2563 2564 ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr; 2565 r_addr = ocm_hdr->read_addr; 2566 r_stride = ocm_hdr->read_addr_stride; 2567 loop_cnt = ocm_hdr->op_count; 2568 2569 ql_dbg(ql_dbg_p3p, vha, 0xb0fa, 2570 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", 2571 __func__, r_addr, r_stride, loop_cnt); 2572 2573 for (i = 0; i < loop_cnt; i++) { 2574 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); 2575 *data_ptr++ = r_value; 2576 r_addr += r_stride; 2577 } 2578 ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n", 2579 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))); 2580 2581 *d_ptr = data_ptr; 2582 } 2583 2584 static void 2585 qla8044_minidump_process_rdmux(struct scsi_qla_host *vha, 2586 struct qla8044_minidump_entry_hdr *entry_hdr, 2587 uint32_t **d_ptr) 2588 { 2589 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value = 0; 2590 struct qla8044_minidump_entry_mux *mux_hdr; 2591 uint32_t *data_ptr = *d_ptr; 2592 2593 ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__); 2594 2595 mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr; 2596 r_addr = mux_hdr->read_addr; 2597 s_addr = mux_hdr->select_addr; 2598 s_stride = mux_hdr->select_value_stride; 2599 s_value = mux_hdr->select_value; 2600 loop_cnt = mux_hdr->op_count; 2601 2602 for (i = 0; i < loop_cnt; i++) { 2603 qla8044_wr_reg_indirect(vha, s_addr, s_value); 2604 qla8044_rd_reg_indirect(vha, r_addr, &r_value); 2605 *data_ptr++ = s_value; 2606 *data_ptr++ = r_value; 2607 s_value += s_stride; 2608 } 2609 *d_ptr = data_ptr; 2610 } 2611 2612 static void 2613 qla8044_minidump_process_queue(struct scsi_qla_host *vha, 2614 struct qla8044_minidump_entry_hdr *entry_hdr, 2615 uint32_t **d_ptr) 2616 { 2617 uint32_t s_addr, r_addr; 2618 uint32_t r_stride, r_value, r_cnt, qid = 0; 2619 uint32_t i, k, loop_cnt; 2620 struct qla8044_minidump_entry_queue *q_hdr; 2621 uint32_t *data_ptr = *d_ptr; 2622 2623 ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__); 2624 q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr; 2625 s_addr = q_hdr->select_addr; 2626 r_cnt = q_hdr->rd_strd.read_addr_cnt; 2627 r_stride = q_hdr->rd_strd.read_addr_stride; 2628 loop_cnt = q_hdr->op_count; 2629 2630 for (i = 0; i < loop_cnt; i++) { 2631 qla8044_wr_reg_indirect(vha, s_addr, qid); 2632 r_addr = q_hdr->read_addr; 2633 for (k = 0; k < r_cnt; k++) { 2634 qla8044_rd_reg_indirect(vha, r_addr, &r_value); 2635 *data_ptr++ = r_value; 2636 r_addr += r_stride; 2637 } 2638 qid += q_hdr->q_strd.queue_id_stride; 2639 } 2640 *d_ptr = data_ptr; 2641 } 2642 2643 /* ISP83xx functions to process new minidump entries... */ 2644 static uint32_t 2645 qla8044_minidump_process_pollrd(struct scsi_qla_host *vha, 2646 struct qla8044_minidump_entry_hdr *entry_hdr, 2647 uint32_t **d_ptr) 2648 { 2649 uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask; 2650 uint16_t s_stride, i; 2651 struct qla8044_minidump_entry_pollrd *pollrd_hdr; 2652 uint32_t *data_ptr = *d_ptr; 2653 2654 pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr; 2655 s_addr = pollrd_hdr->select_addr; 2656 r_addr = pollrd_hdr->read_addr; 2657 s_value = pollrd_hdr->select_value; 2658 s_stride = pollrd_hdr->select_value_stride; 2659 2660 poll_wait = pollrd_hdr->poll_wait; 2661 poll_mask = pollrd_hdr->poll_mask; 2662 2663 for (i = 0; i < pollrd_hdr->op_count; i++) { 2664 qla8044_wr_reg_indirect(vha, s_addr, s_value); 2665 poll_wait = pollrd_hdr->poll_wait; 2666 while (1) { 2667 qla8044_rd_reg_indirect(vha, s_addr, &r_value); 2668 if ((r_value & poll_mask) != 0) { 2669 break; 2670 } else { 2671 usleep_range(1000, 1100); 2672 if (--poll_wait == 0) { 2673 ql_log(ql_log_fatal, vha, 0xb0fe, 2674 "%s: TIMEOUT\n", __func__); 2675 goto error; 2676 } 2677 } 2678 } 2679 qla8044_rd_reg_indirect(vha, r_addr, &r_value); 2680 *data_ptr++ = s_value; 2681 *data_ptr++ = r_value; 2682 2683 s_value += s_stride; 2684 } 2685 *d_ptr = data_ptr; 2686 return QLA_SUCCESS; 2687 2688 error: 2689 return QLA_FUNCTION_FAILED; 2690 } 2691 2692 static void 2693 qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha, 2694 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2695 { 2696 uint32_t sel_val1, sel_val2, t_sel_val, data, i; 2697 uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr; 2698 struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr; 2699 uint32_t *data_ptr = *d_ptr; 2700 2701 rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr; 2702 sel_val1 = rdmux2_hdr->select_value_1; 2703 sel_val2 = rdmux2_hdr->select_value_2; 2704 sel_addr1 = rdmux2_hdr->select_addr_1; 2705 sel_addr2 = rdmux2_hdr->select_addr_2; 2706 sel_val_mask = rdmux2_hdr->select_value_mask; 2707 read_addr = rdmux2_hdr->read_addr; 2708 2709 for (i = 0; i < rdmux2_hdr->op_count; i++) { 2710 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1); 2711 t_sel_val = sel_val1 & sel_val_mask; 2712 *data_ptr++ = t_sel_val; 2713 2714 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val); 2715 qla8044_rd_reg_indirect(vha, read_addr, &data); 2716 2717 *data_ptr++ = data; 2718 2719 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2); 2720 t_sel_val = sel_val2 & sel_val_mask; 2721 *data_ptr++ = t_sel_val; 2722 2723 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val); 2724 qla8044_rd_reg_indirect(vha, read_addr, &data); 2725 2726 *data_ptr++ = data; 2727 2728 sel_val1 += rdmux2_hdr->select_value_stride; 2729 sel_val2 += rdmux2_hdr->select_value_stride; 2730 } 2731 2732 *d_ptr = data_ptr; 2733 } 2734 2735 static uint32_t 2736 qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha, 2737 struct qla8044_minidump_entry_hdr *entry_hdr, 2738 uint32_t **d_ptr) 2739 { 2740 uint32_t poll_wait, poll_mask, r_value, data; 2741 uint32_t addr_1, addr_2, value_1, value_2; 2742 struct qla8044_minidump_entry_pollrdmwr *poll_hdr; 2743 uint32_t *data_ptr = *d_ptr; 2744 2745 poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr; 2746 addr_1 = poll_hdr->addr_1; 2747 addr_2 = poll_hdr->addr_2; 2748 value_1 = poll_hdr->value_1; 2749 value_2 = poll_hdr->value_2; 2750 poll_mask = poll_hdr->poll_mask; 2751 2752 qla8044_wr_reg_indirect(vha, addr_1, value_1); 2753 2754 poll_wait = poll_hdr->poll_wait; 2755 while (1) { 2756 qla8044_rd_reg_indirect(vha, addr_1, &r_value); 2757 2758 if ((r_value & poll_mask) != 0) { 2759 break; 2760 } else { 2761 usleep_range(1000, 1100); 2762 if (--poll_wait == 0) { 2763 ql_log(ql_log_fatal, vha, 0xb0ff, 2764 "%s: TIMEOUT\n", __func__); 2765 goto error; 2766 } 2767 } 2768 } 2769 2770 qla8044_rd_reg_indirect(vha, addr_2, &data); 2771 data &= poll_hdr->modify_mask; 2772 qla8044_wr_reg_indirect(vha, addr_2, data); 2773 qla8044_wr_reg_indirect(vha, addr_1, value_2); 2774 2775 poll_wait = poll_hdr->poll_wait; 2776 while (1) { 2777 qla8044_rd_reg_indirect(vha, addr_1, &r_value); 2778 2779 if ((r_value & poll_mask) != 0) { 2780 break; 2781 } else { 2782 usleep_range(1000, 1100); 2783 if (--poll_wait == 0) { 2784 ql_log(ql_log_fatal, vha, 0xb100, 2785 "%s: TIMEOUT2\n", __func__); 2786 goto error; 2787 } 2788 } 2789 } 2790 2791 *data_ptr++ = addr_2; 2792 *data_ptr++ = data; 2793 2794 *d_ptr = data_ptr; 2795 2796 return QLA_SUCCESS; 2797 2798 error: 2799 return QLA_FUNCTION_FAILED; 2800 } 2801 2802 #define ISP8044_PEX_DMA_ENGINE_INDEX 8 2803 #define ISP8044_PEX_DMA_BASE_ADDRESS 0x77320000 2804 #define ISP8044_PEX_DMA_NUM_OFFSET 0x10000UL 2805 #define ISP8044_PEX_DMA_CMD_ADDR_LOW 0x0 2806 #define ISP8044_PEX_DMA_CMD_ADDR_HIGH 0x04 2807 #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL 0x08 2808 2809 #define ISP8044_PEX_DMA_READ_SIZE (16 * 1024) 2810 #define ISP8044_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */ 2811 2812 static int 2813 qla8044_check_dma_engine_state(struct scsi_qla_host *vha) 2814 { 2815 struct qla_hw_data *ha = vha->hw; 2816 int rval = QLA_SUCCESS; 2817 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 2818 uint64_t dma_base_addr = 0; 2819 struct qla8044_minidump_template_hdr *tmplt_hdr = NULL; 2820 2821 tmplt_hdr = ha->md_tmplt_hdr; 2822 dma_eng_num = 2823 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX]; 2824 dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS + 2825 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET); 2826 2827 /* Read the pex-dma's command-status-and-control register. */ 2828 rval = qla8044_rd_reg_indirect(vha, 2829 (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL), 2830 &cmd_sts_and_cntrl); 2831 if (rval) 2832 return QLA_FUNCTION_FAILED; 2833 2834 /* Check if requested pex-dma engine is available. */ 2835 if (cmd_sts_and_cntrl & BIT_31) 2836 return QLA_SUCCESS; 2837 2838 return QLA_FUNCTION_FAILED; 2839 } 2840 2841 static int 2842 qla8044_start_pex_dma(struct scsi_qla_host *vha, 2843 struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr) 2844 { 2845 struct qla_hw_data *ha = vha->hw; 2846 int rval = QLA_SUCCESS, wait = 0; 2847 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 2848 uint64_t dma_base_addr = 0; 2849 struct qla8044_minidump_template_hdr *tmplt_hdr = NULL; 2850 2851 tmplt_hdr = ha->md_tmplt_hdr; 2852 dma_eng_num = 2853 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX]; 2854 dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS + 2855 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET); 2856 2857 rval = qla8044_wr_reg_indirect(vha, 2858 dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW, 2859 m_hdr->desc_card_addr); 2860 if (rval) 2861 goto error_exit; 2862 2863 rval = qla8044_wr_reg_indirect(vha, 2864 dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0); 2865 if (rval) 2866 goto error_exit; 2867 2868 rval = qla8044_wr_reg_indirect(vha, 2869 dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL, 2870 m_hdr->start_dma_cmd); 2871 if (rval) 2872 goto error_exit; 2873 2874 /* Wait for dma operation to complete. */ 2875 for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) { 2876 rval = qla8044_rd_reg_indirect(vha, 2877 (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL), 2878 &cmd_sts_and_cntrl); 2879 if (rval) 2880 goto error_exit; 2881 2882 if ((cmd_sts_and_cntrl & BIT_1) == 0) 2883 break; 2884 2885 udelay(10); 2886 } 2887 2888 /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */ 2889 if (wait >= ISP8044_PEX_DMA_MAX_WAIT) { 2890 rval = QLA_FUNCTION_FAILED; 2891 goto error_exit; 2892 } 2893 2894 error_exit: 2895 return rval; 2896 } 2897 2898 static int 2899 qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha, 2900 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2901 { 2902 struct qla_hw_data *ha = vha->hw; 2903 int rval = QLA_SUCCESS; 2904 struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL; 2905 uint32_t chunk_size, read_size; 2906 uint8_t *data_ptr = (uint8_t *)*d_ptr; 2907 void *rdmem_buffer = NULL; 2908 dma_addr_t rdmem_dma; 2909 struct qla8044_pex_dma_descriptor dma_desc; 2910 2911 rval = qla8044_check_dma_engine_state(vha); 2912 if (rval != QLA_SUCCESS) { 2913 ql_dbg(ql_dbg_p3p, vha, 0xb147, 2914 "DMA engine not available. Fallback to rdmem-read.\n"); 2915 return QLA_FUNCTION_FAILED; 2916 } 2917 2918 m_hdr = (void *)entry_hdr; 2919 2920 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, 2921 ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL); 2922 if (!rdmem_buffer) { 2923 ql_dbg(ql_dbg_p3p, vha, 0xb148, 2924 "Unable to allocate rdmem dma buffer\n"); 2925 return QLA_FUNCTION_FAILED; 2926 } 2927 2928 /* Prepare pex-dma descriptor to be written to MS memory. */ 2929 /* dma-desc-cmd layout: 2930 * 0-3: dma-desc-cmd 0-3 2931 * 4-7: pcid function number 2932 * 8-15: dma-desc-cmd 8-15 2933 * dma_bus_addr: dma buffer address 2934 * cmd.read_data_size: amount of data-chunk to be read. 2935 */ 2936 dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f); 2937 dma_desc.cmd.dma_desc_cmd |= 2938 ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4); 2939 2940 dma_desc.dma_bus_addr = rdmem_dma; 2941 dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE; 2942 read_size = 0; 2943 2944 /* 2945 * Perform rdmem operation using pex-dma. 2946 * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE. 2947 */ 2948 while (read_size < m_hdr->read_data_size) { 2949 if (m_hdr->read_data_size - read_size < 2950 ISP8044_PEX_DMA_READ_SIZE) { 2951 chunk_size = (m_hdr->read_data_size - read_size); 2952 dma_desc.cmd.read_data_size = chunk_size; 2953 } 2954 2955 dma_desc.src_addr = m_hdr->read_addr + read_size; 2956 2957 /* Prepare: Write pex-dma descriptor to MS memory. */ 2958 rval = qla8044_ms_mem_write_128b(vha, 2959 m_hdr->desc_card_addr, (uint32_t *)&dma_desc, 2960 (sizeof(struct qla8044_pex_dma_descriptor)/16)); 2961 if (rval) { 2962 ql_log(ql_log_warn, vha, 0xb14a, 2963 "%s: Error writing rdmem-dma-init to MS !!!\n", 2964 __func__); 2965 goto error_exit; 2966 } 2967 ql_dbg(ql_dbg_p3p, vha, 0xb14b, 2968 "%s: Dma-descriptor: Instruct for rdmem dma " 2969 "(chunk_size 0x%x).\n", __func__, chunk_size); 2970 2971 /* Execute: Start pex-dma operation. */ 2972 rval = qla8044_start_pex_dma(vha, m_hdr); 2973 if (rval) 2974 goto error_exit; 2975 2976 memcpy(data_ptr, rdmem_buffer, chunk_size); 2977 data_ptr += chunk_size; 2978 read_size += chunk_size; 2979 } 2980 2981 *d_ptr = (uint32_t *)data_ptr; 2982 2983 error_exit: 2984 if (rdmem_buffer) 2985 dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE, 2986 rdmem_buffer, rdmem_dma); 2987 2988 return rval; 2989 } 2990 2991 static uint32_t 2992 qla8044_minidump_process_rddfe(struct scsi_qla_host *vha, 2993 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2994 { 2995 int loop_cnt; 2996 uint32_t addr1, addr2, value, data, temp, wrVal; 2997 uint8_t stride, stride2; 2998 uint16_t count; 2999 uint32_t poll, mask, modify_mask; 3000 uint32_t wait_count = 0; 3001 uint32_t *data_ptr = *d_ptr; 3002 struct qla8044_minidump_entry_rddfe *rddfe; 3003 3004 rddfe = (struct qla8044_minidump_entry_rddfe *) entry_hdr; 3005 3006 addr1 = rddfe->addr_1; 3007 value = rddfe->value; 3008 stride = rddfe->stride; 3009 stride2 = rddfe->stride2; 3010 count = rddfe->count; 3011 3012 poll = rddfe->poll; 3013 mask = rddfe->mask; 3014 modify_mask = rddfe->modify_mask; 3015 3016 addr2 = addr1 + stride; 3017 3018 for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) { 3019 qla8044_wr_reg_indirect(vha, addr1, (0x40000000 | value)); 3020 3021 wait_count = 0; 3022 while (wait_count < poll) { 3023 qla8044_rd_reg_indirect(vha, addr1, &temp); 3024 if ((temp & mask) != 0) 3025 break; 3026 wait_count++; 3027 } 3028 3029 if (wait_count == poll) { 3030 ql_log(ql_log_warn, vha, 0xb153, 3031 "%s: TIMEOUT\n", __func__); 3032 goto error; 3033 } else { 3034 qla8044_rd_reg_indirect(vha, addr2, &temp); 3035 temp = temp & modify_mask; 3036 temp = (temp | ((loop_cnt << 16) | loop_cnt)); 3037 wrVal = ((temp << 16) | temp); 3038 3039 qla8044_wr_reg_indirect(vha, addr2, wrVal); 3040 qla8044_wr_reg_indirect(vha, addr1, value); 3041 3042 wait_count = 0; 3043 while (wait_count < poll) { 3044 qla8044_rd_reg_indirect(vha, addr1, &temp); 3045 if ((temp & mask) != 0) 3046 break; 3047 wait_count++; 3048 } 3049 if (wait_count == poll) { 3050 ql_log(ql_log_warn, vha, 0xb154, 3051 "%s: TIMEOUT\n", __func__); 3052 goto error; 3053 } 3054 3055 qla8044_wr_reg_indirect(vha, addr1, 3056 ((0x40000000 | value) + stride2)); 3057 wait_count = 0; 3058 while (wait_count < poll) { 3059 qla8044_rd_reg_indirect(vha, addr1, &temp); 3060 if ((temp & mask) != 0) 3061 break; 3062 wait_count++; 3063 } 3064 3065 if (wait_count == poll) { 3066 ql_log(ql_log_warn, vha, 0xb155, 3067 "%s: TIMEOUT\n", __func__); 3068 goto error; 3069 } 3070 3071 qla8044_rd_reg_indirect(vha, addr2, &data); 3072 3073 *data_ptr++ = wrVal; 3074 *data_ptr++ = data; 3075 } 3076 3077 } 3078 3079 *d_ptr = data_ptr; 3080 return QLA_SUCCESS; 3081 3082 error: 3083 return -1; 3084 3085 } 3086 3087 static uint32_t 3088 qla8044_minidump_process_rdmdio(struct scsi_qla_host *vha, 3089 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 3090 { 3091 int ret = 0; 3092 uint32_t addr1, addr2, value1, value2, data, selVal; 3093 uint8_t stride1, stride2; 3094 uint32_t addr3, addr4, addr5, addr6, addr7; 3095 uint16_t count, loop_cnt; 3096 uint32_t mask; 3097 uint32_t *data_ptr = *d_ptr; 3098 3099 struct qla8044_minidump_entry_rdmdio *rdmdio; 3100 3101 rdmdio = (struct qla8044_minidump_entry_rdmdio *) entry_hdr; 3102 3103 addr1 = rdmdio->addr_1; 3104 addr2 = rdmdio->addr_2; 3105 value1 = rdmdio->value_1; 3106 stride1 = rdmdio->stride_1; 3107 stride2 = rdmdio->stride_2; 3108 count = rdmdio->count; 3109 3110 mask = rdmdio->mask; 3111 value2 = rdmdio->value_2; 3112 3113 addr3 = addr1 + stride1; 3114 3115 for (loop_cnt = 0; loop_cnt < count; loop_cnt++) { 3116 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2, 3117 addr3, mask); 3118 if (ret == -1) 3119 goto error; 3120 3121 addr4 = addr2 - stride1; 3122 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr4, 3123 value2); 3124 if (ret == -1) 3125 goto error; 3126 3127 addr5 = addr2 - (2 * stride1); 3128 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr5, 3129 value1); 3130 if (ret == -1) 3131 goto error; 3132 3133 addr6 = addr2 - (3 * stride1); 3134 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, 3135 addr6, 0x2); 3136 if (ret == -1) 3137 goto error; 3138 3139 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2, 3140 addr3, mask); 3141 if (ret == -1) 3142 goto error; 3143 3144 addr7 = addr2 - (4 * stride1); 3145 data = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr7); 3146 if (data == -1) 3147 goto error; 3148 3149 selVal = (value2 << 18) | (value1 << 2) | 2; 3150 3151 stride2 = rdmdio->stride_2; 3152 *data_ptr++ = selVal; 3153 *data_ptr++ = data; 3154 3155 value1 = value1 + stride2; 3156 *d_ptr = data_ptr; 3157 } 3158 3159 return 0; 3160 3161 error: 3162 return -1; 3163 } 3164 3165 static uint32_t qla8044_minidump_process_pollwr(struct scsi_qla_host *vha, 3166 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 3167 { 3168 uint32_t addr1, addr2, value1, value2, poll, r_value; 3169 uint32_t wait_count = 0; 3170 struct qla8044_minidump_entry_pollwr *pollwr_hdr; 3171 3172 pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr; 3173 addr1 = pollwr_hdr->addr_1; 3174 addr2 = pollwr_hdr->addr_2; 3175 value1 = pollwr_hdr->value_1; 3176 value2 = pollwr_hdr->value_2; 3177 3178 poll = pollwr_hdr->poll; 3179 3180 while (wait_count < poll) { 3181 qla8044_rd_reg_indirect(vha, addr1, &r_value); 3182 3183 if ((r_value & poll) != 0) 3184 break; 3185 wait_count++; 3186 } 3187 3188 if (wait_count == poll) { 3189 ql_log(ql_log_warn, vha, 0xb156, "%s: TIMEOUT\n", __func__); 3190 goto error; 3191 } 3192 3193 qla8044_wr_reg_indirect(vha, addr2, value2); 3194 qla8044_wr_reg_indirect(vha, addr1, value1); 3195 3196 wait_count = 0; 3197 while (wait_count < poll) { 3198 qla8044_rd_reg_indirect(vha, addr1, &r_value); 3199 3200 if ((r_value & poll) != 0) 3201 break; 3202 wait_count++; 3203 } 3204 3205 return QLA_SUCCESS; 3206 3207 error: 3208 return -1; 3209 } 3210 3211 /* 3212 * 3213 * qla8044_collect_md_data - Retrieve firmware minidump data. 3214 * @ha: pointer to adapter structure 3215 **/ 3216 int 3217 qla8044_collect_md_data(struct scsi_qla_host *vha) 3218 { 3219 int num_entry_hdr = 0; 3220 struct qla8044_minidump_entry_hdr *entry_hdr; 3221 struct qla8044_minidump_template_hdr *tmplt_hdr; 3222 uint32_t *data_ptr; 3223 uint32_t data_collected = 0, f_capture_mask; 3224 int i, rval = QLA_FUNCTION_FAILED; 3225 uint64_t now; 3226 uint32_t timestamp, idc_control; 3227 struct qla_hw_data *ha = vha->hw; 3228 3229 if (!ha->md_dump) { 3230 ql_log(ql_log_info, vha, 0xb101, 3231 "%s(%ld) No buffer to dump\n", 3232 __func__, vha->host_no); 3233 return rval; 3234 } 3235 3236 if (ha->fw_dumped) { 3237 ql_log(ql_log_warn, vha, 0xb10d, 3238 "Firmware has been previously dumped (%p) " 3239 "-- ignoring request.\n", ha->fw_dump); 3240 goto md_failed; 3241 } 3242 3243 ha->fw_dumped = false; 3244 3245 if (!ha->md_tmplt_hdr || !ha->md_dump) { 3246 ql_log(ql_log_warn, vha, 0xb10e, 3247 "Memory not allocated for minidump capture\n"); 3248 goto md_failed; 3249 } 3250 3251 qla8044_idc_lock(ha); 3252 idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 3253 if (idc_control & GRACEFUL_RESET_BIT1) { 3254 ql_log(ql_log_warn, vha, 0xb112, 3255 "Forced reset from application, " 3256 "ignore minidump capture\n"); 3257 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, 3258 (idc_control & ~GRACEFUL_RESET_BIT1)); 3259 qla8044_idc_unlock(ha); 3260 3261 goto md_failed; 3262 } 3263 qla8044_idc_unlock(ha); 3264 3265 if (qla82xx_validate_template_chksum(vha)) { 3266 ql_log(ql_log_info, vha, 0xb109, 3267 "Template checksum validation error\n"); 3268 goto md_failed; 3269 } 3270 3271 tmplt_hdr = (struct qla8044_minidump_template_hdr *) 3272 ha->md_tmplt_hdr; 3273 data_ptr = (uint32_t *)((uint8_t *)ha->md_dump); 3274 num_entry_hdr = tmplt_hdr->num_of_entries; 3275 3276 ql_dbg(ql_dbg_p3p, vha, 0xb11a, 3277 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 3278 3279 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 3280 3281 /* Validate whether required debug level is set */ 3282 if ((f_capture_mask & 0x3) != 0x3) { 3283 ql_log(ql_log_warn, vha, 0xb10f, 3284 "Minimum required capture mask[0x%x] level not set\n", 3285 f_capture_mask); 3286 3287 } 3288 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 3289 ql_log(ql_log_info, vha, 0xb102, 3290 "[%s]: starting data ptr: %p\n", 3291 __func__, data_ptr); 3292 ql_log(ql_log_info, vha, 0xb10b, 3293 "[%s]: no of entry headers in Template: 0x%x\n", 3294 __func__, num_entry_hdr); 3295 ql_log(ql_log_info, vha, 0xb10c, 3296 "[%s]: Total_data_size 0x%x, %d obtained\n", 3297 __func__, ha->md_dump_size, ha->md_dump_size); 3298 3299 /* Update current timestamp before taking dump */ 3300 now = get_jiffies_64(); 3301 timestamp = (u32)(jiffies_to_msecs(now) / 1000); 3302 tmplt_hdr->driver_timestamp = timestamp; 3303 3304 entry_hdr = (struct qla8044_minidump_entry_hdr *) 3305 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 3306 tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] = 3307 tmplt_hdr->ocm_window_reg[ha->portnum]; 3308 3309 /* Walk through the entry headers - validate/perform required action */ 3310 for (i = 0; i < num_entry_hdr; i++) { 3311 if (data_collected > ha->md_dump_size) { 3312 ql_log(ql_log_info, vha, 0xb103, 3313 "Data collected: [0x%x], " 3314 "Total Dump size: [0x%x]\n", 3315 data_collected, ha->md_dump_size); 3316 return rval; 3317 } 3318 3319 if (!(entry_hdr->d_ctrl.entry_capture_mask & 3320 ql2xmdcapmask)) { 3321 entry_hdr->d_ctrl.driver_flags |= 3322 QLA82XX_DBG_SKIPPED_FLAG; 3323 goto skip_nxt_entry; 3324 } 3325 3326 ql_dbg(ql_dbg_p3p, vha, 0xb104, 3327 "Data collected: [0x%x], Dump size left:[0x%x]\n", 3328 data_collected, 3329 (ha->md_dump_size - data_collected)); 3330 3331 /* Decode the entry type and take required action to capture 3332 * debug data 3333 */ 3334 switch (entry_hdr->entry_type) { 3335 case QLA82XX_RDEND: 3336 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3337 break; 3338 case QLA82XX_CNTRL: 3339 rval = qla8044_minidump_process_control(vha, 3340 entry_hdr); 3341 if (rval != QLA_SUCCESS) { 3342 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3343 goto md_failed; 3344 } 3345 break; 3346 case QLA82XX_RDCRB: 3347 qla8044_minidump_process_rdcrb(vha, 3348 entry_hdr, &data_ptr); 3349 break; 3350 case QLA82XX_RDMEM: 3351 rval = qla8044_minidump_pex_dma_read(vha, 3352 entry_hdr, &data_ptr); 3353 if (rval != QLA_SUCCESS) { 3354 rval = qla8044_minidump_process_rdmem(vha, 3355 entry_hdr, &data_ptr); 3356 if (rval != QLA_SUCCESS) { 3357 qla8044_mark_entry_skipped(vha, 3358 entry_hdr, i); 3359 goto md_failed; 3360 } 3361 } 3362 break; 3363 case QLA82XX_BOARD: 3364 case QLA82XX_RDROM: 3365 rval = qla8044_minidump_process_rdrom(vha, 3366 entry_hdr, &data_ptr); 3367 if (rval != QLA_SUCCESS) { 3368 qla8044_mark_entry_skipped(vha, 3369 entry_hdr, i); 3370 } 3371 break; 3372 case QLA82XX_L2DTG: 3373 case QLA82XX_L2ITG: 3374 case QLA82XX_L2DAT: 3375 case QLA82XX_L2INS: 3376 rval = qla8044_minidump_process_l2tag(vha, 3377 entry_hdr, &data_ptr); 3378 if (rval != QLA_SUCCESS) { 3379 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3380 goto md_failed; 3381 } 3382 break; 3383 case QLA8044_L1DTG: 3384 case QLA8044_L1ITG: 3385 case QLA82XX_L1DAT: 3386 case QLA82XX_L1INS: 3387 qla8044_minidump_process_l1cache(vha, 3388 entry_hdr, &data_ptr); 3389 break; 3390 case QLA82XX_RDOCM: 3391 qla8044_minidump_process_rdocm(vha, 3392 entry_hdr, &data_ptr); 3393 break; 3394 case QLA82XX_RDMUX: 3395 qla8044_minidump_process_rdmux(vha, 3396 entry_hdr, &data_ptr); 3397 break; 3398 case QLA82XX_QUEUE: 3399 qla8044_minidump_process_queue(vha, 3400 entry_hdr, &data_ptr); 3401 break; 3402 case QLA8044_POLLRD: 3403 rval = qla8044_minidump_process_pollrd(vha, 3404 entry_hdr, &data_ptr); 3405 if (rval != QLA_SUCCESS) 3406 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3407 break; 3408 case QLA8044_RDMUX2: 3409 qla8044_minidump_process_rdmux2(vha, 3410 entry_hdr, &data_ptr); 3411 break; 3412 case QLA8044_POLLRDMWR: 3413 rval = qla8044_minidump_process_pollrdmwr(vha, 3414 entry_hdr, &data_ptr); 3415 if (rval != QLA_SUCCESS) 3416 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3417 break; 3418 case QLA8044_RDDFE: 3419 rval = qla8044_minidump_process_rddfe(vha, entry_hdr, 3420 &data_ptr); 3421 if (rval != QLA_SUCCESS) 3422 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3423 break; 3424 case QLA8044_RDMDIO: 3425 rval = qla8044_minidump_process_rdmdio(vha, entry_hdr, 3426 &data_ptr); 3427 if (rval != QLA_SUCCESS) 3428 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3429 break; 3430 case QLA8044_POLLWR: 3431 rval = qla8044_minidump_process_pollwr(vha, entry_hdr, 3432 &data_ptr); 3433 if (rval != QLA_SUCCESS) 3434 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3435 break; 3436 case QLA82XX_RDNOP: 3437 default: 3438 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3439 break; 3440 } 3441 3442 data_collected = (uint8_t *)data_ptr - 3443 (uint8_t *)((uint8_t *)ha->md_dump); 3444 skip_nxt_entry: 3445 /* 3446 * next entry in the template 3447 */ 3448 entry_hdr = (struct qla8044_minidump_entry_hdr *) 3449 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 3450 } 3451 3452 if (data_collected != ha->md_dump_size) { 3453 ql_log(ql_log_info, vha, 0xb105, 3454 "Dump data mismatch: Data collected: " 3455 "[0x%x], total_data_size:[0x%x]\n", 3456 data_collected, ha->md_dump_size); 3457 rval = QLA_FUNCTION_FAILED; 3458 goto md_failed; 3459 } 3460 3461 ql_log(ql_log_info, vha, 0xb110, 3462 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 3463 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 3464 ha->fw_dumped = true; 3465 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 3466 3467 3468 ql_log(ql_log_info, vha, 0xb106, 3469 "Leaving fn: %s Last entry: 0x%x\n", 3470 __func__, i); 3471 md_failed: 3472 return rval; 3473 } 3474 3475 void 3476 qla8044_get_minidump(struct scsi_qla_host *vha) 3477 { 3478 struct qla_hw_data *ha = vha->hw; 3479 3480 if (!qla8044_collect_md_data(vha)) { 3481 ha->fw_dumped = true; 3482 ha->prev_minidump_failed = 0; 3483 } else { 3484 ql_log(ql_log_fatal, vha, 0xb0db, 3485 "%s: Unable to collect minidump\n", 3486 __func__); 3487 ha->prev_minidump_failed = 1; 3488 } 3489 } 3490 3491 static int 3492 qla8044_poll_flash_status_reg(struct scsi_qla_host *vha) 3493 { 3494 uint32_t flash_status; 3495 int retries = QLA8044_FLASH_READ_RETRY_COUNT; 3496 int ret_val = QLA_SUCCESS; 3497 3498 while (retries--) { 3499 ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS, 3500 &flash_status); 3501 if (ret_val) { 3502 ql_log(ql_log_warn, vha, 0xb13c, 3503 "%s: Failed to read FLASH_STATUS reg.\n", 3504 __func__); 3505 break; 3506 } 3507 if ((flash_status & QLA8044_FLASH_STATUS_READY) == 3508 QLA8044_FLASH_STATUS_READY) 3509 break; 3510 msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY); 3511 } 3512 3513 if (!retries) 3514 ret_val = QLA_FUNCTION_FAILED; 3515 3516 return ret_val; 3517 } 3518 3519 static int 3520 qla8044_write_flash_status_reg(struct scsi_qla_host *vha, 3521 uint32_t data) 3522 { 3523 int ret_val = QLA_SUCCESS; 3524 uint32_t cmd; 3525 3526 cmd = vha->hw->fdt_wrt_sts_reg_cmd; 3527 3528 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 3529 QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd); 3530 if (ret_val) { 3531 ql_log(ql_log_warn, vha, 0xb125, 3532 "%s: Failed to write to FLASH_ADDR.\n", __func__); 3533 goto exit_func; 3534 } 3535 3536 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data); 3537 if (ret_val) { 3538 ql_log(ql_log_warn, vha, 0xb126, 3539 "%s: Failed to write to FLASH_WRDATA.\n", __func__); 3540 goto exit_func; 3541 } 3542 3543 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 3544 QLA8044_FLASH_SECOND_ERASE_MS_VAL); 3545 if (ret_val) { 3546 ql_log(ql_log_warn, vha, 0xb127, 3547 "%s: Failed to write to FLASH_CONTROL.\n", __func__); 3548 goto exit_func; 3549 } 3550 3551 ret_val = qla8044_poll_flash_status_reg(vha); 3552 if (ret_val) 3553 ql_log(ql_log_warn, vha, 0xb128, 3554 "%s: Error polling flash status reg.\n", __func__); 3555 3556 exit_func: 3557 return ret_val; 3558 } 3559 3560 /* 3561 * This function assumes that the flash lock is held. 3562 */ 3563 static int 3564 qla8044_unprotect_flash(scsi_qla_host_t *vha) 3565 { 3566 int ret_val; 3567 struct qla_hw_data *ha = vha->hw; 3568 3569 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable); 3570 if (ret_val) 3571 ql_log(ql_log_warn, vha, 0xb139, 3572 "%s: Write flash status failed.\n", __func__); 3573 3574 return ret_val; 3575 } 3576 3577 /* 3578 * This function assumes that the flash lock is held. 3579 */ 3580 static int 3581 qla8044_protect_flash(scsi_qla_host_t *vha) 3582 { 3583 int ret_val; 3584 struct qla_hw_data *ha = vha->hw; 3585 3586 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable); 3587 if (ret_val) 3588 ql_log(ql_log_warn, vha, 0xb13b, 3589 "%s: Write flash status failed.\n", __func__); 3590 3591 return ret_val; 3592 } 3593 3594 3595 static int 3596 qla8044_erase_flash_sector(struct scsi_qla_host *vha, 3597 uint32_t sector_start_addr) 3598 { 3599 uint32_t reversed_addr; 3600 int ret_val = QLA_SUCCESS; 3601 3602 ret_val = qla8044_poll_flash_status_reg(vha); 3603 if (ret_val) { 3604 ql_log(ql_log_warn, vha, 0xb12e, 3605 "%s: Poll flash status after erase failed..\n", __func__); 3606 } 3607 3608 reversed_addr = (((sector_start_addr & 0xFF) << 16) | 3609 (sector_start_addr & 0xFF00) | 3610 ((sector_start_addr & 0xFF0000) >> 16)); 3611 3612 ret_val = qla8044_wr_reg_indirect(vha, 3613 QLA8044_FLASH_WRDATA, reversed_addr); 3614 if (ret_val) { 3615 ql_log(ql_log_warn, vha, 0xb12f, 3616 "%s: Failed to write to FLASH_WRDATA.\n", __func__); 3617 } 3618 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 3619 QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd); 3620 if (ret_val) { 3621 ql_log(ql_log_warn, vha, 0xb130, 3622 "%s: Failed to write to FLASH_ADDR.\n", __func__); 3623 } 3624 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 3625 QLA8044_FLASH_LAST_ERASE_MS_VAL); 3626 if (ret_val) { 3627 ql_log(ql_log_warn, vha, 0xb131, 3628 "%s: Failed write to FLASH_CONTROL.\n", __func__); 3629 } 3630 ret_val = qla8044_poll_flash_status_reg(vha); 3631 if (ret_val) { 3632 ql_log(ql_log_warn, vha, 0xb132, 3633 "%s: Poll flash status failed.\n", __func__); 3634 } 3635 3636 3637 return ret_val; 3638 } 3639 3640 /* 3641 * qla8044_flash_write_u32 - Write data to flash 3642 * 3643 * @ha : Pointer to adapter structure 3644 * addr : Flash address to write to 3645 * p_data : Data to be written 3646 * 3647 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 3648 * 3649 * NOTE: Lock should be held on entry 3650 */ 3651 static int 3652 qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr, 3653 uint32_t *p_data) 3654 { 3655 int ret_val = QLA_SUCCESS; 3656 3657 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 3658 0x00800000 | (addr >> 2)); 3659 if (ret_val) { 3660 ql_log(ql_log_warn, vha, 0xb134, 3661 "%s: Failed write to FLASH_ADDR.\n", __func__); 3662 goto exit_func; 3663 } 3664 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data); 3665 if (ret_val) { 3666 ql_log(ql_log_warn, vha, 0xb135, 3667 "%s: Failed write to FLASH_WRDATA.\n", __func__); 3668 goto exit_func; 3669 } 3670 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D); 3671 if (ret_val) { 3672 ql_log(ql_log_warn, vha, 0xb136, 3673 "%s: Failed write to FLASH_CONTROL.\n", __func__); 3674 goto exit_func; 3675 } 3676 ret_val = qla8044_poll_flash_status_reg(vha); 3677 if (ret_val) { 3678 ql_log(ql_log_warn, vha, 0xb137, 3679 "%s: Poll flash status failed.\n", __func__); 3680 } 3681 3682 exit_func: 3683 return ret_val; 3684 } 3685 3686 static int 3687 qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr, 3688 uint32_t faddr, uint32_t dwords) 3689 { 3690 int ret = QLA_FUNCTION_FAILED; 3691 uint32_t spi_val; 3692 3693 if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS || 3694 dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) { 3695 ql_dbg(ql_dbg_user, vha, 0xb123, 3696 "Got unsupported dwords = 0x%x.\n", 3697 dwords); 3698 return QLA_FUNCTION_FAILED; 3699 } 3700 3701 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val); 3702 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, 3703 spi_val | QLA8044_FLASH_SPI_CTL); 3704 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 3705 QLA8044_FLASH_FIRST_TEMP_VAL); 3706 3707 /* First DWORD write to FLASH_WRDATA */ 3708 ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, 3709 *dwptr++); 3710 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 3711 QLA8044_FLASH_FIRST_MS_PATTERN); 3712 3713 ret = qla8044_poll_flash_status_reg(vha); 3714 if (ret) { 3715 ql_log(ql_log_warn, vha, 0xb124, 3716 "%s: Failed.\n", __func__); 3717 goto exit_func; 3718 } 3719 3720 dwords--; 3721 3722 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 3723 QLA8044_FLASH_SECOND_TEMP_VAL); 3724 3725 3726 /* Second to N-1 DWORDS writes */ 3727 while (dwords != 1) { 3728 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++); 3729 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 3730 QLA8044_FLASH_SECOND_MS_PATTERN); 3731 ret = qla8044_poll_flash_status_reg(vha); 3732 if (ret) { 3733 ql_log(ql_log_warn, vha, 0xb129, 3734 "%s: Failed.\n", __func__); 3735 goto exit_func; 3736 } 3737 dwords--; 3738 } 3739 3740 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 3741 QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2)); 3742 3743 /* Last DWORD write */ 3744 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++); 3745 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 3746 QLA8044_FLASH_LAST_MS_PATTERN); 3747 ret = qla8044_poll_flash_status_reg(vha); 3748 if (ret) { 3749 ql_log(ql_log_warn, vha, 0xb12a, 3750 "%s: Failed.\n", __func__); 3751 goto exit_func; 3752 } 3753 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val); 3754 3755 if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) { 3756 ql_log(ql_log_warn, vha, 0xb12b, 3757 "%s: Failed.\n", __func__); 3758 spi_val = 0; 3759 /* Operation failed, clear error bit. */ 3760 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, 3761 &spi_val); 3762 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, 3763 spi_val | QLA8044_FLASH_SPI_CTL); 3764 } 3765 exit_func: 3766 return ret; 3767 } 3768 3769 static int 3770 qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr, 3771 uint32_t faddr, uint32_t dwords) 3772 { 3773 int ret = QLA_FUNCTION_FAILED; 3774 uint32_t liter; 3775 3776 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 3777 ret = qla8044_flash_write_u32(vha, faddr, dwptr); 3778 if (ret) { 3779 ql_dbg(ql_dbg_p3p, vha, 0xb141, 3780 "%s: flash address=%x data=%x.\n", __func__, 3781 faddr, *dwptr); 3782 break; 3783 } 3784 } 3785 3786 return ret; 3787 } 3788 3789 int 3790 qla8044_write_optrom_data(struct scsi_qla_host *vha, void *buf, 3791 uint32_t offset, uint32_t length) 3792 { 3793 int rval = QLA_FUNCTION_FAILED, i, burst_iter_count; 3794 int dword_count, erase_sec_count; 3795 uint32_t erase_offset; 3796 uint8_t *p_cache, *p_src; 3797 3798 erase_offset = offset; 3799 3800 p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL); 3801 if (!p_cache) 3802 return QLA_FUNCTION_FAILED; 3803 3804 memcpy(p_cache, buf, length); 3805 p_src = p_cache; 3806 dword_count = length / sizeof(uint32_t); 3807 /* Since the offset and legth are sector aligned, it will be always 3808 * multiple of burst_iter_count (64) 3809 */ 3810 burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS; 3811 erase_sec_count = length / QLA8044_SECTOR_SIZE; 3812 3813 /* Suspend HBA. */ 3814 scsi_block_requests(vha->host); 3815 /* Lock and enable write for whole operation. */ 3816 qla8044_flash_lock(vha); 3817 qla8044_unprotect_flash(vha); 3818 3819 /* Erasing the sectors */ 3820 for (i = 0; i < erase_sec_count; i++) { 3821 rval = qla8044_erase_flash_sector(vha, erase_offset); 3822 ql_dbg(ql_dbg_user, vha, 0xb138, 3823 "Done erase of sector=0x%x.\n", 3824 erase_offset); 3825 if (rval) { 3826 ql_log(ql_log_warn, vha, 0xb121, 3827 "Failed to erase the sector having address: " 3828 "0x%x.\n", erase_offset); 3829 goto out; 3830 } 3831 erase_offset += QLA8044_SECTOR_SIZE; 3832 } 3833 ql_dbg(ql_dbg_user, vha, 0xb13f, 3834 "Got write for addr = 0x%x length=0x%x.\n", 3835 offset, length); 3836 3837 for (i = 0; i < burst_iter_count; i++) { 3838 3839 /* Go with write. */ 3840 rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src, 3841 offset, QLA8044_MAX_OPTROM_BURST_DWORDS); 3842 if (rval) { 3843 /* Buffer Mode failed skip to dword mode */ 3844 ql_log(ql_log_warn, vha, 0xb122, 3845 "Failed to write flash in buffer mode, " 3846 "Reverting to slow-write.\n"); 3847 rval = qla8044_write_flash_dword_mode(vha, 3848 (uint32_t *)p_src, offset, 3849 QLA8044_MAX_OPTROM_BURST_DWORDS); 3850 } 3851 p_src += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS; 3852 offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS; 3853 } 3854 ql_dbg(ql_dbg_user, vha, 0xb133, 3855 "Done writing.\n"); 3856 3857 out: 3858 qla8044_protect_flash(vha); 3859 qla8044_flash_unlock(vha); 3860 scsi_unblock_requests(vha->host); 3861 kfree(p_cache); 3862 3863 return rval; 3864 } 3865 3866 #define LEG_INT_PTR_B31 (1 << 31) 3867 #define LEG_INT_PTR_B30 (1 << 30) 3868 #define PF_BITS_MASK (0xF << 16) 3869 /** 3870 * qla8044_intr_handler() - Process interrupts for the ISP8044 3871 * @irq: interrupt number 3872 * @dev_id: SCSI driver HA context 3873 * 3874 * Called by system whenever the host adapter generates an interrupt. 3875 * 3876 * Returns handled flag. 3877 */ 3878 irqreturn_t 3879 qla8044_intr_handler(int irq, void *dev_id) 3880 { 3881 scsi_qla_host_t *vha; 3882 struct qla_hw_data *ha; 3883 struct rsp_que *rsp; 3884 struct device_reg_82xx __iomem *reg; 3885 int status = 0; 3886 unsigned long flags; 3887 unsigned long iter; 3888 uint32_t stat; 3889 uint16_t mb[8]; 3890 uint32_t leg_int_ptr = 0, pf_bit; 3891 3892 rsp = (struct rsp_que *) dev_id; 3893 if (!rsp) { 3894 ql_log(ql_log_info, NULL, 0xb143, 3895 "%s(): NULL response queue pointer\n", __func__); 3896 return IRQ_NONE; 3897 } 3898 ha = rsp->hw; 3899 vha = pci_get_drvdata(ha->pdev); 3900 3901 if (unlikely(pci_channel_offline(ha->pdev))) 3902 return IRQ_HANDLED; 3903 3904 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET); 3905 3906 /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */ 3907 if (!(leg_int_ptr & (LEG_INT_PTR_B31))) { 3908 ql_dbg(ql_dbg_p3p, vha, 0xb144, 3909 "%s: Legacy Interrupt Bit 31 not set, " 3910 "spurious interrupt!\n", __func__); 3911 return IRQ_NONE; 3912 } 3913 3914 pf_bit = ha->portnum << 16; 3915 /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */ 3916 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) { 3917 ql_dbg(ql_dbg_p3p, vha, 0xb145, 3918 "%s: Incorrect function ID 0x%x in " 3919 "legacy interrupt register, " 3920 "ha->pf_bit = 0x%x\n", __func__, 3921 (leg_int_ptr & (PF_BITS_MASK)), pf_bit); 3922 return IRQ_NONE; 3923 } 3924 3925 /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger 3926 * Control register and poll till Legacy Interrupt Pointer register 3927 * bit32 is 0. 3928 */ 3929 qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0); 3930 do { 3931 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET); 3932 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) 3933 break; 3934 } while (leg_int_ptr & (LEG_INT_PTR_B30)); 3935 3936 reg = &ha->iobase->isp82; 3937 spin_lock_irqsave(&ha->hardware_lock, flags); 3938 for (iter = 1; iter--; ) { 3939 3940 if (rd_reg_dword(®->host_int)) { 3941 stat = rd_reg_dword(®->host_status); 3942 if ((stat & HSRX_RISC_INT) == 0) 3943 break; 3944 3945 switch (stat & 0xff) { 3946 case 0x1: 3947 case 0x2: 3948 case 0x10: 3949 case 0x11: 3950 qla82xx_mbx_completion(vha, MSW(stat)); 3951 status |= MBX_INTERRUPT; 3952 break; 3953 case 0x12: 3954 mb[0] = MSW(stat); 3955 mb[1] = rd_reg_word(®->mailbox_out[1]); 3956 mb[2] = rd_reg_word(®->mailbox_out[2]); 3957 mb[3] = rd_reg_word(®->mailbox_out[3]); 3958 qla2x00_async_event(vha, rsp, mb); 3959 break; 3960 case 0x13: 3961 qla24xx_process_response_queue(vha, rsp); 3962 break; 3963 default: 3964 ql_dbg(ql_dbg_p3p, vha, 0xb146, 3965 "Unrecognized interrupt type " 3966 "(%d).\n", stat & 0xff); 3967 break; 3968 } 3969 } 3970 wrt_reg_dword(®->host_int, 0); 3971 } 3972 3973 qla2x00_handle_mbx_completion(ha, status); 3974 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3975 3976 return IRQ_HANDLED; 3977 } 3978 3979 static int 3980 qla8044_idc_dontreset(struct qla_hw_data *ha) 3981 { 3982 uint32_t idc_ctrl; 3983 3984 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 3985 return idc_ctrl & DONTRESET_BIT0; 3986 } 3987 3988 static void 3989 qla8044_clear_rst_ready(scsi_qla_host_t *vha) 3990 { 3991 uint32_t drv_state; 3992 3993 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 3994 3995 /* 3996 * For ISP8044, drv_active register has 1 bit per function, 3997 * shift 1 by func_num to set a bit for the function. 3998 * For ISP82xx, drv_active has 4 bits per function 3999 */ 4000 drv_state &= ~(1 << vha->hw->portnum); 4001 4002 ql_dbg(ql_dbg_p3p, vha, 0xb13d, 4003 "drv_state: 0x%08x\n", drv_state); 4004 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state); 4005 } 4006 4007 int 4008 qla8044_abort_isp(scsi_qla_host_t *vha) 4009 { 4010 int rval; 4011 uint32_t dev_state; 4012 struct qla_hw_data *ha = vha->hw; 4013 4014 qla8044_idc_lock(ha); 4015 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 4016 4017 if (ql2xdontresethba) 4018 qla8044_set_idc_dontreset(vha); 4019 4020 /* If device_state is NEED_RESET, go ahead with 4021 * Reset,irrespective of ql2xdontresethba. This is to allow a 4022 * non-reset-owner to force a reset. Non-reset-owner sets 4023 * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset 4024 * and then forces a Reset by setting device_state to 4025 * NEED_RESET. */ 4026 if (dev_state == QLA8XXX_DEV_READY) { 4027 /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset 4028 * recovery */ 4029 if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) { 4030 ql_dbg(ql_dbg_p3p, vha, 0xb13e, 4031 "Reset recovery disabled\n"); 4032 rval = QLA_FUNCTION_FAILED; 4033 goto exit_isp_reset; 4034 } 4035 4036 ql_dbg(ql_dbg_p3p, vha, 0xb140, 4037 "HW State: NEED RESET\n"); 4038 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 4039 QLA8XXX_DEV_NEED_RESET); 4040 } 4041 4042 /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority 4043 * and which drivers are present. Unlike ISP82XX, the function setting 4044 * NEED_RESET, may not be the Reset owner. */ 4045 qla83xx_reset_ownership(vha); 4046 4047 qla8044_idc_unlock(ha); 4048 rval = qla8044_device_state_handler(vha); 4049 qla8044_idc_lock(ha); 4050 qla8044_clear_rst_ready(vha); 4051 4052 exit_isp_reset: 4053 qla8044_idc_unlock(ha); 4054 if (rval == QLA_SUCCESS) { 4055 ha->flags.isp82xx_fw_hung = 0; 4056 ha->flags.nic_core_reset_hdlr_active = 0; 4057 rval = qla82xx_restart_isp(vha); 4058 } 4059 4060 return rval; 4061 } 4062 4063 void 4064 qla8044_fw_dump(scsi_qla_host_t *vha) 4065 { 4066 struct qla_hw_data *ha = vha->hw; 4067 4068 if (!ha->allow_cna_fw_dump) 4069 return; 4070 4071 scsi_block_requests(vha->host); 4072 ha->flags.isp82xx_no_md_cap = 1; 4073 qla8044_idc_lock(ha); 4074 qla82xx_set_reset_owner(vha); 4075 qla8044_idc_unlock(ha); 4076 qla2x00_wait_for_chip_reset(vha); 4077 scsi_unblock_requests(vha->host); 4078 } 4079