1 /* 2 * QLogic Fibre Channel HBA Driver 3 * Copyright (c) 2003-2013 QLogic Corporation 4 * 5 * See LICENSE.qla2xxx for copyright and licensing details. 6 */ 7 8 #include <linux/vmalloc.h> 9 10 #include "qla_def.h" 11 #include "qla_gbl.h" 12 13 #include <linux/delay.h> 14 15 #define TIMEOUT_100_MS 100 16 17 /* 8044 Flash Read/Write functions */ 18 uint32_t 19 qla8044_rd_reg(struct qla_hw_data *ha, ulong addr) 20 { 21 return readl((void __iomem *) (ha->nx_pcibase + addr)); 22 } 23 24 void 25 qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val) 26 { 27 writel(val, (void __iomem *)((ha)->nx_pcibase + addr)); 28 } 29 30 int 31 qla8044_rd_direct(struct scsi_qla_host *vha, 32 const uint32_t crb_reg) 33 { 34 struct qla_hw_data *ha = vha->hw; 35 36 if (crb_reg < CRB_REG_INDEX_MAX) 37 return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]); 38 else 39 return QLA_FUNCTION_FAILED; 40 } 41 42 void 43 qla8044_wr_direct(struct scsi_qla_host *vha, 44 const uint32_t crb_reg, 45 const uint32_t value) 46 { 47 struct qla_hw_data *ha = vha->hw; 48 49 if (crb_reg < CRB_REG_INDEX_MAX) 50 qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value); 51 } 52 53 static int 54 qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr) 55 { 56 uint32_t val; 57 int ret_val = QLA_SUCCESS; 58 struct qla_hw_data *ha = vha->hw; 59 60 qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr); 61 val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum)); 62 63 if (val != addr) { 64 ql_log(ql_log_warn, vha, 0xb087, 65 "%s: Failed to set register window : " 66 "addr written 0x%x, read 0x%x!\n", 67 __func__, addr, val); 68 ret_val = QLA_FUNCTION_FAILED; 69 } 70 return ret_val; 71 } 72 73 static int 74 qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) 75 { 76 int ret_val = QLA_SUCCESS; 77 struct qla_hw_data *ha = vha->hw; 78 79 ret_val = qla8044_set_win_base(vha, addr); 80 if (!ret_val) 81 *data = qla8044_rd_reg(ha, QLA8044_WILDCARD); 82 else 83 ql_log(ql_log_warn, vha, 0xb088, 84 "%s: failed read of addr 0x%x!\n", __func__, addr); 85 return ret_val; 86 } 87 88 static int 89 qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) 90 { 91 int ret_val = QLA_SUCCESS; 92 struct qla_hw_data *ha = vha->hw; 93 94 ret_val = qla8044_set_win_base(vha, addr); 95 if (!ret_val) 96 qla8044_wr_reg(ha, QLA8044_WILDCARD, data); 97 else 98 ql_log(ql_log_warn, vha, 0xb089, 99 "%s: failed wrt to addr 0x%x, data 0x%x\n", 100 __func__, addr, data); 101 return ret_val; 102 } 103 104 /* 105 * qla8044_read_write_crb_reg - Read from raddr and write value to waddr. 106 * 107 * @ha : Pointer to adapter structure 108 * @raddr : CRB address to read from 109 * @waddr : CRB address to write to 110 * 111 */ 112 static void 113 qla8044_read_write_crb_reg(struct scsi_qla_host *vha, 114 uint32_t raddr, uint32_t waddr) 115 { 116 uint32_t value; 117 118 qla8044_rd_reg_indirect(vha, raddr, &value); 119 qla8044_wr_reg_indirect(vha, waddr, value); 120 } 121 122 static int 123 qla8044_poll_wait_for_ready(struct scsi_qla_host *vha, uint32_t addr1, 124 uint32_t mask) 125 { 126 unsigned long timeout; 127 uint32_t temp; 128 129 /* jiffies after 100ms */ 130 timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS); 131 do { 132 qla8044_rd_reg_indirect(vha, addr1, &temp); 133 if ((temp & mask) != 0) 134 break; 135 if (time_after_eq(jiffies, timeout)) { 136 ql_log(ql_log_warn, vha, 0xb151, 137 "Error in processing rdmdio entry\n"); 138 return -1; 139 } 140 } while (1); 141 142 return 0; 143 } 144 145 static uint32_t 146 qla8044_ipmdio_rd_reg(struct scsi_qla_host *vha, 147 uint32_t addr1, uint32_t addr3, uint32_t mask, uint32_t addr) 148 { 149 uint32_t temp; 150 int ret = 0; 151 152 ret = qla8044_poll_wait_for_ready(vha, addr1, mask); 153 if (ret == -1) 154 return -1; 155 156 temp = (0x40000000 | addr); 157 qla8044_wr_reg_indirect(vha, addr1, temp); 158 159 ret = qla8044_poll_wait_for_ready(vha, addr1, mask); 160 if (ret == -1) 161 return 0; 162 163 qla8044_rd_reg_indirect(vha, addr3, &ret); 164 165 return ret; 166 } 167 168 169 static int 170 qla8044_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *vha, 171 uint32_t addr1, uint32_t addr2, uint32_t addr3, uint32_t mask) 172 { 173 unsigned long timeout; 174 uint32_t temp; 175 176 /* jiffies after 100 msecs */ 177 timeout = jiffies + (HZ / 1000) * TIMEOUT_100_MS; 178 do { 179 temp = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr2); 180 if ((temp & 0x1) != 1) 181 break; 182 } while (!time_after_eq(jiffies, timeout)); 183 184 if (time_after_eq(jiffies, timeout)) { 185 ql_log(ql_log_warn, vha, 0xb152, 186 "Error in processing mdiobus idle\n"); 187 return -1; 188 } 189 190 return 0; 191 } 192 193 static int 194 qla8044_ipmdio_wr_reg(struct scsi_qla_host *vha, uint32_t addr1, 195 uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t value) 196 { 197 int ret = 0; 198 199 ret = qla8044_poll_wait_for_ready(vha, addr1, mask); 200 if (ret == -1) 201 return -1; 202 203 qla8044_wr_reg_indirect(vha, addr3, value); 204 qla8044_wr_reg_indirect(vha, addr1, addr); 205 206 ret = qla8044_poll_wait_for_ready(vha, addr1, mask); 207 if (ret == -1) 208 return -1; 209 210 return 0; 211 } 212 /* 213 * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask, 214 * Shift Left,Right/OR/XOR with values RMW header and write value to waddr. 215 * 216 * @vha : Pointer to adapter structure 217 * @raddr : CRB address to read from 218 * @waddr : CRB address to write to 219 * @p_rmw_hdr : header with shift/or/xor values. 220 * 221 */ 222 static void 223 qla8044_rmw_crb_reg(struct scsi_qla_host *vha, 224 uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr) 225 { 226 uint32_t value; 227 228 if (p_rmw_hdr->index_a) 229 value = vha->reset_tmplt.array[p_rmw_hdr->index_a]; 230 else 231 qla8044_rd_reg_indirect(vha, raddr, &value); 232 value &= p_rmw_hdr->test_mask; 233 value <<= p_rmw_hdr->shl; 234 value >>= p_rmw_hdr->shr; 235 value |= p_rmw_hdr->or_value; 236 value ^= p_rmw_hdr->xor_value; 237 qla8044_wr_reg_indirect(vha, waddr, value); 238 return; 239 } 240 241 inline void 242 qla8044_set_qsnt_ready(struct scsi_qla_host *vha) 243 { 244 uint32_t qsnt_state; 245 struct qla_hw_data *ha = vha->hw; 246 247 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 248 qsnt_state |= (1 << ha->portnum); 249 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state); 250 ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n", 251 __func__, vha->host_no, qsnt_state); 252 } 253 254 void 255 qla8044_clear_qsnt_ready(struct scsi_qla_host *vha) 256 { 257 uint32_t qsnt_state; 258 struct qla_hw_data *ha = vha->hw; 259 260 qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 261 qsnt_state &= ~(1 << ha->portnum); 262 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state); 263 ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n", 264 __func__, vha->host_no, qsnt_state); 265 } 266 267 /** 268 * 269 * qla8044_lock_recovery - Recovers the idc_lock. 270 * @ha : Pointer to adapter structure 271 * 272 * Lock Recovery Register 273 * 5-2 Lock recovery owner: Function ID of driver doing lock recovery, 274 * valid if bits 1..0 are set by driver doing lock recovery. 275 * 1-0 1 - Driver intends to force unlock the IDC lock. 276 * 2 - Driver is moving forward to unlock the IDC lock. Driver clears 277 * this field after force unlocking the IDC lock. 278 * 279 * Lock Recovery process 280 * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is 281 * greater than 0, then wait for the other driver to unlock otherwise 282 * move to the next step. 283 * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY 284 * register bits 1..0 and also set the function# in bits 5..2. 285 * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms. 286 * Wait for the other driver to perform lock recovery if the function 287 * number in bits 5..2 has changed, otherwise move to the next step. 288 * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0 289 * leaving your function# in bits 5..2. 290 * e. Force unlock using the DRIVER_UNLOCK register and immediately clear 291 * the IDC_LOCK_RECOVERY bits 5..0 by writing 0. 292 **/ 293 static int 294 qla8044_lock_recovery(struct scsi_qla_host *vha) 295 { 296 uint32_t lock = 0, lockid; 297 struct qla_hw_data *ha = vha->hw; 298 299 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY); 300 301 /* Check for other Recovery in progress, go wait */ 302 if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0) 303 return QLA_FUNCTION_FAILED; 304 305 /* Intent to Recover */ 306 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 307 (ha->portnum << 308 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER); 309 msleep(200); 310 311 /* Check Intent to Recover is advertised */ 312 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY); 313 if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum << 314 IDC_LOCK_RECOVERY_STATE_SHIFT_BITS)) 315 return QLA_FUNCTION_FAILED; 316 317 ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n" 318 , __func__, ha->portnum); 319 320 /* Proceed to Recover */ 321 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 322 (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | 323 PROCEED_TO_RECOVER); 324 325 /* Force Unlock() */ 326 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF); 327 qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK); 328 329 /* Clear bits 0-5 in IDC_RECOVERY register*/ 330 qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0); 331 332 /* Get lock() */ 333 lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK); 334 if (lock) { 335 lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 336 lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum; 337 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid); 338 return QLA_SUCCESS; 339 } else 340 return QLA_FUNCTION_FAILED; 341 } 342 343 int 344 qla8044_idc_lock(struct qla_hw_data *ha) 345 { 346 uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0; 347 uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0; 348 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 349 350 while (status == 0) { 351 /* acquire semaphore5 from PCI HW block */ 352 status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK); 353 354 if (status) { 355 /* Increment Counter (8-31) and update func_num (0-7) on 356 * getting a successful lock */ 357 lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 358 lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum; 359 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id); 360 break; 361 } 362 363 if (timeout == 0) 364 first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 365 366 if (++timeout >= 367 (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) { 368 tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 369 func_num = tmo_owner & 0xFF; 370 lock_cnt = tmo_owner >> 8; 371 ql_log(ql_log_warn, vha, 0xb114, 372 "%s: Lock by func %d failed after 2s, lock held " 373 "by func %d, lock count %d, first_owner %d\n", 374 __func__, ha->portnum, func_num, lock_cnt, 375 (first_owner & 0xFF)); 376 if (first_owner != tmo_owner) { 377 /* Some other driver got lock, 378 * OR same driver got lock again (counter 379 * value changed), when we were waiting for 380 * lock. Retry for another 2 sec */ 381 ql_dbg(ql_dbg_p3p, vha, 0xb115, 382 "%s: %d: IDC lock failed\n", 383 __func__, ha->portnum); 384 timeout = 0; 385 } else { 386 /* Same driver holding lock > 2sec. 387 * Force Recovery */ 388 if (qla8044_lock_recovery(vha) == QLA_SUCCESS) { 389 /* Recovered and got lock */ 390 ret_val = QLA_SUCCESS; 391 ql_dbg(ql_dbg_p3p, vha, 0xb116, 392 "%s:IDC lock Recovery by %d" 393 "successful...\n", __func__, 394 ha->portnum); 395 } 396 /* Recovery Failed, some other function 397 * has the lock, wait for 2secs 398 * and retry 399 */ 400 ql_dbg(ql_dbg_p3p, vha, 0xb08a, 401 "%s: IDC lock Recovery by %d " 402 "failed, Retrying timout\n", __func__, 403 ha->portnum); 404 timeout = 0; 405 } 406 } 407 msleep(QLA8044_DRV_LOCK_MSLEEP); 408 } 409 return ret_val; 410 } 411 412 void 413 qla8044_idc_unlock(struct qla_hw_data *ha) 414 { 415 int id; 416 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 417 418 id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 419 420 if ((id & 0xFF) != ha->portnum) { 421 ql_log(ql_log_warn, vha, 0xb118, 422 "%s: IDC Unlock by %d failed, lock owner is %d!\n", 423 __func__, ha->portnum, (id & 0xFF)); 424 return; 425 } 426 427 /* Keep lock counter value, update the ha->func_num to 0xFF */ 428 qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF)); 429 qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK); 430 } 431 432 /* 8044 Flash Lock/Unlock functions */ 433 static int 434 qla8044_flash_lock(scsi_qla_host_t *vha) 435 { 436 int lock_owner; 437 int timeout = 0; 438 uint32_t lock_status = 0; 439 int ret_val = QLA_SUCCESS; 440 struct qla_hw_data *ha = vha->hw; 441 442 while (lock_status == 0) { 443 lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK); 444 if (lock_status) 445 break; 446 447 if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) { 448 lock_owner = qla8044_rd_reg(ha, 449 QLA8044_FLASH_LOCK_ID); 450 ql_log(ql_log_warn, vha, 0xb113, 451 "%s: flash lock by %d failed, held by %d\n", 452 __func__, ha->portnum, lock_owner); 453 ret_val = QLA_FUNCTION_FAILED; 454 break; 455 } 456 msleep(20); 457 } 458 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum); 459 return ret_val; 460 } 461 462 static void 463 qla8044_flash_unlock(scsi_qla_host_t *vha) 464 { 465 int ret_val; 466 struct qla_hw_data *ha = vha->hw; 467 468 /* Reading FLASH_UNLOCK register unlocks the Flash */ 469 qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF); 470 ret_val = qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK); 471 } 472 473 474 static 475 void qla8044_flash_lock_recovery(struct scsi_qla_host *vha) 476 { 477 478 if (qla8044_flash_lock(vha)) { 479 /* Someone else is holding the lock. */ 480 ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n"); 481 } 482 483 /* 484 * Either we got the lock, or someone 485 * else died while holding it. 486 * In either case, unlock. 487 */ 488 qla8044_flash_unlock(vha); 489 } 490 491 /* 492 * Address and length are byte address 493 */ 494 static int 495 qla8044_read_flash_data(scsi_qla_host_t *vha, uint8_t *p_data, 496 uint32_t flash_addr, int u32_word_count) 497 { 498 int i, ret_val = QLA_SUCCESS; 499 uint32_t u32_word; 500 501 if (qla8044_flash_lock(vha) != QLA_SUCCESS) { 502 ret_val = QLA_FUNCTION_FAILED; 503 goto exit_lock_error; 504 } 505 506 if (flash_addr & 0x03) { 507 ql_log(ql_log_warn, vha, 0xb117, 508 "%s: Illegal addr = 0x%x\n", __func__, flash_addr); 509 ret_val = QLA_FUNCTION_FAILED; 510 goto exit_flash_read; 511 } 512 513 for (i = 0; i < u32_word_count; i++) { 514 if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW, 515 (flash_addr & 0xFFFF0000))) { 516 ql_log(ql_log_warn, vha, 0xb119, 517 "%s: failed to write addr 0x%x to " 518 "FLASH_DIRECT_WINDOW\n! ", 519 __func__, flash_addr); 520 ret_val = QLA_FUNCTION_FAILED; 521 goto exit_flash_read; 522 } 523 524 ret_val = qla8044_rd_reg_indirect(vha, 525 QLA8044_FLASH_DIRECT_DATA(flash_addr), 526 &u32_word); 527 if (ret_val != QLA_SUCCESS) { 528 ql_log(ql_log_warn, vha, 0xb08c, 529 "%s: failed to read addr 0x%x!\n", 530 __func__, flash_addr); 531 goto exit_flash_read; 532 } 533 534 *(uint32_t *)p_data = u32_word; 535 p_data = p_data + 4; 536 flash_addr = flash_addr + 4; 537 } 538 539 exit_flash_read: 540 qla8044_flash_unlock(vha); 541 542 exit_lock_error: 543 return ret_val; 544 } 545 546 /* 547 * Address and length are byte address 548 */ 549 uint8_t * 550 qla8044_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 551 uint32_t offset, uint32_t length) 552 { 553 scsi_block_requests(vha->host); 554 if (qla8044_read_flash_data(vha, (uint8_t *)buf, offset, length / 4) 555 != QLA_SUCCESS) { 556 ql_log(ql_log_warn, vha, 0xb08d, 557 "%s: Failed to read from flash\n", 558 __func__); 559 } 560 scsi_unblock_requests(vha->host); 561 return buf; 562 } 563 564 inline int 565 qla8044_need_reset(struct scsi_qla_host *vha) 566 { 567 uint32_t drv_state, drv_active; 568 int rval; 569 struct qla_hw_data *ha = vha->hw; 570 571 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 572 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 573 574 rval = drv_state & (1 << ha->portnum); 575 576 if (ha->flags.eeh_busy && drv_active) 577 rval = 1; 578 return rval; 579 } 580 581 /* 582 * qla8044_write_list - Write the value (p_entry->arg2) to address specified 583 * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between 584 * entries. 585 * 586 * @vha : Pointer to adapter structure 587 * @p_hdr : reset_entry header for WRITE_LIST opcode. 588 * 589 */ 590 static void 591 qla8044_write_list(struct scsi_qla_host *vha, 592 struct qla8044_reset_entry_hdr *p_hdr) 593 { 594 struct qla8044_entry *p_entry; 595 uint32_t i; 596 597 p_entry = (struct qla8044_entry *)((char *)p_hdr + 598 sizeof(struct qla8044_reset_entry_hdr)); 599 600 for (i = 0; i < p_hdr->count; i++, p_entry++) { 601 qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2); 602 if (p_hdr->delay) 603 udelay((uint32_t)(p_hdr->delay)); 604 } 605 } 606 607 /* 608 * qla8044_read_write_list - Read from address specified by p_entry->arg1, 609 * write value read to address specified by p_entry->arg2, for all entries in 610 * header with delay of p_hdr->delay between entries. 611 * 612 * @vha : Pointer to adapter structure 613 * @p_hdr : reset_entry header for READ_WRITE_LIST opcode. 614 * 615 */ 616 static void 617 qla8044_read_write_list(struct scsi_qla_host *vha, 618 struct qla8044_reset_entry_hdr *p_hdr) 619 { 620 struct qla8044_entry *p_entry; 621 uint32_t i; 622 623 p_entry = (struct qla8044_entry *)((char *)p_hdr + 624 sizeof(struct qla8044_reset_entry_hdr)); 625 626 for (i = 0; i < p_hdr->count; i++, p_entry++) { 627 qla8044_read_write_crb_reg(vha, p_entry->arg1, 628 p_entry->arg2); 629 if (p_hdr->delay) 630 udelay((uint32_t)(p_hdr->delay)); 631 } 632 } 633 634 /* 635 * qla8044_poll_reg - Poll the given CRB addr for duration msecs till 636 * value read ANDed with test_mask is equal to test_result. 637 * 638 * @ha : Pointer to adapter structure 639 * @addr : CRB register address 640 * @duration : Poll for total of "duration" msecs 641 * @test_mask : Mask value read with "test_mask" 642 * @test_result : Compare (value&test_mask) with test_result. 643 * 644 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 645 */ 646 static int 647 qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr, 648 int duration, uint32_t test_mask, uint32_t test_result) 649 { 650 uint32_t value; 651 int timeout_error; 652 uint8_t retries; 653 int ret_val = QLA_SUCCESS; 654 655 ret_val = qla8044_rd_reg_indirect(vha, addr, &value); 656 if (ret_val == QLA_FUNCTION_FAILED) { 657 timeout_error = 1; 658 goto exit_poll_reg; 659 } 660 661 /* poll every 1/10 of the total duration */ 662 retries = duration/10; 663 664 do { 665 if ((value & test_mask) != test_result) { 666 timeout_error = 1; 667 msleep(duration/10); 668 ret_val = qla8044_rd_reg_indirect(vha, addr, &value); 669 if (ret_val == QLA_FUNCTION_FAILED) { 670 timeout_error = 1; 671 goto exit_poll_reg; 672 } 673 } else { 674 timeout_error = 0; 675 break; 676 } 677 } while (retries--); 678 679 exit_poll_reg: 680 if (timeout_error) { 681 vha->reset_tmplt.seq_error++; 682 ql_log(ql_log_fatal, vha, 0xb090, 683 "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n", 684 __func__, value, test_mask, test_result); 685 } 686 687 return timeout_error; 688 } 689 690 /* 691 * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB 692 * register specified by p_entry->arg1 and compare (value AND test_mask) with 693 * test_result to validate it. Wait for p_hdr->delay between processing entries. 694 * 695 * @ha : Pointer to adapter structure 696 * @p_hdr : reset_entry header for POLL_LIST opcode. 697 * 698 */ 699 static void 700 qla8044_poll_list(struct scsi_qla_host *vha, 701 struct qla8044_reset_entry_hdr *p_hdr) 702 { 703 long delay; 704 struct qla8044_entry *p_entry; 705 struct qla8044_poll *p_poll; 706 uint32_t i; 707 uint32_t value; 708 709 p_poll = (struct qla8044_poll *) 710 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr)); 711 712 /* Entries start after 8 byte qla8044_poll, poll header contains 713 * the test_mask, test_value. 714 */ 715 p_entry = (struct qla8044_entry *)((char *)p_poll + 716 sizeof(struct qla8044_poll)); 717 718 delay = (long)p_hdr->delay; 719 720 if (!delay) { 721 for (i = 0; i < p_hdr->count; i++, p_entry++) 722 qla8044_poll_reg(vha, p_entry->arg1, 723 delay, p_poll->test_mask, p_poll->test_value); 724 } else { 725 for (i = 0; i < p_hdr->count; i++, p_entry++) { 726 if (delay) { 727 if (qla8044_poll_reg(vha, 728 p_entry->arg1, delay, 729 p_poll->test_mask, 730 p_poll->test_value)) { 731 /*If 732 * (data_read&test_mask != test_value) 733 * read TIMEOUT_ADDR (arg1) and 734 * ADDR (arg2) registers 735 */ 736 qla8044_rd_reg_indirect(vha, 737 p_entry->arg1, &value); 738 qla8044_rd_reg_indirect(vha, 739 p_entry->arg2, &value); 740 } 741 } 742 } 743 } 744 } 745 746 /* 747 * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr, 748 * read ar_addr, if (value& test_mask != test_mask) re-read till timeout 749 * expires. 750 * 751 * @vha : Pointer to adapter structure 752 * @p_hdr : reset entry header for POLL_WRITE_LIST opcode. 753 * 754 */ 755 static void 756 qla8044_poll_write_list(struct scsi_qla_host *vha, 757 struct qla8044_reset_entry_hdr *p_hdr) 758 { 759 long delay; 760 struct qla8044_quad_entry *p_entry; 761 struct qla8044_poll *p_poll; 762 uint32_t i; 763 764 p_poll = (struct qla8044_poll *)((char *)p_hdr + 765 sizeof(struct qla8044_reset_entry_hdr)); 766 767 p_entry = (struct qla8044_quad_entry *)((char *)p_poll + 768 sizeof(struct qla8044_poll)); 769 770 delay = (long)p_hdr->delay; 771 772 for (i = 0; i < p_hdr->count; i++, p_entry++) { 773 qla8044_wr_reg_indirect(vha, 774 p_entry->dr_addr, p_entry->dr_value); 775 qla8044_wr_reg_indirect(vha, 776 p_entry->ar_addr, p_entry->ar_value); 777 if (delay) { 778 if (qla8044_poll_reg(vha, 779 p_entry->ar_addr, delay, 780 p_poll->test_mask, 781 p_poll->test_value)) { 782 ql_dbg(ql_dbg_p3p, vha, 0xb091, 783 "%s: Timeout Error: poll list, ", 784 __func__); 785 ql_dbg(ql_dbg_p3p, vha, 0xb092, 786 "item_num %d, entry_num %d\n", i, 787 vha->reset_tmplt.seq_index); 788 } 789 } 790 } 791 } 792 793 /* 794 * qla8044_read_modify_write - Read value from p_entry->arg1, modify the 795 * value, write value to p_entry->arg2. Process entries with p_hdr->delay 796 * between entries. 797 * 798 * @vha : Pointer to adapter structure 799 * @p_hdr : header with shift/or/xor values. 800 * 801 */ 802 static void 803 qla8044_read_modify_write(struct scsi_qla_host *vha, 804 struct qla8044_reset_entry_hdr *p_hdr) 805 { 806 struct qla8044_entry *p_entry; 807 struct qla8044_rmw *p_rmw_hdr; 808 uint32_t i; 809 810 p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr + 811 sizeof(struct qla8044_reset_entry_hdr)); 812 813 p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr + 814 sizeof(struct qla8044_rmw)); 815 816 for (i = 0; i < p_hdr->count; i++, p_entry++) { 817 qla8044_rmw_crb_reg(vha, p_entry->arg1, 818 p_entry->arg2, p_rmw_hdr); 819 if (p_hdr->delay) 820 udelay((uint32_t)(p_hdr->delay)); 821 } 822 } 823 824 /* 825 * qla8044_pause - Wait for p_hdr->delay msecs, called between processing 826 * two entries of a sequence. 827 * 828 * @vha : Pointer to adapter structure 829 * @p_hdr : Common reset entry header. 830 * 831 */ 832 static 833 void qla8044_pause(struct scsi_qla_host *vha, 834 struct qla8044_reset_entry_hdr *p_hdr) 835 { 836 if (p_hdr->delay) 837 mdelay((uint32_t)((long)p_hdr->delay)); 838 } 839 840 /* 841 * qla8044_template_end - Indicates end of reset sequence processing. 842 * 843 * @vha : Pointer to adapter structure 844 * @p_hdr : Common reset entry header. 845 * 846 */ 847 static void 848 qla8044_template_end(struct scsi_qla_host *vha, 849 struct qla8044_reset_entry_hdr *p_hdr) 850 { 851 vha->reset_tmplt.template_end = 1; 852 853 if (vha->reset_tmplt.seq_error == 0) { 854 ql_dbg(ql_dbg_p3p, vha, 0xb093, 855 "%s: Reset sequence completed SUCCESSFULLY.\n", __func__); 856 } else { 857 ql_log(ql_log_fatal, vha, 0xb094, 858 "%s: Reset sequence completed with some timeout " 859 "errors.\n", __func__); 860 } 861 } 862 863 /* 864 * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr, 865 * if (value & test_mask != test_value) re-read till timeout value expires, 866 * read dr_addr register and assign to reset_tmplt.array. 867 * 868 * @vha : Pointer to adapter structure 869 * @p_hdr : Common reset entry header. 870 * 871 */ 872 static void 873 qla8044_poll_read_list(struct scsi_qla_host *vha, 874 struct qla8044_reset_entry_hdr *p_hdr) 875 { 876 long delay; 877 int index; 878 struct qla8044_quad_entry *p_entry; 879 struct qla8044_poll *p_poll; 880 uint32_t i; 881 uint32_t value; 882 883 p_poll = (struct qla8044_poll *) 884 ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr)); 885 886 p_entry = (struct qla8044_quad_entry *) 887 ((char *)p_poll + sizeof(struct qla8044_poll)); 888 889 delay = (long)p_hdr->delay; 890 891 for (i = 0; i < p_hdr->count; i++, p_entry++) { 892 qla8044_wr_reg_indirect(vha, p_entry->ar_addr, 893 p_entry->ar_value); 894 if (delay) { 895 if (qla8044_poll_reg(vha, p_entry->ar_addr, delay, 896 p_poll->test_mask, p_poll->test_value)) { 897 ql_dbg(ql_dbg_p3p, vha, 0xb095, 898 "%s: Timeout Error: poll " 899 "list, ", __func__); 900 ql_dbg(ql_dbg_p3p, vha, 0xb096, 901 "Item_num %d, " 902 "entry_num %d\n", i, 903 vha->reset_tmplt.seq_index); 904 } else { 905 index = vha->reset_tmplt.array_index; 906 qla8044_rd_reg_indirect(vha, 907 p_entry->dr_addr, &value); 908 vha->reset_tmplt.array[index++] = value; 909 if (index == QLA8044_MAX_RESET_SEQ_ENTRIES) 910 vha->reset_tmplt.array_index = 1; 911 } 912 } 913 } 914 } 915 916 /* 917 * qla8031_process_reset_template - Process all entries in reset template 918 * till entry with SEQ_END opcode, which indicates end of the reset template 919 * processing. Each entry has a Reset Entry header, entry opcode/command, with 920 * size of the entry, number of entries in sub-sequence and delay in microsecs 921 * or timeout in millisecs. 922 * 923 * @ha : Pointer to adapter structure 924 * @p_buff : Common reset entry header. 925 * 926 */ 927 static void 928 qla8044_process_reset_template(struct scsi_qla_host *vha, 929 char *p_buff) 930 { 931 int index, entries; 932 struct qla8044_reset_entry_hdr *p_hdr; 933 char *p_entry = p_buff; 934 935 vha->reset_tmplt.seq_end = 0; 936 vha->reset_tmplt.template_end = 0; 937 entries = vha->reset_tmplt.hdr->entries; 938 index = vha->reset_tmplt.seq_index; 939 940 for (; (!vha->reset_tmplt.seq_end) && (index < entries); index++) { 941 p_hdr = (struct qla8044_reset_entry_hdr *)p_entry; 942 switch (p_hdr->cmd) { 943 case OPCODE_NOP: 944 break; 945 case OPCODE_WRITE_LIST: 946 qla8044_write_list(vha, p_hdr); 947 break; 948 case OPCODE_READ_WRITE_LIST: 949 qla8044_read_write_list(vha, p_hdr); 950 break; 951 case OPCODE_POLL_LIST: 952 qla8044_poll_list(vha, p_hdr); 953 break; 954 case OPCODE_POLL_WRITE_LIST: 955 qla8044_poll_write_list(vha, p_hdr); 956 break; 957 case OPCODE_READ_MODIFY_WRITE: 958 qla8044_read_modify_write(vha, p_hdr); 959 break; 960 case OPCODE_SEQ_PAUSE: 961 qla8044_pause(vha, p_hdr); 962 break; 963 case OPCODE_SEQ_END: 964 vha->reset_tmplt.seq_end = 1; 965 break; 966 case OPCODE_TMPL_END: 967 qla8044_template_end(vha, p_hdr); 968 break; 969 case OPCODE_POLL_READ_LIST: 970 qla8044_poll_read_list(vha, p_hdr); 971 break; 972 default: 973 ql_log(ql_log_fatal, vha, 0xb097, 974 "%s: Unknown command ==> 0x%04x on " 975 "entry = %d\n", __func__, p_hdr->cmd, index); 976 break; 977 } 978 /* 979 *Set pointer to next entry in the sequence. 980 */ 981 p_entry += p_hdr->size; 982 } 983 vha->reset_tmplt.seq_index = index; 984 } 985 986 static void 987 qla8044_process_init_seq(struct scsi_qla_host *vha) 988 { 989 qla8044_process_reset_template(vha, 990 vha->reset_tmplt.init_offset); 991 if (vha->reset_tmplt.seq_end != 1) 992 ql_log(ql_log_fatal, vha, 0xb098, 993 "%s: Abrupt INIT Sub-Sequence end.\n", 994 __func__); 995 } 996 997 static void 998 qla8044_process_stop_seq(struct scsi_qla_host *vha) 999 { 1000 vha->reset_tmplt.seq_index = 0; 1001 qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset); 1002 if (vha->reset_tmplt.seq_end != 1) 1003 ql_log(ql_log_fatal, vha, 0xb099, 1004 "%s: Abrupt STOP Sub-Sequence end.\n", __func__); 1005 } 1006 1007 static void 1008 qla8044_process_start_seq(struct scsi_qla_host *vha) 1009 { 1010 qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset); 1011 if (vha->reset_tmplt.template_end != 1) 1012 ql_log(ql_log_fatal, vha, 0xb09a, 1013 "%s: Abrupt START Sub-Sequence end.\n", 1014 __func__); 1015 } 1016 1017 static int 1018 qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha, 1019 uint32_t flash_addr, uint8_t *p_data, int u32_word_count) 1020 { 1021 uint32_t i; 1022 uint32_t u32_word; 1023 uint32_t flash_offset; 1024 uint32_t addr = flash_addr; 1025 int ret_val = QLA_SUCCESS; 1026 1027 flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1); 1028 1029 if (addr & 0x3) { 1030 ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n", 1031 __func__, addr); 1032 ret_val = QLA_FUNCTION_FAILED; 1033 goto exit_lockless_read; 1034 } 1035 1036 ret_val = qla8044_wr_reg_indirect(vha, 1037 QLA8044_FLASH_DIRECT_WINDOW, (addr)); 1038 1039 if (ret_val != QLA_SUCCESS) { 1040 ql_log(ql_log_fatal, vha, 0xb09c, 1041 "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n", 1042 __func__, addr); 1043 goto exit_lockless_read; 1044 } 1045 1046 /* Check if data is spread across multiple sectors */ 1047 if ((flash_offset + (u32_word_count * sizeof(uint32_t))) > 1048 (QLA8044_FLASH_SECTOR_SIZE - 1)) { 1049 /* Multi sector read */ 1050 for (i = 0; i < u32_word_count; i++) { 1051 ret_val = qla8044_rd_reg_indirect(vha, 1052 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word); 1053 if (ret_val != QLA_SUCCESS) { 1054 ql_log(ql_log_fatal, vha, 0xb09d, 1055 "%s: failed to read addr 0x%x!\n", 1056 __func__, addr); 1057 goto exit_lockless_read; 1058 } 1059 *(uint32_t *)p_data = u32_word; 1060 p_data = p_data + 4; 1061 addr = addr + 4; 1062 flash_offset = flash_offset + 4; 1063 if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) { 1064 /* This write is needed once for each sector */ 1065 ret_val = qla8044_wr_reg_indirect(vha, 1066 QLA8044_FLASH_DIRECT_WINDOW, (addr)); 1067 if (ret_val != QLA_SUCCESS) { 1068 ql_log(ql_log_fatal, vha, 0xb09f, 1069 "%s: failed to write addr " 1070 "0x%x to FLASH_DIRECT_WINDOW!\n", 1071 __func__, addr); 1072 goto exit_lockless_read; 1073 } 1074 flash_offset = 0; 1075 } 1076 } 1077 } else { 1078 /* Single sector read */ 1079 for (i = 0; i < u32_word_count; i++) { 1080 ret_val = qla8044_rd_reg_indirect(vha, 1081 QLA8044_FLASH_DIRECT_DATA(addr), &u32_word); 1082 if (ret_val != QLA_SUCCESS) { 1083 ql_log(ql_log_fatal, vha, 0xb0a0, 1084 "%s: failed to read addr 0x%x!\n", 1085 __func__, addr); 1086 goto exit_lockless_read; 1087 } 1088 *(uint32_t *)p_data = u32_word; 1089 p_data = p_data + 4; 1090 addr = addr + 4; 1091 } 1092 } 1093 1094 exit_lockless_read: 1095 return ret_val; 1096 } 1097 1098 /* 1099 * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory 1100 * 1101 * @vha : Pointer to adapter structure 1102 * addr : Flash address to write to 1103 * data : Data to be written 1104 * count : word_count to be written 1105 * 1106 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 1107 */ 1108 static int 1109 qla8044_ms_mem_write_128b(struct scsi_qla_host *vha, 1110 uint64_t addr, uint32_t *data, uint32_t count) 1111 { 1112 int i, j, ret_val = QLA_SUCCESS; 1113 uint32_t agt_ctrl; 1114 unsigned long flags; 1115 struct qla_hw_data *ha = vha->hw; 1116 1117 /* Only 128-bit aligned access */ 1118 if (addr & 0xF) { 1119 ret_val = QLA_FUNCTION_FAILED; 1120 goto exit_ms_mem_write; 1121 } 1122 write_lock_irqsave(&ha->hw_lock, flags); 1123 1124 /* Write address */ 1125 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0); 1126 if (ret_val == QLA_FUNCTION_FAILED) { 1127 ql_log(ql_log_fatal, vha, 0xb0a1, 1128 "%s: write to AGT_ADDR_HI failed!\n", __func__); 1129 goto exit_ms_mem_write_unlock; 1130 } 1131 1132 for (i = 0; i < count; i++, addr += 16) { 1133 if (!((QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_QDR_NET, 1134 QLA8044_ADDR_QDR_NET_MAX)) || 1135 (QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_DDR_NET, 1136 QLA8044_ADDR_DDR_NET_MAX)))) { 1137 ret_val = QLA_FUNCTION_FAILED; 1138 goto exit_ms_mem_write_unlock; 1139 } 1140 1141 ret_val = qla8044_wr_reg_indirect(vha, 1142 MD_MIU_TEST_AGT_ADDR_LO, addr); 1143 1144 /* Write data */ 1145 ret_val += qla8044_wr_reg_indirect(vha, 1146 MD_MIU_TEST_AGT_WRDATA_LO, *data++); 1147 ret_val += qla8044_wr_reg_indirect(vha, 1148 MD_MIU_TEST_AGT_WRDATA_HI, *data++); 1149 ret_val += qla8044_wr_reg_indirect(vha, 1150 MD_MIU_TEST_AGT_WRDATA_ULO, *data++); 1151 ret_val += qla8044_wr_reg_indirect(vha, 1152 MD_MIU_TEST_AGT_WRDATA_UHI, *data++); 1153 if (ret_val == QLA_FUNCTION_FAILED) { 1154 ql_log(ql_log_fatal, vha, 0xb0a2, 1155 "%s: write to AGT_WRDATA failed!\n", 1156 __func__); 1157 goto exit_ms_mem_write_unlock; 1158 } 1159 1160 /* Check write status */ 1161 ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, 1162 MIU_TA_CTL_WRITE_ENABLE); 1163 ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, 1164 MIU_TA_CTL_WRITE_START); 1165 if (ret_val == QLA_FUNCTION_FAILED) { 1166 ql_log(ql_log_fatal, vha, 0xb0a3, 1167 "%s: write to AGT_CTRL failed!\n", __func__); 1168 goto exit_ms_mem_write_unlock; 1169 } 1170 1171 for (j = 0; j < MAX_CTL_CHECK; j++) { 1172 ret_val = qla8044_rd_reg_indirect(vha, 1173 MD_MIU_TEST_AGT_CTRL, &agt_ctrl); 1174 if (ret_val == QLA_FUNCTION_FAILED) { 1175 ql_log(ql_log_fatal, vha, 0xb0a4, 1176 "%s: failed to read " 1177 "MD_MIU_TEST_AGT_CTRL!\n", __func__); 1178 goto exit_ms_mem_write_unlock; 1179 } 1180 if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0) 1181 break; 1182 } 1183 1184 /* Status check failed */ 1185 if (j >= MAX_CTL_CHECK) { 1186 ql_log(ql_log_fatal, vha, 0xb0a5, 1187 "%s: MS memory write failed!\n", 1188 __func__); 1189 ret_val = QLA_FUNCTION_FAILED; 1190 goto exit_ms_mem_write_unlock; 1191 } 1192 } 1193 1194 exit_ms_mem_write_unlock: 1195 write_unlock_irqrestore(&ha->hw_lock, flags); 1196 1197 exit_ms_mem_write: 1198 return ret_val; 1199 } 1200 1201 static int 1202 qla8044_copy_bootloader(struct scsi_qla_host *vha) 1203 { 1204 uint8_t *p_cache; 1205 uint32_t src, count, size; 1206 uint64_t dest; 1207 int ret_val = QLA_SUCCESS; 1208 struct qla_hw_data *ha = vha->hw; 1209 1210 src = QLA8044_BOOTLOADER_FLASH_ADDR; 1211 dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR); 1212 size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE); 1213 1214 /* 128 bit alignment check */ 1215 if (size & 0xF) 1216 size = (size + 16) & ~0xF; 1217 1218 /* 16 byte count */ 1219 count = size/16; 1220 1221 p_cache = vmalloc(size); 1222 if (p_cache == NULL) { 1223 ql_log(ql_log_fatal, vha, 0xb0a6, 1224 "%s: Failed to allocate memory for " 1225 "boot loader cache\n", __func__); 1226 ret_val = QLA_FUNCTION_FAILED; 1227 goto exit_copy_bootloader; 1228 } 1229 1230 ret_val = qla8044_lockless_flash_read_u32(vha, src, 1231 p_cache, size/sizeof(uint32_t)); 1232 if (ret_val == QLA_FUNCTION_FAILED) { 1233 ql_log(ql_log_fatal, vha, 0xb0a7, 1234 "%s: Error reading F/W from flash!!!\n", __func__); 1235 goto exit_copy_error; 1236 } 1237 ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n", 1238 __func__); 1239 1240 /* 128 bit/16 byte write to MS memory */ 1241 ret_val = qla8044_ms_mem_write_128b(vha, dest, 1242 (uint32_t *)p_cache, count); 1243 if (ret_val == QLA_FUNCTION_FAILED) { 1244 ql_log(ql_log_fatal, vha, 0xb0a9, 1245 "%s: Error writing F/W to MS !!!\n", __func__); 1246 goto exit_copy_error; 1247 } 1248 ql_dbg(ql_dbg_p3p, vha, 0xb0aa, 1249 "%s: Wrote F/W (size %d) to MS !!!\n", 1250 __func__, size); 1251 1252 exit_copy_error: 1253 vfree(p_cache); 1254 1255 exit_copy_bootloader: 1256 return ret_val; 1257 } 1258 1259 static int 1260 qla8044_restart(struct scsi_qla_host *vha) 1261 { 1262 int ret_val = QLA_SUCCESS; 1263 struct qla_hw_data *ha = vha->hw; 1264 1265 qla8044_process_stop_seq(vha); 1266 1267 /* Collect minidump */ 1268 if (ql2xmdenable) 1269 qla8044_get_minidump(vha); 1270 else 1271 ql_log(ql_log_fatal, vha, 0xb14c, 1272 "Minidump disabled.\n"); 1273 1274 qla8044_process_init_seq(vha); 1275 1276 if (qla8044_copy_bootloader(vha)) { 1277 ql_log(ql_log_fatal, vha, 0xb0ab, 1278 "%s: Copy bootloader, firmware restart failed!\n", 1279 __func__); 1280 ret_val = QLA_FUNCTION_FAILED; 1281 goto exit_restart; 1282 } 1283 1284 /* 1285 * Loads F/W from flash 1286 */ 1287 qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH); 1288 1289 qla8044_process_start_seq(vha); 1290 1291 exit_restart: 1292 return ret_val; 1293 } 1294 1295 /* 1296 * qla8044_check_cmd_peg_status - Check peg status to see if Peg is 1297 * initialized. 1298 * 1299 * @ha : Pointer to adapter structure 1300 * 1301 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 1302 */ 1303 static int 1304 qla8044_check_cmd_peg_status(struct scsi_qla_host *vha) 1305 { 1306 uint32_t val, ret_val = QLA_FUNCTION_FAILED; 1307 int retries = CRB_CMDPEG_CHECK_RETRY_COUNT; 1308 struct qla_hw_data *ha = vha->hw; 1309 1310 do { 1311 val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE); 1312 if (val == PHAN_INITIALIZE_COMPLETE) { 1313 ql_dbg(ql_dbg_p3p, vha, 0xb0ac, 1314 "%s: Command Peg initialization " 1315 "complete! state=0x%x\n", __func__, val); 1316 ret_val = QLA_SUCCESS; 1317 break; 1318 } 1319 msleep(CRB_CMDPEG_CHECK_DELAY); 1320 } while (--retries); 1321 1322 return ret_val; 1323 } 1324 1325 static int 1326 qla8044_start_firmware(struct scsi_qla_host *vha) 1327 { 1328 int ret_val = QLA_SUCCESS; 1329 1330 if (qla8044_restart(vha)) { 1331 ql_log(ql_log_fatal, vha, 0xb0ad, 1332 "%s: Restart Error!!!, Need Reset!!!\n", 1333 __func__); 1334 ret_val = QLA_FUNCTION_FAILED; 1335 goto exit_start_fw; 1336 } else 1337 ql_dbg(ql_dbg_p3p, vha, 0xb0af, 1338 "%s: Restart done!\n", __func__); 1339 1340 ret_val = qla8044_check_cmd_peg_status(vha); 1341 if (ret_val) { 1342 ql_log(ql_log_fatal, vha, 0xb0b0, 1343 "%s: Peg not initialized!\n", __func__); 1344 ret_val = QLA_FUNCTION_FAILED; 1345 } 1346 1347 exit_start_fw: 1348 return ret_val; 1349 } 1350 1351 void 1352 qla8044_clear_drv_active(struct qla_hw_data *ha) 1353 { 1354 uint32_t drv_active; 1355 struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev); 1356 1357 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 1358 drv_active &= ~(1 << (ha->portnum)); 1359 1360 ql_log(ql_log_info, vha, 0xb0b1, 1361 "%s(%ld): drv_active: 0x%08x\n", 1362 __func__, vha->host_no, drv_active); 1363 1364 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active); 1365 } 1366 1367 /* 1368 * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw 1369 * @ha: pointer to adapter structure 1370 * 1371 * Note: IDC lock must be held upon entry 1372 **/ 1373 static int 1374 qla8044_device_bootstrap(struct scsi_qla_host *vha) 1375 { 1376 int rval = QLA_FUNCTION_FAILED; 1377 int i; 1378 uint32_t old_count = 0, count = 0; 1379 int need_reset = 0; 1380 uint32_t idc_ctrl; 1381 struct qla_hw_data *ha = vha->hw; 1382 1383 need_reset = qla8044_need_reset(vha); 1384 1385 if (!need_reset) { 1386 old_count = qla8044_rd_direct(vha, 1387 QLA8044_PEG_ALIVE_COUNTER_INDEX); 1388 1389 for (i = 0; i < 10; i++) { 1390 msleep(200); 1391 1392 count = qla8044_rd_direct(vha, 1393 QLA8044_PEG_ALIVE_COUNTER_INDEX); 1394 if (count != old_count) { 1395 rval = QLA_SUCCESS; 1396 goto dev_ready; 1397 } 1398 } 1399 qla8044_flash_lock_recovery(vha); 1400 } else { 1401 /* We are trying to perform a recovery here. */ 1402 if (ha->flags.isp82xx_fw_hung) 1403 qla8044_flash_lock_recovery(vha); 1404 } 1405 1406 /* set to DEV_INITIALIZING */ 1407 ql_log(ql_log_info, vha, 0xb0b2, 1408 "%s: HW State: INITIALIZING\n", __func__); 1409 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 1410 QLA8XXX_DEV_INITIALIZING); 1411 1412 qla8044_idc_unlock(ha); 1413 rval = qla8044_start_firmware(vha); 1414 qla8044_idc_lock(ha); 1415 1416 if (rval != QLA_SUCCESS) { 1417 ql_log(ql_log_info, vha, 0xb0b3, 1418 "%s: HW State: FAILED\n", __func__); 1419 qla8044_clear_drv_active(ha); 1420 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 1421 QLA8XXX_DEV_FAILED); 1422 return rval; 1423 } 1424 1425 /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after 1426 * device goes to INIT state. */ 1427 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 1428 if (idc_ctrl & GRACEFUL_RESET_BIT1) { 1429 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, 1430 (idc_ctrl & ~GRACEFUL_RESET_BIT1)); 1431 ha->fw_dumped = 0; 1432 } 1433 1434 dev_ready: 1435 ql_log(ql_log_info, vha, 0xb0b4, 1436 "%s: HW State: READY\n", __func__); 1437 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY); 1438 1439 return rval; 1440 } 1441 1442 /*-------------------------Reset Sequence Functions-----------------------*/ 1443 static void 1444 qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha) 1445 { 1446 u8 *phdr; 1447 1448 if (!vha->reset_tmplt.buff) { 1449 ql_log(ql_log_fatal, vha, 0xb0b5, 1450 "%s: Error Invalid reset_seq_template\n", __func__); 1451 return; 1452 } 1453 1454 phdr = vha->reset_tmplt.buff; 1455 ql_dbg(ql_dbg_p3p, vha, 0xb0b6, 1456 "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X" 1457 "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n" 1458 "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n", 1459 *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4), 1460 *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8), 1461 *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12), 1462 *(phdr+13), *(phdr+14), *(phdr+15)); 1463 } 1464 1465 /* 1466 * qla8044_reset_seq_checksum_test - Validate Reset Sequence template. 1467 * 1468 * @ha : Pointer to adapter structure 1469 * 1470 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 1471 */ 1472 static int 1473 qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha) 1474 { 1475 uint32_t sum = 0; 1476 uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff; 1477 int u16_count = vha->reset_tmplt.hdr->size / sizeof(uint16_t); 1478 1479 while (u16_count-- > 0) 1480 sum += *buff++; 1481 1482 while (sum >> 16) 1483 sum = (sum & 0xFFFF) + (sum >> 16); 1484 1485 /* checksum of 0 indicates a valid template */ 1486 if (~sum) { 1487 return QLA_SUCCESS; 1488 } else { 1489 ql_log(ql_log_fatal, vha, 0xb0b7, 1490 "%s: Reset seq checksum failed\n", __func__); 1491 return QLA_FUNCTION_FAILED; 1492 } 1493 } 1494 1495 /* 1496 * qla8044_read_reset_template - Read Reset Template from Flash, validate 1497 * the template and store offsets of stop/start/init offsets in ha->reset_tmplt. 1498 * 1499 * @ha : Pointer to adapter structure 1500 */ 1501 void 1502 qla8044_read_reset_template(struct scsi_qla_host *vha) 1503 { 1504 uint8_t *p_buff; 1505 uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size; 1506 1507 vha->reset_tmplt.seq_error = 0; 1508 vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE); 1509 if (vha->reset_tmplt.buff == NULL) { 1510 ql_log(ql_log_fatal, vha, 0xb0b8, 1511 "%s: Failed to allocate reset template resources\n", 1512 __func__); 1513 goto exit_read_reset_template; 1514 } 1515 1516 p_buff = vha->reset_tmplt.buff; 1517 addr = QLA8044_RESET_TEMPLATE_ADDR; 1518 1519 tmplt_hdr_def_size = 1520 sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t); 1521 1522 ql_dbg(ql_dbg_p3p, vha, 0xb0b9, 1523 "%s: Read template hdr size %d from Flash\n", 1524 __func__, tmplt_hdr_def_size); 1525 1526 /* Copy template header from flash */ 1527 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) { 1528 ql_log(ql_log_fatal, vha, 0xb0ba, 1529 "%s: Failed to read reset template\n", __func__); 1530 goto exit_read_template_error; 1531 } 1532 1533 vha->reset_tmplt.hdr = 1534 (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff; 1535 1536 /* Validate the template header size and signature */ 1537 tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t); 1538 if ((tmplt_hdr_size != tmplt_hdr_def_size) || 1539 (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) { 1540 ql_log(ql_log_fatal, vha, 0xb0bb, 1541 "%s: Template Header size invalid %d " 1542 "tmplt_hdr_def_size %d!!!\n", __func__, 1543 tmplt_hdr_size, tmplt_hdr_def_size); 1544 goto exit_read_template_error; 1545 } 1546 1547 addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size; 1548 p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size; 1549 tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size - 1550 vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t); 1551 1552 ql_dbg(ql_dbg_p3p, vha, 0xb0bc, 1553 "%s: Read rest of the template size %d\n", 1554 __func__, vha->reset_tmplt.hdr->size); 1555 1556 /* Copy rest of the template */ 1557 if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) { 1558 ql_log(ql_log_fatal, vha, 0xb0bd, 1559 "%s: Failed to read reset tempelate\n", __func__); 1560 goto exit_read_template_error; 1561 } 1562 1563 /* Integrity check */ 1564 if (qla8044_reset_seq_checksum_test(vha)) { 1565 ql_log(ql_log_fatal, vha, 0xb0be, 1566 "%s: Reset Seq checksum failed!\n", __func__); 1567 goto exit_read_template_error; 1568 } 1569 1570 ql_dbg(ql_dbg_p3p, vha, 0xb0bf, 1571 "%s: Reset Seq checksum passed! Get stop, " 1572 "start and init seq offsets\n", __func__); 1573 1574 /* Get STOP, START, INIT sequence offsets */ 1575 vha->reset_tmplt.init_offset = vha->reset_tmplt.buff + 1576 vha->reset_tmplt.hdr->init_seq_offset; 1577 1578 vha->reset_tmplt.start_offset = vha->reset_tmplt.buff + 1579 vha->reset_tmplt.hdr->start_seq_offset; 1580 1581 vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff + 1582 vha->reset_tmplt.hdr->hdr_size; 1583 1584 qla8044_dump_reset_seq_hdr(vha); 1585 1586 goto exit_read_reset_template; 1587 1588 exit_read_template_error: 1589 vfree(vha->reset_tmplt.buff); 1590 1591 exit_read_reset_template: 1592 return; 1593 } 1594 1595 void 1596 qla8044_set_idc_dontreset(struct scsi_qla_host *vha) 1597 { 1598 uint32_t idc_ctrl; 1599 struct qla_hw_data *ha = vha->hw; 1600 1601 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 1602 idc_ctrl |= DONTRESET_BIT0; 1603 ql_dbg(ql_dbg_p3p, vha, 0xb0c0, 1604 "%s: idc_ctrl = %d\n", __func__, idc_ctrl); 1605 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl); 1606 } 1607 1608 inline void 1609 qla8044_set_rst_ready(struct scsi_qla_host *vha) 1610 { 1611 uint32_t drv_state; 1612 struct qla_hw_data *ha = vha->hw; 1613 1614 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 1615 1616 /* For ISP8044, drv_active register has 1 bit per function, 1617 * shift 1 by func_num to set a bit for the function.*/ 1618 drv_state |= (1 << ha->portnum); 1619 1620 ql_log(ql_log_info, vha, 0xb0c1, 1621 "%s(%ld): drv_state: 0x%08x\n", 1622 __func__, vha->host_no, drv_state); 1623 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state); 1624 } 1625 1626 /** 1627 * qla8044_need_reset_handler - Code to start reset sequence 1628 * @ha: pointer to adapter structure 1629 * 1630 * Note: IDC lock must be held upon entry 1631 **/ 1632 static void 1633 qla8044_need_reset_handler(struct scsi_qla_host *vha) 1634 { 1635 uint32_t dev_state = 0, drv_state, drv_active; 1636 unsigned long reset_timeout, dev_init_timeout; 1637 struct qla_hw_data *ha = vha->hw; 1638 1639 ql_log(ql_log_fatal, vha, 0xb0c2, 1640 "%s: Performing ISP error recovery\n", __func__); 1641 1642 if (vha->flags.online) { 1643 qla8044_idc_unlock(ha); 1644 qla2x00_abort_isp_cleanup(vha); 1645 ha->isp_ops->get_flash_version(vha, vha->req->ring); 1646 ha->isp_ops->nvram_config(vha); 1647 qla8044_idc_lock(ha); 1648 } 1649 1650 drv_state = qla8044_rd_direct(vha, 1651 QLA8044_CRB_DRV_STATE_INDEX); 1652 drv_active = qla8044_rd_direct(vha, 1653 QLA8044_CRB_DRV_ACTIVE_INDEX); 1654 1655 ql_log(ql_log_info, vha, 0xb0c5, 1656 "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 1657 __func__, vha->host_no, drv_state, drv_active); 1658 1659 if (!ha->flags.nic_core_reset_owner) { 1660 ql_dbg(ql_dbg_p3p, vha, 0xb0c3, 1661 "%s(%ld): reset acknowledged\n", 1662 __func__, vha->host_no); 1663 qla8044_set_rst_ready(vha); 1664 1665 /* Non-reset owners ACK Reset and wait for device INIT state 1666 * as part of Reset Recovery by Reset Owner 1667 */ 1668 dev_init_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 1669 1670 do { 1671 if (time_after_eq(jiffies, dev_init_timeout)) { 1672 ql_log(ql_log_info, vha, 0xb0c4, 1673 "%s: Non Reset owner: Reset Ack Timeout!\n", 1674 __func__); 1675 break; 1676 } 1677 1678 qla8044_idc_unlock(ha); 1679 msleep(1000); 1680 qla8044_idc_lock(ha); 1681 1682 dev_state = qla8044_rd_direct(vha, 1683 QLA8044_CRB_DEV_STATE_INDEX); 1684 } while (((drv_state & drv_active) != drv_active) && 1685 (dev_state == QLA8XXX_DEV_NEED_RESET)); 1686 } else { 1687 qla8044_set_rst_ready(vha); 1688 1689 /* wait for 10 seconds for reset ack from all functions */ 1690 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 1691 1692 while ((drv_state & drv_active) != drv_active) { 1693 if (time_after_eq(jiffies, reset_timeout)) { 1694 ql_log(ql_log_info, vha, 0xb0c6, 1695 "%s: RESET TIMEOUT!" 1696 "drv_state: 0x%08x, drv_active: 0x%08x\n", 1697 QLA2XXX_DRIVER_NAME, drv_state, drv_active); 1698 break; 1699 } 1700 1701 qla8044_idc_unlock(ha); 1702 msleep(1000); 1703 qla8044_idc_lock(ha); 1704 1705 drv_state = qla8044_rd_direct(vha, 1706 QLA8044_CRB_DRV_STATE_INDEX); 1707 drv_active = qla8044_rd_direct(vha, 1708 QLA8044_CRB_DRV_ACTIVE_INDEX); 1709 } 1710 1711 if (drv_state != drv_active) { 1712 ql_log(ql_log_info, vha, 0xb0c7, 1713 "%s(%ld): Reset_owner turning off drv_active " 1714 "of non-acking function 0x%x\n", __func__, 1715 vha->host_no, (drv_active ^ drv_state)); 1716 drv_active = drv_active & drv_state; 1717 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, 1718 drv_active); 1719 } 1720 1721 /* 1722 * Clear RESET OWNER, will be set at next reset 1723 * by next RST_OWNER 1724 */ 1725 ha->flags.nic_core_reset_owner = 0; 1726 1727 /* Start Reset Recovery */ 1728 qla8044_device_bootstrap(vha); 1729 } 1730 } 1731 1732 static void 1733 qla8044_set_drv_active(struct scsi_qla_host *vha) 1734 { 1735 uint32_t drv_active; 1736 struct qla_hw_data *ha = vha->hw; 1737 1738 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 1739 1740 /* For ISP8044, drv_active register has 1 bit per function, 1741 * shift 1 by func_num to set a bit for the function.*/ 1742 drv_active |= (1 << ha->portnum); 1743 1744 ql_log(ql_log_info, vha, 0xb0c8, 1745 "%s(%ld): drv_active: 0x%08x\n", 1746 __func__, vha->host_no, drv_active); 1747 qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active); 1748 } 1749 1750 static int 1751 qla8044_check_drv_active(struct scsi_qla_host *vha) 1752 { 1753 uint32_t drv_active; 1754 struct qla_hw_data *ha = vha->hw; 1755 1756 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 1757 if (drv_active & (1 << ha->portnum)) 1758 return QLA_SUCCESS; 1759 else 1760 return QLA_TEST_FAILED; 1761 } 1762 1763 static void 1764 qla8044_clear_idc_dontreset(struct scsi_qla_host *vha) 1765 { 1766 uint32_t idc_ctrl; 1767 struct qla_hw_data *ha = vha->hw; 1768 1769 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 1770 idc_ctrl &= ~DONTRESET_BIT0; 1771 ql_log(ql_log_info, vha, 0xb0c9, 1772 "%s: idc_ctrl = %d\n", __func__, 1773 idc_ctrl); 1774 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl); 1775 } 1776 1777 static int 1778 qla8044_set_idc_ver(struct scsi_qla_host *vha) 1779 { 1780 int idc_ver; 1781 uint32_t drv_active; 1782 int rval = QLA_SUCCESS; 1783 struct qla_hw_data *ha = vha->hw; 1784 1785 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 1786 if (drv_active == (1 << ha->portnum)) { 1787 idc_ver = qla8044_rd_direct(vha, 1788 QLA8044_CRB_DRV_IDC_VERSION_INDEX); 1789 idc_ver &= (~0xFF); 1790 idc_ver |= QLA8044_IDC_VER_MAJ_VALUE; 1791 qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX, 1792 idc_ver); 1793 ql_log(ql_log_info, vha, 0xb0ca, 1794 "%s: IDC version updated to %d\n", 1795 __func__, idc_ver); 1796 } else { 1797 idc_ver = qla8044_rd_direct(vha, 1798 QLA8044_CRB_DRV_IDC_VERSION_INDEX); 1799 idc_ver &= 0xFF; 1800 if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) { 1801 ql_log(ql_log_info, vha, 0xb0cb, 1802 "%s: qla4xxx driver IDC version %d " 1803 "is not compatible with IDC version %d " 1804 "of other drivers!\n", 1805 __func__, QLA8044_IDC_VER_MAJ_VALUE, 1806 idc_ver); 1807 rval = QLA_FUNCTION_FAILED; 1808 goto exit_set_idc_ver; 1809 } 1810 } 1811 1812 /* Update IDC_MINOR_VERSION */ 1813 idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR); 1814 idc_ver &= ~(0x03 << (ha->portnum * 2)); 1815 idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2)); 1816 qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver); 1817 1818 exit_set_idc_ver: 1819 return rval; 1820 } 1821 1822 static int 1823 qla8044_update_idc_reg(struct scsi_qla_host *vha) 1824 { 1825 uint32_t drv_active; 1826 int rval = QLA_SUCCESS; 1827 struct qla_hw_data *ha = vha->hw; 1828 1829 if (vha->flags.init_done) 1830 goto exit_update_idc_reg; 1831 1832 qla8044_idc_lock(ha); 1833 qla8044_set_drv_active(vha); 1834 1835 drv_active = qla8044_rd_direct(vha, 1836 QLA8044_CRB_DRV_ACTIVE_INDEX); 1837 1838 /* If we are the first driver to load and 1839 * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */ 1840 if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba) 1841 qla8044_clear_idc_dontreset(vha); 1842 1843 rval = qla8044_set_idc_ver(vha); 1844 if (rval == QLA_FUNCTION_FAILED) 1845 qla8044_clear_drv_active(ha); 1846 qla8044_idc_unlock(ha); 1847 1848 exit_update_idc_reg: 1849 return rval; 1850 } 1851 1852 /** 1853 * qla8044_need_qsnt_handler - Code to start qsnt 1854 * @ha: pointer to adapter structure 1855 **/ 1856 static void 1857 qla8044_need_qsnt_handler(struct scsi_qla_host *vha) 1858 { 1859 unsigned long qsnt_timeout; 1860 uint32_t drv_state, drv_active, dev_state; 1861 struct qla_hw_data *ha = vha->hw; 1862 1863 if (vha->flags.online) 1864 qla2x00_quiesce_io(vha); 1865 else 1866 return; 1867 1868 qla8044_set_qsnt_ready(vha); 1869 1870 /* Wait for 30 secs for all functions to ack qsnt mode */ 1871 qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ); 1872 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 1873 drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 1874 1875 /* Shift drv_active by 1 to match drv_state. As quiescent ready bit 1876 position is at bit 1 and drv active is at bit 0 */ 1877 drv_active = drv_active << 1; 1878 1879 while (drv_state != drv_active) { 1880 if (time_after_eq(jiffies, qsnt_timeout)) { 1881 /* Other functions did not ack, changing state to 1882 * DEV_READY 1883 */ 1884 clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 1885 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 1886 QLA8XXX_DEV_READY); 1887 qla8044_clear_qsnt_ready(vha); 1888 ql_log(ql_log_info, vha, 0xb0cc, 1889 "Timeout waiting for quiescent ack!!!\n"); 1890 return; 1891 } 1892 qla8044_idc_unlock(ha); 1893 msleep(1000); 1894 qla8044_idc_lock(ha); 1895 1896 drv_state = qla8044_rd_direct(vha, 1897 QLA8044_CRB_DRV_STATE_INDEX); 1898 drv_active = qla8044_rd_direct(vha, 1899 QLA8044_CRB_DRV_ACTIVE_INDEX); 1900 drv_active = drv_active << 1; 1901 } 1902 1903 /* All functions have Acked. Set quiescent state */ 1904 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 1905 1906 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 1907 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 1908 QLA8XXX_DEV_QUIESCENT); 1909 ql_log(ql_log_info, vha, 0xb0cd, 1910 "%s: HW State: QUIESCENT\n", __func__); 1911 } 1912 } 1913 1914 /* 1915 * qla8044_device_state_handler - Adapter state machine 1916 * @ha: pointer to host adapter structure. 1917 * 1918 * Note: IDC lock must be UNLOCKED upon entry 1919 **/ 1920 int 1921 qla8044_device_state_handler(struct scsi_qla_host *vha) 1922 { 1923 uint32_t dev_state; 1924 int rval = QLA_SUCCESS; 1925 unsigned long dev_init_timeout; 1926 struct qla_hw_data *ha = vha->hw; 1927 1928 rval = qla8044_update_idc_reg(vha); 1929 if (rval == QLA_FUNCTION_FAILED) 1930 goto exit_error; 1931 1932 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 1933 ql_dbg(ql_dbg_p3p, vha, 0xb0ce, 1934 "Device state is 0x%x = %s\n", 1935 dev_state, dev_state < MAX_STATES ? 1936 qdev_state(dev_state) : "Unknown"); 1937 1938 /* wait for 30 seconds for device to go ready */ 1939 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 1940 1941 qla8044_idc_lock(ha); 1942 1943 while (1) { 1944 if (time_after_eq(jiffies, dev_init_timeout)) { 1945 if (qla8044_check_drv_active(vha) == QLA_SUCCESS) { 1946 ql_log(ql_log_warn, vha, 0xb0cf, 1947 "%s: Device Init Failed 0x%x = %s\n", 1948 QLA2XXX_DRIVER_NAME, dev_state, 1949 dev_state < MAX_STATES ? 1950 qdev_state(dev_state) : "Unknown"); 1951 qla8044_wr_direct(vha, 1952 QLA8044_CRB_DEV_STATE_INDEX, 1953 QLA8XXX_DEV_FAILED); 1954 } 1955 } 1956 1957 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 1958 ql_log(ql_log_info, vha, 0xb0d0, 1959 "Device state is 0x%x = %s\n", 1960 dev_state, dev_state < MAX_STATES ? 1961 qdev_state(dev_state) : "Unknown"); 1962 1963 /* NOTE: Make sure idc unlocked upon exit of switch statement */ 1964 switch (dev_state) { 1965 case QLA8XXX_DEV_READY: 1966 ha->flags.nic_core_reset_owner = 0; 1967 goto exit; 1968 case QLA8XXX_DEV_COLD: 1969 rval = qla8044_device_bootstrap(vha); 1970 break; 1971 case QLA8XXX_DEV_INITIALIZING: 1972 qla8044_idc_unlock(ha); 1973 msleep(1000); 1974 qla8044_idc_lock(ha); 1975 break; 1976 case QLA8XXX_DEV_NEED_RESET: 1977 /* For ISP8044, if NEED_RESET is set by any driver, 1978 * it should be honored, irrespective of IDC_CTRL 1979 * DONTRESET_BIT0 */ 1980 qla8044_need_reset_handler(vha); 1981 break; 1982 case QLA8XXX_DEV_NEED_QUIESCENT: 1983 /* idc locked/unlocked in handler */ 1984 qla8044_need_qsnt_handler(vha); 1985 1986 /* Reset the init timeout after qsnt handler */ 1987 dev_init_timeout = jiffies + 1988 (ha->fcoe_reset_timeout * HZ); 1989 break; 1990 case QLA8XXX_DEV_QUIESCENT: 1991 ql_log(ql_log_info, vha, 0xb0d1, 1992 "HW State: QUIESCENT\n"); 1993 1994 qla8044_idc_unlock(ha); 1995 msleep(1000); 1996 qla8044_idc_lock(ha); 1997 1998 /* Reset the init timeout after qsnt handler */ 1999 dev_init_timeout = jiffies + 2000 (ha->fcoe_reset_timeout * HZ); 2001 break; 2002 case QLA8XXX_DEV_FAILED: 2003 ha->flags.nic_core_reset_owner = 0; 2004 qla8044_idc_unlock(ha); 2005 qla8xxx_dev_failed_handler(vha); 2006 rval = QLA_FUNCTION_FAILED; 2007 qla8044_idc_lock(ha); 2008 goto exit; 2009 default: 2010 qla8044_idc_unlock(ha); 2011 qla8xxx_dev_failed_handler(vha); 2012 rval = QLA_FUNCTION_FAILED; 2013 qla8044_idc_lock(ha); 2014 goto exit; 2015 } 2016 } 2017 exit: 2018 qla8044_idc_unlock(ha); 2019 2020 exit_error: 2021 return rval; 2022 } 2023 2024 /** 2025 * qla4_8xxx_check_temp - Check the ISP82XX temperature. 2026 * @ha: adapter block pointer. 2027 * 2028 * Note: The caller should not hold the idc lock. 2029 **/ 2030 static int 2031 qla8044_check_temp(struct scsi_qla_host *vha) 2032 { 2033 uint32_t temp, temp_state, temp_val; 2034 int status = QLA_SUCCESS; 2035 2036 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX); 2037 temp_state = qla82xx_get_temp_state(temp); 2038 temp_val = qla82xx_get_temp_val(temp); 2039 2040 if (temp_state == QLA82XX_TEMP_PANIC) { 2041 ql_log(ql_log_warn, vha, 0xb0d2, 2042 "Device temperature %d degrees C" 2043 " exceeds maximum allowed. Hardware has been shut" 2044 " down\n", temp_val); 2045 status = QLA_FUNCTION_FAILED; 2046 return status; 2047 } else if (temp_state == QLA82XX_TEMP_WARN) { 2048 ql_log(ql_log_warn, vha, 0xb0d3, 2049 "Device temperature %d" 2050 " degrees C exceeds operating range." 2051 " Immediate action needed.\n", temp_val); 2052 } 2053 return 0; 2054 } 2055 2056 int qla8044_read_temperature(scsi_qla_host_t *vha) 2057 { 2058 uint32_t temp; 2059 2060 temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX); 2061 return qla82xx_get_temp_val(temp); 2062 } 2063 2064 /** 2065 * qla8044_check_fw_alive - Check firmware health 2066 * @ha: Pointer to host adapter structure. 2067 * 2068 * Context: Interrupt 2069 **/ 2070 int 2071 qla8044_check_fw_alive(struct scsi_qla_host *vha) 2072 { 2073 uint32_t fw_heartbeat_counter; 2074 uint32_t halt_status1, halt_status2; 2075 int status = QLA_SUCCESS; 2076 2077 fw_heartbeat_counter = qla8044_rd_direct(vha, 2078 QLA8044_PEG_ALIVE_COUNTER_INDEX); 2079 2080 /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */ 2081 if (fw_heartbeat_counter == 0xffffffff) { 2082 ql_dbg(ql_dbg_p3p, vha, 0xb0d4, 2083 "scsi%ld: %s: Device in frozen " 2084 "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n", 2085 vha->host_no, __func__); 2086 return status; 2087 } 2088 2089 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 2090 vha->seconds_since_last_heartbeat++; 2091 /* FW not alive after 2 seconds */ 2092 if (vha->seconds_since_last_heartbeat == 2) { 2093 vha->seconds_since_last_heartbeat = 0; 2094 halt_status1 = qla8044_rd_direct(vha, 2095 QLA8044_PEG_HALT_STATUS1_INDEX); 2096 halt_status2 = qla8044_rd_direct(vha, 2097 QLA8044_PEG_HALT_STATUS2_INDEX); 2098 2099 ql_log(ql_log_info, vha, 0xb0d5, 2100 "scsi(%ld): %s, ISP8044 " 2101 "Dumping hw/fw registers:\n" 2102 " PEG_HALT_STATUS1: 0x%x, " 2103 "PEG_HALT_STATUS2: 0x%x,\n", 2104 vha->host_no, __func__, halt_status1, 2105 halt_status2); 2106 status = QLA_FUNCTION_FAILED; 2107 } 2108 } else 2109 vha->seconds_since_last_heartbeat = 0; 2110 2111 vha->fw_heartbeat_counter = fw_heartbeat_counter; 2112 return status; 2113 } 2114 2115 void 2116 qla8044_watchdog(struct scsi_qla_host *vha) 2117 { 2118 uint32_t dev_state, halt_status; 2119 int halt_status_unrecoverable = 0; 2120 struct qla_hw_data *ha = vha->hw; 2121 2122 /* don't poll if reset is going on or FW hang in quiescent state */ 2123 if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) || 2124 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) { 2125 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 2126 2127 if (qla8044_check_temp(vha)) { 2128 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 2129 ha->flags.isp82xx_fw_hung = 1; 2130 qla2xxx_wake_dpc(vha); 2131 } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 2132 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 2133 ql_log(ql_log_info, vha, 0xb0d6, 2134 "%s: HW State: NEED RESET!\n", 2135 __func__); 2136 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2137 qla2xxx_wake_dpc(vha); 2138 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 2139 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 2140 ql_log(ql_log_info, vha, 0xb0d7, 2141 "%s: HW State: NEED QUIES detected!\n", 2142 __func__); 2143 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 2144 qla2xxx_wake_dpc(vha); 2145 } else { 2146 /* Check firmware health */ 2147 if (qla8044_check_fw_alive(vha)) { 2148 halt_status = qla8044_rd_direct(vha, 2149 QLA8044_PEG_HALT_STATUS1_INDEX); 2150 if (halt_status & 2151 QLA8044_HALT_STATUS_FW_RESET) { 2152 ql_log(ql_log_fatal, vha, 2153 0xb0d8, "%s: Firmware " 2154 "error detected device " 2155 "is being reset\n", 2156 __func__); 2157 } else if (halt_status & 2158 QLA8044_HALT_STATUS_UNRECOVERABLE) { 2159 halt_status_unrecoverable = 1; 2160 } 2161 2162 /* Since we cannot change dev_state in interrupt 2163 * context, set appropriate DPC flag then wakeup 2164 * DPC */ 2165 if (halt_status_unrecoverable) { 2166 set_bit(ISP_UNRECOVERABLE, 2167 &vha->dpc_flags); 2168 } else { 2169 if (dev_state == 2170 QLA8XXX_DEV_QUIESCENT) { 2171 set_bit(FCOE_CTX_RESET_NEEDED, 2172 &vha->dpc_flags); 2173 ql_log(ql_log_info, vha, 0xb0d9, 2174 "%s: FW CONTEXT Reset " 2175 "needed!\n", __func__); 2176 } else { 2177 ql_log(ql_log_info, vha, 2178 0xb0da, "%s: " 2179 "detect abort needed\n", 2180 __func__); 2181 set_bit(ISP_ABORT_NEEDED, 2182 &vha->dpc_flags); 2183 qla82xx_clear_pending_mbx(vha); 2184 } 2185 } 2186 ha->flags.isp82xx_fw_hung = 1; 2187 ql_log(ql_log_warn, vha, 0xb10a, 2188 "Firmware hung.\n"); 2189 qla2xxx_wake_dpc(vha); 2190 } 2191 } 2192 2193 } 2194 } 2195 2196 static int 2197 qla8044_minidump_process_control(struct scsi_qla_host *vha, 2198 struct qla8044_minidump_entry_hdr *entry_hdr) 2199 { 2200 struct qla8044_minidump_entry_crb *crb_entry; 2201 uint32_t read_value, opcode, poll_time, addr, index; 2202 uint32_t crb_addr, rval = QLA_SUCCESS; 2203 unsigned long wtime; 2204 struct qla8044_minidump_template_hdr *tmplt_hdr; 2205 int i; 2206 struct qla_hw_data *ha = vha->hw; 2207 2208 ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__); 2209 tmplt_hdr = (struct qla8044_minidump_template_hdr *) 2210 ha->md_tmplt_hdr; 2211 crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr; 2212 2213 crb_addr = crb_entry->addr; 2214 for (i = 0; i < crb_entry->op_count; i++) { 2215 opcode = crb_entry->crb_ctrl.opcode; 2216 2217 if (opcode & QLA82XX_DBG_OPCODE_WR) { 2218 qla8044_wr_reg_indirect(vha, crb_addr, 2219 crb_entry->value_1); 2220 opcode &= ~QLA82XX_DBG_OPCODE_WR; 2221 } 2222 2223 if (opcode & QLA82XX_DBG_OPCODE_RW) { 2224 qla8044_rd_reg_indirect(vha, crb_addr, &read_value); 2225 qla8044_wr_reg_indirect(vha, crb_addr, read_value); 2226 opcode &= ~QLA82XX_DBG_OPCODE_RW; 2227 } 2228 2229 if (opcode & QLA82XX_DBG_OPCODE_AND) { 2230 qla8044_rd_reg_indirect(vha, crb_addr, &read_value); 2231 read_value &= crb_entry->value_2; 2232 opcode &= ~QLA82XX_DBG_OPCODE_AND; 2233 if (opcode & QLA82XX_DBG_OPCODE_OR) { 2234 read_value |= crb_entry->value_3; 2235 opcode &= ~QLA82XX_DBG_OPCODE_OR; 2236 } 2237 qla8044_wr_reg_indirect(vha, crb_addr, read_value); 2238 } 2239 if (opcode & QLA82XX_DBG_OPCODE_OR) { 2240 qla8044_rd_reg_indirect(vha, crb_addr, &read_value); 2241 read_value |= crb_entry->value_3; 2242 qla8044_wr_reg_indirect(vha, crb_addr, read_value); 2243 opcode &= ~QLA82XX_DBG_OPCODE_OR; 2244 } 2245 if (opcode & QLA82XX_DBG_OPCODE_POLL) { 2246 poll_time = crb_entry->crb_strd.poll_timeout; 2247 wtime = jiffies + poll_time; 2248 qla8044_rd_reg_indirect(vha, crb_addr, &read_value); 2249 2250 do { 2251 if ((read_value & crb_entry->value_2) == 2252 crb_entry->value_1) { 2253 break; 2254 } else if (time_after_eq(jiffies, wtime)) { 2255 /* capturing dump failed */ 2256 rval = QLA_FUNCTION_FAILED; 2257 break; 2258 } else { 2259 qla8044_rd_reg_indirect(vha, 2260 crb_addr, &read_value); 2261 } 2262 } while (1); 2263 opcode &= ~QLA82XX_DBG_OPCODE_POLL; 2264 } 2265 2266 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 2267 if (crb_entry->crb_strd.state_index_a) { 2268 index = crb_entry->crb_strd.state_index_a; 2269 addr = tmplt_hdr->saved_state_array[index]; 2270 } else { 2271 addr = crb_addr; 2272 } 2273 2274 qla8044_rd_reg_indirect(vha, addr, &read_value); 2275 index = crb_entry->crb_ctrl.state_index_v; 2276 tmplt_hdr->saved_state_array[index] = read_value; 2277 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 2278 } 2279 2280 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 2281 if (crb_entry->crb_strd.state_index_a) { 2282 index = crb_entry->crb_strd.state_index_a; 2283 addr = tmplt_hdr->saved_state_array[index]; 2284 } else { 2285 addr = crb_addr; 2286 } 2287 2288 if (crb_entry->crb_ctrl.state_index_v) { 2289 index = crb_entry->crb_ctrl.state_index_v; 2290 read_value = 2291 tmplt_hdr->saved_state_array[index]; 2292 } else { 2293 read_value = crb_entry->value_1; 2294 } 2295 2296 qla8044_wr_reg_indirect(vha, addr, read_value); 2297 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 2298 } 2299 2300 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 2301 index = crb_entry->crb_ctrl.state_index_v; 2302 read_value = tmplt_hdr->saved_state_array[index]; 2303 read_value <<= crb_entry->crb_ctrl.shl; 2304 read_value >>= crb_entry->crb_ctrl.shr; 2305 if (crb_entry->value_2) 2306 read_value &= crb_entry->value_2; 2307 read_value |= crb_entry->value_3; 2308 read_value += crb_entry->value_1; 2309 tmplt_hdr->saved_state_array[index] = read_value; 2310 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 2311 } 2312 crb_addr += crb_entry->crb_strd.addr_stride; 2313 } 2314 return rval; 2315 } 2316 2317 static void 2318 qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha, 2319 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2320 { 2321 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 2322 struct qla8044_minidump_entry_crb *crb_hdr; 2323 uint32_t *data_ptr = *d_ptr; 2324 2325 ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__); 2326 crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr; 2327 r_addr = crb_hdr->addr; 2328 r_stride = crb_hdr->crb_strd.addr_stride; 2329 loop_cnt = crb_hdr->op_count; 2330 2331 for (i = 0; i < loop_cnt; i++) { 2332 qla8044_rd_reg_indirect(vha, r_addr, &r_value); 2333 *data_ptr++ = r_addr; 2334 *data_ptr++ = r_value; 2335 r_addr += r_stride; 2336 } 2337 *d_ptr = data_ptr; 2338 } 2339 2340 static int 2341 qla8044_minidump_process_rdmem(struct scsi_qla_host *vha, 2342 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2343 { 2344 uint32_t r_addr, r_value, r_data; 2345 uint32_t i, j, loop_cnt; 2346 struct qla8044_minidump_entry_rdmem *m_hdr; 2347 unsigned long flags; 2348 uint32_t *data_ptr = *d_ptr; 2349 struct qla_hw_data *ha = vha->hw; 2350 2351 ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__); 2352 m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr; 2353 r_addr = m_hdr->read_addr; 2354 loop_cnt = m_hdr->read_data_size/16; 2355 2356 ql_dbg(ql_dbg_p3p, vha, 0xb0f0, 2357 "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", 2358 __func__, r_addr, m_hdr->read_data_size); 2359 2360 if (r_addr & 0xf) { 2361 ql_dbg(ql_dbg_p3p, vha, 0xb0f1, 2362 "[%s]: Read addr 0x%x not 16 bytes aligned\n", 2363 __func__, r_addr); 2364 return QLA_FUNCTION_FAILED; 2365 } 2366 2367 if (m_hdr->read_data_size % 16) { 2368 ql_dbg(ql_dbg_p3p, vha, 0xb0f2, 2369 "[%s]: Read data[0x%x] not multiple of 16 bytes\n", 2370 __func__, m_hdr->read_data_size); 2371 return QLA_FUNCTION_FAILED; 2372 } 2373 2374 ql_dbg(ql_dbg_p3p, vha, 0xb0f3, 2375 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 2376 __func__, r_addr, m_hdr->read_data_size, loop_cnt); 2377 2378 write_lock_irqsave(&ha->hw_lock, flags); 2379 for (i = 0; i < loop_cnt; i++) { 2380 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr); 2381 r_value = 0; 2382 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value); 2383 r_value = MIU_TA_CTL_ENABLE; 2384 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value); 2385 r_value = MIU_TA_CTL_START_ENABLE; 2386 qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value); 2387 2388 for (j = 0; j < MAX_CTL_CHECK; j++) { 2389 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, 2390 &r_value); 2391 if ((r_value & MIU_TA_CTL_BUSY) == 0) 2392 break; 2393 } 2394 2395 if (j >= MAX_CTL_CHECK) { 2396 printk_ratelimited(KERN_ERR 2397 "%s: failed to read through agent\n", __func__); 2398 write_unlock_irqrestore(&ha->hw_lock, flags); 2399 return QLA_SUCCESS; 2400 } 2401 2402 for (j = 0; j < 4; j++) { 2403 qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j], 2404 &r_data); 2405 *data_ptr++ = r_data; 2406 } 2407 2408 r_addr += 16; 2409 } 2410 write_unlock_irqrestore(&ha->hw_lock, flags); 2411 2412 ql_dbg(ql_dbg_p3p, vha, 0xb0f4, 2413 "Leaving fn: %s datacount: 0x%x\n", 2414 __func__, (loop_cnt * 16)); 2415 2416 *d_ptr = data_ptr; 2417 return QLA_SUCCESS; 2418 } 2419 2420 /* ISP83xx flash read for _RDROM _BOARD */ 2421 static uint32_t 2422 qla8044_minidump_process_rdrom(struct scsi_qla_host *vha, 2423 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2424 { 2425 uint32_t fl_addr, u32_count, rval; 2426 struct qla8044_minidump_entry_rdrom *rom_hdr; 2427 uint32_t *data_ptr = *d_ptr; 2428 2429 rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr; 2430 fl_addr = rom_hdr->read_addr; 2431 u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t); 2432 2433 ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n", 2434 __func__, fl_addr, u32_count); 2435 2436 rval = qla8044_lockless_flash_read_u32(vha, fl_addr, 2437 (u8 *)(data_ptr), u32_count); 2438 2439 if (rval != QLA_SUCCESS) { 2440 ql_log(ql_log_fatal, vha, 0xb0f6, 2441 "%s: Flash Read Error,Count=%d\n", __func__, u32_count); 2442 return QLA_FUNCTION_FAILED; 2443 } else { 2444 data_ptr += u32_count; 2445 *d_ptr = data_ptr; 2446 return QLA_SUCCESS; 2447 } 2448 } 2449 2450 static void 2451 qla8044_mark_entry_skipped(struct scsi_qla_host *vha, 2452 struct qla8044_minidump_entry_hdr *entry_hdr, int index) 2453 { 2454 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 2455 2456 ql_log(ql_log_info, vha, 0xb0f7, 2457 "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", 2458 vha->host_no, index, entry_hdr->entry_type, 2459 entry_hdr->d_ctrl.entry_capture_mask); 2460 } 2461 2462 static int 2463 qla8044_minidump_process_l2tag(struct scsi_qla_host *vha, 2464 struct qla8044_minidump_entry_hdr *entry_hdr, 2465 uint32_t **d_ptr) 2466 { 2467 uint32_t addr, r_addr, c_addr, t_r_addr; 2468 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 2469 unsigned long p_wait, w_time, p_mask; 2470 uint32_t c_value_w, c_value_r; 2471 struct qla8044_minidump_entry_cache *cache_hdr; 2472 int rval = QLA_FUNCTION_FAILED; 2473 uint32_t *data_ptr = *d_ptr; 2474 2475 ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__); 2476 cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr; 2477 2478 loop_count = cache_hdr->op_count; 2479 r_addr = cache_hdr->read_addr; 2480 c_addr = cache_hdr->control_addr; 2481 c_value_w = cache_hdr->cache_ctrl.write_value; 2482 2483 t_r_addr = cache_hdr->tag_reg_addr; 2484 t_value = cache_hdr->addr_ctrl.init_tag_value; 2485 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 2486 p_wait = cache_hdr->cache_ctrl.poll_wait; 2487 p_mask = cache_hdr->cache_ctrl.poll_mask; 2488 2489 for (i = 0; i < loop_count; i++) { 2490 qla8044_wr_reg_indirect(vha, t_r_addr, t_value); 2491 if (c_value_w) 2492 qla8044_wr_reg_indirect(vha, c_addr, c_value_w); 2493 2494 if (p_mask) { 2495 w_time = jiffies + p_wait; 2496 do { 2497 qla8044_rd_reg_indirect(vha, c_addr, 2498 &c_value_r); 2499 if ((c_value_r & p_mask) == 0) { 2500 break; 2501 } else if (time_after_eq(jiffies, w_time)) { 2502 /* capturing dump failed */ 2503 return rval; 2504 } 2505 } while (1); 2506 } 2507 2508 addr = r_addr; 2509 for (k = 0; k < r_cnt; k++) { 2510 qla8044_rd_reg_indirect(vha, addr, &r_value); 2511 *data_ptr++ = r_value; 2512 addr += cache_hdr->read_ctrl.read_addr_stride; 2513 } 2514 t_value += cache_hdr->addr_ctrl.tag_value_stride; 2515 } 2516 *d_ptr = data_ptr; 2517 return QLA_SUCCESS; 2518 } 2519 2520 static void 2521 qla8044_minidump_process_l1cache(struct scsi_qla_host *vha, 2522 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2523 { 2524 uint32_t addr, r_addr, c_addr, t_r_addr; 2525 uint32_t i, k, loop_count, t_value, r_cnt, r_value; 2526 uint32_t c_value_w; 2527 struct qla8044_minidump_entry_cache *cache_hdr; 2528 uint32_t *data_ptr = *d_ptr; 2529 2530 cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr; 2531 loop_count = cache_hdr->op_count; 2532 r_addr = cache_hdr->read_addr; 2533 c_addr = cache_hdr->control_addr; 2534 c_value_w = cache_hdr->cache_ctrl.write_value; 2535 2536 t_r_addr = cache_hdr->tag_reg_addr; 2537 t_value = cache_hdr->addr_ctrl.init_tag_value; 2538 r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 2539 2540 for (i = 0; i < loop_count; i++) { 2541 qla8044_wr_reg_indirect(vha, t_r_addr, t_value); 2542 qla8044_wr_reg_indirect(vha, c_addr, c_value_w); 2543 addr = r_addr; 2544 for (k = 0; k < r_cnt; k++) { 2545 qla8044_rd_reg_indirect(vha, addr, &r_value); 2546 *data_ptr++ = r_value; 2547 addr += cache_hdr->read_ctrl.read_addr_stride; 2548 } 2549 t_value += cache_hdr->addr_ctrl.tag_value_stride; 2550 } 2551 *d_ptr = data_ptr; 2552 } 2553 2554 static void 2555 qla8044_minidump_process_rdocm(struct scsi_qla_host *vha, 2556 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2557 { 2558 uint32_t r_addr, r_stride, loop_cnt, i, r_value; 2559 struct qla8044_minidump_entry_rdocm *ocm_hdr; 2560 uint32_t *data_ptr = *d_ptr; 2561 struct qla_hw_data *ha = vha->hw; 2562 2563 ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__); 2564 2565 ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr; 2566 r_addr = ocm_hdr->read_addr; 2567 r_stride = ocm_hdr->read_addr_stride; 2568 loop_cnt = ocm_hdr->op_count; 2569 2570 ql_dbg(ql_dbg_p3p, vha, 0xb0fa, 2571 "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", 2572 __func__, r_addr, r_stride, loop_cnt); 2573 2574 for (i = 0; i < loop_cnt; i++) { 2575 r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); 2576 *data_ptr++ = r_value; 2577 r_addr += r_stride; 2578 } 2579 ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n", 2580 __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))); 2581 2582 *d_ptr = data_ptr; 2583 } 2584 2585 static void 2586 qla8044_minidump_process_rdmux(struct scsi_qla_host *vha, 2587 struct qla8044_minidump_entry_hdr *entry_hdr, 2588 uint32_t **d_ptr) 2589 { 2590 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 2591 struct qla8044_minidump_entry_mux *mux_hdr; 2592 uint32_t *data_ptr = *d_ptr; 2593 2594 ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__); 2595 2596 mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr; 2597 r_addr = mux_hdr->read_addr; 2598 s_addr = mux_hdr->select_addr; 2599 s_stride = mux_hdr->select_value_stride; 2600 s_value = mux_hdr->select_value; 2601 loop_cnt = mux_hdr->op_count; 2602 2603 for (i = 0; i < loop_cnt; i++) { 2604 qla8044_wr_reg_indirect(vha, s_addr, s_value); 2605 qla8044_rd_reg_indirect(vha, r_addr, &r_value); 2606 *data_ptr++ = s_value; 2607 *data_ptr++ = r_value; 2608 s_value += s_stride; 2609 } 2610 *d_ptr = data_ptr; 2611 } 2612 2613 static void 2614 qla8044_minidump_process_queue(struct scsi_qla_host *vha, 2615 struct qla8044_minidump_entry_hdr *entry_hdr, 2616 uint32_t **d_ptr) 2617 { 2618 uint32_t s_addr, r_addr; 2619 uint32_t r_stride, r_value, r_cnt, qid = 0; 2620 uint32_t i, k, loop_cnt; 2621 struct qla8044_minidump_entry_queue *q_hdr; 2622 uint32_t *data_ptr = *d_ptr; 2623 2624 ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__); 2625 q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr; 2626 s_addr = q_hdr->select_addr; 2627 r_cnt = q_hdr->rd_strd.read_addr_cnt; 2628 r_stride = q_hdr->rd_strd.read_addr_stride; 2629 loop_cnt = q_hdr->op_count; 2630 2631 for (i = 0; i < loop_cnt; i++) { 2632 qla8044_wr_reg_indirect(vha, s_addr, qid); 2633 r_addr = q_hdr->read_addr; 2634 for (k = 0; k < r_cnt; k++) { 2635 qla8044_rd_reg_indirect(vha, r_addr, &r_value); 2636 *data_ptr++ = r_value; 2637 r_addr += r_stride; 2638 } 2639 qid += q_hdr->q_strd.queue_id_stride; 2640 } 2641 *d_ptr = data_ptr; 2642 } 2643 2644 /* ISP83xx functions to process new minidump entries... */ 2645 static uint32_t 2646 qla8044_minidump_process_pollrd(struct scsi_qla_host *vha, 2647 struct qla8044_minidump_entry_hdr *entry_hdr, 2648 uint32_t **d_ptr) 2649 { 2650 uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask; 2651 uint16_t s_stride, i; 2652 struct qla8044_minidump_entry_pollrd *pollrd_hdr; 2653 uint32_t *data_ptr = *d_ptr; 2654 2655 pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr; 2656 s_addr = pollrd_hdr->select_addr; 2657 r_addr = pollrd_hdr->read_addr; 2658 s_value = pollrd_hdr->select_value; 2659 s_stride = pollrd_hdr->select_value_stride; 2660 2661 poll_wait = pollrd_hdr->poll_wait; 2662 poll_mask = pollrd_hdr->poll_mask; 2663 2664 for (i = 0; i < pollrd_hdr->op_count; i++) { 2665 qla8044_wr_reg_indirect(vha, s_addr, s_value); 2666 poll_wait = pollrd_hdr->poll_wait; 2667 while (1) { 2668 qla8044_rd_reg_indirect(vha, s_addr, &r_value); 2669 if ((r_value & poll_mask) != 0) { 2670 break; 2671 } else { 2672 usleep_range(1000, 1100); 2673 if (--poll_wait == 0) { 2674 ql_log(ql_log_fatal, vha, 0xb0fe, 2675 "%s: TIMEOUT\n", __func__); 2676 goto error; 2677 } 2678 } 2679 } 2680 qla8044_rd_reg_indirect(vha, r_addr, &r_value); 2681 *data_ptr++ = s_value; 2682 *data_ptr++ = r_value; 2683 2684 s_value += s_stride; 2685 } 2686 *d_ptr = data_ptr; 2687 return QLA_SUCCESS; 2688 2689 error: 2690 return QLA_FUNCTION_FAILED; 2691 } 2692 2693 static void 2694 qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha, 2695 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2696 { 2697 uint32_t sel_val1, sel_val2, t_sel_val, data, i; 2698 uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr; 2699 struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr; 2700 uint32_t *data_ptr = *d_ptr; 2701 2702 rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr; 2703 sel_val1 = rdmux2_hdr->select_value_1; 2704 sel_val2 = rdmux2_hdr->select_value_2; 2705 sel_addr1 = rdmux2_hdr->select_addr_1; 2706 sel_addr2 = rdmux2_hdr->select_addr_2; 2707 sel_val_mask = rdmux2_hdr->select_value_mask; 2708 read_addr = rdmux2_hdr->read_addr; 2709 2710 for (i = 0; i < rdmux2_hdr->op_count; i++) { 2711 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1); 2712 t_sel_val = sel_val1 & sel_val_mask; 2713 *data_ptr++ = t_sel_val; 2714 2715 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val); 2716 qla8044_rd_reg_indirect(vha, read_addr, &data); 2717 2718 *data_ptr++ = data; 2719 2720 qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2); 2721 t_sel_val = sel_val2 & sel_val_mask; 2722 *data_ptr++ = t_sel_val; 2723 2724 qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val); 2725 qla8044_rd_reg_indirect(vha, read_addr, &data); 2726 2727 *data_ptr++ = data; 2728 2729 sel_val1 += rdmux2_hdr->select_value_stride; 2730 sel_val2 += rdmux2_hdr->select_value_stride; 2731 } 2732 2733 *d_ptr = data_ptr; 2734 } 2735 2736 static uint32_t 2737 qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha, 2738 struct qla8044_minidump_entry_hdr *entry_hdr, 2739 uint32_t **d_ptr) 2740 { 2741 uint32_t poll_wait, poll_mask, r_value, data; 2742 uint32_t addr_1, addr_2, value_1, value_2; 2743 struct qla8044_minidump_entry_pollrdmwr *poll_hdr; 2744 uint32_t *data_ptr = *d_ptr; 2745 2746 poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr; 2747 addr_1 = poll_hdr->addr_1; 2748 addr_2 = poll_hdr->addr_2; 2749 value_1 = poll_hdr->value_1; 2750 value_2 = poll_hdr->value_2; 2751 poll_mask = poll_hdr->poll_mask; 2752 2753 qla8044_wr_reg_indirect(vha, addr_1, value_1); 2754 2755 poll_wait = poll_hdr->poll_wait; 2756 while (1) { 2757 qla8044_rd_reg_indirect(vha, addr_1, &r_value); 2758 2759 if ((r_value & poll_mask) != 0) { 2760 break; 2761 } else { 2762 usleep_range(1000, 1100); 2763 if (--poll_wait == 0) { 2764 ql_log(ql_log_fatal, vha, 0xb0ff, 2765 "%s: TIMEOUT\n", __func__); 2766 goto error; 2767 } 2768 } 2769 } 2770 2771 qla8044_rd_reg_indirect(vha, addr_2, &data); 2772 data &= poll_hdr->modify_mask; 2773 qla8044_wr_reg_indirect(vha, addr_2, data); 2774 qla8044_wr_reg_indirect(vha, addr_1, value_2); 2775 2776 poll_wait = poll_hdr->poll_wait; 2777 while (1) { 2778 qla8044_rd_reg_indirect(vha, addr_1, &r_value); 2779 2780 if ((r_value & poll_mask) != 0) { 2781 break; 2782 } else { 2783 usleep_range(1000, 1100); 2784 if (--poll_wait == 0) { 2785 ql_log(ql_log_fatal, vha, 0xb100, 2786 "%s: TIMEOUT2\n", __func__); 2787 goto error; 2788 } 2789 } 2790 } 2791 2792 *data_ptr++ = addr_2; 2793 *data_ptr++ = data; 2794 2795 *d_ptr = data_ptr; 2796 2797 return QLA_SUCCESS; 2798 2799 error: 2800 return QLA_FUNCTION_FAILED; 2801 } 2802 2803 #define ISP8044_PEX_DMA_ENGINE_INDEX 8 2804 #define ISP8044_PEX_DMA_BASE_ADDRESS 0x77320000 2805 #define ISP8044_PEX_DMA_NUM_OFFSET 0x10000 2806 #define ISP8044_PEX_DMA_CMD_ADDR_LOW 0x0 2807 #define ISP8044_PEX_DMA_CMD_ADDR_HIGH 0x04 2808 #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL 0x08 2809 2810 #define ISP8044_PEX_DMA_READ_SIZE (16 * 1024) 2811 #define ISP8044_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */ 2812 2813 static int 2814 qla8044_check_dma_engine_state(struct scsi_qla_host *vha) 2815 { 2816 struct qla_hw_data *ha = vha->hw; 2817 int rval = QLA_SUCCESS; 2818 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 2819 uint64_t dma_base_addr = 0; 2820 struct qla8044_minidump_template_hdr *tmplt_hdr = NULL; 2821 2822 tmplt_hdr = ha->md_tmplt_hdr; 2823 dma_eng_num = 2824 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX]; 2825 dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS + 2826 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET); 2827 2828 /* Read the pex-dma's command-status-and-control register. */ 2829 rval = qla8044_rd_reg_indirect(vha, 2830 (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL), 2831 &cmd_sts_and_cntrl); 2832 if (rval) 2833 return QLA_FUNCTION_FAILED; 2834 2835 /* Check if requested pex-dma engine is available. */ 2836 if (cmd_sts_and_cntrl & BIT_31) 2837 return QLA_SUCCESS; 2838 2839 return QLA_FUNCTION_FAILED; 2840 } 2841 2842 static int 2843 qla8044_start_pex_dma(struct scsi_qla_host *vha, 2844 struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr) 2845 { 2846 struct qla_hw_data *ha = vha->hw; 2847 int rval = QLA_SUCCESS, wait = 0; 2848 uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 2849 uint64_t dma_base_addr = 0; 2850 struct qla8044_minidump_template_hdr *tmplt_hdr = NULL; 2851 2852 tmplt_hdr = ha->md_tmplt_hdr; 2853 dma_eng_num = 2854 tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX]; 2855 dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS + 2856 (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET); 2857 2858 rval = qla8044_wr_reg_indirect(vha, 2859 dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW, 2860 m_hdr->desc_card_addr); 2861 if (rval) 2862 goto error_exit; 2863 2864 rval = qla8044_wr_reg_indirect(vha, 2865 dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0); 2866 if (rval) 2867 goto error_exit; 2868 2869 rval = qla8044_wr_reg_indirect(vha, 2870 dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL, 2871 m_hdr->start_dma_cmd); 2872 if (rval) 2873 goto error_exit; 2874 2875 /* Wait for dma operation to complete. */ 2876 for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) { 2877 rval = qla8044_rd_reg_indirect(vha, 2878 (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL), 2879 &cmd_sts_and_cntrl); 2880 if (rval) 2881 goto error_exit; 2882 2883 if ((cmd_sts_and_cntrl & BIT_1) == 0) 2884 break; 2885 2886 udelay(10); 2887 } 2888 2889 /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */ 2890 if (wait >= ISP8044_PEX_DMA_MAX_WAIT) { 2891 rval = QLA_FUNCTION_FAILED; 2892 goto error_exit; 2893 } 2894 2895 error_exit: 2896 return rval; 2897 } 2898 2899 static int 2900 qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha, 2901 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2902 { 2903 struct qla_hw_data *ha = vha->hw; 2904 int rval = QLA_SUCCESS; 2905 struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL; 2906 uint32_t chunk_size, read_size; 2907 uint8_t *data_ptr = (uint8_t *)*d_ptr; 2908 void *rdmem_buffer = NULL; 2909 dma_addr_t rdmem_dma; 2910 struct qla8044_pex_dma_descriptor dma_desc; 2911 2912 rval = qla8044_check_dma_engine_state(vha); 2913 if (rval != QLA_SUCCESS) { 2914 ql_dbg(ql_dbg_p3p, vha, 0xb147, 2915 "DMA engine not available. Fallback to rdmem-read.\n"); 2916 return QLA_FUNCTION_FAILED; 2917 } 2918 2919 m_hdr = (void *)entry_hdr; 2920 2921 rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, 2922 ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL); 2923 if (!rdmem_buffer) { 2924 ql_dbg(ql_dbg_p3p, vha, 0xb148, 2925 "Unable to allocate rdmem dma buffer\n"); 2926 return QLA_FUNCTION_FAILED; 2927 } 2928 2929 /* Prepare pex-dma descriptor to be written to MS memory. */ 2930 /* dma-desc-cmd layout: 2931 * 0-3: dma-desc-cmd 0-3 2932 * 4-7: pcid function number 2933 * 8-15: dma-desc-cmd 8-15 2934 * dma_bus_addr: dma buffer address 2935 * cmd.read_data_size: amount of data-chunk to be read. 2936 */ 2937 dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f); 2938 dma_desc.cmd.dma_desc_cmd |= 2939 ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4); 2940 2941 dma_desc.dma_bus_addr = rdmem_dma; 2942 dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE; 2943 read_size = 0; 2944 2945 /* 2946 * Perform rdmem operation using pex-dma. 2947 * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE. 2948 */ 2949 while (read_size < m_hdr->read_data_size) { 2950 if (m_hdr->read_data_size - read_size < 2951 ISP8044_PEX_DMA_READ_SIZE) { 2952 chunk_size = (m_hdr->read_data_size - read_size); 2953 dma_desc.cmd.read_data_size = chunk_size; 2954 } 2955 2956 dma_desc.src_addr = m_hdr->read_addr + read_size; 2957 2958 /* Prepare: Write pex-dma descriptor to MS memory. */ 2959 rval = qla8044_ms_mem_write_128b(vha, 2960 m_hdr->desc_card_addr, (void *)&dma_desc, 2961 (sizeof(struct qla8044_pex_dma_descriptor)/16)); 2962 if (rval) { 2963 ql_log(ql_log_warn, vha, 0xb14a, 2964 "%s: Error writing rdmem-dma-init to MS !!!\n", 2965 __func__); 2966 goto error_exit; 2967 } 2968 ql_dbg(ql_dbg_p3p, vha, 0xb14b, 2969 "%s: Dma-descriptor: Instruct for rdmem dma " 2970 "(chunk_size 0x%x).\n", __func__, chunk_size); 2971 2972 /* Execute: Start pex-dma operation. */ 2973 rval = qla8044_start_pex_dma(vha, m_hdr); 2974 if (rval) 2975 goto error_exit; 2976 2977 memcpy(data_ptr, rdmem_buffer, chunk_size); 2978 data_ptr += chunk_size; 2979 read_size += chunk_size; 2980 } 2981 2982 *d_ptr = (void *)data_ptr; 2983 2984 error_exit: 2985 if (rdmem_buffer) 2986 dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE, 2987 rdmem_buffer, rdmem_dma); 2988 2989 return rval; 2990 } 2991 2992 static uint32_t 2993 qla8044_minidump_process_rddfe(struct scsi_qla_host *vha, 2994 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 2995 { 2996 int loop_cnt; 2997 uint32_t addr1, addr2, value, data, temp, wrVal; 2998 uint8_t stride, stride2; 2999 uint16_t count; 3000 uint32_t poll, mask, data_size, modify_mask; 3001 uint32_t wait_count = 0; 3002 3003 uint32_t *data_ptr = *d_ptr; 3004 3005 struct qla8044_minidump_entry_rddfe *rddfe; 3006 rddfe = (struct qla8044_minidump_entry_rddfe *) entry_hdr; 3007 3008 addr1 = rddfe->addr_1; 3009 value = rddfe->value; 3010 stride = rddfe->stride; 3011 stride2 = rddfe->stride2; 3012 count = rddfe->count; 3013 3014 poll = rddfe->poll; 3015 mask = rddfe->mask; 3016 modify_mask = rddfe->modify_mask; 3017 data_size = rddfe->data_size; 3018 3019 addr2 = addr1 + stride; 3020 3021 for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) { 3022 qla8044_wr_reg_indirect(vha, addr1, (0x40000000 | value)); 3023 3024 wait_count = 0; 3025 while (wait_count < poll) { 3026 qla8044_rd_reg_indirect(vha, addr1, &temp); 3027 if ((temp & mask) != 0) 3028 break; 3029 wait_count++; 3030 } 3031 3032 if (wait_count == poll) { 3033 ql_log(ql_log_warn, vha, 0xb153, 3034 "%s: TIMEOUT\n", __func__); 3035 goto error; 3036 } else { 3037 qla8044_rd_reg_indirect(vha, addr2, &temp); 3038 temp = temp & modify_mask; 3039 temp = (temp | ((loop_cnt << 16) | loop_cnt)); 3040 wrVal = ((temp << 16) | temp); 3041 3042 qla8044_wr_reg_indirect(vha, addr2, wrVal); 3043 qla8044_wr_reg_indirect(vha, addr1, value); 3044 3045 wait_count = 0; 3046 while (wait_count < poll) { 3047 qla8044_rd_reg_indirect(vha, addr1, &temp); 3048 if ((temp & mask) != 0) 3049 break; 3050 wait_count++; 3051 } 3052 if (wait_count == poll) { 3053 ql_log(ql_log_warn, vha, 0xb154, 3054 "%s: TIMEOUT\n", __func__); 3055 goto error; 3056 } 3057 3058 qla8044_wr_reg_indirect(vha, addr1, 3059 ((0x40000000 | value) + stride2)); 3060 wait_count = 0; 3061 while (wait_count < poll) { 3062 qla8044_rd_reg_indirect(vha, addr1, &temp); 3063 if ((temp & mask) != 0) 3064 break; 3065 wait_count++; 3066 } 3067 3068 if (wait_count == poll) { 3069 ql_log(ql_log_warn, vha, 0xb155, 3070 "%s: TIMEOUT\n", __func__); 3071 goto error; 3072 } 3073 3074 qla8044_rd_reg_indirect(vha, addr2, &data); 3075 3076 *data_ptr++ = wrVal; 3077 *data_ptr++ = data; 3078 } 3079 3080 } 3081 3082 *d_ptr = data_ptr; 3083 return QLA_SUCCESS; 3084 3085 error: 3086 return -1; 3087 3088 } 3089 3090 static uint32_t 3091 qla8044_minidump_process_rdmdio(struct scsi_qla_host *vha, 3092 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 3093 { 3094 int ret = 0; 3095 uint32_t addr1, addr2, value1, value2, data, selVal; 3096 uint8_t stride1, stride2; 3097 uint32_t addr3, addr4, addr5, addr6, addr7; 3098 uint16_t count, loop_cnt; 3099 uint32_t poll, mask; 3100 uint32_t *data_ptr = *d_ptr; 3101 3102 struct qla8044_minidump_entry_rdmdio *rdmdio; 3103 3104 rdmdio = (struct qla8044_minidump_entry_rdmdio *) entry_hdr; 3105 3106 addr1 = rdmdio->addr_1; 3107 addr2 = rdmdio->addr_2; 3108 value1 = rdmdio->value_1; 3109 stride1 = rdmdio->stride_1; 3110 stride2 = rdmdio->stride_2; 3111 count = rdmdio->count; 3112 3113 poll = rdmdio->poll; 3114 mask = rdmdio->mask; 3115 value2 = rdmdio->value_2; 3116 3117 addr3 = addr1 + stride1; 3118 3119 for (loop_cnt = 0; loop_cnt < count; loop_cnt++) { 3120 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2, 3121 addr3, mask); 3122 if (ret == -1) 3123 goto error; 3124 3125 addr4 = addr2 - stride1; 3126 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr4, 3127 value2); 3128 if (ret == -1) 3129 goto error; 3130 3131 addr5 = addr2 - (2 * stride1); 3132 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr5, 3133 value1); 3134 if (ret == -1) 3135 goto error; 3136 3137 addr6 = addr2 - (3 * stride1); 3138 ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, 3139 addr6, 0x2); 3140 if (ret == -1) 3141 goto error; 3142 3143 ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2, 3144 addr3, mask); 3145 if (ret == -1) 3146 goto error; 3147 3148 addr7 = addr2 - (4 * stride1); 3149 data = qla8044_ipmdio_rd_reg(vha, addr1, addr3, 3150 mask, addr7); 3151 if (data == -1) 3152 goto error; 3153 3154 selVal = (value2 << 18) | (value1 << 2) | 2; 3155 3156 stride2 = rdmdio->stride_2; 3157 *data_ptr++ = selVal; 3158 *data_ptr++ = data; 3159 3160 value1 = value1 + stride2; 3161 *d_ptr = data_ptr; 3162 } 3163 3164 return 0; 3165 3166 error: 3167 return -1; 3168 } 3169 3170 static uint32_t qla8044_minidump_process_pollwr(struct scsi_qla_host *vha, 3171 struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 3172 { 3173 uint32_t addr1, addr2, value1, value2, poll, mask, r_value; 3174 uint32_t wait_count = 0; 3175 struct qla8044_minidump_entry_pollwr *pollwr_hdr; 3176 3177 pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr; 3178 addr1 = pollwr_hdr->addr_1; 3179 addr2 = pollwr_hdr->addr_2; 3180 value1 = pollwr_hdr->value_1; 3181 value2 = pollwr_hdr->value_2; 3182 3183 poll = pollwr_hdr->poll; 3184 mask = pollwr_hdr->mask; 3185 3186 while (wait_count < poll) { 3187 qla8044_rd_reg_indirect(vha, addr1, &r_value); 3188 3189 if ((r_value & poll) != 0) 3190 break; 3191 wait_count++; 3192 } 3193 3194 if (wait_count == poll) { 3195 ql_log(ql_log_warn, vha, 0xb156, "%s: TIMEOUT\n", __func__); 3196 goto error; 3197 } 3198 3199 qla8044_wr_reg_indirect(vha, addr2, value2); 3200 qla8044_wr_reg_indirect(vha, addr1, value1); 3201 3202 wait_count = 0; 3203 while (wait_count < poll) { 3204 qla8044_rd_reg_indirect(vha, addr1, &r_value); 3205 3206 if ((r_value & poll) != 0) 3207 break; 3208 wait_count++; 3209 } 3210 3211 return QLA_SUCCESS; 3212 3213 error: 3214 return -1; 3215 } 3216 3217 /* 3218 * 3219 * qla8044_collect_md_data - Retrieve firmware minidump data. 3220 * @ha: pointer to adapter structure 3221 **/ 3222 int 3223 qla8044_collect_md_data(struct scsi_qla_host *vha) 3224 { 3225 int num_entry_hdr = 0; 3226 struct qla8044_minidump_entry_hdr *entry_hdr; 3227 struct qla8044_minidump_template_hdr *tmplt_hdr; 3228 uint32_t *data_ptr; 3229 uint32_t data_collected = 0, f_capture_mask; 3230 int i, rval = QLA_FUNCTION_FAILED; 3231 uint64_t now; 3232 uint32_t timestamp, idc_control; 3233 struct qla_hw_data *ha = vha->hw; 3234 3235 if (!ha->md_dump) { 3236 ql_log(ql_log_info, vha, 0xb101, 3237 "%s(%ld) No buffer to dump\n", 3238 __func__, vha->host_no); 3239 return rval; 3240 } 3241 3242 if (ha->fw_dumped) { 3243 ql_log(ql_log_warn, vha, 0xb10d, 3244 "Firmware has been previously dumped (%p) " 3245 "-- ignoring request.\n", ha->fw_dump); 3246 goto md_failed; 3247 } 3248 3249 ha->fw_dumped = 0; 3250 3251 if (!ha->md_tmplt_hdr || !ha->md_dump) { 3252 ql_log(ql_log_warn, vha, 0xb10e, 3253 "Memory not allocated for minidump capture\n"); 3254 goto md_failed; 3255 } 3256 3257 qla8044_idc_lock(ha); 3258 idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 3259 if (idc_control & GRACEFUL_RESET_BIT1) { 3260 ql_log(ql_log_warn, vha, 0xb112, 3261 "Forced reset from application, " 3262 "ignore minidump capture\n"); 3263 qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, 3264 (idc_control & ~GRACEFUL_RESET_BIT1)); 3265 qla8044_idc_unlock(ha); 3266 3267 goto md_failed; 3268 } 3269 qla8044_idc_unlock(ha); 3270 3271 if (qla82xx_validate_template_chksum(vha)) { 3272 ql_log(ql_log_info, vha, 0xb109, 3273 "Template checksum validation error\n"); 3274 goto md_failed; 3275 } 3276 3277 tmplt_hdr = (struct qla8044_minidump_template_hdr *) 3278 ha->md_tmplt_hdr; 3279 data_ptr = (uint32_t *)((uint8_t *)ha->md_dump); 3280 num_entry_hdr = tmplt_hdr->num_of_entries; 3281 3282 ql_dbg(ql_dbg_p3p, vha, 0xb11a, 3283 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 3284 3285 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 3286 3287 /* Validate whether required debug level is set */ 3288 if ((f_capture_mask & 0x3) != 0x3) { 3289 ql_log(ql_log_warn, vha, 0xb10f, 3290 "Minimum required capture mask[0x%x] level not set\n", 3291 f_capture_mask); 3292 3293 } 3294 tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 3295 ql_log(ql_log_info, vha, 0xb102, 3296 "[%s]: starting data ptr: %p\n", 3297 __func__, data_ptr); 3298 ql_log(ql_log_info, vha, 0xb10b, 3299 "[%s]: no of entry headers in Template: 0x%x\n", 3300 __func__, num_entry_hdr); 3301 ql_log(ql_log_info, vha, 0xb10c, 3302 "[%s]: Total_data_size 0x%x, %d obtained\n", 3303 __func__, ha->md_dump_size, ha->md_dump_size); 3304 3305 /* Update current timestamp before taking dump */ 3306 now = get_jiffies_64(); 3307 timestamp = (u32)(jiffies_to_msecs(now) / 1000); 3308 tmplt_hdr->driver_timestamp = timestamp; 3309 3310 entry_hdr = (struct qla8044_minidump_entry_hdr *) 3311 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 3312 tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] = 3313 tmplt_hdr->ocm_window_reg[ha->portnum]; 3314 3315 /* Walk through the entry headers - validate/perform required action */ 3316 for (i = 0; i < num_entry_hdr; i++) { 3317 if (data_collected > ha->md_dump_size) { 3318 ql_log(ql_log_info, vha, 0xb103, 3319 "Data collected: [0x%x], " 3320 "Total Dump size: [0x%x]\n", 3321 data_collected, ha->md_dump_size); 3322 return rval; 3323 } 3324 3325 if (!(entry_hdr->d_ctrl.entry_capture_mask & 3326 ql2xmdcapmask)) { 3327 entry_hdr->d_ctrl.driver_flags |= 3328 QLA82XX_DBG_SKIPPED_FLAG; 3329 goto skip_nxt_entry; 3330 } 3331 3332 ql_dbg(ql_dbg_p3p, vha, 0xb104, 3333 "Data collected: [0x%x], Dump size left:[0x%x]\n", 3334 data_collected, 3335 (ha->md_dump_size - data_collected)); 3336 3337 /* Decode the entry type and take required action to capture 3338 * debug data 3339 */ 3340 switch (entry_hdr->entry_type) { 3341 case QLA82XX_RDEND: 3342 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3343 break; 3344 case QLA82XX_CNTRL: 3345 rval = qla8044_minidump_process_control(vha, 3346 entry_hdr); 3347 if (rval != QLA_SUCCESS) { 3348 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3349 goto md_failed; 3350 } 3351 break; 3352 case QLA82XX_RDCRB: 3353 qla8044_minidump_process_rdcrb(vha, 3354 entry_hdr, &data_ptr); 3355 break; 3356 case QLA82XX_RDMEM: 3357 rval = qla8044_minidump_pex_dma_read(vha, 3358 entry_hdr, &data_ptr); 3359 if (rval != QLA_SUCCESS) { 3360 rval = qla8044_minidump_process_rdmem(vha, 3361 entry_hdr, &data_ptr); 3362 if (rval != QLA_SUCCESS) { 3363 qla8044_mark_entry_skipped(vha, 3364 entry_hdr, i); 3365 goto md_failed; 3366 } 3367 } 3368 break; 3369 case QLA82XX_BOARD: 3370 case QLA82XX_RDROM: 3371 rval = qla8044_minidump_process_rdrom(vha, 3372 entry_hdr, &data_ptr); 3373 if (rval != QLA_SUCCESS) { 3374 qla8044_mark_entry_skipped(vha, 3375 entry_hdr, i); 3376 } 3377 break; 3378 case QLA82XX_L2DTG: 3379 case QLA82XX_L2ITG: 3380 case QLA82XX_L2DAT: 3381 case QLA82XX_L2INS: 3382 rval = qla8044_minidump_process_l2tag(vha, 3383 entry_hdr, &data_ptr); 3384 if (rval != QLA_SUCCESS) { 3385 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3386 goto md_failed; 3387 } 3388 break; 3389 case QLA8044_L1DTG: 3390 case QLA8044_L1ITG: 3391 case QLA82XX_L1DAT: 3392 case QLA82XX_L1INS: 3393 qla8044_minidump_process_l1cache(vha, 3394 entry_hdr, &data_ptr); 3395 break; 3396 case QLA82XX_RDOCM: 3397 qla8044_minidump_process_rdocm(vha, 3398 entry_hdr, &data_ptr); 3399 break; 3400 case QLA82XX_RDMUX: 3401 qla8044_minidump_process_rdmux(vha, 3402 entry_hdr, &data_ptr); 3403 break; 3404 case QLA82XX_QUEUE: 3405 qla8044_minidump_process_queue(vha, 3406 entry_hdr, &data_ptr); 3407 break; 3408 case QLA8044_POLLRD: 3409 rval = qla8044_minidump_process_pollrd(vha, 3410 entry_hdr, &data_ptr); 3411 if (rval != QLA_SUCCESS) 3412 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3413 break; 3414 case QLA8044_RDMUX2: 3415 qla8044_minidump_process_rdmux2(vha, 3416 entry_hdr, &data_ptr); 3417 break; 3418 case QLA8044_POLLRDMWR: 3419 rval = qla8044_minidump_process_pollrdmwr(vha, 3420 entry_hdr, &data_ptr); 3421 if (rval != QLA_SUCCESS) 3422 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3423 break; 3424 case QLA8044_RDDFE: 3425 rval = qla8044_minidump_process_rddfe(vha, entry_hdr, 3426 &data_ptr); 3427 if (rval != QLA_SUCCESS) 3428 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3429 break; 3430 case QLA8044_RDMDIO: 3431 rval = qla8044_minidump_process_rdmdio(vha, entry_hdr, 3432 &data_ptr); 3433 if (rval != QLA_SUCCESS) 3434 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3435 break; 3436 case QLA8044_POLLWR: 3437 rval = qla8044_minidump_process_pollwr(vha, entry_hdr, 3438 &data_ptr); 3439 if (rval != QLA_SUCCESS) 3440 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3441 break; 3442 case QLA82XX_RDNOP: 3443 default: 3444 qla8044_mark_entry_skipped(vha, entry_hdr, i); 3445 break; 3446 } 3447 3448 data_collected = (uint8_t *)data_ptr - 3449 (uint8_t *)((uint8_t *)ha->md_dump); 3450 skip_nxt_entry: 3451 /* 3452 * next entry in the template 3453 */ 3454 entry_hdr = (struct qla8044_minidump_entry_hdr *) 3455 (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 3456 } 3457 3458 if (data_collected != ha->md_dump_size) { 3459 ql_log(ql_log_info, vha, 0xb105, 3460 "Dump data mismatch: Data collected: " 3461 "[0x%x], total_data_size:[0x%x]\n", 3462 data_collected, ha->md_dump_size); 3463 rval = QLA_FUNCTION_FAILED; 3464 goto md_failed; 3465 } 3466 3467 ql_log(ql_log_info, vha, 0xb110, 3468 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 3469 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 3470 ha->fw_dumped = 1; 3471 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 3472 3473 3474 ql_log(ql_log_info, vha, 0xb106, 3475 "Leaving fn: %s Last entry: 0x%x\n", 3476 __func__, i); 3477 md_failed: 3478 return rval; 3479 } 3480 3481 void 3482 qla8044_get_minidump(struct scsi_qla_host *vha) 3483 { 3484 struct qla_hw_data *ha = vha->hw; 3485 3486 if (!qla8044_collect_md_data(vha)) { 3487 ha->fw_dumped = 1; 3488 ha->prev_minidump_failed = 0; 3489 } else { 3490 ql_log(ql_log_fatal, vha, 0xb0db, 3491 "%s: Unable to collect minidump\n", 3492 __func__); 3493 ha->prev_minidump_failed = 1; 3494 } 3495 } 3496 3497 static int 3498 qla8044_poll_flash_status_reg(struct scsi_qla_host *vha) 3499 { 3500 uint32_t flash_status; 3501 int retries = QLA8044_FLASH_READ_RETRY_COUNT; 3502 int ret_val = QLA_SUCCESS; 3503 3504 while (retries--) { 3505 ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS, 3506 &flash_status); 3507 if (ret_val) { 3508 ql_log(ql_log_warn, vha, 0xb13c, 3509 "%s: Failed to read FLASH_STATUS reg.\n", 3510 __func__); 3511 break; 3512 } 3513 if ((flash_status & QLA8044_FLASH_STATUS_READY) == 3514 QLA8044_FLASH_STATUS_READY) 3515 break; 3516 msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY); 3517 } 3518 3519 if (!retries) 3520 ret_val = QLA_FUNCTION_FAILED; 3521 3522 return ret_val; 3523 } 3524 3525 static int 3526 qla8044_write_flash_status_reg(struct scsi_qla_host *vha, 3527 uint32_t data) 3528 { 3529 int ret_val = QLA_SUCCESS; 3530 uint32_t cmd; 3531 3532 cmd = vha->hw->fdt_wrt_sts_reg_cmd; 3533 3534 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 3535 QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd); 3536 if (ret_val) { 3537 ql_log(ql_log_warn, vha, 0xb125, 3538 "%s: Failed to write to FLASH_ADDR.\n", __func__); 3539 goto exit_func; 3540 } 3541 3542 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data); 3543 if (ret_val) { 3544 ql_log(ql_log_warn, vha, 0xb126, 3545 "%s: Failed to write to FLASH_WRDATA.\n", __func__); 3546 goto exit_func; 3547 } 3548 3549 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 3550 QLA8044_FLASH_SECOND_ERASE_MS_VAL); 3551 if (ret_val) { 3552 ql_log(ql_log_warn, vha, 0xb127, 3553 "%s: Failed to write to FLASH_CONTROL.\n", __func__); 3554 goto exit_func; 3555 } 3556 3557 ret_val = qla8044_poll_flash_status_reg(vha); 3558 if (ret_val) 3559 ql_log(ql_log_warn, vha, 0xb128, 3560 "%s: Error polling flash status reg.\n", __func__); 3561 3562 exit_func: 3563 return ret_val; 3564 } 3565 3566 /* 3567 * This function assumes that the flash lock is held. 3568 */ 3569 static int 3570 qla8044_unprotect_flash(scsi_qla_host_t *vha) 3571 { 3572 int ret_val; 3573 struct qla_hw_data *ha = vha->hw; 3574 3575 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable); 3576 if (ret_val) 3577 ql_log(ql_log_warn, vha, 0xb139, 3578 "%s: Write flash status failed.\n", __func__); 3579 3580 return ret_val; 3581 } 3582 3583 /* 3584 * This function assumes that the flash lock is held. 3585 */ 3586 static int 3587 qla8044_protect_flash(scsi_qla_host_t *vha) 3588 { 3589 int ret_val; 3590 struct qla_hw_data *ha = vha->hw; 3591 3592 ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable); 3593 if (ret_val) 3594 ql_log(ql_log_warn, vha, 0xb13b, 3595 "%s: Write flash status failed.\n", __func__); 3596 3597 return ret_val; 3598 } 3599 3600 3601 static int 3602 qla8044_erase_flash_sector(struct scsi_qla_host *vha, 3603 uint32_t sector_start_addr) 3604 { 3605 uint32_t reversed_addr; 3606 int ret_val = QLA_SUCCESS; 3607 3608 ret_val = qla8044_poll_flash_status_reg(vha); 3609 if (ret_val) { 3610 ql_log(ql_log_warn, vha, 0xb12e, 3611 "%s: Poll flash status after erase failed..\n", __func__); 3612 } 3613 3614 reversed_addr = (((sector_start_addr & 0xFF) << 16) | 3615 (sector_start_addr & 0xFF00) | 3616 ((sector_start_addr & 0xFF0000) >> 16)); 3617 3618 ret_val = qla8044_wr_reg_indirect(vha, 3619 QLA8044_FLASH_WRDATA, reversed_addr); 3620 if (ret_val) { 3621 ql_log(ql_log_warn, vha, 0xb12f, 3622 "%s: Failed to write to FLASH_WRDATA.\n", __func__); 3623 } 3624 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 3625 QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd); 3626 if (ret_val) { 3627 ql_log(ql_log_warn, vha, 0xb130, 3628 "%s: Failed to write to FLASH_ADDR.\n", __func__); 3629 } 3630 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 3631 QLA8044_FLASH_LAST_ERASE_MS_VAL); 3632 if (ret_val) { 3633 ql_log(ql_log_warn, vha, 0xb131, 3634 "%s: Failed write to FLASH_CONTROL.\n", __func__); 3635 } 3636 ret_val = qla8044_poll_flash_status_reg(vha); 3637 if (ret_val) { 3638 ql_log(ql_log_warn, vha, 0xb132, 3639 "%s: Poll flash status failed.\n", __func__); 3640 } 3641 3642 3643 return ret_val; 3644 } 3645 3646 /* 3647 * qla8044_flash_write_u32 - Write data to flash 3648 * 3649 * @ha : Pointer to adapter structure 3650 * addr : Flash address to write to 3651 * p_data : Data to be written 3652 * 3653 * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 3654 * 3655 * NOTE: Lock should be held on entry 3656 */ 3657 static int 3658 qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr, 3659 uint32_t *p_data) 3660 { 3661 int ret_val = QLA_SUCCESS; 3662 3663 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 3664 0x00800000 | (addr >> 2)); 3665 if (ret_val) { 3666 ql_log(ql_log_warn, vha, 0xb134, 3667 "%s: Failed write to FLASH_ADDR.\n", __func__); 3668 goto exit_func; 3669 } 3670 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data); 3671 if (ret_val) { 3672 ql_log(ql_log_warn, vha, 0xb135, 3673 "%s: Failed write to FLASH_WRDATA.\n", __func__); 3674 goto exit_func; 3675 } 3676 ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D); 3677 if (ret_val) { 3678 ql_log(ql_log_warn, vha, 0xb136, 3679 "%s: Failed write to FLASH_CONTROL.\n", __func__); 3680 goto exit_func; 3681 } 3682 ret_val = qla8044_poll_flash_status_reg(vha); 3683 if (ret_val) { 3684 ql_log(ql_log_warn, vha, 0xb137, 3685 "%s: Poll flash status failed.\n", __func__); 3686 } 3687 3688 exit_func: 3689 return ret_val; 3690 } 3691 3692 static int 3693 qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr, 3694 uint32_t faddr, uint32_t dwords) 3695 { 3696 int ret = QLA_FUNCTION_FAILED; 3697 uint32_t spi_val; 3698 3699 if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS || 3700 dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) { 3701 ql_dbg(ql_dbg_user, vha, 0xb123, 3702 "Got unsupported dwords = 0x%x.\n", 3703 dwords); 3704 return QLA_FUNCTION_FAILED; 3705 } 3706 3707 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val); 3708 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, 3709 spi_val | QLA8044_FLASH_SPI_CTL); 3710 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 3711 QLA8044_FLASH_FIRST_TEMP_VAL); 3712 3713 /* First DWORD write to FLASH_WRDATA */ 3714 ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, 3715 *dwptr++); 3716 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 3717 QLA8044_FLASH_FIRST_MS_PATTERN); 3718 3719 ret = qla8044_poll_flash_status_reg(vha); 3720 if (ret) { 3721 ql_log(ql_log_warn, vha, 0xb124, 3722 "%s: Failed.\n", __func__); 3723 goto exit_func; 3724 } 3725 3726 dwords--; 3727 3728 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 3729 QLA8044_FLASH_SECOND_TEMP_VAL); 3730 3731 3732 /* Second to N-1 DWORDS writes */ 3733 while (dwords != 1) { 3734 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++); 3735 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 3736 QLA8044_FLASH_SECOND_MS_PATTERN); 3737 ret = qla8044_poll_flash_status_reg(vha); 3738 if (ret) { 3739 ql_log(ql_log_warn, vha, 0xb129, 3740 "%s: Failed.\n", __func__); 3741 goto exit_func; 3742 } 3743 dwords--; 3744 } 3745 3746 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 3747 QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2)); 3748 3749 /* Last DWORD write */ 3750 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++); 3751 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 3752 QLA8044_FLASH_LAST_MS_PATTERN); 3753 ret = qla8044_poll_flash_status_reg(vha); 3754 if (ret) { 3755 ql_log(ql_log_warn, vha, 0xb12a, 3756 "%s: Failed.\n", __func__); 3757 goto exit_func; 3758 } 3759 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val); 3760 3761 if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) { 3762 ql_log(ql_log_warn, vha, 0xb12b, 3763 "%s: Failed.\n", __func__); 3764 spi_val = 0; 3765 /* Operation failed, clear error bit. */ 3766 qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, 3767 &spi_val); 3768 qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, 3769 spi_val | QLA8044_FLASH_SPI_CTL); 3770 } 3771 exit_func: 3772 return ret; 3773 } 3774 3775 static int 3776 qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr, 3777 uint32_t faddr, uint32_t dwords) 3778 { 3779 int ret = QLA_FUNCTION_FAILED; 3780 uint32_t liter; 3781 3782 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 3783 ret = qla8044_flash_write_u32(vha, faddr, dwptr); 3784 if (ret) { 3785 ql_dbg(ql_dbg_p3p, vha, 0xb141, 3786 "%s: flash address=%x data=%x.\n", __func__, 3787 faddr, *dwptr); 3788 break; 3789 } 3790 } 3791 3792 return ret; 3793 } 3794 3795 int 3796 qla8044_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 3797 uint32_t offset, uint32_t length) 3798 { 3799 int rval = QLA_FUNCTION_FAILED, i, burst_iter_count; 3800 int dword_count, erase_sec_count; 3801 uint32_t erase_offset; 3802 uint8_t *p_cache, *p_src; 3803 3804 erase_offset = offset; 3805 3806 p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL); 3807 if (!p_cache) 3808 return QLA_FUNCTION_FAILED; 3809 3810 memcpy(p_cache, buf, length); 3811 p_src = p_cache; 3812 dword_count = length / sizeof(uint32_t); 3813 /* Since the offset and legth are sector aligned, it will be always 3814 * multiple of burst_iter_count (64) 3815 */ 3816 burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS; 3817 erase_sec_count = length / QLA8044_SECTOR_SIZE; 3818 3819 /* Suspend HBA. */ 3820 scsi_block_requests(vha->host); 3821 /* Lock and enable write for whole operation. */ 3822 qla8044_flash_lock(vha); 3823 qla8044_unprotect_flash(vha); 3824 3825 /* Erasing the sectors */ 3826 for (i = 0; i < erase_sec_count; i++) { 3827 rval = qla8044_erase_flash_sector(vha, erase_offset); 3828 ql_dbg(ql_dbg_user, vha, 0xb138, 3829 "Done erase of sector=0x%x.\n", 3830 erase_offset); 3831 if (rval) { 3832 ql_log(ql_log_warn, vha, 0xb121, 3833 "Failed to erase the sector having address: " 3834 "0x%x.\n", erase_offset); 3835 goto out; 3836 } 3837 erase_offset += QLA8044_SECTOR_SIZE; 3838 } 3839 ql_dbg(ql_dbg_user, vha, 0xb13f, 3840 "Got write for addr = 0x%x length=0x%x.\n", 3841 offset, length); 3842 3843 for (i = 0; i < burst_iter_count; i++) { 3844 3845 /* Go with write. */ 3846 rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src, 3847 offset, QLA8044_MAX_OPTROM_BURST_DWORDS); 3848 if (rval) { 3849 /* Buffer Mode failed skip to dword mode */ 3850 ql_log(ql_log_warn, vha, 0xb122, 3851 "Failed to write flash in buffer mode, " 3852 "Reverting to slow-write.\n"); 3853 rval = qla8044_write_flash_dword_mode(vha, 3854 (uint32_t *)p_src, offset, 3855 QLA8044_MAX_OPTROM_BURST_DWORDS); 3856 } 3857 p_src += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS; 3858 offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS; 3859 } 3860 ql_dbg(ql_dbg_user, vha, 0xb133, 3861 "Done writing.\n"); 3862 3863 out: 3864 qla8044_protect_flash(vha); 3865 qla8044_flash_unlock(vha); 3866 scsi_unblock_requests(vha->host); 3867 kfree(p_cache); 3868 3869 return rval; 3870 } 3871 3872 #define LEG_INT_PTR_B31 (1 << 31) 3873 #define LEG_INT_PTR_B30 (1 << 30) 3874 #define PF_BITS_MASK (0xF << 16) 3875 /** 3876 * qla8044_intr_handler() - Process interrupts for the ISP8044 3877 * @irq: 3878 * @dev_id: SCSI driver HA context 3879 * 3880 * Called by system whenever the host adapter generates an interrupt. 3881 * 3882 * Returns handled flag. 3883 */ 3884 irqreturn_t 3885 qla8044_intr_handler(int irq, void *dev_id) 3886 { 3887 scsi_qla_host_t *vha; 3888 struct qla_hw_data *ha; 3889 struct rsp_que *rsp; 3890 struct device_reg_82xx __iomem *reg; 3891 int status = 0; 3892 unsigned long flags; 3893 unsigned long iter; 3894 uint32_t stat; 3895 uint16_t mb[4]; 3896 uint32_t leg_int_ptr = 0, pf_bit; 3897 3898 rsp = (struct rsp_que *) dev_id; 3899 if (!rsp) { 3900 ql_log(ql_log_info, NULL, 0xb143, 3901 "%s(): NULL response queue pointer\n", __func__); 3902 return IRQ_NONE; 3903 } 3904 ha = rsp->hw; 3905 vha = pci_get_drvdata(ha->pdev); 3906 3907 if (unlikely(pci_channel_offline(ha->pdev))) 3908 return IRQ_HANDLED; 3909 3910 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET); 3911 3912 /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */ 3913 if (!(leg_int_ptr & (LEG_INT_PTR_B31))) { 3914 ql_dbg(ql_dbg_p3p, vha, 0xb144, 3915 "%s: Legacy Interrupt Bit 31 not set, " 3916 "spurious interrupt!\n", __func__); 3917 return IRQ_NONE; 3918 } 3919 3920 pf_bit = ha->portnum << 16; 3921 /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */ 3922 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) { 3923 ql_dbg(ql_dbg_p3p, vha, 0xb145, 3924 "%s: Incorrect function ID 0x%x in " 3925 "legacy interrupt register, " 3926 "ha->pf_bit = 0x%x\n", __func__, 3927 (leg_int_ptr & (PF_BITS_MASK)), pf_bit); 3928 return IRQ_NONE; 3929 } 3930 3931 /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger 3932 * Control register and poll till Legacy Interrupt Pointer register 3933 * bit32 is 0. 3934 */ 3935 qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0); 3936 do { 3937 leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET); 3938 if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) 3939 break; 3940 } while (leg_int_ptr & (LEG_INT_PTR_B30)); 3941 3942 reg = &ha->iobase->isp82; 3943 spin_lock_irqsave(&ha->hardware_lock, flags); 3944 for (iter = 1; iter--; ) { 3945 3946 if (RD_REG_DWORD(®->host_int)) { 3947 stat = RD_REG_DWORD(®->host_status); 3948 if ((stat & HSRX_RISC_INT) == 0) 3949 break; 3950 3951 switch (stat & 0xff) { 3952 case 0x1: 3953 case 0x2: 3954 case 0x10: 3955 case 0x11: 3956 qla82xx_mbx_completion(vha, MSW(stat)); 3957 status |= MBX_INTERRUPT; 3958 break; 3959 case 0x12: 3960 mb[0] = MSW(stat); 3961 mb[1] = RD_REG_WORD(®->mailbox_out[1]); 3962 mb[2] = RD_REG_WORD(®->mailbox_out[2]); 3963 mb[3] = RD_REG_WORD(®->mailbox_out[3]); 3964 qla2x00_async_event(vha, rsp, mb); 3965 break; 3966 case 0x13: 3967 qla24xx_process_response_queue(vha, rsp); 3968 break; 3969 default: 3970 ql_dbg(ql_dbg_p3p, vha, 0xb146, 3971 "Unrecognized interrupt type " 3972 "(%d).\n", stat & 0xff); 3973 break; 3974 } 3975 } 3976 WRT_REG_DWORD(®->host_int, 0); 3977 } 3978 3979 qla2x00_handle_mbx_completion(ha, status); 3980 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3981 3982 return IRQ_HANDLED; 3983 } 3984 3985 static int 3986 qla8044_idc_dontreset(struct qla_hw_data *ha) 3987 { 3988 uint32_t idc_ctrl; 3989 3990 idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 3991 return idc_ctrl & DONTRESET_BIT0; 3992 } 3993 3994 static void 3995 qla8044_clear_rst_ready(scsi_qla_host_t *vha) 3996 { 3997 uint32_t drv_state; 3998 3999 drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 4000 4001 /* 4002 * For ISP8044, drv_active register has 1 bit per function, 4003 * shift 1 by func_num to set a bit for the function. 4004 * For ISP82xx, drv_active has 4 bits per function 4005 */ 4006 drv_state &= ~(1 << vha->hw->portnum); 4007 4008 ql_dbg(ql_dbg_p3p, vha, 0xb13d, 4009 "drv_state: 0x%08x\n", drv_state); 4010 qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state); 4011 } 4012 4013 int 4014 qla8044_abort_isp(scsi_qla_host_t *vha) 4015 { 4016 int rval; 4017 uint32_t dev_state; 4018 struct qla_hw_data *ha = vha->hw; 4019 4020 qla8044_idc_lock(ha); 4021 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 4022 4023 if (ql2xdontresethba) 4024 qla8044_set_idc_dontreset(vha); 4025 4026 /* If device_state is NEED_RESET, go ahead with 4027 * Reset,irrespective of ql2xdontresethba. This is to allow a 4028 * non-reset-owner to force a reset. Non-reset-owner sets 4029 * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset 4030 * and then forces a Reset by setting device_state to 4031 * NEED_RESET. */ 4032 if (dev_state == QLA8XXX_DEV_READY) { 4033 /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset 4034 * recovery */ 4035 if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) { 4036 ql_dbg(ql_dbg_p3p, vha, 0xb13e, 4037 "Reset recovery disabled\n"); 4038 rval = QLA_FUNCTION_FAILED; 4039 goto exit_isp_reset; 4040 } 4041 4042 ql_dbg(ql_dbg_p3p, vha, 0xb140, 4043 "HW State: NEED RESET\n"); 4044 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 4045 QLA8XXX_DEV_NEED_RESET); 4046 } 4047 4048 /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority 4049 * and which drivers are present. Unlike ISP82XX, the function setting 4050 * NEED_RESET, may not be the Reset owner. */ 4051 qla83xx_reset_ownership(vha); 4052 4053 qla8044_idc_unlock(ha); 4054 rval = qla8044_device_state_handler(vha); 4055 qla8044_idc_lock(ha); 4056 qla8044_clear_rst_ready(vha); 4057 4058 exit_isp_reset: 4059 qla8044_idc_unlock(ha); 4060 if (rval == QLA_SUCCESS) { 4061 ha->flags.isp82xx_fw_hung = 0; 4062 ha->flags.nic_core_reset_hdlr_active = 0; 4063 rval = qla82xx_restart_isp(vha); 4064 } 4065 4066 return rval; 4067 } 4068 4069 void 4070 qla8044_fw_dump(scsi_qla_host_t *vha, int hardware_locked) 4071 { 4072 struct qla_hw_data *ha = vha->hw; 4073 4074 if (!ha->allow_cna_fw_dump) 4075 return; 4076 4077 scsi_block_requests(vha->host); 4078 ha->flags.isp82xx_no_md_cap = 1; 4079 qla8044_idc_lock(ha); 4080 qla82xx_set_reset_owner(vha); 4081 qla8044_idc_unlock(ha); 4082 qla2x00_wait_for_chip_reset(vha); 4083 scsi_unblock_requests(vha->host); 4084 } 4085