17ec0effdSAtul Deshmukh /* 27ec0effdSAtul Deshmukh * QLogic Fibre Channel HBA Driver 37ec0effdSAtul Deshmukh * Copyright (c) 2003-2013 QLogic Corporation 47ec0effdSAtul Deshmukh * 57ec0effdSAtul Deshmukh * See LICENSE.qla2xxx for copyright and licensing details. 67ec0effdSAtul Deshmukh */ 77ec0effdSAtul Deshmukh 87ec0effdSAtul Deshmukh #include <linux/vmalloc.h> 97ec0effdSAtul Deshmukh 107ec0effdSAtul Deshmukh #include "qla_def.h" 117ec0effdSAtul Deshmukh #include "qla_gbl.h" 127ec0effdSAtul Deshmukh 137ec0effdSAtul Deshmukh #include <linux/delay.h> 147ec0effdSAtul Deshmukh 157ec0effdSAtul Deshmukh /* 8044 Flash Read/Write functions */ 167ec0effdSAtul Deshmukh uint32_t 177ec0effdSAtul Deshmukh qla8044_rd_reg(struct qla_hw_data *ha, ulong addr) 187ec0effdSAtul Deshmukh { 197ec0effdSAtul Deshmukh return readl((void __iomem *) (ha->nx_pcibase + addr)); 207ec0effdSAtul Deshmukh } 217ec0effdSAtul Deshmukh 227ec0effdSAtul Deshmukh void 237ec0effdSAtul Deshmukh qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val) 247ec0effdSAtul Deshmukh { 257ec0effdSAtul Deshmukh writel(val, (void __iomem *)((ha)->nx_pcibase + addr)); 267ec0effdSAtul Deshmukh } 277ec0effdSAtul Deshmukh 287ec0effdSAtul Deshmukh int 297ec0effdSAtul Deshmukh qla8044_rd_direct(struct scsi_qla_host *vha, 307ec0effdSAtul Deshmukh const uint32_t crb_reg) 317ec0effdSAtul Deshmukh { 327ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 337ec0effdSAtul Deshmukh 347ec0effdSAtul Deshmukh if (crb_reg < CRB_REG_INDEX_MAX) 357ec0effdSAtul Deshmukh return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]); 367ec0effdSAtul Deshmukh else 377ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 387ec0effdSAtul Deshmukh } 397ec0effdSAtul Deshmukh 407ec0effdSAtul Deshmukh void 417ec0effdSAtul Deshmukh qla8044_wr_direct(struct scsi_qla_host *vha, 427ec0effdSAtul Deshmukh const uint32_t crb_reg, 437ec0effdSAtul Deshmukh const uint32_t value) 447ec0effdSAtul Deshmukh { 457ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 467ec0effdSAtul Deshmukh 477ec0effdSAtul Deshmukh if (crb_reg < CRB_REG_INDEX_MAX) 487ec0effdSAtul Deshmukh qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value); 497ec0effdSAtul Deshmukh } 507ec0effdSAtul Deshmukh 517ec0effdSAtul Deshmukh static int 527ec0effdSAtul Deshmukh qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr) 537ec0effdSAtul Deshmukh { 547ec0effdSAtul Deshmukh uint32_t val; 557ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 567ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 577ec0effdSAtul Deshmukh 587ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr); 597ec0effdSAtul Deshmukh val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum)); 607ec0effdSAtul Deshmukh 617ec0effdSAtul Deshmukh if (val != addr) { 627ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb087, 637ec0effdSAtul Deshmukh "%s: Failed to set register window : " 647ec0effdSAtul Deshmukh "addr written 0x%x, read 0x%x!\n", 657ec0effdSAtul Deshmukh __func__, addr, val); 667ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 677ec0effdSAtul Deshmukh } 687ec0effdSAtul Deshmukh return ret_val; 697ec0effdSAtul Deshmukh } 707ec0effdSAtul Deshmukh 717ec0effdSAtul Deshmukh static int 727ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data) 737ec0effdSAtul Deshmukh { 747ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 757ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 767ec0effdSAtul Deshmukh 777ec0effdSAtul Deshmukh ret_val = qla8044_set_win_base(vha, addr); 787ec0effdSAtul Deshmukh if (!ret_val) 797ec0effdSAtul Deshmukh *data = qla8044_rd_reg(ha, QLA8044_WILDCARD); 807ec0effdSAtul Deshmukh else 817ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb088, 827ec0effdSAtul Deshmukh "%s: failed read of addr 0x%x!\n", __func__, addr); 837ec0effdSAtul Deshmukh return ret_val; 847ec0effdSAtul Deshmukh } 857ec0effdSAtul Deshmukh 867ec0effdSAtul Deshmukh static int 877ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data) 887ec0effdSAtul Deshmukh { 897ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 907ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 917ec0effdSAtul Deshmukh 927ec0effdSAtul Deshmukh ret_val = qla8044_set_win_base(vha, addr); 937ec0effdSAtul Deshmukh if (!ret_val) 947ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_WILDCARD, data); 957ec0effdSAtul Deshmukh else 967ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb089, 977ec0effdSAtul Deshmukh "%s: failed wrt to addr 0x%x, data 0x%x\n", 987ec0effdSAtul Deshmukh __func__, addr, data); 997ec0effdSAtul Deshmukh return ret_val; 1007ec0effdSAtul Deshmukh } 1017ec0effdSAtul Deshmukh 1027ec0effdSAtul Deshmukh /* 1037ec0effdSAtul Deshmukh * qla8044_read_write_crb_reg - Read from raddr and write value to waddr. 1047ec0effdSAtul Deshmukh * 1057ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure 1067ec0effdSAtul Deshmukh * @raddr : CRB address to read from 1077ec0effdSAtul Deshmukh * @waddr : CRB address to write to 1087ec0effdSAtul Deshmukh * 1097ec0effdSAtul Deshmukh */ 1107ec0effdSAtul Deshmukh static void 1117ec0effdSAtul Deshmukh qla8044_read_write_crb_reg(struct scsi_qla_host *vha, 1127ec0effdSAtul Deshmukh uint32_t raddr, uint32_t waddr) 1137ec0effdSAtul Deshmukh { 1147ec0effdSAtul Deshmukh uint32_t value; 1157ec0effdSAtul Deshmukh 1167ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, raddr, &value); 1177ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, waddr, value); 1187ec0effdSAtul Deshmukh } 1197ec0effdSAtul Deshmukh 1207ec0effdSAtul Deshmukh /* 1217ec0effdSAtul Deshmukh * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask, 1227ec0effdSAtul Deshmukh * Shift Left,Right/OR/XOR with values RMW header and write value to waddr. 1237ec0effdSAtul Deshmukh * 1247ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure 1257ec0effdSAtul Deshmukh * @raddr : CRB address to read from 1267ec0effdSAtul Deshmukh * @waddr : CRB address to write to 1277ec0effdSAtul Deshmukh * @p_rmw_hdr : header with shift/or/xor values. 1287ec0effdSAtul Deshmukh * 1297ec0effdSAtul Deshmukh */ 1307ec0effdSAtul Deshmukh static void 1317ec0effdSAtul Deshmukh qla8044_rmw_crb_reg(struct scsi_qla_host *vha, 1327ec0effdSAtul Deshmukh uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr) 1337ec0effdSAtul Deshmukh { 1347ec0effdSAtul Deshmukh uint32_t value; 1357ec0effdSAtul Deshmukh 1367ec0effdSAtul Deshmukh if (p_rmw_hdr->index_a) 1377ec0effdSAtul Deshmukh value = vha->reset_tmplt.array[p_rmw_hdr->index_a]; 1387ec0effdSAtul Deshmukh else 1397ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, raddr, &value); 1407ec0effdSAtul Deshmukh value &= p_rmw_hdr->test_mask; 1417ec0effdSAtul Deshmukh value <<= p_rmw_hdr->shl; 1427ec0effdSAtul Deshmukh value >>= p_rmw_hdr->shr; 1437ec0effdSAtul Deshmukh value |= p_rmw_hdr->or_value; 1447ec0effdSAtul Deshmukh value ^= p_rmw_hdr->xor_value; 1457ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, waddr, value); 1467ec0effdSAtul Deshmukh return; 1477ec0effdSAtul Deshmukh } 1487ec0effdSAtul Deshmukh 1497ec0effdSAtul Deshmukh inline void 1507ec0effdSAtul Deshmukh qla8044_set_qsnt_ready(struct scsi_qla_host *vha) 1517ec0effdSAtul Deshmukh { 1527ec0effdSAtul Deshmukh uint32_t qsnt_state; 1537ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 1547ec0effdSAtul Deshmukh 1557ec0effdSAtul Deshmukh qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 1567ec0effdSAtul Deshmukh qsnt_state |= (1 << ha->portnum); 1577ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state); 1587ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n", 1597ec0effdSAtul Deshmukh __func__, vha->host_no, qsnt_state); 1607ec0effdSAtul Deshmukh } 1617ec0effdSAtul Deshmukh 1627ec0effdSAtul Deshmukh void 1637ec0effdSAtul Deshmukh qla8044_clear_qsnt_ready(struct scsi_qla_host *vha) 1647ec0effdSAtul Deshmukh { 1657ec0effdSAtul Deshmukh uint32_t qsnt_state; 1667ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 1677ec0effdSAtul Deshmukh 1687ec0effdSAtul Deshmukh qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 1697ec0effdSAtul Deshmukh qsnt_state &= ~(1 << ha->portnum); 1707ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state); 1717ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n", 1727ec0effdSAtul Deshmukh __func__, vha->host_no, qsnt_state); 1737ec0effdSAtul Deshmukh } 1747ec0effdSAtul Deshmukh 1757ec0effdSAtul Deshmukh /** 1767ec0effdSAtul Deshmukh * 1777ec0effdSAtul Deshmukh * qla8044_lock_recovery - Recovers the idc_lock. 1787ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure 1797ec0effdSAtul Deshmukh * 1807ec0effdSAtul Deshmukh * Lock Recovery Register 1817ec0effdSAtul Deshmukh * 5-2 Lock recovery owner: Function ID of driver doing lock recovery, 1827ec0effdSAtul Deshmukh * valid if bits 1..0 are set by driver doing lock recovery. 1837ec0effdSAtul Deshmukh * 1-0 1 - Driver intends to force unlock the IDC lock. 1847ec0effdSAtul Deshmukh * 2 - Driver is moving forward to unlock the IDC lock. Driver clears 1857ec0effdSAtul Deshmukh * this field after force unlocking the IDC lock. 1867ec0effdSAtul Deshmukh * 1877ec0effdSAtul Deshmukh * Lock Recovery process 1887ec0effdSAtul Deshmukh * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is 1897ec0effdSAtul Deshmukh * greater than 0, then wait for the other driver to unlock otherwise 1907ec0effdSAtul Deshmukh * move to the next step. 1917ec0effdSAtul Deshmukh * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY 1927ec0effdSAtul Deshmukh * register bits 1..0 and also set the function# in bits 5..2. 1937ec0effdSAtul Deshmukh * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms. 1947ec0effdSAtul Deshmukh * Wait for the other driver to perform lock recovery if the function 1957ec0effdSAtul Deshmukh * number in bits 5..2 has changed, otherwise move to the next step. 1967ec0effdSAtul Deshmukh * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0 1977ec0effdSAtul Deshmukh * leaving your function# in bits 5..2. 1987ec0effdSAtul Deshmukh * e. Force unlock using the DRIVER_UNLOCK register and immediately clear 1997ec0effdSAtul Deshmukh * the IDC_LOCK_RECOVERY bits 5..0 by writing 0. 2007ec0effdSAtul Deshmukh **/ 2017ec0effdSAtul Deshmukh static int 2027ec0effdSAtul Deshmukh qla8044_lock_recovery(struct scsi_qla_host *vha) 2037ec0effdSAtul Deshmukh { 2047ec0effdSAtul Deshmukh uint32_t lock = 0, lockid; 2057ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 2067ec0effdSAtul Deshmukh 2077ec0effdSAtul Deshmukh lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY); 2087ec0effdSAtul Deshmukh 2097ec0effdSAtul Deshmukh /* Check for other Recovery in progress, go wait */ 2107ec0effdSAtul Deshmukh if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0) 2117ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 2127ec0effdSAtul Deshmukh 2137ec0effdSAtul Deshmukh /* Intent to Recover */ 2147ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 2157ec0effdSAtul Deshmukh (ha->portnum << 2167ec0effdSAtul Deshmukh IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER); 2177ec0effdSAtul Deshmukh msleep(200); 2187ec0effdSAtul Deshmukh 2197ec0effdSAtul Deshmukh /* Check Intent to Recover is advertised */ 2207ec0effdSAtul Deshmukh lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY); 2217ec0effdSAtul Deshmukh if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum << 2227ec0effdSAtul Deshmukh IDC_LOCK_RECOVERY_STATE_SHIFT_BITS)) 2237ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 2247ec0effdSAtul Deshmukh 2257ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n" 2267ec0effdSAtul Deshmukh , __func__, ha->portnum); 2277ec0effdSAtul Deshmukh 2287ec0effdSAtul Deshmukh /* Proceed to Recover */ 2297ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 2307ec0effdSAtul Deshmukh (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | 2317ec0effdSAtul Deshmukh PROCEED_TO_RECOVER); 2327ec0effdSAtul Deshmukh 2337ec0effdSAtul Deshmukh /* Force Unlock() */ 2347ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF); 2357ec0effdSAtul Deshmukh qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK); 2367ec0effdSAtul Deshmukh 2377ec0effdSAtul Deshmukh /* Clear bits 0-5 in IDC_RECOVERY register*/ 2387ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0); 2397ec0effdSAtul Deshmukh 2407ec0effdSAtul Deshmukh /* Get lock() */ 2417ec0effdSAtul Deshmukh lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK); 2427ec0effdSAtul Deshmukh if (lock) { 2437ec0effdSAtul Deshmukh lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 2447ec0effdSAtul Deshmukh lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum; 2457ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid); 2467ec0effdSAtul Deshmukh return QLA_SUCCESS; 2477ec0effdSAtul Deshmukh } else 2487ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 2497ec0effdSAtul Deshmukh } 2507ec0effdSAtul Deshmukh 2517ec0effdSAtul Deshmukh int 2527ec0effdSAtul Deshmukh qla8044_idc_lock(struct qla_hw_data *ha) 2537ec0effdSAtul Deshmukh { 2547ec0effdSAtul Deshmukh uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0; 2557ec0effdSAtul Deshmukh uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0; 2567ec0effdSAtul Deshmukh scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 2577ec0effdSAtul Deshmukh 2587ec0effdSAtul Deshmukh while (status == 0) { 2597ec0effdSAtul Deshmukh /* acquire semaphore5 from PCI HW block */ 2607ec0effdSAtul Deshmukh status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK); 2617ec0effdSAtul Deshmukh 2627ec0effdSAtul Deshmukh if (status) { 2637ec0effdSAtul Deshmukh /* Increment Counter (8-31) and update func_num (0-7) on 2647ec0effdSAtul Deshmukh * getting a successful lock */ 2657ec0effdSAtul Deshmukh lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 2667ec0effdSAtul Deshmukh lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum; 2677ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id); 2687ec0effdSAtul Deshmukh break; 2697ec0effdSAtul Deshmukh } 2707ec0effdSAtul Deshmukh 2717ec0effdSAtul Deshmukh if (timeout == 0) 2727ec0effdSAtul Deshmukh first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 2737ec0effdSAtul Deshmukh 2747ec0effdSAtul Deshmukh if (++timeout >= 2757ec0effdSAtul Deshmukh (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) { 2767ec0effdSAtul Deshmukh tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 2777ec0effdSAtul Deshmukh func_num = tmo_owner & 0xFF; 2787ec0effdSAtul Deshmukh lock_cnt = tmo_owner >> 8; 2797ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb114, 2807ec0effdSAtul Deshmukh "%s: Lock by func %d failed after 2s, lock held " 2817ec0effdSAtul Deshmukh "by func %d, lock count %d, first_owner %d\n", 2827ec0effdSAtul Deshmukh __func__, ha->portnum, func_num, lock_cnt, 2837ec0effdSAtul Deshmukh (first_owner & 0xFF)); 2847ec0effdSAtul Deshmukh if (first_owner != tmo_owner) { 2857ec0effdSAtul Deshmukh /* Some other driver got lock, 2867ec0effdSAtul Deshmukh * OR same driver got lock again (counter 2877ec0effdSAtul Deshmukh * value changed), when we were waiting for 2887ec0effdSAtul Deshmukh * lock. Retry for another 2 sec */ 2897ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb115, 2907ec0effdSAtul Deshmukh "%s: %d: IDC lock failed\n", 2917ec0effdSAtul Deshmukh __func__, ha->portnum); 2927ec0effdSAtul Deshmukh timeout = 0; 2937ec0effdSAtul Deshmukh } else { 2947ec0effdSAtul Deshmukh /* Same driver holding lock > 2sec. 2957ec0effdSAtul Deshmukh * Force Recovery */ 2967ec0effdSAtul Deshmukh if (qla8044_lock_recovery(vha) == QLA_SUCCESS) { 2977ec0effdSAtul Deshmukh /* Recovered and got lock */ 2987ec0effdSAtul Deshmukh ret_val = QLA_SUCCESS; 2997ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb116, 3007ec0effdSAtul Deshmukh "%s:IDC lock Recovery by %d" 3017ec0effdSAtul Deshmukh "successful...\n", __func__, 3027ec0effdSAtul Deshmukh ha->portnum); 3037ec0effdSAtul Deshmukh } 3047ec0effdSAtul Deshmukh /* Recovery Failed, some other function 3057ec0effdSAtul Deshmukh * has the lock, wait for 2secs 3067ec0effdSAtul Deshmukh * and retry 3077ec0effdSAtul Deshmukh */ 3087ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb08a, 3097ec0effdSAtul Deshmukh "%s: IDC lock Recovery by %d " 3107ec0effdSAtul Deshmukh "failed, Retrying timout\n", __func__, 3117ec0effdSAtul Deshmukh ha->portnum); 3127ec0effdSAtul Deshmukh timeout = 0; 3137ec0effdSAtul Deshmukh } 3147ec0effdSAtul Deshmukh } 3157ec0effdSAtul Deshmukh msleep(QLA8044_DRV_LOCK_MSLEEP); 3167ec0effdSAtul Deshmukh } 3177ec0effdSAtul Deshmukh return ret_val; 3187ec0effdSAtul Deshmukh } 3197ec0effdSAtul Deshmukh 3207ec0effdSAtul Deshmukh void 3217ec0effdSAtul Deshmukh qla8044_idc_unlock(struct qla_hw_data *ha) 3227ec0effdSAtul Deshmukh { 3237ec0effdSAtul Deshmukh int id; 3247ec0effdSAtul Deshmukh scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 3257ec0effdSAtul Deshmukh 3267ec0effdSAtul Deshmukh id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID); 3277ec0effdSAtul Deshmukh 3287ec0effdSAtul Deshmukh if ((id & 0xFF) != ha->portnum) { 3297ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb118, 3307ec0effdSAtul Deshmukh "%s: IDC Unlock by %d failed, lock owner is %d!\n", 3317ec0effdSAtul Deshmukh __func__, ha->portnum, (id & 0xFF)); 3327ec0effdSAtul Deshmukh return; 3337ec0effdSAtul Deshmukh } 3347ec0effdSAtul Deshmukh 3357ec0effdSAtul Deshmukh /* Keep lock counter value, update the ha->func_num to 0xFF */ 3367ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF)); 3377ec0effdSAtul Deshmukh qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK); 3387ec0effdSAtul Deshmukh } 3397ec0effdSAtul Deshmukh 3407ec0effdSAtul Deshmukh /* 8044 Flash Lock/Unlock functions */ 3417ec0effdSAtul Deshmukh static int 3427ec0effdSAtul Deshmukh qla8044_flash_lock(scsi_qla_host_t *vha) 3437ec0effdSAtul Deshmukh { 3447ec0effdSAtul Deshmukh int lock_owner; 3457ec0effdSAtul Deshmukh int timeout = 0; 3467ec0effdSAtul Deshmukh uint32_t lock_status = 0; 3477ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 3487ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 3497ec0effdSAtul Deshmukh 3507ec0effdSAtul Deshmukh while (lock_status == 0) { 3517ec0effdSAtul Deshmukh lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK); 3527ec0effdSAtul Deshmukh if (lock_status) 3537ec0effdSAtul Deshmukh break; 3547ec0effdSAtul Deshmukh 3557ec0effdSAtul Deshmukh if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) { 3567ec0effdSAtul Deshmukh lock_owner = qla8044_rd_reg(ha, 3577ec0effdSAtul Deshmukh QLA8044_FLASH_LOCK_ID); 3587ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb113, 3597ec0effdSAtul Deshmukh "%s: flash lock by %d failed, held by %d\n", 3607ec0effdSAtul Deshmukh __func__, ha->portnum, lock_owner); 3617ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 3627ec0effdSAtul Deshmukh break; 3637ec0effdSAtul Deshmukh } 3647ec0effdSAtul Deshmukh msleep(20); 3657ec0effdSAtul Deshmukh } 3667ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum); 3677ec0effdSAtul Deshmukh return ret_val; 3687ec0effdSAtul Deshmukh } 3697ec0effdSAtul Deshmukh 3707ec0effdSAtul Deshmukh static void 3717ec0effdSAtul Deshmukh qla8044_flash_unlock(scsi_qla_host_t *vha) 3727ec0effdSAtul Deshmukh { 3737ec0effdSAtul Deshmukh int ret_val; 3747ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 3757ec0effdSAtul Deshmukh 3767ec0effdSAtul Deshmukh /* Reading FLASH_UNLOCK register unlocks the Flash */ 3777ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF); 3787ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK); 3797ec0effdSAtul Deshmukh } 3807ec0effdSAtul Deshmukh 3817ec0effdSAtul Deshmukh 3827ec0effdSAtul Deshmukh static 3837ec0effdSAtul Deshmukh void qla8044_flash_lock_recovery(struct scsi_qla_host *vha) 3847ec0effdSAtul Deshmukh { 3857ec0effdSAtul Deshmukh 3867ec0effdSAtul Deshmukh if (qla8044_flash_lock(vha)) { 3877ec0effdSAtul Deshmukh /* Someone else is holding the lock. */ 3887ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n"); 3897ec0effdSAtul Deshmukh } 3907ec0effdSAtul Deshmukh 3917ec0effdSAtul Deshmukh /* 3927ec0effdSAtul Deshmukh * Either we got the lock, or someone 3937ec0effdSAtul Deshmukh * else died while holding it. 3947ec0effdSAtul Deshmukh * In either case, unlock. 3957ec0effdSAtul Deshmukh */ 3967ec0effdSAtul Deshmukh qla8044_flash_unlock(vha); 3977ec0effdSAtul Deshmukh } 3987ec0effdSAtul Deshmukh 3997ec0effdSAtul Deshmukh /* 4007ec0effdSAtul Deshmukh * Address and length are byte address 4017ec0effdSAtul Deshmukh */ 4027ec0effdSAtul Deshmukh static int 4037ec0effdSAtul Deshmukh qla8044_read_flash_data(scsi_qla_host_t *vha, uint8_t *p_data, 4047ec0effdSAtul Deshmukh uint32_t flash_addr, int u32_word_count) 4057ec0effdSAtul Deshmukh { 4067ec0effdSAtul Deshmukh int i, ret_val = QLA_SUCCESS; 4077ec0effdSAtul Deshmukh uint32_t u32_word; 4087ec0effdSAtul Deshmukh 4097ec0effdSAtul Deshmukh if (qla8044_flash_lock(vha) != QLA_SUCCESS) { 4107ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 4117ec0effdSAtul Deshmukh goto exit_lock_error; 4127ec0effdSAtul Deshmukh } 4137ec0effdSAtul Deshmukh 4147ec0effdSAtul Deshmukh if (flash_addr & 0x03) { 4157ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb117, 4167ec0effdSAtul Deshmukh "%s: Illegal addr = 0x%x\n", __func__, flash_addr); 4177ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 4187ec0effdSAtul Deshmukh goto exit_flash_read; 4197ec0effdSAtul Deshmukh } 4207ec0effdSAtul Deshmukh 4217ec0effdSAtul Deshmukh for (i = 0; i < u32_word_count; i++) { 4227ec0effdSAtul Deshmukh if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW, 4237ec0effdSAtul Deshmukh (flash_addr & 0xFFFF0000))) { 4247ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb119, 4257ec0effdSAtul Deshmukh "%s: failed to write addr 0x%x to " 4267ec0effdSAtul Deshmukh "FLASH_DIRECT_WINDOW\n! ", 4277ec0effdSAtul Deshmukh __func__, flash_addr); 4287ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 4297ec0effdSAtul Deshmukh goto exit_flash_read; 4307ec0effdSAtul Deshmukh } 4317ec0effdSAtul Deshmukh 4327ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha, 4337ec0effdSAtul Deshmukh QLA8044_FLASH_DIRECT_DATA(flash_addr), 4347ec0effdSAtul Deshmukh &u32_word); 4357ec0effdSAtul Deshmukh if (ret_val != QLA_SUCCESS) { 4367ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb08c, 4377ec0effdSAtul Deshmukh "%s: failed to read addr 0x%x!\n", 4387ec0effdSAtul Deshmukh __func__, flash_addr); 4397ec0effdSAtul Deshmukh goto exit_flash_read; 4407ec0effdSAtul Deshmukh } 4417ec0effdSAtul Deshmukh 4427ec0effdSAtul Deshmukh *(uint32_t *)p_data = u32_word; 4437ec0effdSAtul Deshmukh p_data = p_data + 4; 4447ec0effdSAtul Deshmukh flash_addr = flash_addr + 4; 4457ec0effdSAtul Deshmukh } 4467ec0effdSAtul Deshmukh 4477ec0effdSAtul Deshmukh exit_flash_read: 4487ec0effdSAtul Deshmukh qla8044_flash_unlock(vha); 4497ec0effdSAtul Deshmukh 4507ec0effdSAtul Deshmukh exit_lock_error: 4517ec0effdSAtul Deshmukh return ret_val; 4527ec0effdSAtul Deshmukh } 4537ec0effdSAtul Deshmukh 4547ec0effdSAtul Deshmukh /* 4557ec0effdSAtul Deshmukh * Address and length are byte address 4567ec0effdSAtul Deshmukh */ 4577ec0effdSAtul Deshmukh uint8_t * 4587ec0effdSAtul Deshmukh qla8044_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 4597ec0effdSAtul Deshmukh uint32_t offset, uint32_t length) 4607ec0effdSAtul Deshmukh { 4617ec0effdSAtul Deshmukh scsi_block_requests(vha->host); 4627ec0effdSAtul Deshmukh if (qla8044_read_flash_data(vha, (uint8_t *)buf, offset, length / 4) 4637ec0effdSAtul Deshmukh != QLA_SUCCESS) { 4647ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb08d, 4657ec0effdSAtul Deshmukh "%s: Failed to read from flash\n", 4667ec0effdSAtul Deshmukh __func__); 4677ec0effdSAtul Deshmukh } 4687ec0effdSAtul Deshmukh scsi_unblock_requests(vha->host); 4697ec0effdSAtul Deshmukh return buf; 4707ec0effdSAtul Deshmukh } 4717ec0effdSAtul Deshmukh 4727ec0effdSAtul Deshmukh inline int 4737ec0effdSAtul Deshmukh qla8044_need_reset(struct scsi_qla_host *vha) 4747ec0effdSAtul Deshmukh { 4757ec0effdSAtul Deshmukh uint32_t drv_state, drv_active; 4767ec0effdSAtul Deshmukh int rval; 4777ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 4787ec0effdSAtul Deshmukh 4797ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 4807ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 4817ec0effdSAtul Deshmukh 4827ec0effdSAtul Deshmukh rval = drv_state & (1 << ha->portnum); 4837ec0effdSAtul Deshmukh 4847ec0effdSAtul Deshmukh if (ha->flags.eeh_busy && drv_active) 4857ec0effdSAtul Deshmukh rval = 1; 4867ec0effdSAtul Deshmukh return rval; 4877ec0effdSAtul Deshmukh } 4887ec0effdSAtul Deshmukh 4897ec0effdSAtul Deshmukh /* 4907ec0effdSAtul Deshmukh * qla8044_write_list - Write the value (p_entry->arg2) to address specified 4917ec0effdSAtul Deshmukh * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between 4927ec0effdSAtul Deshmukh * entries. 4937ec0effdSAtul Deshmukh * 4947ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure 4957ec0effdSAtul Deshmukh * @p_hdr : reset_entry header for WRITE_LIST opcode. 4967ec0effdSAtul Deshmukh * 4977ec0effdSAtul Deshmukh */ 4987ec0effdSAtul Deshmukh static void 4997ec0effdSAtul Deshmukh qla8044_write_list(struct scsi_qla_host *vha, 5007ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr) 5017ec0effdSAtul Deshmukh { 5027ec0effdSAtul Deshmukh struct qla8044_entry *p_entry; 5037ec0effdSAtul Deshmukh uint32_t i; 5047ec0effdSAtul Deshmukh 5057ec0effdSAtul Deshmukh p_entry = (struct qla8044_entry *)((char *)p_hdr + 5067ec0effdSAtul Deshmukh sizeof(struct qla8044_reset_entry_hdr)); 5077ec0effdSAtul Deshmukh 5087ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) { 5097ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2); 5107ec0effdSAtul Deshmukh if (p_hdr->delay) 5117ec0effdSAtul Deshmukh udelay((uint32_t)(p_hdr->delay)); 5127ec0effdSAtul Deshmukh } 5137ec0effdSAtul Deshmukh } 5147ec0effdSAtul Deshmukh 5157ec0effdSAtul Deshmukh /* 5167ec0effdSAtul Deshmukh * qla8044_read_write_list - Read from address specified by p_entry->arg1, 5177ec0effdSAtul Deshmukh * write value read to address specified by p_entry->arg2, for all entries in 5187ec0effdSAtul Deshmukh * header with delay of p_hdr->delay between entries. 5197ec0effdSAtul Deshmukh * 5207ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure 5217ec0effdSAtul Deshmukh * @p_hdr : reset_entry header for READ_WRITE_LIST opcode. 5227ec0effdSAtul Deshmukh * 5237ec0effdSAtul Deshmukh */ 5247ec0effdSAtul Deshmukh static void 5257ec0effdSAtul Deshmukh qla8044_read_write_list(struct scsi_qla_host *vha, 5267ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr) 5277ec0effdSAtul Deshmukh { 5287ec0effdSAtul Deshmukh struct qla8044_entry *p_entry; 5297ec0effdSAtul Deshmukh uint32_t i; 5307ec0effdSAtul Deshmukh 5317ec0effdSAtul Deshmukh p_entry = (struct qla8044_entry *)((char *)p_hdr + 5327ec0effdSAtul Deshmukh sizeof(struct qla8044_reset_entry_hdr)); 5337ec0effdSAtul Deshmukh 5347ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) { 5357ec0effdSAtul Deshmukh qla8044_read_write_crb_reg(vha, p_entry->arg1, 5367ec0effdSAtul Deshmukh p_entry->arg2); 5377ec0effdSAtul Deshmukh if (p_hdr->delay) 5387ec0effdSAtul Deshmukh udelay((uint32_t)(p_hdr->delay)); 5397ec0effdSAtul Deshmukh } 5407ec0effdSAtul Deshmukh } 5417ec0effdSAtul Deshmukh 5427ec0effdSAtul Deshmukh /* 5437ec0effdSAtul Deshmukh * qla8044_poll_reg - Poll the given CRB addr for duration msecs till 5447ec0effdSAtul Deshmukh * value read ANDed with test_mask is equal to test_result. 5457ec0effdSAtul Deshmukh * 5467ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure 5477ec0effdSAtul Deshmukh * @addr : CRB register address 5487ec0effdSAtul Deshmukh * @duration : Poll for total of "duration" msecs 5497ec0effdSAtul Deshmukh * @test_mask : Mask value read with "test_mask" 5507ec0effdSAtul Deshmukh * @test_result : Compare (value&test_mask) with test_result. 5517ec0effdSAtul Deshmukh * 5527ec0effdSAtul Deshmukh * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 5537ec0effdSAtul Deshmukh */ 5547ec0effdSAtul Deshmukh static int 5557ec0effdSAtul Deshmukh qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr, 5567ec0effdSAtul Deshmukh int duration, uint32_t test_mask, uint32_t test_result) 5577ec0effdSAtul Deshmukh { 5587ec0effdSAtul Deshmukh uint32_t value; 5597ec0effdSAtul Deshmukh int timeout_error; 5607ec0effdSAtul Deshmukh uint8_t retries; 5617ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 5627ec0effdSAtul Deshmukh 5637ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha, addr, &value); 5647ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) { 5657ec0effdSAtul Deshmukh timeout_error = 1; 5667ec0effdSAtul Deshmukh goto exit_poll_reg; 5677ec0effdSAtul Deshmukh } 5687ec0effdSAtul Deshmukh 5697ec0effdSAtul Deshmukh /* poll every 1/10 of the total duration */ 5707ec0effdSAtul Deshmukh retries = duration/10; 5717ec0effdSAtul Deshmukh 5727ec0effdSAtul Deshmukh do { 5737ec0effdSAtul Deshmukh if ((value & test_mask) != test_result) { 5747ec0effdSAtul Deshmukh timeout_error = 1; 5757ec0effdSAtul Deshmukh msleep(duration/10); 5767ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha, addr, &value); 5777ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) { 5787ec0effdSAtul Deshmukh timeout_error = 1; 5797ec0effdSAtul Deshmukh goto exit_poll_reg; 5807ec0effdSAtul Deshmukh } 5817ec0effdSAtul Deshmukh } else { 5827ec0effdSAtul Deshmukh timeout_error = 0; 5837ec0effdSAtul Deshmukh break; 5847ec0effdSAtul Deshmukh } 5857ec0effdSAtul Deshmukh } while (retries--); 5867ec0effdSAtul Deshmukh 5877ec0effdSAtul Deshmukh exit_poll_reg: 5887ec0effdSAtul Deshmukh if (timeout_error) { 5897ec0effdSAtul Deshmukh vha->reset_tmplt.seq_error++; 5907ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb090, 5917ec0effdSAtul Deshmukh "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n", 5927ec0effdSAtul Deshmukh __func__, value, test_mask, test_result); 5937ec0effdSAtul Deshmukh } 5947ec0effdSAtul Deshmukh 5957ec0effdSAtul Deshmukh return timeout_error; 5967ec0effdSAtul Deshmukh } 5977ec0effdSAtul Deshmukh 5987ec0effdSAtul Deshmukh /* 5997ec0effdSAtul Deshmukh * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB 6007ec0effdSAtul Deshmukh * register specified by p_entry->arg1 and compare (value AND test_mask) with 6017ec0effdSAtul Deshmukh * test_result to validate it. Wait for p_hdr->delay between processing entries. 6027ec0effdSAtul Deshmukh * 6037ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure 6047ec0effdSAtul Deshmukh * @p_hdr : reset_entry header for POLL_LIST opcode. 6057ec0effdSAtul Deshmukh * 6067ec0effdSAtul Deshmukh */ 6077ec0effdSAtul Deshmukh static void 6087ec0effdSAtul Deshmukh qla8044_poll_list(struct scsi_qla_host *vha, 6097ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr) 6107ec0effdSAtul Deshmukh { 6117ec0effdSAtul Deshmukh long delay; 6127ec0effdSAtul Deshmukh struct qla8044_entry *p_entry; 6137ec0effdSAtul Deshmukh struct qla8044_poll *p_poll; 6147ec0effdSAtul Deshmukh uint32_t i; 6157ec0effdSAtul Deshmukh uint32_t value; 6167ec0effdSAtul Deshmukh 6177ec0effdSAtul Deshmukh p_poll = (struct qla8044_poll *) 6187ec0effdSAtul Deshmukh ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr)); 6197ec0effdSAtul Deshmukh 6207ec0effdSAtul Deshmukh /* Entries start after 8 byte qla8044_poll, poll header contains 6217ec0effdSAtul Deshmukh * the test_mask, test_value. 6227ec0effdSAtul Deshmukh */ 6237ec0effdSAtul Deshmukh p_entry = (struct qla8044_entry *)((char *)p_poll + 6247ec0effdSAtul Deshmukh sizeof(struct qla8044_poll)); 6257ec0effdSAtul Deshmukh 6267ec0effdSAtul Deshmukh delay = (long)p_hdr->delay; 6277ec0effdSAtul Deshmukh 6287ec0effdSAtul Deshmukh if (!delay) { 6297ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) 6307ec0effdSAtul Deshmukh qla8044_poll_reg(vha, p_entry->arg1, 6317ec0effdSAtul Deshmukh delay, p_poll->test_mask, p_poll->test_value); 6327ec0effdSAtul Deshmukh } else { 6337ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) { 6347ec0effdSAtul Deshmukh if (delay) { 6357ec0effdSAtul Deshmukh if (qla8044_poll_reg(vha, 6367ec0effdSAtul Deshmukh p_entry->arg1, delay, 6377ec0effdSAtul Deshmukh p_poll->test_mask, 6387ec0effdSAtul Deshmukh p_poll->test_value)) { 6397ec0effdSAtul Deshmukh /*If 6407ec0effdSAtul Deshmukh * (data_read&test_mask != test_value) 6417ec0effdSAtul Deshmukh * read TIMEOUT_ADDR (arg1) and 6427ec0effdSAtul Deshmukh * ADDR (arg2) registers 6437ec0effdSAtul Deshmukh */ 6447ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, 6457ec0effdSAtul Deshmukh p_entry->arg1, &value); 6467ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, 6477ec0effdSAtul Deshmukh p_entry->arg2, &value); 6487ec0effdSAtul Deshmukh } 6497ec0effdSAtul Deshmukh } 6507ec0effdSAtul Deshmukh } 6517ec0effdSAtul Deshmukh } 6527ec0effdSAtul Deshmukh } 6537ec0effdSAtul Deshmukh 6547ec0effdSAtul Deshmukh /* 6557ec0effdSAtul Deshmukh * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr, 6567ec0effdSAtul Deshmukh * read ar_addr, if (value& test_mask != test_mask) re-read till timeout 6577ec0effdSAtul Deshmukh * expires. 6587ec0effdSAtul Deshmukh * 6597ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure 6607ec0effdSAtul Deshmukh * @p_hdr : reset entry header for POLL_WRITE_LIST opcode. 6617ec0effdSAtul Deshmukh * 6627ec0effdSAtul Deshmukh */ 6637ec0effdSAtul Deshmukh static void 6647ec0effdSAtul Deshmukh qla8044_poll_write_list(struct scsi_qla_host *vha, 6657ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr) 6667ec0effdSAtul Deshmukh { 6677ec0effdSAtul Deshmukh long delay; 6687ec0effdSAtul Deshmukh struct qla8044_quad_entry *p_entry; 6697ec0effdSAtul Deshmukh struct qla8044_poll *p_poll; 6707ec0effdSAtul Deshmukh uint32_t i; 6717ec0effdSAtul Deshmukh 6727ec0effdSAtul Deshmukh p_poll = (struct qla8044_poll *)((char *)p_hdr + 6737ec0effdSAtul Deshmukh sizeof(struct qla8044_reset_entry_hdr)); 6747ec0effdSAtul Deshmukh 6757ec0effdSAtul Deshmukh p_entry = (struct qla8044_quad_entry *)((char *)p_poll + 6767ec0effdSAtul Deshmukh sizeof(struct qla8044_poll)); 6777ec0effdSAtul Deshmukh 6787ec0effdSAtul Deshmukh delay = (long)p_hdr->delay; 6797ec0effdSAtul Deshmukh 6807ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) { 6817ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, 6827ec0effdSAtul Deshmukh p_entry->dr_addr, p_entry->dr_value); 6837ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, 6847ec0effdSAtul Deshmukh p_entry->ar_addr, p_entry->ar_value); 6857ec0effdSAtul Deshmukh if (delay) { 6867ec0effdSAtul Deshmukh if (qla8044_poll_reg(vha, 6877ec0effdSAtul Deshmukh p_entry->ar_addr, delay, 6887ec0effdSAtul Deshmukh p_poll->test_mask, 6897ec0effdSAtul Deshmukh p_poll->test_value)) { 6907ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb091, 6917ec0effdSAtul Deshmukh "%s: Timeout Error: poll list, ", 6927ec0effdSAtul Deshmukh __func__); 6937ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb092, 6947ec0effdSAtul Deshmukh "item_num %d, entry_num %d\n", i, 6957ec0effdSAtul Deshmukh vha->reset_tmplt.seq_index); 6967ec0effdSAtul Deshmukh } 6977ec0effdSAtul Deshmukh } 6987ec0effdSAtul Deshmukh } 6997ec0effdSAtul Deshmukh } 7007ec0effdSAtul Deshmukh 7017ec0effdSAtul Deshmukh /* 7027ec0effdSAtul Deshmukh * qla8044_read_modify_write - Read value from p_entry->arg1, modify the 7037ec0effdSAtul Deshmukh * value, write value to p_entry->arg2. Process entries with p_hdr->delay 7047ec0effdSAtul Deshmukh * between entries. 7057ec0effdSAtul Deshmukh * 7067ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure 7077ec0effdSAtul Deshmukh * @p_hdr : header with shift/or/xor values. 7087ec0effdSAtul Deshmukh * 7097ec0effdSAtul Deshmukh */ 7107ec0effdSAtul Deshmukh static void 7117ec0effdSAtul Deshmukh qla8044_read_modify_write(struct scsi_qla_host *vha, 7127ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr) 7137ec0effdSAtul Deshmukh { 7147ec0effdSAtul Deshmukh struct qla8044_entry *p_entry; 7157ec0effdSAtul Deshmukh struct qla8044_rmw *p_rmw_hdr; 7167ec0effdSAtul Deshmukh uint32_t i; 7177ec0effdSAtul Deshmukh 7187ec0effdSAtul Deshmukh p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr + 7197ec0effdSAtul Deshmukh sizeof(struct qla8044_reset_entry_hdr)); 7207ec0effdSAtul Deshmukh 7217ec0effdSAtul Deshmukh p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr + 7227ec0effdSAtul Deshmukh sizeof(struct qla8044_rmw)); 7237ec0effdSAtul Deshmukh 7247ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) { 7257ec0effdSAtul Deshmukh qla8044_rmw_crb_reg(vha, p_entry->arg1, 7267ec0effdSAtul Deshmukh p_entry->arg2, p_rmw_hdr); 7277ec0effdSAtul Deshmukh if (p_hdr->delay) 7287ec0effdSAtul Deshmukh udelay((uint32_t)(p_hdr->delay)); 7297ec0effdSAtul Deshmukh } 7307ec0effdSAtul Deshmukh } 7317ec0effdSAtul Deshmukh 7327ec0effdSAtul Deshmukh /* 7337ec0effdSAtul Deshmukh * qla8044_pause - Wait for p_hdr->delay msecs, called between processing 7347ec0effdSAtul Deshmukh * two entries of a sequence. 7357ec0effdSAtul Deshmukh * 7367ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure 7377ec0effdSAtul Deshmukh * @p_hdr : Common reset entry header. 7387ec0effdSAtul Deshmukh * 7397ec0effdSAtul Deshmukh */ 7407ec0effdSAtul Deshmukh static 7417ec0effdSAtul Deshmukh void qla8044_pause(struct scsi_qla_host *vha, 7427ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr) 7437ec0effdSAtul Deshmukh { 7447ec0effdSAtul Deshmukh if (p_hdr->delay) 7457ec0effdSAtul Deshmukh mdelay((uint32_t)((long)p_hdr->delay)); 7467ec0effdSAtul Deshmukh } 7477ec0effdSAtul Deshmukh 7487ec0effdSAtul Deshmukh /* 7497ec0effdSAtul Deshmukh * qla8044_template_end - Indicates end of reset sequence processing. 7507ec0effdSAtul Deshmukh * 7517ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure 7527ec0effdSAtul Deshmukh * @p_hdr : Common reset entry header. 7537ec0effdSAtul Deshmukh * 7547ec0effdSAtul Deshmukh */ 7557ec0effdSAtul Deshmukh static void 7567ec0effdSAtul Deshmukh qla8044_template_end(struct scsi_qla_host *vha, 7577ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr) 7587ec0effdSAtul Deshmukh { 7597ec0effdSAtul Deshmukh vha->reset_tmplt.template_end = 1; 7607ec0effdSAtul Deshmukh 7617ec0effdSAtul Deshmukh if (vha->reset_tmplt.seq_error == 0) { 7627ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb093, 7637ec0effdSAtul Deshmukh "%s: Reset sequence completed SUCCESSFULLY.\n", __func__); 7647ec0effdSAtul Deshmukh } else { 7657ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb094, 7667ec0effdSAtul Deshmukh "%s: Reset sequence completed with some timeout " 7677ec0effdSAtul Deshmukh "errors.\n", __func__); 7687ec0effdSAtul Deshmukh } 7697ec0effdSAtul Deshmukh } 7707ec0effdSAtul Deshmukh 7717ec0effdSAtul Deshmukh /* 7727ec0effdSAtul Deshmukh * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr, 7737ec0effdSAtul Deshmukh * if (value & test_mask != test_value) re-read till timeout value expires, 7747ec0effdSAtul Deshmukh * read dr_addr register and assign to reset_tmplt.array. 7757ec0effdSAtul Deshmukh * 7767ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure 7777ec0effdSAtul Deshmukh * @p_hdr : Common reset entry header. 7787ec0effdSAtul Deshmukh * 7797ec0effdSAtul Deshmukh */ 7807ec0effdSAtul Deshmukh static void 7817ec0effdSAtul Deshmukh qla8044_poll_read_list(struct scsi_qla_host *vha, 7827ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr) 7837ec0effdSAtul Deshmukh { 7847ec0effdSAtul Deshmukh long delay; 7857ec0effdSAtul Deshmukh int index; 7867ec0effdSAtul Deshmukh struct qla8044_quad_entry *p_entry; 7877ec0effdSAtul Deshmukh struct qla8044_poll *p_poll; 7887ec0effdSAtul Deshmukh uint32_t i; 7897ec0effdSAtul Deshmukh uint32_t value; 7907ec0effdSAtul Deshmukh 7917ec0effdSAtul Deshmukh p_poll = (struct qla8044_poll *) 7927ec0effdSAtul Deshmukh ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr)); 7937ec0effdSAtul Deshmukh 7947ec0effdSAtul Deshmukh p_entry = (struct qla8044_quad_entry *) 7957ec0effdSAtul Deshmukh ((char *)p_poll + sizeof(struct qla8044_poll)); 7967ec0effdSAtul Deshmukh 7977ec0effdSAtul Deshmukh delay = (long)p_hdr->delay; 7987ec0effdSAtul Deshmukh 7997ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) { 8007ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, p_entry->ar_addr, 8017ec0effdSAtul Deshmukh p_entry->ar_value); 8027ec0effdSAtul Deshmukh if (delay) { 8037ec0effdSAtul Deshmukh if (qla8044_poll_reg(vha, p_entry->ar_addr, delay, 8047ec0effdSAtul Deshmukh p_poll->test_mask, p_poll->test_value)) { 8057ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb095, 8067ec0effdSAtul Deshmukh "%s: Timeout Error: poll " 8077ec0effdSAtul Deshmukh "list, ", __func__); 8087ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb096, 8097ec0effdSAtul Deshmukh "Item_num %d, " 8107ec0effdSAtul Deshmukh "entry_num %d\n", i, 8117ec0effdSAtul Deshmukh vha->reset_tmplt.seq_index); 8127ec0effdSAtul Deshmukh } else { 8137ec0effdSAtul Deshmukh index = vha->reset_tmplt.array_index; 8147ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, 8157ec0effdSAtul Deshmukh p_entry->dr_addr, &value); 8167ec0effdSAtul Deshmukh vha->reset_tmplt.array[index++] = value; 8177ec0effdSAtul Deshmukh if (index == QLA8044_MAX_RESET_SEQ_ENTRIES) 8187ec0effdSAtul Deshmukh vha->reset_tmplt.array_index = 1; 8197ec0effdSAtul Deshmukh } 8207ec0effdSAtul Deshmukh } 8217ec0effdSAtul Deshmukh } 8227ec0effdSAtul Deshmukh } 8237ec0effdSAtul Deshmukh 8247ec0effdSAtul Deshmukh /* 8257ec0effdSAtul Deshmukh * qla8031_process_reset_template - Process all entries in reset template 8267ec0effdSAtul Deshmukh * till entry with SEQ_END opcode, which indicates end of the reset template 8277ec0effdSAtul Deshmukh * processing. Each entry has a Reset Entry header, entry opcode/command, with 8287ec0effdSAtul Deshmukh * size of the entry, number of entries in sub-sequence and delay in microsecs 8297ec0effdSAtul Deshmukh * or timeout in millisecs. 8307ec0effdSAtul Deshmukh * 8317ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure 8327ec0effdSAtul Deshmukh * @p_buff : Common reset entry header. 8337ec0effdSAtul Deshmukh * 8347ec0effdSAtul Deshmukh */ 8357ec0effdSAtul Deshmukh static void 8367ec0effdSAtul Deshmukh qla8044_process_reset_template(struct scsi_qla_host *vha, 8377ec0effdSAtul Deshmukh char *p_buff) 8387ec0effdSAtul Deshmukh { 8397ec0effdSAtul Deshmukh int index, entries; 8407ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr; 8417ec0effdSAtul Deshmukh char *p_entry = p_buff; 8427ec0effdSAtul Deshmukh 8437ec0effdSAtul Deshmukh vha->reset_tmplt.seq_end = 0; 8447ec0effdSAtul Deshmukh vha->reset_tmplt.template_end = 0; 8457ec0effdSAtul Deshmukh entries = vha->reset_tmplt.hdr->entries; 8467ec0effdSAtul Deshmukh index = vha->reset_tmplt.seq_index; 8477ec0effdSAtul Deshmukh 8487ec0effdSAtul Deshmukh for (; (!vha->reset_tmplt.seq_end) && (index < entries); index++) { 8497ec0effdSAtul Deshmukh p_hdr = (struct qla8044_reset_entry_hdr *)p_entry; 8507ec0effdSAtul Deshmukh switch (p_hdr->cmd) { 8517ec0effdSAtul Deshmukh case OPCODE_NOP: 8527ec0effdSAtul Deshmukh break; 8537ec0effdSAtul Deshmukh case OPCODE_WRITE_LIST: 8547ec0effdSAtul Deshmukh qla8044_write_list(vha, p_hdr); 8557ec0effdSAtul Deshmukh break; 8567ec0effdSAtul Deshmukh case OPCODE_READ_WRITE_LIST: 8577ec0effdSAtul Deshmukh qla8044_read_write_list(vha, p_hdr); 8587ec0effdSAtul Deshmukh break; 8597ec0effdSAtul Deshmukh case OPCODE_POLL_LIST: 8607ec0effdSAtul Deshmukh qla8044_poll_list(vha, p_hdr); 8617ec0effdSAtul Deshmukh break; 8627ec0effdSAtul Deshmukh case OPCODE_POLL_WRITE_LIST: 8637ec0effdSAtul Deshmukh qla8044_poll_write_list(vha, p_hdr); 8647ec0effdSAtul Deshmukh break; 8657ec0effdSAtul Deshmukh case OPCODE_READ_MODIFY_WRITE: 8667ec0effdSAtul Deshmukh qla8044_read_modify_write(vha, p_hdr); 8677ec0effdSAtul Deshmukh break; 8687ec0effdSAtul Deshmukh case OPCODE_SEQ_PAUSE: 8697ec0effdSAtul Deshmukh qla8044_pause(vha, p_hdr); 8707ec0effdSAtul Deshmukh break; 8717ec0effdSAtul Deshmukh case OPCODE_SEQ_END: 8727ec0effdSAtul Deshmukh vha->reset_tmplt.seq_end = 1; 8737ec0effdSAtul Deshmukh break; 8747ec0effdSAtul Deshmukh case OPCODE_TMPL_END: 8757ec0effdSAtul Deshmukh qla8044_template_end(vha, p_hdr); 8767ec0effdSAtul Deshmukh break; 8777ec0effdSAtul Deshmukh case OPCODE_POLL_READ_LIST: 8787ec0effdSAtul Deshmukh qla8044_poll_read_list(vha, p_hdr); 8797ec0effdSAtul Deshmukh break; 8807ec0effdSAtul Deshmukh default: 8817ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb097, 8827ec0effdSAtul Deshmukh "%s: Unknown command ==> 0x%04x on " 8837ec0effdSAtul Deshmukh "entry = %d\n", __func__, p_hdr->cmd, index); 8847ec0effdSAtul Deshmukh break; 8857ec0effdSAtul Deshmukh } 8867ec0effdSAtul Deshmukh /* 8877ec0effdSAtul Deshmukh *Set pointer to next entry in the sequence. 8887ec0effdSAtul Deshmukh */ 8897ec0effdSAtul Deshmukh p_entry += p_hdr->size; 8907ec0effdSAtul Deshmukh } 8917ec0effdSAtul Deshmukh vha->reset_tmplt.seq_index = index; 8927ec0effdSAtul Deshmukh } 8937ec0effdSAtul Deshmukh 8947ec0effdSAtul Deshmukh static void 8957ec0effdSAtul Deshmukh qla8044_process_init_seq(struct scsi_qla_host *vha) 8967ec0effdSAtul Deshmukh { 8977ec0effdSAtul Deshmukh qla8044_process_reset_template(vha, 8987ec0effdSAtul Deshmukh vha->reset_tmplt.init_offset); 8997ec0effdSAtul Deshmukh if (vha->reset_tmplt.seq_end != 1) 9007ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb098, 9017ec0effdSAtul Deshmukh "%s: Abrupt INIT Sub-Sequence end.\n", 9027ec0effdSAtul Deshmukh __func__); 9037ec0effdSAtul Deshmukh } 9047ec0effdSAtul Deshmukh 9057ec0effdSAtul Deshmukh static void 9067ec0effdSAtul Deshmukh qla8044_process_stop_seq(struct scsi_qla_host *vha) 9077ec0effdSAtul Deshmukh { 9087ec0effdSAtul Deshmukh vha->reset_tmplt.seq_index = 0; 9097ec0effdSAtul Deshmukh qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset); 9107ec0effdSAtul Deshmukh if (vha->reset_tmplt.seq_end != 1) 9117ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb099, 9127ec0effdSAtul Deshmukh "%s: Abrupt STOP Sub-Sequence end.\n", __func__); 9137ec0effdSAtul Deshmukh } 9147ec0effdSAtul Deshmukh 9157ec0effdSAtul Deshmukh static void 9167ec0effdSAtul Deshmukh qla8044_process_start_seq(struct scsi_qla_host *vha) 9177ec0effdSAtul Deshmukh { 9187ec0effdSAtul Deshmukh qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset); 9197ec0effdSAtul Deshmukh if (vha->reset_tmplt.template_end != 1) 9207ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb09a, 9217ec0effdSAtul Deshmukh "%s: Abrupt START Sub-Sequence end.\n", 9227ec0effdSAtul Deshmukh __func__); 9237ec0effdSAtul Deshmukh } 9247ec0effdSAtul Deshmukh 9257ec0effdSAtul Deshmukh static int 9267ec0effdSAtul Deshmukh qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha, 9277ec0effdSAtul Deshmukh uint32_t flash_addr, uint8_t *p_data, int u32_word_count) 9287ec0effdSAtul Deshmukh { 9297ec0effdSAtul Deshmukh uint32_t i; 9307ec0effdSAtul Deshmukh uint32_t u32_word; 9317ec0effdSAtul Deshmukh uint32_t flash_offset; 9327ec0effdSAtul Deshmukh uint32_t addr = flash_addr; 9337ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 9347ec0effdSAtul Deshmukh 9357ec0effdSAtul Deshmukh flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1); 9367ec0effdSAtul Deshmukh 9377ec0effdSAtul Deshmukh if (addr & 0x3) { 9387ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n", 9397ec0effdSAtul Deshmukh __func__, addr); 9407ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 9417ec0effdSAtul Deshmukh goto exit_lockless_read; 9427ec0effdSAtul Deshmukh } 9437ec0effdSAtul Deshmukh 9447ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, 9457ec0effdSAtul Deshmukh QLA8044_FLASH_DIRECT_WINDOW, (addr)); 9467ec0effdSAtul Deshmukh 9477ec0effdSAtul Deshmukh if (ret_val != QLA_SUCCESS) { 9487ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb09c, 9497ec0effdSAtul Deshmukh "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n", 9507ec0effdSAtul Deshmukh __func__, addr); 9517ec0effdSAtul Deshmukh goto exit_lockless_read; 9527ec0effdSAtul Deshmukh } 9537ec0effdSAtul Deshmukh 9547ec0effdSAtul Deshmukh /* Check if data is spread across multiple sectors */ 9557ec0effdSAtul Deshmukh if ((flash_offset + (u32_word_count * sizeof(uint32_t))) > 9567ec0effdSAtul Deshmukh (QLA8044_FLASH_SECTOR_SIZE - 1)) { 9577ec0effdSAtul Deshmukh /* Multi sector read */ 9587ec0effdSAtul Deshmukh for (i = 0; i < u32_word_count; i++) { 9597ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha, 9607ec0effdSAtul Deshmukh QLA8044_FLASH_DIRECT_DATA(addr), &u32_word); 9617ec0effdSAtul Deshmukh if (ret_val != QLA_SUCCESS) { 9627ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb09d, 9637ec0effdSAtul Deshmukh "%s: failed to read addr 0x%x!\n", 9647ec0effdSAtul Deshmukh __func__, addr); 9657ec0effdSAtul Deshmukh goto exit_lockless_read; 9667ec0effdSAtul Deshmukh } 9677ec0effdSAtul Deshmukh *(uint32_t *)p_data = u32_word; 9687ec0effdSAtul Deshmukh p_data = p_data + 4; 9697ec0effdSAtul Deshmukh addr = addr + 4; 9707ec0effdSAtul Deshmukh flash_offset = flash_offset + 4; 9717ec0effdSAtul Deshmukh if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) { 9727ec0effdSAtul Deshmukh /* This write is needed once for each sector */ 9737ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, 9747ec0effdSAtul Deshmukh QLA8044_FLASH_DIRECT_WINDOW, (addr)); 9757ec0effdSAtul Deshmukh if (ret_val != QLA_SUCCESS) { 9767ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb09f, 9777ec0effdSAtul Deshmukh "%s: failed to write addr " 9787ec0effdSAtul Deshmukh "0x%x to FLASH_DIRECT_WINDOW!\n", 9797ec0effdSAtul Deshmukh __func__, addr); 9807ec0effdSAtul Deshmukh goto exit_lockless_read; 9817ec0effdSAtul Deshmukh } 9827ec0effdSAtul Deshmukh flash_offset = 0; 9837ec0effdSAtul Deshmukh } 9847ec0effdSAtul Deshmukh } 9857ec0effdSAtul Deshmukh } else { 9867ec0effdSAtul Deshmukh /* Single sector read */ 9877ec0effdSAtul Deshmukh for (i = 0; i < u32_word_count; i++) { 9887ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha, 9897ec0effdSAtul Deshmukh QLA8044_FLASH_DIRECT_DATA(addr), &u32_word); 9907ec0effdSAtul Deshmukh if (ret_val != QLA_SUCCESS) { 9917ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a0, 9927ec0effdSAtul Deshmukh "%s: failed to read addr 0x%x!\n", 9937ec0effdSAtul Deshmukh __func__, addr); 9947ec0effdSAtul Deshmukh goto exit_lockless_read; 9957ec0effdSAtul Deshmukh } 9967ec0effdSAtul Deshmukh *(uint32_t *)p_data = u32_word; 9977ec0effdSAtul Deshmukh p_data = p_data + 4; 9987ec0effdSAtul Deshmukh addr = addr + 4; 9997ec0effdSAtul Deshmukh } 10007ec0effdSAtul Deshmukh } 10017ec0effdSAtul Deshmukh 10027ec0effdSAtul Deshmukh exit_lockless_read: 10037ec0effdSAtul Deshmukh return ret_val; 10047ec0effdSAtul Deshmukh } 10057ec0effdSAtul Deshmukh 10067ec0effdSAtul Deshmukh /* 10077ec0effdSAtul Deshmukh * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory 10087ec0effdSAtul Deshmukh * 10097ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure 10107ec0effdSAtul Deshmukh * addr : Flash address to write to 10117ec0effdSAtul Deshmukh * data : Data to be written 10127ec0effdSAtul Deshmukh * count : word_count to be written 10137ec0effdSAtul Deshmukh * 10147ec0effdSAtul Deshmukh * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 10157ec0effdSAtul Deshmukh */ 10167ec0effdSAtul Deshmukh static int 10177ec0effdSAtul Deshmukh qla8044_ms_mem_write_128b(struct scsi_qla_host *vha, 10187ec0effdSAtul Deshmukh uint64_t addr, uint32_t *data, uint32_t count) 10197ec0effdSAtul Deshmukh { 10207ec0effdSAtul Deshmukh int i, j, ret_val = QLA_SUCCESS; 10217ec0effdSAtul Deshmukh uint32_t agt_ctrl; 10227ec0effdSAtul Deshmukh unsigned long flags; 10237ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 10247ec0effdSAtul Deshmukh 10257ec0effdSAtul Deshmukh /* Only 128-bit aligned access */ 10267ec0effdSAtul Deshmukh if (addr & 0xF) { 10277ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 10287ec0effdSAtul Deshmukh goto exit_ms_mem_write; 10297ec0effdSAtul Deshmukh } 10307ec0effdSAtul Deshmukh write_lock_irqsave(&ha->hw_lock, flags); 10317ec0effdSAtul Deshmukh 10327ec0effdSAtul Deshmukh /* Write address */ 10337ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0); 10347ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) { 10357ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a1, 10367ec0effdSAtul Deshmukh "%s: write to AGT_ADDR_HI failed!\n", __func__); 10377ec0effdSAtul Deshmukh goto exit_ms_mem_write_unlock; 10387ec0effdSAtul Deshmukh } 10397ec0effdSAtul Deshmukh 10407ec0effdSAtul Deshmukh for (i = 0; i < count; i++, addr += 16) { 10417ec0effdSAtul Deshmukh if (!((QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_QDR_NET, 10427ec0effdSAtul Deshmukh QLA8044_ADDR_QDR_NET_MAX)) || 10437ec0effdSAtul Deshmukh (QLA8044_ADDR_IN_RANGE(addr, QLA8044_ADDR_DDR_NET, 10447ec0effdSAtul Deshmukh QLA8044_ADDR_DDR_NET_MAX)))) { 10457ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 10467ec0effdSAtul Deshmukh goto exit_ms_mem_write_unlock; 10477ec0effdSAtul Deshmukh } 10487ec0effdSAtul Deshmukh 10497ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, 10507ec0effdSAtul Deshmukh MD_MIU_TEST_AGT_ADDR_LO, addr); 10517ec0effdSAtul Deshmukh 10527ec0effdSAtul Deshmukh /* Write data */ 10537ec0effdSAtul Deshmukh ret_val += qla8044_wr_reg_indirect(vha, 10547ec0effdSAtul Deshmukh MD_MIU_TEST_AGT_WRDATA_LO, *data++); 10557ec0effdSAtul Deshmukh ret_val += qla8044_wr_reg_indirect(vha, 10567ec0effdSAtul Deshmukh MD_MIU_TEST_AGT_WRDATA_HI, *data++); 10577ec0effdSAtul Deshmukh ret_val += qla8044_wr_reg_indirect(vha, 10587ec0effdSAtul Deshmukh MD_MIU_TEST_AGT_WRDATA_ULO, *data++); 10597ec0effdSAtul Deshmukh ret_val += qla8044_wr_reg_indirect(vha, 10607ec0effdSAtul Deshmukh MD_MIU_TEST_AGT_WRDATA_UHI, *data++); 10617ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) { 10627ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a2, 10637ec0effdSAtul Deshmukh "%s: write to AGT_WRDATA failed!\n", 10647ec0effdSAtul Deshmukh __func__); 10657ec0effdSAtul Deshmukh goto exit_ms_mem_write_unlock; 10667ec0effdSAtul Deshmukh } 10677ec0effdSAtul Deshmukh 10687ec0effdSAtul Deshmukh /* Check write status */ 10697ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, 10707ec0effdSAtul Deshmukh MIU_TA_CTL_WRITE_ENABLE); 10717ec0effdSAtul Deshmukh ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, 10727ec0effdSAtul Deshmukh MIU_TA_CTL_WRITE_START); 10737ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) { 10747ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a3, 10757ec0effdSAtul Deshmukh "%s: write to AGT_CTRL failed!\n", __func__); 10767ec0effdSAtul Deshmukh goto exit_ms_mem_write_unlock; 10777ec0effdSAtul Deshmukh } 10787ec0effdSAtul Deshmukh 10797ec0effdSAtul Deshmukh for (j = 0; j < MAX_CTL_CHECK; j++) { 10807ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha, 10817ec0effdSAtul Deshmukh MD_MIU_TEST_AGT_CTRL, &agt_ctrl); 10827ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) { 10837ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a4, 10847ec0effdSAtul Deshmukh "%s: failed to read " 10857ec0effdSAtul Deshmukh "MD_MIU_TEST_AGT_CTRL!\n", __func__); 10867ec0effdSAtul Deshmukh goto exit_ms_mem_write_unlock; 10877ec0effdSAtul Deshmukh } 10887ec0effdSAtul Deshmukh if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0) 10897ec0effdSAtul Deshmukh break; 10907ec0effdSAtul Deshmukh } 10917ec0effdSAtul Deshmukh 10927ec0effdSAtul Deshmukh /* Status check failed */ 10937ec0effdSAtul Deshmukh if (j >= MAX_CTL_CHECK) { 10947ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a5, 10957ec0effdSAtul Deshmukh "%s: MS memory write failed!\n", 10967ec0effdSAtul Deshmukh __func__); 10977ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 10987ec0effdSAtul Deshmukh goto exit_ms_mem_write_unlock; 10997ec0effdSAtul Deshmukh } 11007ec0effdSAtul Deshmukh } 11017ec0effdSAtul Deshmukh 11027ec0effdSAtul Deshmukh exit_ms_mem_write_unlock: 11037ec0effdSAtul Deshmukh write_unlock_irqrestore(&ha->hw_lock, flags); 11047ec0effdSAtul Deshmukh 11057ec0effdSAtul Deshmukh exit_ms_mem_write: 11067ec0effdSAtul Deshmukh return ret_val; 11077ec0effdSAtul Deshmukh } 11087ec0effdSAtul Deshmukh 11097ec0effdSAtul Deshmukh static int 11107ec0effdSAtul Deshmukh qla8044_copy_bootloader(struct scsi_qla_host *vha) 11117ec0effdSAtul Deshmukh { 11127ec0effdSAtul Deshmukh uint8_t *p_cache; 11137ec0effdSAtul Deshmukh uint32_t src, count, size; 11147ec0effdSAtul Deshmukh uint64_t dest; 11157ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 11167ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 11177ec0effdSAtul Deshmukh 11187ec0effdSAtul Deshmukh src = QLA8044_BOOTLOADER_FLASH_ADDR; 11197ec0effdSAtul Deshmukh dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR); 11207ec0effdSAtul Deshmukh size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE); 11217ec0effdSAtul Deshmukh 11227ec0effdSAtul Deshmukh /* 128 bit alignment check */ 11237ec0effdSAtul Deshmukh if (size & 0xF) 11247ec0effdSAtul Deshmukh size = (size + 16) & ~0xF; 11257ec0effdSAtul Deshmukh 11267ec0effdSAtul Deshmukh /* 16 byte count */ 11277ec0effdSAtul Deshmukh count = size/16; 11287ec0effdSAtul Deshmukh 11297ec0effdSAtul Deshmukh p_cache = vmalloc(size); 11307ec0effdSAtul Deshmukh if (p_cache == NULL) { 11317ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a6, 11327ec0effdSAtul Deshmukh "%s: Failed to allocate memory for " 11337ec0effdSAtul Deshmukh "boot loader cache\n", __func__); 11347ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 11357ec0effdSAtul Deshmukh goto exit_copy_bootloader; 11367ec0effdSAtul Deshmukh } 11377ec0effdSAtul Deshmukh 11387ec0effdSAtul Deshmukh ret_val = qla8044_lockless_flash_read_u32(vha, src, 11397ec0effdSAtul Deshmukh p_cache, size/sizeof(uint32_t)); 11407ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) { 11417ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a7, 11427ec0effdSAtul Deshmukh "%s: Error reading F/W from flash!!!\n", __func__); 11437ec0effdSAtul Deshmukh goto exit_copy_error; 11447ec0effdSAtul Deshmukh } 11457ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n", 11467ec0effdSAtul Deshmukh __func__); 11477ec0effdSAtul Deshmukh 11487ec0effdSAtul Deshmukh /* 128 bit/16 byte write to MS memory */ 11497ec0effdSAtul Deshmukh ret_val = qla8044_ms_mem_write_128b(vha, dest, 11507ec0effdSAtul Deshmukh (uint32_t *)p_cache, count); 11517ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) { 11527ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a9, 11537ec0effdSAtul Deshmukh "%s: Error writing F/W to MS !!!\n", __func__); 11547ec0effdSAtul Deshmukh goto exit_copy_error; 11557ec0effdSAtul Deshmukh } 11567ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0aa, 11577ec0effdSAtul Deshmukh "%s: Wrote F/W (size %d) to MS !!!\n", 11587ec0effdSAtul Deshmukh __func__, size); 11597ec0effdSAtul Deshmukh 11607ec0effdSAtul Deshmukh exit_copy_error: 11617ec0effdSAtul Deshmukh vfree(p_cache); 11627ec0effdSAtul Deshmukh 11637ec0effdSAtul Deshmukh exit_copy_bootloader: 11647ec0effdSAtul Deshmukh return ret_val; 11657ec0effdSAtul Deshmukh } 11667ec0effdSAtul Deshmukh 11677ec0effdSAtul Deshmukh static int 11687ec0effdSAtul Deshmukh qla8044_restart(struct scsi_qla_host *vha) 11697ec0effdSAtul Deshmukh { 11707ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 11717ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 11727ec0effdSAtul Deshmukh 11737ec0effdSAtul Deshmukh qla8044_process_stop_seq(vha); 11747ec0effdSAtul Deshmukh 11757ec0effdSAtul Deshmukh /* Collect minidump */ 11767ec0effdSAtul Deshmukh if (ql2xmdenable) 11777ec0effdSAtul Deshmukh qla8044_get_minidump(vha); 11787ec0effdSAtul Deshmukh else 11797ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb14c, 11807ec0effdSAtul Deshmukh "Minidump disabled.\n"); 11817ec0effdSAtul Deshmukh 11827ec0effdSAtul Deshmukh qla8044_process_init_seq(vha); 11837ec0effdSAtul Deshmukh 11847ec0effdSAtul Deshmukh if (qla8044_copy_bootloader(vha)) { 11857ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0ab, 11867ec0effdSAtul Deshmukh "%s: Copy bootloader, firmware restart failed!\n", 11877ec0effdSAtul Deshmukh __func__); 11887ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 11897ec0effdSAtul Deshmukh goto exit_restart; 11907ec0effdSAtul Deshmukh } 11917ec0effdSAtul Deshmukh 11927ec0effdSAtul Deshmukh /* 11937ec0effdSAtul Deshmukh * Loads F/W from flash 11947ec0effdSAtul Deshmukh */ 11957ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH); 11967ec0effdSAtul Deshmukh 11977ec0effdSAtul Deshmukh qla8044_process_start_seq(vha); 11987ec0effdSAtul Deshmukh 11997ec0effdSAtul Deshmukh exit_restart: 12007ec0effdSAtul Deshmukh return ret_val; 12017ec0effdSAtul Deshmukh } 12027ec0effdSAtul Deshmukh 12037ec0effdSAtul Deshmukh /* 12047ec0effdSAtul Deshmukh * qla8044_check_cmd_peg_status - Check peg status to see if Peg is 12057ec0effdSAtul Deshmukh * initialized. 12067ec0effdSAtul Deshmukh * 12077ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure 12087ec0effdSAtul Deshmukh * 12097ec0effdSAtul Deshmukh * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 12107ec0effdSAtul Deshmukh */ 12117ec0effdSAtul Deshmukh static int 12127ec0effdSAtul Deshmukh qla8044_check_cmd_peg_status(struct scsi_qla_host *vha) 12137ec0effdSAtul Deshmukh { 12147ec0effdSAtul Deshmukh uint32_t val, ret_val = QLA_FUNCTION_FAILED; 12157ec0effdSAtul Deshmukh int retries = CRB_CMDPEG_CHECK_RETRY_COUNT; 12167ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 12177ec0effdSAtul Deshmukh 12187ec0effdSAtul Deshmukh do { 12197ec0effdSAtul Deshmukh val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE); 12207ec0effdSAtul Deshmukh if (val == PHAN_INITIALIZE_COMPLETE) { 12217ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0ac, 12227ec0effdSAtul Deshmukh "%s: Command Peg initialization " 12237ec0effdSAtul Deshmukh "complete! state=0x%x\n", __func__, val); 12247ec0effdSAtul Deshmukh ret_val = QLA_SUCCESS; 12257ec0effdSAtul Deshmukh break; 12267ec0effdSAtul Deshmukh } 12277ec0effdSAtul Deshmukh msleep(CRB_CMDPEG_CHECK_DELAY); 12287ec0effdSAtul Deshmukh } while (--retries); 12297ec0effdSAtul Deshmukh 12307ec0effdSAtul Deshmukh return ret_val; 12317ec0effdSAtul Deshmukh } 12327ec0effdSAtul Deshmukh 12337ec0effdSAtul Deshmukh static int 12347ec0effdSAtul Deshmukh qla8044_start_firmware(struct scsi_qla_host *vha) 12357ec0effdSAtul Deshmukh { 12367ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 12377ec0effdSAtul Deshmukh 12387ec0effdSAtul Deshmukh if (qla8044_restart(vha)) { 12397ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0ad, 12407ec0effdSAtul Deshmukh "%s: Restart Error!!!, Need Reset!!!\n", 12417ec0effdSAtul Deshmukh __func__); 12427ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 12437ec0effdSAtul Deshmukh goto exit_start_fw; 12447ec0effdSAtul Deshmukh } else 12457ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0af, 12467ec0effdSAtul Deshmukh "%s: Restart done!\n", __func__); 12477ec0effdSAtul Deshmukh 12487ec0effdSAtul Deshmukh ret_val = qla8044_check_cmd_peg_status(vha); 12497ec0effdSAtul Deshmukh if (ret_val) { 12507ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0b0, 12517ec0effdSAtul Deshmukh "%s: Peg not initialized!\n", __func__); 12527ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 12537ec0effdSAtul Deshmukh } 12547ec0effdSAtul Deshmukh 12557ec0effdSAtul Deshmukh exit_start_fw: 12567ec0effdSAtul Deshmukh return ret_val; 12577ec0effdSAtul Deshmukh } 12587ec0effdSAtul Deshmukh 12597ec0effdSAtul Deshmukh void 12607ec0effdSAtul Deshmukh qla8044_clear_drv_active(struct scsi_qla_host *vha) 12617ec0effdSAtul Deshmukh { 12627ec0effdSAtul Deshmukh uint32_t drv_active; 12637ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 12647ec0effdSAtul Deshmukh 12657ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 12667ec0effdSAtul Deshmukh drv_active &= ~(1 << (ha->portnum)); 12677ec0effdSAtul Deshmukh 12687ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0b1, 12697ec0effdSAtul Deshmukh "%s(%ld): drv_active: 0x%08x\n", 12707ec0effdSAtul Deshmukh __func__, vha->host_no, drv_active); 12717ec0effdSAtul Deshmukh 12727ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active); 12737ec0effdSAtul Deshmukh } 12747ec0effdSAtul Deshmukh 12757ec0effdSAtul Deshmukh /* 12767ec0effdSAtul Deshmukh * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw 12777ec0effdSAtul Deshmukh * @ha: pointer to adapter structure 12787ec0effdSAtul Deshmukh * 12797ec0effdSAtul Deshmukh * Note: IDC lock must be held upon entry 12807ec0effdSAtul Deshmukh **/ 12817ec0effdSAtul Deshmukh static int 12827ec0effdSAtul Deshmukh qla8044_device_bootstrap(struct scsi_qla_host *vha) 12837ec0effdSAtul Deshmukh { 12847ec0effdSAtul Deshmukh int rval = QLA_FUNCTION_FAILED; 12857ec0effdSAtul Deshmukh int i; 12867ec0effdSAtul Deshmukh uint32_t old_count = 0, count = 0; 12877ec0effdSAtul Deshmukh int need_reset = 0; 12887ec0effdSAtul Deshmukh uint32_t idc_ctrl; 12897ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 12907ec0effdSAtul Deshmukh 12917ec0effdSAtul Deshmukh need_reset = qla8044_need_reset(vha); 12927ec0effdSAtul Deshmukh 12937ec0effdSAtul Deshmukh if (!need_reset) { 12947ec0effdSAtul Deshmukh old_count = qla8044_rd_direct(vha, 12957ec0effdSAtul Deshmukh QLA8044_PEG_ALIVE_COUNTER_INDEX); 12967ec0effdSAtul Deshmukh 12977ec0effdSAtul Deshmukh for (i = 0; i < 10; i++) { 12987ec0effdSAtul Deshmukh msleep(200); 12997ec0effdSAtul Deshmukh 13007ec0effdSAtul Deshmukh count = qla8044_rd_direct(vha, 13017ec0effdSAtul Deshmukh QLA8044_PEG_ALIVE_COUNTER_INDEX); 13027ec0effdSAtul Deshmukh if (count != old_count) { 13037ec0effdSAtul Deshmukh rval = QLA_SUCCESS; 13047ec0effdSAtul Deshmukh goto dev_ready; 13057ec0effdSAtul Deshmukh } 13067ec0effdSAtul Deshmukh } 13077ec0effdSAtul Deshmukh qla8044_flash_lock_recovery(vha); 13087ec0effdSAtul Deshmukh } else { 13097ec0effdSAtul Deshmukh /* We are trying to perform a recovery here. */ 13107ec0effdSAtul Deshmukh if (ha->flags.isp82xx_fw_hung) 13117ec0effdSAtul Deshmukh qla8044_flash_lock_recovery(vha); 13127ec0effdSAtul Deshmukh } 13137ec0effdSAtul Deshmukh 13147ec0effdSAtul Deshmukh /* set to DEV_INITIALIZING */ 13157ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0b2, 13167ec0effdSAtul Deshmukh "%s: HW State: INITIALIZING\n", __func__); 13177ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 13187ec0effdSAtul Deshmukh QLA8XXX_DEV_INITIALIZING); 13197ec0effdSAtul Deshmukh 13207ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 13217ec0effdSAtul Deshmukh rval = qla8044_start_firmware(vha); 13227ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 13237ec0effdSAtul Deshmukh 13247ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) { 13257ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0b3, 13267ec0effdSAtul Deshmukh "%s: HW State: FAILED\n", __func__); 13277ec0effdSAtul Deshmukh qla8044_clear_drv_active(vha); 13287ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 13297ec0effdSAtul Deshmukh QLA8XXX_DEV_FAILED); 13307ec0effdSAtul Deshmukh return rval; 13317ec0effdSAtul Deshmukh } 13327ec0effdSAtul Deshmukh 13337ec0effdSAtul Deshmukh /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after 13347ec0effdSAtul Deshmukh * device goes to INIT state. */ 13357ec0effdSAtul Deshmukh idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 13367ec0effdSAtul Deshmukh if (idc_ctrl & GRACEFUL_RESET_BIT1) { 13377ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, 13387ec0effdSAtul Deshmukh (idc_ctrl & ~GRACEFUL_RESET_BIT1)); 13397ec0effdSAtul Deshmukh ha->fw_dumped = 0; 13407ec0effdSAtul Deshmukh } 13417ec0effdSAtul Deshmukh 13427ec0effdSAtul Deshmukh dev_ready: 13437ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0b4, 13447ec0effdSAtul Deshmukh "%s: HW State: READY\n", __func__); 13457ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY); 13467ec0effdSAtul Deshmukh 13477ec0effdSAtul Deshmukh return rval; 13487ec0effdSAtul Deshmukh } 13497ec0effdSAtul Deshmukh 13507ec0effdSAtul Deshmukh /*-------------------------Reset Sequence Functions-----------------------*/ 13517ec0effdSAtul Deshmukh static void 13527ec0effdSAtul Deshmukh qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha) 13537ec0effdSAtul Deshmukh { 13547ec0effdSAtul Deshmukh u8 *phdr; 13557ec0effdSAtul Deshmukh 13567ec0effdSAtul Deshmukh if (!vha->reset_tmplt.buff) { 13577ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0b5, 13587ec0effdSAtul Deshmukh "%s: Error Invalid reset_seq_template\n", __func__); 13597ec0effdSAtul Deshmukh return; 13607ec0effdSAtul Deshmukh } 13617ec0effdSAtul Deshmukh 13627ec0effdSAtul Deshmukh phdr = vha->reset_tmplt.buff; 13637ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0b6, 13647ec0effdSAtul Deshmukh "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X" 13657ec0effdSAtul Deshmukh "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n" 13667ec0effdSAtul Deshmukh "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n", 13677ec0effdSAtul Deshmukh *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4), 13687ec0effdSAtul Deshmukh *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8), 13697ec0effdSAtul Deshmukh *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12), 13707ec0effdSAtul Deshmukh *(phdr+13), *(phdr+14), *(phdr+15)); 13717ec0effdSAtul Deshmukh } 13727ec0effdSAtul Deshmukh 13737ec0effdSAtul Deshmukh /* 13747ec0effdSAtul Deshmukh * qla8044_reset_seq_checksum_test - Validate Reset Sequence template. 13757ec0effdSAtul Deshmukh * 13767ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure 13777ec0effdSAtul Deshmukh * 13787ec0effdSAtul Deshmukh * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 13797ec0effdSAtul Deshmukh */ 13807ec0effdSAtul Deshmukh static int 13817ec0effdSAtul Deshmukh qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha) 13827ec0effdSAtul Deshmukh { 13837ec0effdSAtul Deshmukh uint32_t sum = 0; 13847ec0effdSAtul Deshmukh uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff; 13857ec0effdSAtul Deshmukh int u16_count = vha->reset_tmplt.hdr->size / sizeof(uint16_t); 13867ec0effdSAtul Deshmukh 13877ec0effdSAtul Deshmukh while (u16_count-- > 0) 13887ec0effdSAtul Deshmukh sum += *buff++; 13897ec0effdSAtul Deshmukh 13907ec0effdSAtul Deshmukh while (sum >> 16) 13917ec0effdSAtul Deshmukh sum = (sum & 0xFFFF) + (sum >> 16); 13927ec0effdSAtul Deshmukh 13937ec0effdSAtul Deshmukh /* checksum of 0 indicates a valid template */ 13947ec0effdSAtul Deshmukh if (~sum) { 13957ec0effdSAtul Deshmukh return QLA_SUCCESS; 13967ec0effdSAtul Deshmukh } else { 13977ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0b7, 13987ec0effdSAtul Deshmukh "%s: Reset seq checksum failed\n", __func__); 13997ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 14007ec0effdSAtul Deshmukh } 14017ec0effdSAtul Deshmukh } 14027ec0effdSAtul Deshmukh 14037ec0effdSAtul Deshmukh /* 14047ec0effdSAtul Deshmukh * qla8044_read_reset_template - Read Reset Template from Flash, validate 14057ec0effdSAtul Deshmukh * the template and store offsets of stop/start/init offsets in ha->reset_tmplt. 14067ec0effdSAtul Deshmukh * 14077ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure 14087ec0effdSAtul Deshmukh */ 14097ec0effdSAtul Deshmukh void 14107ec0effdSAtul Deshmukh qla8044_read_reset_template(struct scsi_qla_host *vha) 14117ec0effdSAtul Deshmukh { 14127ec0effdSAtul Deshmukh uint8_t *p_buff; 14137ec0effdSAtul Deshmukh uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size; 14147ec0effdSAtul Deshmukh 14157ec0effdSAtul Deshmukh vha->reset_tmplt.seq_error = 0; 14167ec0effdSAtul Deshmukh vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE); 14177ec0effdSAtul Deshmukh if (vha->reset_tmplt.buff == NULL) { 14187ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0b8, 14197ec0effdSAtul Deshmukh "%s: Failed to allocate reset template resources\n", 14207ec0effdSAtul Deshmukh __func__); 14217ec0effdSAtul Deshmukh goto exit_read_reset_template; 14227ec0effdSAtul Deshmukh } 14237ec0effdSAtul Deshmukh 14247ec0effdSAtul Deshmukh p_buff = vha->reset_tmplt.buff; 14257ec0effdSAtul Deshmukh addr = QLA8044_RESET_TEMPLATE_ADDR; 14267ec0effdSAtul Deshmukh 14277ec0effdSAtul Deshmukh tmplt_hdr_def_size = 14287ec0effdSAtul Deshmukh sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t); 14297ec0effdSAtul Deshmukh 14307ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0b9, 14317ec0effdSAtul Deshmukh "%s: Read template hdr size %d from Flash\n", 14327ec0effdSAtul Deshmukh __func__, tmplt_hdr_def_size); 14337ec0effdSAtul Deshmukh 14347ec0effdSAtul Deshmukh /* Copy template header from flash */ 14357ec0effdSAtul Deshmukh if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) { 14367ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0ba, 14377ec0effdSAtul Deshmukh "%s: Failed to read reset template\n", __func__); 14387ec0effdSAtul Deshmukh goto exit_read_template_error; 14397ec0effdSAtul Deshmukh } 14407ec0effdSAtul Deshmukh 14417ec0effdSAtul Deshmukh vha->reset_tmplt.hdr = 14427ec0effdSAtul Deshmukh (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff; 14437ec0effdSAtul Deshmukh 14447ec0effdSAtul Deshmukh /* Validate the template header size and signature */ 14457ec0effdSAtul Deshmukh tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t); 14467ec0effdSAtul Deshmukh if ((tmplt_hdr_size != tmplt_hdr_def_size) || 14477ec0effdSAtul Deshmukh (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) { 14487ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0bb, 14497ec0effdSAtul Deshmukh "%s: Template Header size invalid %d " 14507ec0effdSAtul Deshmukh "tmplt_hdr_def_size %d!!!\n", __func__, 14517ec0effdSAtul Deshmukh tmplt_hdr_size, tmplt_hdr_def_size); 14527ec0effdSAtul Deshmukh goto exit_read_template_error; 14537ec0effdSAtul Deshmukh } 14547ec0effdSAtul Deshmukh 14557ec0effdSAtul Deshmukh addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size; 14567ec0effdSAtul Deshmukh p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size; 14577ec0effdSAtul Deshmukh tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size - 14587ec0effdSAtul Deshmukh vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t); 14597ec0effdSAtul Deshmukh 14607ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0bc, 14617ec0effdSAtul Deshmukh "%s: Read rest of the template size %d\n", 14627ec0effdSAtul Deshmukh __func__, vha->reset_tmplt.hdr->size); 14637ec0effdSAtul Deshmukh 14647ec0effdSAtul Deshmukh /* Copy rest of the template */ 14657ec0effdSAtul Deshmukh if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) { 14667ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0bd, 14677ec0effdSAtul Deshmukh "%s: Failed to read reset tempelate\n", __func__); 14687ec0effdSAtul Deshmukh goto exit_read_template_error; 14697ec0effdSAtul Deshmukh } 14707ec0effdSAtul Deshmukh 14717ec0effdSAtul Deshmukh /* Integrity check */ 14727ec0effdSAtul Deshmukh if (qla8044_reset_seq_checksum_test(vha)) { 14737ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0be, 14747ec0effdSAtul Deshmukh "%s: Reset Seq checksum failed!\n", __func__); 14757ec0effdSAtul Deshmukh goto exit_read_template_error; 14767ec0effdSAtul Deshmukh } 14777ec0effdSAtul Deshmukh 14787ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0bf, 14797ec0effdSAtul Deshmukh "%s: Reset Seq checksum passed! Get stop, " 14807ec0effdSAtul Deshmukh "start and init seq offsets\n", __func__); 14817ec0effdSAtul Deshmukh 14827ec0effdSAtul Deshmukh /* Get STOP, START, INIT sequence offsets */ 14837ec0effdSAtul Deshmukh vha->reset_tmplt.init_offset = vha->reset_tmplt.buff + 14847ec0effdSAtul Deshmukh vha->reset_tmplt.hdr->init_seq_offset; 14857ec0effdSAtul Deshmukh 14867ec0effdSAtul Deshmukh vha->reset_tmplt.start_offset = vha->reset_tmplt.buff + 14877ec0effdSAtul Deshmukh vha->reset_tmplt.hdr->start_seq_offset; 14887ec0effdSAtul Deshmukh 14897ec0effdSAtul Deshmukh vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff + 14907ec0effdSAtul Deshmukh vha->reset_tmplt.hdr->hdr_size; 14917ec0effdSAtul Deshmukh 14927ec0effdSAtul Deshmukh qla8044_dump_reset_seq_hdr(vha); 14937ec0effdSAtul Deshmukh 14947ec0effdSAtul Deshmukh goto exit_read_reset_template; 14957ec0effdSAtul Deshmukh 14967ec0effdSAtul Deshmukh exit_read_template_error: 14977ec0effdSAtul Deshmukh vfree(vha->reset_tmplt.buff); 14987ec0effdSAtul Deshmukh 14997ec0effdSAtul Deshmukh exit_read_reset_template: 15007ec0effdSAtul Deshmukh return; 15017ec0effdSAtul Deshmukh } 15027ec0effdSAtul Deshmukh 15037ec0effdSAtul Deshmukh void 15047ec0effdSAtul Deshmukh qla8044_set_idc_dontreset(struct scsi_qla_host *vha) 15057ec0effdSAtul Deshmukh { 15067ec0effdSAtul Deshmukh uint32_t idc_ctrl; 15077ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 15087ec0effdSAtul Deshmukh 15097ec0effdSAtul Deshmukh idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 15107ec0effdSAtul Deshmukh idc_ctrl |= DONTRESET_BIT0; 15117ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0c0, 15127ec0effdSAtul Deshmukh "%s: idc_ctrl = %d\n", __func__, idc_ctrl); 15137ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl); 15147ec0effdSAtul Deshmukh } 15157ec0effdSAtul Deshmukh 15167ec0effdSAtul Deshmukh inline void 15177ec0effdSAtul Deshmukh qla8044_set_rst_ready(struct scsi_qla_host *vha) 15187ec0effdSAtul Deshmukh { 15197ec0effdSAtul Deshmukh uint32_t drv_state; 15207ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 15217ec0effdSAtul Deshmukh 15227ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 15237ec0effdSAtul Deshmukh 15247ec0effdSAtul Deshmukh /* For ISP8044, drv_active register has 1 bit per function, 15257ec0effdSAtul Deshmukh * shift 1 by func_num to set a bit for the function.*/ 15267ec0effdSAtul Deshmukh drv_state |= (1 << ha->portnum); 15277ec0effdSAtul Deshmukh 15287ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0c1, 15297ec0effdSAtul Deshmukh "%s(%ld): drv_state: 0x%08x\n", 15307ec0effdSAtul Deshmukh __func__, vha->host_no, drv_state); 15317ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state); 15327ec0effdSAtul Deshmukh } 15337ec0effdSAtul Deshmukh 15347ec0effdSAtul Deshmukh /** 15357ec0effdSAtul Deshmukh * qla8044_need_reset_handler - Code to start reset sequence 15367ec0effdSAtul Deshmukh * @ha: pointer to adapter structure 15377ec0effdSAtul Deshmukh * 15387ec0effdSAtul Deshmukh * Note: IDC lock must be held upon entry 15397ec0effdSAtul Deshmukh **/ 15407ec0effdSAtul Deshmukh static void 15417ec0effdSAtul Deshmukh qla8044_need_reset_handler(struct scsi_qla_host *vha) 15427ec0effdSAtul Deshmukh { 15437ec0effdSAtul Deshmukh uint32_t dev_state = 0, drv_state, drv_active; 15447ec0effdSAtul Deshmukh unsigned long reset_timeout, dev_init_timeout; 15457ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 15467ec0effdSAtul Deshmukh 15477ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0c2, 15487ec0effdSAtul Deshmukh "%s: Performing ISP error recovery\n", __func__); 15497ec0effdSAtul Deshmukh 15507ec0effdSAtul Deshmukh if (vha->flags.online) { 15517ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 15527ec0effdSAtul Deshmukh qla2x00_abort_isp_cleanup(vha); 15537ec0effdSAtul Deshmukh ha->isp_ops->get_flash_version(vha, vha->req->ring); 15547ec0effdSAtul Deshmukh ha->isp_ops->nvram_config(vha); 15557ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 15567ec0effdSAtul Deshmukh } 15577ec0effdSAtul Deshmukh 15587ec0effdSAtul Deshmukh if (!ha->flags.nic_core_reset_owner) { 15597ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0c3, 15607ec0effdSAtul Deshmukh "%s(%ld): reset acknowledged\n", 15617ec0effdSAtul Deshmukh __func__, vha->host_no); 15627ec0effdSAtul Deshmukh qla8044_set_rst_ready(vha); 15637ec0effdSAtul Deshmukh 15647ec0effdSAtul Deshmukh /* Non-reset owners ACK Reset and wait for device INIT state 15657ec0effdSAtul Deshmukh * as part of Reset Recovery by Reset Owner 15667ec0effdSAtul Deshmukh */ 15677ec0effdSAtul Deshmukh dev_init_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 15687ec0effdSAtul Deshmukh 15697ec0effdSAtul Deshmukh do { 15707ec0effdSAtul Deshmukh if (time_after_eq(jiffies, dev_init_timeout)) { 15717ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0c4, 15727ec0effdSAtul Deshmukh "%s: Non Reset owner DEV INIT " 15737ec0effdSAtul Deshmukh "TIMEOUT!\n", __func__); 15747ec0effdSAtul Deshmukh break; 15757ec0effdSAtul Deshmukh } 15767ec0effdSAtul Deshmukh 15777ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 15787ec0effdSAtul Deshmukh msleep(1000); 15797ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 15807ec0effdSAtul Deshmukh 15817ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, 15827ec0effdSAtul Deshmukh QLA8044_CRB_DEV_STATE_INDEX); 15837ec0effdSAtul Deshmukh } while (dev_state == QLA8XXX_DEV_NEED_RESET); 15847ec0effdSAtul Deshmukh } else { 15857ec0effdSAtul Deshmukh qla8044_set_rst_ready(vha); 15867ec0effdSAtul Deshmukh 15877ec0effdSAtul Deshmukh /* wait for 10 seconds for reset ack from all functions */ 15887ec0effdSAtul Deshmukh reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 15897ec0effdSAtul Deshmukh 15907ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha, 15917ec0effdSAtul Deshmukh QLA8044_CRB_DRV_STATE_INDEX); 15927ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, 15937ec0effdSAtul Deshmukh QLA8044_CRB_DRV_ACTIVE_INDEX); 15947ec0effdSAtul Deshmukh 15957ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0c5, 15967ec0effdSAtul Deshmukh "%s(%ld): drv_state = 0x%x, drv_active = 0x%x\n", 15977ec0effdSAtul Deshmukh __func__, vha->host_no, drv_state, drv_active); 15987ec0effdSAtul Deshmukh 15997ec0effdSAtul Deshmukh while (drv_state != drv_active) { 16007ec0effdSAtul Deshmukh if (time_after_eq(jiffies, reset_timeout)) { 16017ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0c6, 16027ec0effdSAtul Deshmukh "%s: RESET TIMEOUT!" 16037ec0effdSAtul Deshmukh "drv_state: 0x%08x, drv_active: 0x%08x\n", 16047ec0effdSAtul Deshmukh QLA2XXX_DRIVER_NAME, drv_state, drv_active); 16057ec0effdSAtul Deshmukh break; 16067ec0effdSAtul Deshmukh } 16077ec0effdSAtul Deshmukh 16087ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 16097ec0effdSAtul Deshmukh msleep(1000); 16107ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 16117ec0effdSAtul Deshmukh 16127ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha, 16137ec0effdSAtul Deshmukh QLA8044_CRB_DRV_STATE_INDEX); 16147ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, 16157ec0effdSAtul Deshmukh QLA8044_CRB_DRV_ACTIVE_INDEX); 16167ec0effdSAtul Deshmukh } 16177ec0effdSAtul Deshmukh 16187ec0effdSAtul Deshmukh if (drv_state != drv_active) { 16197ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0c7, 16207ec0effdSAtul Deshmukh "%s(%ld): Reset_owner turning off drv_active " 16217ec0effdSAtul Deshmukh "of non-acking function 0x%x\n", __func__, 16227ec0effdSAtul Deshmukh vha->host_no, (drv_active ^ drv_state)); 16237ec0effdSAtul Deshmukh drv_active = drv_active & drv_state; 16247ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, 16257ec0effdSAtul Deshmukh drv_active); 16267ec0effdSAtul Deshmukh } 16277ec0effdSAtul Deshmukh 16287ec0effdSAtul Deshmukh /* 16297ec0effdSAtul Deshmukh * Clear RESET OWNER, will be set at next reset 16307ec0effdSAtul Deshmukh * by next RST_OWNER 16317ec0effdSAtul Deshmukh */ 16327ec0effdSAtul Deshmukh ha->flags.nic_core_reset_owner = 0; 16337ec0effdSAtul Deshmukh 16347ec0effdSAtul Deshmukh /* Start Reset Recovery */ 16357ec0effdSAtul Deshmukh qla8044_device_bootstrap(vha); 16367ec0effdSAtul Deshmukh } 16377ec0effdSAtul Deshmukh } 16387ec0effdSAtul Deshmukh 16397ec0effdSAtul Deshmukh static void 16407ec0effdSAtul Deshmukh qla8044_set_drv_active(struct scsi_qla_host *vha) 16417ec0effdSAtul Deshmukh { 16427ec0effdSAtul Deshmukh uint32_t drv_active; 16437ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 16447ec0effdSAtul Deshmukh 16457ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 16467ec0effdSAtul Deshmukh 16477ec0effdSAtul Deshmukh /* For ISP8044, drv_active register has 1 bit per function, 16487ec0effdSAtul Deshmukh * shift 1 by func_num to set a bit for the function.*/ 16497ec0effdSAtul Deshmukh drv_active |= (1 << ha->portnum); 16507ec0effdSAtul Deshmukh 16517ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0c8, 16527ec0effdSAtul Deshmukh "%s(%ld): drv_active: 0x%08x\n", 16537ec0effdSAtul Deshmukh __func__, vha->host_no, drv_active); 16547ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active); 16557ec0effdSAtul Deshmukh } 16567ec0effdSAtul Deshmukh 16577ec0effdSAtul Deshmukh static void 16587ec0effdSAtul Deshmukh qla8044_clear_idc_dontreset(struct scsi_qla_host *vha) 16597ec0effdSAtul Deshmukh { 16607ec0effdSAtul Deshmukh uint32_t idc_ctrl; 16617ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 16627ec0effdSAtul Deshmukh 16637ec0effdSAtul Deshmukh idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 16647ec0effdSAtul Deshmukh idc_ctrl &= ~DONTRESET_BIT0; 16657ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0c9, 16667ec0effdSAtul Deshmukh "%s: idc_ctrl = %d\n", __func__, 16677ec0effdSAtul Deshmukh idc_ctrl); 16687ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl); 16697ec0effdSAtul Deshmukh } 16707ec0effdSAtul Deshmukh 16717ec0effdSAtul Deshmukh static int 16727ec0effdSAtul Deshmukh qla8044_set_idc_ver(struct scsi_qla_host *vha) 16737ec0effdSAtul Deshmukh { 16747ec0effdSAtul Deshmukh int idc_ver; 16757ec0effdSAtul Deshmukh uint32_t drv_active; 16767ec0effdSAtul Deshmukh int rval = QLA_SUCCESS; 16777ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 16787ec0effdSAtul Deshmukh 16797ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 16807ec0effdSAtul Deshmukh if (drv_active == (1 << ha->portnum)) { 16817ec0effdSAtul Deshmukh idc_ver = qla8044_rd_direct(vha, 16827ec0effdSAtul Deshmukh QLA8044_CRB_DRV_IDC_VERSION_INDEX); 16837ec0effdSAtul Deshmukh idc_ver &= (~0xFF); 16847ec0effdSAtul Deshmukh idc_ver |= QLA8044_IDC_VER_MAJ_VALUE; 16857ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX, 16867ec0effdSAtul Deshmukh idc_ver); 16877ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0ca, 16887ec0effdSAtul Deshmukh "%s: IDC version updated to %d\n", 16897ec0effdSAtul Deshmukh __func__, idc_ver); 16907ec0effdSAtul Deshmukh } else { 16917ec0effdSAtul Deshmukh idc_ver = qla8044_rd_direct(vha, 16927ec0effdSAtul Deshmukh QLA8044_CRB_DRV_IDC_VERSION_INDEX); 16937ec0effdSAtul Deshmukh idc_ver &= 0xFF; 16947ec0effdSAtul Deshmukh if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) { 16957ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0cb, 16967ec0effdSAtul Deshmukh "%s: qla4xxx driver IDC version %d " 16977ec0effdSAtul Deshmukh "is not compatible with IDC version %d " 16987ec0effdSAtul Deshmukh "of other drivers!\n", 16997ec0effdSAtul Deshmukh __func__, QLA8044_IDC_VER_MAJ_VALUE, 17007ec0effdSAtul Deshmukh idc_ver); 17017ec0effdSAtul Deshmukh rval = QLA_FUNCTION_FAILED; 17027ec0effdSAtul Deshmukh goto exit_set_idc_ver; 17037ec0effdSAtul Deshmukh } 17047ec0effdSAtul Deshmukh } 17057ec0effdSAtul Deshmukh 17067ec0effdSAtul Deshmukh /* Update IDC_MINOR_VERSION */ 17077ec0effdSAtul Deshmukh idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR); 17087ec0effdSAtul Deshmukh idc_ver &= ~(0x03 << (ha->portnum * 2)); 17097ec0effdSAtul Deshmukh idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2)); 17107ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver); 17117ec0effdSAtul Deshmukh 17127ec0effdSAtul Deshmukh exit_set_idc_ver: 17137ec0effdSAtul Deshmukh return rval; 17147ec0effdSAtul Deshmukh } 17157ec0effdSAtul Deshmukh 17167ec0effdSAtul Deshmukh static int 17177ec0effdSAtul Deshmukh qla8044_update_idc_reg(struct scsi_qla_host *vha) 17187ec0effdSAtul Deshmukh { 17197ec0effdSAtul Deshmukh uint32_t drv_active; 17207ec0effdSAtul Deshmukh int rval = QLA_SUCCESS; 17217ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 17227ec0effdSAtul Deshmukh 17237ec0effdSAtul Deshmukh if (vha->flags.init_done) 17247ec0effdSAtul Deshmukh goto exit_update_idc_reg; 17257ec0effdSAtul Deshmukh 17267ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 17277ec0effdSAtul Deshmukh qla8044_set_drv_active(vha); 17287ec0effdSAtul Deshmukh 17297ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, 17307ec0effdSAtul Deshmukh QLA8044_CRB_DRV_ACTIVE_INDEX); 17317ec0effdSAtul Deshmukh 17327ec0effdSAtul Deshmukh /* If we are the first driver to load and 17337ec0effdSAtul Deshmukh * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */ 17347ec0effdSAtul Deshmukh if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba) 17357ec0effdSAtul Deshmukh qla8044_clear_idc_dontreset(vha); 17367ec0effdSAtul Deshmukh 17377ec0effdSAtul Deshmukh rval = qla8044_set_idc_ver(vha); 17387ec0effdSAtul Deshmukh if (rval == QLA_FUNCTION_FAILED) 17397ec0effdSAtul Deshmukh qla8044_clear_drv_active(vha); 17407ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 17417ec0effdSAtul Deshmukh 17427ec0effdSAtul Deshmukh exit_update_idc_reg: 17437ec0effdSAtul Deshmukh return rval; 17447ec0effdSAtul Deshmukh } 17457ec0effdSAtul Deshmukh 17467ec0effdSAtul Deshmukh /** 17477ec0effdSAtul Deshmukh * qla8044_need_qsnt_handler - Code to start qsnt 17487ec0effdSAtul Deshmukh * @ha: pointer to adapter structure 17497ec0effdSAtul Deshmukh **/ 17507ec0effdSAtul Deshmukh static void 17517ec0effdSAtul Deshmukh qla8044_need_qsnt_handler(struct scsi_qla_host *vha) 17527ec0effdSAtul Deshmukh { 17537ec0effdSAtul Deshmukh unsigned long qsnt_timeout; 17547ec0effdSAtul Deshmukh uint32_t drv_state, drv_active, dev_state; 17557ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 17567ec0effdSAtul Deshmukh 17577ec0effdSAtul Deshmukh if (vha->flags.online) 17587ec0effdSAtul Deshmukh qla2x00_quiesce_io(vha); 17597ec0effdSAtul Deshmukh else 17607ec0effdSAtul Deshmukh return; 17617ec0effdSAtul Deshmukh 17627ec0effdSAtul Deshmukh qla8044_set_qsnt_ready(vha); 17637ec0effdSAtul Deshmukh 17647ec0effdSAtul Deshmukh /* Wait for 30 secs for all functions to ack qsnt mode */ 17657ec0effdSAtul Deshmukh qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ); 17667ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 17677ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX); 17687ec0effdSAtul Deshmukh 17697ec0effdSAtul Deshmukh /* Shift drv_active by 1 to match drv_state. As quiescent ready bit 17707ec0effdSAtul Deshmukh position is at bit 1 and drv active is at bit 0 */ 17717ec0effdSAtul Deshmukh drv_active = drv_active << 1; 17727ec0effdSAtul Deshmukh 17737ec0effdSAtul Deshmukh while (drv_state != drv_active) { 17747ec0effdSAtul Deshmukh if (time_after_eq(jiffies, qsnt_timeout)) { 17757ec0effdSAtul Deshmukh /* Other functions did not ack, changing state to 17767ec0effdSAtul Deshmukh * DEV_READY 17777ec0effdSAtul Deshmukh */ 17787ec0effdSAtul Deshmukh clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 17797ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 17807ec0effdSAtul Deshmukh QLA8XXX_DEV_READY); 17817ec0effdSAtul Deshmukh qla8044_clear_qsnt_ready(vha); 17827ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0cc, 17837ec0effdSAtul Deshmukh "Timeout waiting for quiescent ack!!!\n"); 17847ec0effdSAtul Deshmukh return; 17857ec0effdSAtul Deshmukh } 17867ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 17877ec0effdSAtul Deshmukh msleep(1000); 17887ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 17897ec0effdSAtul Deshmukh 17907ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha, 17917ec0effdSAtul Deshmukh QLA8044_CRB_DRV_STATE_INDEX); 17927ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, 17937ec0effdSAtul Deshmukh QLA8044_CRB_DRV_ACTIVE_INDEX); 17947ec0effdSAtul Deshmukh drv_active = drv_active << 1; 17957ec0effdSAtul Deshmukh } 17967ec0effdSAtul Deshmukh 17977ec0effdSAtul Deshmukh /* All functions have Acked. Set quiescent state */ 17987ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 17997ec0effdSAtul Deshmukh 18007ec0effdSAtul Deshmukh if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 18017ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 18027ec0effdSAtul Deshmukh QLA8XXX_DEV_QUIESCENT); 18037ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0cd, 18047ec0effdSAtul Deshmukh "%s: HW State: QUIESCENT\n", __func__); 18057ec0effdSAtul Deshmukh } 18067ec0effdSAtul Deshmukh } 18077ec0effdSAtul Deshmukh 18087ec0effdSAtul Deshmukh /* 18097ec0effdSAtul Deshmukh * qla8044_device_state_handler - Adapter state machine 18107ec0effdSAtul Deshmukh * @ha: pointer to host adapter structure. 18117ec0effdSAtul Deshmukh * 18127ec0effdSAtul Deshmukh * Note: IDC lock must be UNLOCKED upon entry 18137ec0effdSAtul Deshmukh **/ 18147ec0effdSAtul Deshmukh int 18157ec0effdSAtul Deshmukh qla8044_device_state_handler(struct scsi_qla_host *vha) 18167ec0effdSAtul Deshmukh { 18177ec0effdSAtul Deshmukh uint32_t dev_state; 18187ec0effdSAtul Deshmukh int rval = QLA_SUCCESS; 18197ec0effdSAtul Deshmukh unsigned long dev_init_timeout; 18207ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 18217ec0effdSAtul Deshmukh 18227ec0effdSAtul Deshmukh rval = qla8044_update_idc_reg(vha); 18237ec0effdSAtul Deshmukh if (rval == QLA_FUNCTION_FAILED) 18247ec0effdSAtul Deshmukh goto exit_error; 18257ec0effdSAtul Deshmukh 18267ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 18277ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0ce, 18287ec0effdSAtul Deshmukh "Device state is 0x%x = %s\n", 18297ec0effdSAtul Deshmukh dev_state, dev_state < MAX_STATES ? 18307ec0effdSAtul Deshmukh qdev_state(dev_state) : "Unknown"); 18317ec0effdSAtul Deshmukh 18327ec0effdSAtul Deshmukh /* wait for 30 seconds for device to go ready */ 18337ec0effdSAtul Deshmukh dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 18347ec0effdSAtul Deshmukh 18357ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 18367ec0effdSAtul Deshmukh 18377ec0effdSAtul Deshmukh while (1) { 18387ec0effdSAtul Deshmukh if (time_after_eq(jiffies, dev_init_timeout)) { 18397ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb0cf, 18407ec0effdSAtul Deshmukh "%s: Device Init Failed 0x%x = %s\n", 18417ec0effdSAtul Deshmukh QLA2XXX_DRIVER_NAME, dev_state, 18427ec0effdSAtul Deshmukh dev_state < MAX_STATES ? 18437ec0effdSAtul Deshmukh qdev_state(dev_state) : "Unknown"); 18447ec0effdSAtul Deshmukh 18457ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 18467ec0effdSAtul Deshmukh QLA8XXX_DEV_FAILED); 18477ec0effdSAtul Deshmukh } 18487ec0effdSAtul Deshmukh 18497ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 18507ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0d0, 18517ec0effdSAtul Deshmukh "Device state is 0x%x = %s\n", 18527ec0effdSAtul Deshmukh dev_state, dev_state < MAX_STATES ? 18537ec0effdSAtul Deshmukh qdev_state(dev_state) : "Unknown"); 18547ec0effdSAtul Deshmukh 18557ec0effdSAtul Deshmukh /* NOTE: Make sure idc unlocked upon exit of switch statement */ 18567ec0effdSAtul Deshmukh switch (dev_state) { 18577ec0effdSAtul Deshmukh case QLA8XXX_DEV_READY: 18587ec0effdSAtul Deshmukh ha->flags.nic_core_reset_owner = 0; 18597ec0effdSAtul Deshmukh goto exit; 18607ec0effdSAtul Deshmukh case QLA8XXX_DEV_COLD: 18617ec0effdSAtul Deshmukh rval = qla8044_device_bootstrap(vha); 18627ec0effdSAtul Deshmukh goto exit; 18637ec0effdSAtul Deshmukh case QLA8XXX_DEV_INITIALIZING: 18647ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 18657ec0effdSAtul Deshmukh msleep(1000); 18667ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 18677ec0effdSAtul Deshmukh break; 18687ec0effdSAtul Deshmukh case QLA8XXX_DEV_NEED_RESET: 18697ec0effdSAtul Deshmukh /* For ISP8044, if NEED_RESET is set by any driver, 18707ec0effdSAtul Deshmukh * it should be honored, irrespective of IDC_CTRL 18717ec0effdSAtul Deshmukh * DONTRESET_BIT0 */ 18727ec0effdSAtul Deshmukh qla8044_need_reset_handler(vha); 18737ec0effdSAtul Deshmukh break; 18747ec0effdSAtul Deshmukh case QLA8XXX_DEV_NEED_QUIESCENT: 18757ec0effdSAtul Deshmukh /* idc locked/unlocked in handler */ 18767ec0effdSAtul Deshmukh qla8044_need_qsnt_handler(vha); 18777ec0effdSAtul Deshmukh 18787ec0effdSAtul Deshmukh /* Reset the init timeout after qsnt handler */ 18797ec0effdSAtul Deshmukh dev_init_timeout = jiffies + 18807ec0effdSAtul Deshmukh (ha->fcoe_reset_timeout * HZ); 18817ec0effdSAtul Deshmukh break; 18827ec0effdSAtul Deshmukh case QLA8XXX_DEV_QUIESCENT: 18837ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0d1, 18847ec0effdSAtul Deshmukh "HW State: QUIESCENT\n"); 18857ec0effdSAtul Deshmukh 18867ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 18877ec0effdSAtul Deshmukh msleep(1000); 18887ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 18897ec0effdSAtul Deshmukh 18907ec0effdSAtul Deshmukh /* Reset the init timeout after qsnt handler */ 18917ec0effdSAtul Deshmukh dev_init_timeout = jiffies + 18927ec0effdSAtul Deshmukh (ha->fcoe_reset_timeout * HZ); 18937ec0effdSAtul Deshmukh break; 18947ec0effdSAtul Deshmukh case QLA8XXX_DEV_FAILED: 18957ec0effdSAtul Deshmukh ha->flags.nic_core_reset_owner = 0; 18967ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 18977ec0effdSAtul Deshmukh qla8xxx_dev_failed_handler(vha); 18987ec0effdSAtul Deshmukh rval = QLA_FUNCTION_FAILED; 18997ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 19007ec0effdSAtul Deshmukh goto exit; 19017ec0effdSAtul Deshmukh default: 19027ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 19037ec0effdSAtul Deshmukh qla8xxx_dev_failed_handler(vha); 19047ec0effdSAtul Deshmukh rval = QLA_FUNCTION_FAILED; 19057ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 19067ec0effdSAtul Deshmukh goto exit; 19077ec0effdSAtul Deshmukh } 19087ec0effdSAtul Deshmukh } 19097ec0effdSAtul Deshmukh exit: 19107ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 19117ec0effdSAtul Deshmukh 19127ec0effdSAtul Deshmukh exit_error: 19137ec0effdSAtul Deshmukh return rval; 19147ec0effdSAtul Deshmukh } 19157ec0effdSAtul Deshmukh 19167ec0effdSAtul Deshmukh /** 19177ec0effdSAtul Deshmukh * qla4_8xxx_check_temp - Check the ISP82XX temperature. 19187ec0effdSAtul Deshmukh * @ha: adapter block pointer. 19197ec0effdSAtul Deshmukh * 19207ec0effdSAtul Deshmukh * Note: The caller should not hold the idc lock. 19217ec0effdSAtul Deshmukh **/ 19227ec0effdSAtul Deshmukh static int 19237ec0effdSAtul Deshmukh qla8044_check_temp(struct scsi_qla_host *vha) 19247ec0effdSAtul Deshmukh { 19257ec0effdSAtul Deshmukh uint32_t temp, temp_state, temp_val; 19267ec0effdSAtul Deshmukh int status = QLA_SUCCESS; 19277ec0effdSAtul Deshmukh 19287ec0effdSAtul Deshmukh temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX); 19297ec0effdSAtul Deshmukh temp_state = qla82xx_get_temp_state(temp); 19307ec0effdSAtul Deshmukh temp_val = qla82xx_get_temp_val(temp); 19317ec0effdSAtul Deshmukh 19327ec0effdSAtul Deshmukh if (temp_state == QLA82XX_TEMP_PANIC) { 19337ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb0d2, 19347ec0effdSAtul Deshmukh "Device temperature %d degrees C" 19357ec0effdSAtul Deshmukh " exceeds maximum allowed. Hardware has been shut" 19367ec0effdSAtul Deshmukh " down\n", temp_val); 19377ec0effdSAtul Deshmukh status = QLA_FUNCTION_FAILED; 19387ec0effdSAtul Deshmukh return status; 19397ec0effdSAtul Deshmukh } else if (temp_state == QLA82XX_TEMP_WARN) { 19407ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb0d3, 19417ec0effdSAtul Deshmukh "Device temperature %d" 19427ec0effdSAtul Deshmukh " degrees C exceeds operating range." 19437ec0effdSAtul Deshmukh " Immediate action needed.\n", temp_val); 19447ec0effdSAtul Deshmukh } 19457ec0effdSAtul Deshmukh return 0; 19467ec0effdSAtul Deshmukh } 19477ec0effdSAtul Deshmukh 19481ae47cf3SJoe Carnuccio int qla8044_read_temperature(scsi_qla_host_t *vha) 19491ae47cf3SJoe Carnuccio { 19501ae47cf3SJoe Carnuccio uint32_t temp; 19511ae47cf3SJoe Carnuccio 19521ae47cf3SJoe Carnuccio temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX); 19531ae47cf3SJoe Carnuccio return qla82xx_get_temp_val(temp); 19541ae47cf3SJoe Carnuccio } 19551ae47cf3SJoe Carnuccio 19567ec0effdSAtul Deshmukh /** 19577ec0effdSAtul Deshmukh * qla8044_check_fw_alive - Check firmware health 19587ec0effdSAtul Deshmukh * @ha: Pointer to host adapter structure. 19597ec0effdSAtul Deshmukh * 19607ec0effdSAtul Deshmukh * Context: Interrupt 19617ec0effdSAtul Deshmukh **/ 19627ec0effdSAtul Deshmukh int 19637ec0effdSAtul Deshmukh qla8044_check_fw_alive(struct scsi_qla_host *vha) 19647ec0effdSAtul Deshmukh { 19657ec0effdSAtul Deshmukh uint32_t fw_heartbeat_counter; 19667ec0effdSAtul Deshmukh uint32_t halt_status1, halt_status2; 19677ec0effdSAtul Deshmukh int status = QLA_SUCCESS; 19687ec0effdSAtul Deshmukh 19697ec0effdSAtul Deshmukh fw_heartbeat_counter = qla8044_rd_direct(vha, 19707ec0effdSAtul Deshmukh QLA8044_PEG_ALIVE_COUNTER_INDEX); 19717ec0effdSAtul Deshmukh 19727ec0effdSAtul Deshmukh /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */ 19737ec0effdSAtul Deshmukh if (fw_heartbeat_counter == 0xffffffff) { 19747ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0d4, 19757ec0effdSAtul Deshmukh "scsi%ld: %s: Device in frozen " 19767ec0effdSAtul Deshmukh "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n", 19777ec0effdSAtul Deshmukh vha->host_no, __func__); 19787ec0effdSAtul Deshmukh return status; 19797ec0effdSAtul Deshmukh } 19807ec0effdSAtul Deshmukh 19817ec0effdSAtul Deshmukh if (vha->fw_heartbeat_counter == fw_heartbeat_counter) { 19827ec0effdSAtul Deshmukh vha->seconds_since_last_heartbeat++; 19837ec0effdSAtul Deshmukh /* FW not alive after 2 seconds */ 19847ec0effdSAtul Deshmukh if (vha->seconds_since_last_heartbeat == 2) { 19857ec0effdSAtul Deshmukh vha->seconds_since_last_heartbeat = 0; 19867ec0effdSAtul Deshmukh halt_status1 = qla8044_rd_direct(vha, 19877ec0effdSAtul Deshmukh QLA8044_PEG_HALT_STATUS1_INDEX); 19887ec0effdSAtul Deshmukh halt_status2 = qla8044_rd_direct(vha, 19897ec0effdSAtul Deshmukh QLA8044_PEG_HALT_STATUS2_INDEX); 19907ec0effdSAtul Deshmukh 19917ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0d5, 19927ec0effdSAtul Deshmukh "scsi(%ld): %s, ISP8044 " 19937ec0effdSAtul Deshmukh "Dumping hw/fw registers:\n" 19947ec0effdSAtul Deshmukh " PEG_HALT_STATUS1: 0x%x, " 19957ec0effdSAtul Deshmukh "PEG_HALT_STATUS2: 0x%x,\n", 19967ec0effdSAtul Deshmukh vha->host_no, __func__, halt_status1, 19977ec0effdSAtul Deshmukh halt_status2); 19987ec0effdSAtul Deshmukh status = QLA_FUNCTION_FAILED; 19997ec0effdSAtul Deshmukh } 20007ec0effdSAtul Deshmukh } else 20017ec0effdSAtul Deshmukh vha->seconds_since_last_heartbeat = 0; 20027ec0effdSAtul Deshmukh 20037ec0effdSAtul Deshmukh vha->fw_heartbeat_counter = fw_heartbeat_counter; 20047ec0effdSAtul Deshmukh return status; 20057ec0effdSAtul Deshmukh } 20067ec0effdSAtul Deshmukh 20077ec0effdSAtul Deshmukh void 20087ec0effdSAtul Deshmukh qla8044_watchdog(struct scsi_qla_host *vha) 20097ec0effdSAtul Deshmukh { 20107ec0effdSAtul Deshmukh uint32_t dev_state, halt_status; 20117ec0effdSAtul Deshmukh int halt_status_unrecoverable = 0; 20127ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 20137ec0effdSAtul Deshmukh 20147ec0effdSAtul Deshmukh /* don't poll if reset is going on or FW hang in quiescent state */ 20157ec0effdSAtul Deshmukh if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) || 20167ec0effdSAtul Deshmukh test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 20177ec0effdSAtul Deshmukh test_bit(ISP_ABORT_RETRY, &vha->dpc_flags) || 20187ec0effdSAtul Deshmukh test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) { 20197ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 20207ec0effdSAtul Deshmukh 20217ec0effdSAtul Deshmukh if (qla8044_check_temp(vha)) { 20227ec0effdSAtul Deshmukh set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags); 20237ec0effdSAtul Deshmukh ha->flags.isp82xx_fw_hung = 1; 20247ec0effdSAtul Deshmukh qla2xxx_wake_dpc(vha); 20257ec0effdSAtul Deshmukh } else if (dev_state == QLA8XXX_DEV_NEED_RESET && 20267ec0effdSAtul Deshmukh !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) { 20277ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0d6, 20287ec0effdSAtul Deshmukh "%s: HW State: NEED RESET!\n", 20297ec0effdSAtul Deshmukh __func__); 20307ec0effdSAtul Deshmukh set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 20317ec0effdSAtul Deshmukh qla2xxx_wake_dpc(vha); 20327ec0effdSAtul Deshmukh } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT && 20337ec0effdSAtul Deshmukh !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) { 20347ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0d7, 20357ec0effdSAtul Deshmukh "%s: HW State: NEED QUIES detected!\n", 20367ec0effdSAtul Deshmukh __func__); 20377ec0effdSAtul Deshmukh set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags); 20387ec0effdSAtul Deshmukh qla2xxx_wake_dpc(vha); 20397ec0effdSAtul Deshmukh } else { 20407ec0effdSAtul Deshmukh /* Check firmware health */ 20417ec0effdSAtul Deshmukh if (qla8044_check_fw_alive(vha)) { 20427ec0effdSAtul Deshmukh halt_status = qla8044_rd_direct(vha, 20437ec0effdSAtul Deshmukh QLA8044_PEG_HALT_STATUS1_INDEX); 20447ec0effdSAtul Deshmukh if (halt_status & 20457ec0effdSAtul Deshmukh QLA8044_HALT_STATUS_FW_RESET) { 20467ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 20477ec0effdSAtul Deshmukh 0xb0d8, "%s: Firmware " 20487ec0effdSAtul Deshmukh "error detected device " 20497ec0effdSAtul Deshmukh "is being reset\n", 20507ec0effdSAtul Deshmukh __func__); 20517ec0effdSAtul Deshmukh } else if (halt_status & 20527ec0effdSAtul Deshmukh QLA8044_HALT_STATUS_UNRECOVERABLE) { 20537ec0effdSAtul Deshmukh halt_status_unrecoverable = 1; 20547ec0effdSAtul Deshmukh } 20557ec0effdSAtul Deshmukh 20567ec0effdSAtul Deshmukh /* Since we cannot change dev_state in interrupt 20577ec0effdSAtul Deshmukh * context, set appropriate DPC flag then wakeup 20587ec0effdSAtul Deshmukh * DPC */ 20597ec0effdSAtul Deshmukh if (halt_status_unrecoverable) { 20607ec0effdSAtul Deshmukh set_bit(ISP_UNRECOVERABLE, 20617ec0effdSAtul Deshmukh &vha->dpc_flags); 20627ec0effdSAtul Deshmukh } else { 20637ec0effdSAtul Deshmukh if (dev_state == 20647ec0effdSAtul Deshmukh QLA8XXX_DEV_QUIESCENT) { 20657ec0effdSAtul Deshmukh set_bit(FCOE_CTX_RESET_NEEDED, 20667ec0effdSAtul Deshmukh &vha->dpc_flags); 20677ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0d9, 20687ec0effdSAtul Deshmukh "%s: FW CONTEXT Reset " 20697ec0effdSAtul Deshmukh "needed!\n", __func__); 20707ec0effdSAtul Deshmukh } else { 20717ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 20727ec0effdSAtul Deshmukh 0xb0da, "%s: " 20737ec0effdSAtul Deshmukh "detect abort needed\n", 20747ec0effdSAtul Deshmukh __func__); 20757ec0effdSAtul Deshmukh set_bit(ISP_ABORT_NEEDED, 20767ec0effdSAtul Deshmukh &vha->dpc_flags); 20777ec0effdSAtul Deshmukh qla82xx_clear_pending_mbx(vha); 20787ec0effdSAtul Deshmukh } 20797ec0effdSAtul Deshmukh } 20807ec0effdSAtul Deshmukh ha->flags.isp82xx_fw_hung = 1; 20817ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb10a, 20827ec0effdSAtul Deshmukh "Firmware hung.\n"); 20837ec0effdSAtul Deshmukh qla2xxx_wake_dpc(vha); 20847ec0effdSAtul Deshmukh } 20857ec0effdSAtul Deshmukh } 20867ec0effdSAtul Deshmukh 20877ec0effdSAtul Deshmukh } 20887ec0effdSAtul Deshmukh } 20897ec0effdSAtul Deshmukh 20907ec0effdSAtul Deshmukh static int 20917ec0effdSAtul Deshmukh qla8044_minidump_process_control(struct scsi_qla_host *vha, 20927ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr) 20937ec0effdSAtul Deshmukh { 20947ec0effdSAtul Deshmukh struct qla8044_minidump_entry_crb *crb_entry; 20957ec0effdSAtul Deshmukh uint32_t read_value, opcode, poll_time, addr, index; 20967ec0effdSAtul Deshmukh uint32_t crb_addr, rval = QLA_SUCCESS; 20977ec0effdSAtul Deshmukh unsigned long wtime; 20987ec0effdSAtul Deshmukh struct qla8044_minidump_template_hdr *tmplt_hdr; 20997ec0effdSAtul Deshmukh int i; 21007ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 21017ec0effdSAtul Deshmukh 21027ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__); 21037ec0effdSAtul Deshmukh tmplt_hdr = (struct qla8044_minidump_template_hdr *) 21047ec0effdSAtul Deshmukh ha->md_tmplt_hdr; 21057ec0effdSAtul Deshmukh crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr; 21067ec0effdSAtul Deshmukh 21077ec0effdSAtul Deshmukh crb_addr = crb_entry->addr; 21087ec0effdSAtul Deshmukh for (i = 0; i < crb_entry->op_count; i++) { 21097ec0effdSAtul Deshmukh opcode = crb_entry->crb_ctrl.opcode; 21107ec0effdSAtul Deshmukh 21117ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_WR) { 21127ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, crb_addr, 21137ec0effdSAtul Deshmukh crb_entry->value_1); 21147ec0effdSAtul Deshmukh opcode &= ~QLA82XX_DBG_OPCODE_WR; 21157ec0effdSAtul Deshmukh } 21167ec0effdSAtul Deshmukh 21177ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_RW) { 21187ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, crb_addr, &read_value); 21197ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, crb_addr, read_value); 21207ec0effdSAtul Deshmukh opcode &= ~QLA82XX_DBG_OPCODE_RW; 21217ec0effdSAtul Deshmukh } 21227ec0effdSAtul Deshmukh 21237ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_AND) { 21247ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, crb_addr, &read_value); 21257ec0effdSAtul Deshmukh read_value &= crb_entry->value_2; 21267ec0effdSAtul Deshmukh opcode &= ~QLA82XX_DBG_OPCODE_AND; 21277ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_OR) { 21287ec0effdSAtul Deshmukh read_value |= crb_entry->value_3; 21297ec0effdSAtul Deshmukh opcode &= ~QLA82XX_DBG_OPCODE_OR; 21307ec0effdSAtul Deshmukh } 21317ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, crb_addr, read_value); 21327ec0effdSAtul Deshmukh } 21337ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_OR) { 21347ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, crb_addr, &read_value); 21357ec0effdSAtul Deshmukh read_value |= crb_entry->value_3; 21367ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, crb_addr, read_value); 21377ec0effdSAtul Deshmukh opcode &= ~QLA82XX_DBG_OPCODE_OR; 21387ec0effdSAtul Deshmukh } 21397ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_POLL) { 21407ec0effdSAtul Deshmukh poll_time = crb_entry->crb_strd.poll_timeout; 21417ec0effdSAtul Deshmukh wtime = jiffies + poll_time; 21427ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, crb_addr, &read_value); 21437ec0effdSAtul Deshmukh 21447ec0effdSAtul Deshmukh do { 21457ec0effdSAtul Deshmukh if ((read_value & crb_entry->value_2) == 21467ec0effdSAtul Deshmukh crb_entry->value_1) { 21477ec0effdSAtul Deshmukh break; 21487ec0effdSAtul Deshmukh } else if (time_after_eq(jiffies, wtime)) { 21497ec0effdSAtul Deshmukh /* capturing dump failed */ 21507ec0effdSAtul Deshmukh rval = QLA_FUNCTION_FAILED; 21517ec0effdSAtul Deshmukh break; 21527ec0effdSAtul Deshmukh } else { 21537ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, 21547ec0effdSAtul Deshmukh crb_addr, &read_value); 21557ec0effdSAtul Deshmukh } 21567ec0effdSAtul Deshmukh } while (1); 21577ec0effdSAtul Deshmukh opcode &= ~QLA82XX_DBG_OPCODE_POLL; 21587ec0effdSAtul Deshmukh } 21597ec0effdSAtul Deshmukh 21607ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) { 21617ec0effdSAtul Deshmukh if (crb_entry->crb_strd.state_index_a) { 21627ec0effdSAtul Deshmukh index = crb_entry->crb_strd.state_index_a; 21637ec0effdSAtul Deshmukh addr = tmplt_hdr->saved_state_array[index]; 21647ec0effdSAtul Deshmukh } else { 21657ec0effdSAtul Deshmukh addr = crb_addr; 21667ec0effdSAtul Deshmukh } 21677ec0effdSAtul Deshmukh 21687ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, addr, &read_value); 21697ec0effdSAtul Deshmukh index = crb_entry->crb_ctrl.state_index_v; 21707ec0effdSAtul Deshmukh tmplt_hdr->saved_state_array[index] = read_value; 21717ec0effdSAtul Deshmukh opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE; 21727ec0effdSAtul Deshmukh } 21737ec0effdSAtul Deshmukh 21747ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) { 21757ec0effdSAtul Deshmukh if (crb_entry->crb_strd.state_index_a) { 21767ec0effdSAtul Deshmukh index = crb_entry->crb_strd.state_index_a; 21777ec0effdSAtul Deshmukh addr = tmplt_hdr->saved_state_array[index]; 21787ec0effdSAtul Deshmukh } else { 21797ec0effdSAtul Deshmukh addr = crb_addr; 21807ec0effdSAtul Deshmukh } 21817ec0effdSAtul Deshmukh 21827ec0effdSAtul Deshmukh if (crb_entry->crb_ctrl.state_index_v) { 21837ec0effdSAtul Deshmukh index = crb_entry->crb_ctrl.state_index_v; 21847ec0effdSAtul Deshmukh read_value = 21857ec0effdSAtul Deshmukh tmplt_hdr->saved_state_array[index]; 21867ec0effdSAtul Deshmukh } else { 21877ec0effdSAtul Deshmukh read_value = crb_entry->value_1; 21887ec0effdSAtul Deshmukh } 21897ec0effdSAtul Deshmukh 21907ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, addr, read_value); 21917ec0effdSAtul Deshmukh opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE; 21927ec0effdSAtul Deshmukh } 21937ec0effdSAtul Deshmukh 21947ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) { 21957ec0effdSAtul Deshmukh index = crb_entry->crb_ctrl.state_index_v; 21967ec0effdSAtul Deshmukh read_value = tmplt_hdr->saved_state_array[index]; 21977ec0effdSAtul Deshmukh read_value <<= crb_entry->crb_ctrl.shl; 21987ec0effdSAtul Deshmukh read_value >>= crb_entry->crb_ctrl.shr; 21997ec0effdSAtul Deshmukh if (crb_entry->value_2) 22007ec0effdSAtul Deshmukh read_value &= crb_entry->value_2; 22017ec0effdSAtul Deshmukh read_value |= crb_entry->value_3; 22027ec0effdSAtul Deshmukh read_value += crb_entry->value_1; 22037ec0effdSAtul Deshmukh tmplt_hdr->saved_state_array[index] = read_value; 22047ec0effdSAtul Deshmukh opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE; 22057ec0effdSAtul Deshmukh } 22067ec0effdSAtul Deshmukh crb_addr += crb_entry->crb_strd.addr_stride; 22077ec0effdSAtul Deshmukh } 22087ec0effdSAtul Deshmukh return rval; 22097ec0effdSAtul Deshmukh } 22107ec0effdSAtul Deshmukh 22117ec0effdSAtul Deshmukh static void 22127ec0effdSAtul Deshmukh qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha, 22137ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 22147ec0effdSAtul Deshmukh { 22157ec0effdSAtul Deshmukh uint32_t r_addr, r_stride, loop_cnt, i, r_value; 22167ec0effdSAtul Deshmukh struct qla8044_minidump_entry_crb *crb_hdr; 22177ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr; 22187ec0effdSAtul Deshmukh 22197ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__); 22207ec0effdSAtul Deshmukh crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr; 22217ec0effdSAtul Deshmukh r_addr = crb_hdr->addr; 22227ec0effdSAtul Deshmukh r_stride = crb_hdr->crb_strd.addr_stride; 22237ec0effdSAtul Deshmukh loop_cnt = crb_hdr->op_count; 22247ec0effdSAtul Deshmukh 22257ec0effdSAtul Deshmukh for (i = 0; i < loop_cnt; i++) { 22267ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, r_addr, &r_value); 22277ec0effdSAtul Deshmukh *data_ptr++ = r_addr; 22287ec0effdSAtul Deshmukh *data_ptr++ = r_value; 22297ec0effdSAtul Deshmukh r_addr += r_stride; 22307ec0effdSAtul Deshmukh } 22317ec0effdSAtul Deshmukh *d_ptr = data_ptr; 22327ec0effdSAtul Deshmukh } 22337ec0effdSAtul Deshmukh 22347ec0effdSAtul Deshmukh static int 22357ec0effdSAtul Deshmukh qla8044_minidump_process_rdmem(struct scsi_qla_host *vha, 22367ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 22377ec0effdSAtul Deshmukh { 22387ec0effdSAtul Deshmukh uint32_t r_addr, r_value, r_data; 22397ec0effdSAtul Deshmukh uint32_t i, j, loop_cnt; 22407ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdmem *m_hdr; 22417ec0effdSAtul Deshmukh unsigned long flags; 22427ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr; 22437ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 22447ec0effdSAtul Deshmukh 22457ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__); 22467ec0effdSAtul Deshmukh m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr; 22477ec0effdSAtul Deshmukh r_addr = m_hdr->read_addr; 22487ec0effdSAtul Deshmukh loop_cnt = m_hdr->read_data_size/16; 22497ec0effdSAtul Deshmukh 22507ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f0, 22517ec0effdSAtul Deshmukh "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n", 22527ec0effdSAtul Deshmukh __func__, r_addr, m_hdr->read_data_size); 22537ec0effdSAtul Deshmukh 22547ec0effdSAtul Deshmukh if (r_addr & 0xf) { 22557ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f1, 22567ec0effdSAtul Deshmukh "[%s]: Read addr 0x%x not 16 bytes alligned\n", 22577ec0effdSAtul Deshmukh __func__, r_addr); 22587ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 22597ec0effdSAtul Deshmukh } 22607ec0effdSAtul Deshmukh 22617ec0effdSAtul Deshmukh if (m_hdr->read_data_size % 16) { 22627ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f2, 22637ec0effdSAtul Deshmukh "[%s]: Read data[0x%x] not multiple of 16 bytes\n", 22647ec0effdSAtul Deshmukh __func__, m_hdr->read_data_size); 22657ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 22667ec0effdSAtul Deshmukh } 22677ec0effdSAtul Deshmukh 22687ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f3, 22697ec0effdSAtul Deshmukh "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n", 22707ec0effdSAtul Deshmukh __func__, r_addr, m_hdr->read_data_size, loop_cnt); 22717ec0effdSAtul Deshmukh 22727ec0effdSAtul Deshmukh write_lock_irqsave(&ha->hw_lock, flags); 22737ec0effdSAtul Deshmukh for (i = 0; i < loop_cnt; i++) { 22747ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr); 22757ec0effdSAtul Deshmukh r_value = 0; 22767ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value); 22777ec0effdSAtul Deshmukh r_value = MIU_TA_CTL_ENABLE; 22787ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value); 22797ec0effdSAtul Deshmukh r_value = MIU_TA_CTL_START_ENABLE; 22807ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value); 22817ec0effdSAtul Deshmukh 22827ec0effdSAtul Deshmukh for (j = 0; j < MAX_CTL_CHECK; j++) { 22837ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, 22847ec0effdSAtul Deshmukh &r_value); 22857ec0effdSAtul Deshmukh if ((r_value & MIU_TA_CTL_BUSY) == 0) 22867ec0effdSAtul Deshmukh break; 22877ec0effdSAtul Deshmukh } 22887ec0effdSAtul Deshmukh 22897ec0effdSAtul Deshmukh if (j >= MAX_CTL_CHECK) { 22907ec0effdSAtul Deshmukh printk_ratelimited(KERN_ERR 22917ec0effdSAtul Deshmukh "%s: failed to read through agent\n", __func__); 22927ec0effdSAtul Deshmukh write_unlock_irqrestore(&ha->hw_lock, flags); 22937ec0effdSAtul Deshmukh return QLA_SUCCESS; 22947ec0effdSAtul Deshmukh } 22957ec0effdSAtul Deshmukh 22967ec0effdSAtul Deshmukh for (j = 0; j < 4; j++) { 22977ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j], 22987ec0effdSAtul Deshmukh &r_data); 22997ec0effdSAtul Deshmukh *data_ptr++ = r_data; 23007ec0effdSAtul Deshmukh } 23017ec0effdSAtul Deshmukh 23027ec0effdSAtul Deshmukh r_addr += 16; 23037ec0effdSAtul Deshmukh } 23047ec0effdSAtul Deshmukh write_unlock_irqrestore(&ha->hw_lock, flags); 23057ec0effdSAtul Deshmukh 23067ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f4, 23077ec0effdSAtul Deshmukh "Leaving fn: %s datacount: 0x%x\n", 23087ec0effdSAtul Deshmukh __func__, (loop_cnt * 16)); 23097ec0effdSAtul Deshmukh 23107ec0effdSAtul Deshmukh *d_ptr = data_ptr; 23117ec0effdSAtul Deshmukh return QLA_SUCCESS; 23127ec0effdSAtul Deshmukh } 23137ec0effdSAtul Deshmukh 23147ec0effdSAtul Deshmukh /* ISP83xx flash read for _RDROM _BOARD */ 23157ec0effdSAtul Deshmukh static uint32_t 23167ec0effdSAtul Deshmukh qla8044_minidump_process_rdrom(struct scsi_qla_host *vha, 23177ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 23187ec0effdSAtul Deshmukh { 23197ec0effdSAtul Deshmukh uint32_t fl_addr, u32_count, rval; 23207ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdrom *rom_hdr; 23217ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr; 23227ec0effdSAtul Deshmukh 23237ec0effdSAtul Deshmukh rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr; 23247ec0effdSAtul Deshmukh fl_addr = rom_hdr->read_addr; 23257ec0effdSAtul Deshmukh u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t); 23267ec0effdSAtul Deshmukh 23277ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n", 23287ec0effdSAtul Deshmukh __func__, fl_addr, u32_count); 23297ec0effdSAtul Deshmukh 23307ec0effdSAtul Deshmukh rval = qla8044_lockless_flash_read_u32(vha, fl_addr, 23317ec0effdSAtul Deshmukh (u8 *)(data_ptr), u32_count); 23327ec0effdSAtul Deshmukh 23337ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) { 23347ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0f6, 23357ec0effdSAtul Deshmukh "%s: Flash Read Error,Count=%d\n", __func__, u32_count); 23367ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 23377ec0effdSAtul Deshmukh } else { 23387ec0effdSAtul Deshmukh data_ptr += u32_count; 23397ec0effdSAtul Deshmukh *d_ptr = data_ptr; 23407ec0effdSAtul Deshmukh return QLA_SUCCESS; 23417ec0effdSAtul Deshmukh } 23427ec0effdSAtul Deshmukh } 23437ec0effdSAtul Deshmukh 23447ec0effdSAtul Deshmukh static void 23457ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(struct scsi_qla_host *vha, 23467ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, int index) 23477ec0effdSAtul Deshmukh { 23487ec0effdSAtul Deshmukh entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG; 23497ec0effdSAtul Deshmukh 23507ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0f7, 23517ec0effdSAtul Deshmukh "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n", 23527ec0effdSAtul Deshmukh vha->host_no, index, entry_hdr->entry_type, 23537ec0effdSAtul Deshmukh entry_hdr->d_ctrl.entry_capture_mask); 23547ec0effdSAtul Deshmukh } 23557ec0effdSAtul Deshmukh 23567ec0effdSAtul Deshmukh static int 23577ec0effdSAtul Deshmukh qla8044_minidump_process_l2tag(struct scsi_qla_host *vha, 23587ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, 23597ec0effdSAtul Deshmukh uint32_t **d_ptr) 23607ec0effdSAtul Deshmukh { 23617ec0effdSAtul Deshmukh uint32_t addr, r_addr, c_addr, t_r_addr; 23627ec0effdSAtul Deshmukh uint32_t i, k, loop_count, t_value, r_cnt, r_value; 23637ec0effdSAtul Deshmukh unsigned long p_wait, w_time, p_mask; 23647ec0effdSAtul Deshmukh uint32_t c_value_w, c_value_r; 23657ec0effdSAtul Deshmukh struct qla8044_minidump_entry_cache *cache_hdr; 23667ec0effdSAtul Deshmukh int rval = QLA_FUNCTION_FAILED; 23677ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr; 23687ec0effdSAtul Deshmukh 23697ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__); 23707ec0effdSAtul Deshmukh cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr; 23717ec0effdSAtul Deshmukh 23727ec0effdSAtul Deshmukh loop_count = cache_hdr->op_count; 23737ec0effdSAtul Deshmukh r_addr = cache_hdr->read_addr; 23747ec0effdSAtul Deshmukh c_addr = cache_hdr->control_addr; 23757ec0effdSAtul Deshmukh c_value_w = cache_hdr->cache_ctrl.write_value; 23767ec0effdSAtul Deshmukh 23777ec0effdSAtul Deshmukh t_r_addr = cache_hdr->tag_reg_addr; 23787ec0effdSAtul Deshmukh t_value = cache_hdr->addr_ctrl.init_tag_value; 23797ec0effdSAtul Deshmukh r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 23807ec0effdSAtul Deshmukh p_wait = cache_hdr->cache_ctrl.poll_wait; 23817ec0effdSAtul Deshmukh p_mask = cache_hdr->cache_ctrl.poll_mask; 23827ec0effdSAtul Deshmukh 23837ec0effdSAtul Deshmukh for (i = 0; i < loop_count; i++) { 23847ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, t_r_addr, t_value); 23857ec0effdSAtul Deshmukh if (c_value_w) 23867ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, c_addr, c_value_w); 23877ec0effdSAtul Deshmukh 23887ec0effdSAtul Deshmukh if (p_mask) { 23897ec0effdSAtul Deshmukh w_time = jiffies + p_wait; 23907ec0effdSAtul Deshmukh do { 23917ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, c_addr, 23927ec0effdSAtul Deshmukh &c_value_r); 23937ec0effdSAtul Deshmukh if ((c_value_r & p_mask) == 0) { 23947ec0effdSAtul Deshmukh break; 23957ec0effdSAtul Deshmukh } else if (time_after_eq(jiffies, w_time)) { 23967ec0effdSAtul Deshmukh /* capturing dump failed */ 23977ec0effdSAtul Deshmukh return rval; 23987ec0effdSAtul Deshmukh } 23997ec0effdSAtul Deshmukh } while (1); 24007ec0effdSAtul Deshmukh } 24017ec0effdSAtul Deshmukh 24027ec0effdSAtul Deshmukh addr = r_addr; 24037ec0effdSAtul Deshmukh for (k = 0; k < r_cnt; k++) { 24047ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, addr, &r_value); 24057ec0effdSAtul Deshmukh *data_ptr++ = r_value; 24067ec0effdSAtul Deshmukh addr += cache_hdr->read_ctrl.read_addr_stride; 24077ec0effdSAtul Deshmukh } 24087ec0effdSAtul Deshmukh t_value += cache_hdr->addr_ctrl.tag_value_stride; 24097ec0effdSAtul Deshmukh } 24107ec0effdSAtul Deshmukh *d_ptr = data_ptr; 24117ec0effdSAtul Deshmukh return QLA_SUCCESS; 24127ec0effdSAtul Deshmukh } 24137ec0effdSAtul Deshmukh 24147ec0effdSAtul Deshmukh static void 24157ec0effdSAtul Deshmukh qla8044_minidump_process_l1cache(struct scsi_qla_host *vha, 24167ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 24177ec0effdSAtul Deshmukh { 24187ec0effdSAtul Deshmukh uint32_t addr, r_addr, c_addr, t_r_addr; 24197ec0effdSAtul Deshmukh uint32_t i, k, loop_count, t_value, r_cnt, r_value; 24207ec0effdSAtul Deshmukh uint32_t c_value_w; 24217ec0effdSAtul Deshmukh struct qla8044_minidump_entry_cache *cache_hdr; 24227ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr; 24237ec0effdSAtul Deshmukh 24247ec0effdSAtul Deshmukh cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr; 24257ec0effdSAtul Deshmukh loop_count = cache_hdr->op_count; 24267ec0effdSAtul Deshmukh r_addr = cache_hdr->read_addr; 24277ec0effdSAtul Deshmukh c_addr = cache_hdr->control_addr; 24287ec0effdSAtul Deshmukh c_value_w = cache_hdr->cache_ctrl.write_value; 24297ec0effdSAtul Deshmukh 24307ec0effdSAtul Deshmukh t_r_addr = cache_hdr->tag_reg_addr; 24317ec0effdSAtul Deshmukh t_value = cache_hdr->addr_ctrl.init_tag_value; 24327ec0effdSAtul Deshmukh r_cnt = cache_hdr->read_ctrl.read_addr_cnt; 24337ec0effdSAtul Deshmukh 24347ec0effdSAtul Deshmukh for (i = 0; i < loop_count; i++) { 24357ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, t_r_addr, t_value); 24367ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, c_addr, c_value_w); 24377ec0effdSAtul Deshmukh addr = r_addr; 24387ec0effdSAtul Deshmukh for (k = 0; k < r_cnt; k++) { 24397ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, addr, &r_value); 24407ec0effdSAtul Deshmukh *data_ptr++ = r_value; 24417ec0effdSAtul Deshmukh addr += cache_hdr->read_ctrl.read_addr_stride; 24427ec0effdSAtul Deshmukh } 24437ec0effdSAtul Deshmukh t_value += cache_hdr->addr_ctrl.tag_value_stride; 24447ec0effdSAtul Deshmukh } 24457ec0effdSAtul Deshmukh *d_ptr = data_ptr; 24467ec0effdSAtul Deshmukh } 24477ec0effdSAtul Deshmukh 24487ec0effdSAtul Deshmukh static void 24497ec0effdSAtul Deshmukh qla8044_minidump_process_rdocm(struct scsi_qla_host *vha, 24507ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 24517ec0effdSAtul Deshmukh { 24527ec0effdSAtul Deshmukh uint32_t r_addr, r_stride, loop_cnt, i, r_value; 24537ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdocm *ocm_hdr; 24547ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr; 24557ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 24567ec0effdSAtul Deshmukh 24577ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__); 24587ec0effdSAtul Deshmukh 24597ec0effdSAtul Deshmukh ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr; 24607ec0effdSAtul Deshmukh r_addr = ocm_hdr->read_addr; 24617ec0effdSAtul Deshmukh r_stride = ocm_hdr->read_addr_stride; 24627ec0effdSAtul Deshmukh loop_cnt = ocm_hdr->op_count; 24637ec0effdSAtul Deshmukh 24647ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0fa, 24657ec0effdSAtul Deshmukh "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n", 24667ec0effdSAtul Deshmukh __func__, r_addr, r_stride, loop_cnt); 24677ec0effdSAtul Deshmukh 24687ec0effdSAtul Deshmukh for (i = 0; i < loop_cnt; i++) { 24697ec0effdSAtul Deshmukh r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase)); 24707ec0effdSAtul Deshmukh *data_ptr++ = r_value; 24717ec0effdSAtul Deshmukh r_addr += r_stride; 24727ec0effdSAtul Deshmukh } 24737ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n", 24747ec0effdSAtul Deshmukh __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t))); 24757ec0effdSAtul Deshmukh 24767ec0effdSAtul Deshmukh *d_ptr = data_ptr; 24777ec0effdSAtul Deshmukh } 24787ec0effdSAtul Deshmukh 24797ec0effdSAtul Deshmukh static void 24807ec0effdSAtul Deshmukh qla8044_minidump_process_rdmux(struct scsi_qla_host *vha, 24817ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, 24827ec0effdSAtul Deshmukh uint32_t **d_ptr) 24837ec0effdSAtul Deshmukh { 24847ec0effdSAtul Deshmukh uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value; 24857ec0effdSAtul Deshmukh struct qla8044_minidump_entry_mux *mux_hdr; 24867ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr; 24877ec0effdSAtul Deshmukh 24887ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__); 24897ec0effdSAtul Deshmukh 24907ec0effdSAtul Deshmukh mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr; 24917ec0effdSAtul Deshmukh r_addr = mux_hdr->read_addr; 24927ec0effdSAtul Deshmukh s_addr = mux_hdr->select_addr; 24937ec0effdSAtul Deshmukh s_stride = mux_hdr->select_value_stride; 24947ec0effdSAtul Deshmukh s_value = mux_hdr->select_value; 24957ec0effdSAtul Deshmukh loop_cnt = mux_hdr->op_count; 24967ec0effdSAtul Deshmukh 24977ec0effdSAtul Deshmukh for (i = 0; i < loop_cnt; i++) { 24987ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, s_addr, s_value); 24997ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, r_addr, &r_value); 25007ec0effdSAtul Deshmukh *data_ptr++ = s_value; 25017ec0effdSAtul Deshmukh *data_ptr++ = r_value; 25027ec0effdSAtul Deshmukh s_value += s_stride; 25037ec0effdSAtul Deshmukh } 25047ec0effdSAtul Deshmukh *d_ptr = data_ptr; 25057ec0effdSAtul Deshmukh } 25067ec0effdSAtul Deshmukh 25077ec0effdSAtul Deshmukh static void 25087ec0effdSAtul Deshmukh qla8044_minidump_process_queue(struct scsi_qla_host *vha, 25097ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, 25107ec0effdSAtul Deshmukh uint32_t **d_ptr) 25117ec0effdSAtul Deshmukh { 25127ec0effdSAtul Deshmukh uint32_t s_addr, r_addr; 25137ec0effdSAtul Deshmukh uint32_t r_stride, r_value, r_cnt, qid = 0; 25147ec0effdSAtul Deshmukh uint32_t i, k, loop_cnt; 25157ec0effdSAtul Deshmukh struct qla8044_minidump_entry_queue *q_hdr; 25167ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr; 25177ec0effdSAtul Deshmukh 25187ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__); 25197ec0effdSAtul Deshmukh q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr; 25207ec0effdSAtul Deshmukh s_addr = q_hdr->select_addr; 25217ec0effdSAtul Deshmukh r_cnt = q_hdr->rd_strd.read_addr_cnt; 25227ec0effdSAtul Deshmukh r_stride = q_hdr->rd_strd.read_addr_stride; 25237ec0effdSAtul Deshmukh loop_cnt = q_hdr->op_count; 25247ec0effdSAtul Deshmukh 25257ec0effdSAtul Deshmukh for (i = 0; i < loop_cnt; i++) { 25267ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, s_addr, qid); 25277ec0effdSAtul Deshmukh r_addr = q_hdr->read_addr; 25287ec0effdSAtul Deshmukh for (k = 0; k < r_cnt; k++) { 25297ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, r_addr, &r_value); 25307ec0effdSAtul Deshmukh *data_ptr++ = r_value; 25317ec0effdSAtul Deshmukh r_addr += r_stride; 25327ec0effdSAtul Deshmukh } 25337ec0effdSAtul Deshmukh qid += q_hdr->q_strd.queue_id_stride; 25347ec0effdSAtul Deshmukh } 25357ec0effdSAtul Deshmukh *d_ptr = data_ptr; 25367ec0effdSAtul Deshmukh } 25377ec0effdSAtul Deshmukh 25387ec0effdSAtul Deshmukh /* ISP83xx functions to process new minidump entries... */ 25397ec0effdSAtul Deshmukh static uint32_t 25407ec0effdSAtul Deshmukh qla8044_minidump_process_pollrd(struct scsi_qla_host *vha, 25417ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, 25427ec0effdSAtul Deshmukh uint32_t **d_ptr) 25437ec0effdSAtul Deshmukh { 25447ec0effdSAtul Deshmukh uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask; 25457ec0effdSAtul Deshmukh uint16_t s_stride, i; 25467ec0effdSAtul Deshmukh struct qla8044_minidump_entry_pollrd *pollrd_hdr; 25477ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr; 25487ec0effdSAtul Deshmukh 25497ec0effdSAtul Deshmukh pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr; 25507ec0effdSAtul Deshmukh s_addr = pollrd_hdr->select_addr; 25517ec0effdSAtul Deshmukh r_addr = pollrd_hdr->read_addr; 25527ec0effdSAtul Deshmukh s_value = pollrd_hdr->select_value; 25537ec0effdSAtul Deshmukh s_stride = pollrd_hdr->select_value_stride; 25547ec0effdSAtul Deshmukh 25557ec0effdSAtul Deshmukh poll_wait = pollrd_hdr->poll_wait; 25567ec0effdSAtul Deshmukh poll_mask = pollrd_hdr->poll_mask; 25577ec0effdSAtul Deshmukh 25587ec0effdSAtul Deshmukh for (i = 0; i < pollrd_hdr->op_count; i++) { 25597ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, s_addr, s_value); 25607ec0effdSAtul Deshmukh poll_wait = pollrd_hdr->poll_wait; 25617ec0effdSAtul Deshmukh while (1) { 25627ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, s_addr, &r_value); 25637ec0effdSAtul Deshmukh if ((r_value & poll_mask) != 0) { 25647ec0effdSAtul Deshmukh break; 25657ec0effdSAtul Deshmukh } else { 25667ec0effdSAtul Deshmukh usleep_range(1000, 1100); 25677ec0effdSAtul Deshmukh if (--poll_wait == 0) { 25687ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0fe, 25697ec0effdSAtul Deshmukh "%s: TIMEOUT\n", __func__); 25707ec0effdSAtul Deshmukh goto error; 25717ec0effdSAtul Deshmukh } 25727ec0effdSAtul Deshmukh } 25737ec0effdSAtul Deshmukh } 25747ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, r_addr, &r_value); 25757ec0effdSAtul Deshmukh *data_ptr++ = s_value; 25767ec0effdSAtul Deshmukh *data_ptr++ = r_value; 25777ec0effdSAtul Deshmukh 25787ec0effdSAtul Deshmukh s_value += s_stride; 25797ec0effdSAtul Deshmukh } 25807ec0effdSAtul Deshmukh *d_ptr = data_ptr; 25817ec0effdSAtul Deshmukh return QLA_SUCCESS; 25827ec0effdSAtul Deshmukh 25837ec0effdSAtul Deshmukh error: 25847ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 25857ec0effdSAtul Deshmukh } 25867ec0effdSAtul Deshmukh 25877ec0effdSAtul Deshmukh static void 25887ec0effdSAtul Deshmukh qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha, 25897ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 25907ec0effdSAtul Deshmukh { 25917ec0effdSAtul Deshmukh uint32_t sel_val1, sel_val2, t_sel_val, data, i; 25927ec0effdSAtul Deshmukh uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr; 25937ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr; 25947ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr; 25957ec0effdSAtul Deshmukh 25967ec0effdSAtul Deshmukh rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr; 25977ec0effdSAtul Deshmukh sel_val1 = rdmux2_hdr->select_value_1; 25987ec0effdSAtul Deshmukh sel_val2 = rdmux2_hdr->select_value_2; 25997ec0effdSAtul Deshmukh sel_addr1 = rdmux2_hdr->select_addr_1; 26007ec0effdSAtul Deshmukh sel_addr2 = rdmux2_hdr->select_addr_2; 26017ec0effdSAtul Deshmukh sel_val_mask = rdmux2_hdr->select_value_mask; 26027ec0effdSAtul Deshmukh read_addr = rdmux2_hdr->read_addr; 26037ec0effdSAtul Deshmukh 26047ec0effdSAtul Deshmukh for (i = 0; i < rdmux2_hdr->op_count; i++) { 26057ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1); 26067ec0effdSAtul Deshmukh t_sel_val = sel_val1 & sel_val_mask; 26077ec0effdSAtul Deshmukh *data_ptr++ = t_sel_val; 26087ec0effdSAtul Deshmukh 26097ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val); 26107ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, read_addr, &data); 26117ec0effdSAtul Deshmukh 26127ec0effdSAtul Deshmukh *data_ptr++ = data; 26137ec0effdSAtul Deshmukh 26147ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2); 26157ec0effdSAtul Deshmukh t_sel_val = sel_val2 & sel_val_mask; 26167ec0effdSAtul Deshmukh *data_ptr++ = t_sel_val; 26177ec0effdSAtul Deshmukh 26187ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val); 26197ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, read_addr, &data); 26207ec0effdSAtul Deshmukh 26217ec0effdSAtul Deshmukh *data_ptr++ = data; 26227ec0effdSAtul Deshmukh 26237ec0effdSAtul Deshmukh sel_val1 += rdmux2_hdr->select_value_stride; 26247ec0effdSAtul Deshmukh sel_val2 += rdmux2_hdr->select_value_stride; 26257ec0effdSAtul Deshmukh } 26267ec0effdSAtul Deshmukh 26277ec0effdSAtul Deshmukh *d_ptr = data_ptr; 26287ec0effdSAtul Deshmukh } 26297ec0effdSAtul Deshmukh 26307ec0effdSAtul Deshmukh static uint32_t 26317ec0effdSAtul Deshmukh qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha, 26327ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, 26337ec0effdSAtul Deshmukh uint32_t **d_ptr) 26347ec0effdSAtul Deshmukh { 26357ec0effdSAtul Deshmukh uint32_t poll_wait, poll_mask, r_value, data; 26367ec0effdSAtul Deshmukh uint32_t addr_1, addr_2, value_1, value_2; 26377ec0effdSAtul Deshmukh struct qla8044_minidump_entry_pollrdmwr *poll_hdr; 26387ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr; 26397ec0effdSAtul Deshmukh 26407ec0effdSAtul Deshmukh poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr; 26417ec0effdSAtul Deshmukh addr_1 = poll_hdr->addr_1; 26427ec0effdSAtul Deshmukh addr_2 = poll_hdr->addr_2; 26437ec0effdSAtul Deshmukh value_1 = poll_hdr->value_1; 26447ec0effdSAtul Deshmukh value_2 = poll_hdr->value_2; 26457ec0effdSAtul Deshmukh poll_mask = poll_hdr->poll_mask; 26467ec0effdSAtul Deshmukh 26477ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, addr_1, value_1); 26487ec0effdSAtul Deshmukh 26497ec0effdSAtul Deshmukh poll_wait = poll_hdr->poll_wait; 26507ec0effdSAtul Deshmukh while (1) { 26517ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, addr_1, &r_value); 26527ec0effdSAtul Deshmukh 26537ec0effdSAtul Deshmukh if ((r_value & poll_mask) != 0) { 26547ec0effdSAtul Deshmukh break; 26557ec0effdSAtul Deshmukh } else { 26567ec0effdSAtul Deshmukh usleep_range(1000, 1100); 26577ec0effdSAtul Deshmukh if (--poll_wait == 0) { 26587ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0ff, 26597ec0effdSAtul Deshmukh "%s: TIMEOUT\n", __func__); 26607ec0effdSAtul Deshmukh goto error; 26617ec0effdSAtul Deshmukh } 26627ec0effdSAtul Deshmukh } 26637ec0effdSAtul Deshmukh } 26647ec0effdSAtul Deshmukh 26657ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, addr_2, &data); 26667ec0effdSAtul Deshmukh data &= poll_hdr->modify_mask; 26677ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, addr_2, data); 26687ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, addr_1, value_2); 26697ec0effdSAtul Deshmukh 26707ec0effdSAtul Deshmukh poll_wait = poll_hdr->poll_wait; 26717ec0effdSAtul Deshmukh while (1) { 26727ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, addr_1, &r_value); 26737ec0effdSAtul Deshmukh 26747ec0effdSAtul Deshmukh if ((r_value & poll_mask) != 0) { 26757ec0effdSAtul Deshmukh break; 26767ec0effdSAtul Deshmukh } else { 26777ec0effdSAtul Deshmukh usleep_range(1000, 1100); 26787ec0effdSAtul Deshmukh if (--poll_wait == 0) { 26797ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb100, 26807ec0effdSAtul Deshmukh "%s: TIMEOUT2\n", __func__); 26817ec0effdSAtul Deshmukh goto error; 26827ec0effdSAtul Deshmukh } 26837ec0effdSAtul Deshmukh } 26847ec0effdSAtul Deshmukh } 26857ec0effdSAtul Deshmukh 26867ec0effdSAtul Deshmukh *data_ptr++ = addr_2; 26877ec0effdSAtul Deshmukh *data_ptr++ = data; 26887ec0effdSAtul Deshmukh 26897ec0effdSAtul Deshmukh *d_ptr = data_ptr; 26907ec0effdSAtul Deshmukh 26917ec0effdSAtul Deshmukh return QLA_SUCCESS; 26927ec0effdSAtul Deshmukh 26937ec0effdSAtul Deshmukh error: 26947ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 26957ec0effdSAtul Deshmukh } 26967ec0effdSAtul Deshmukh 26977ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_ENGINE_INDEX 8 26987ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_BASE_ADDRESS 0x77320000 26997ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_NUM_OFFSET 0x10000 27007ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_CMD_ADDR_LOW 0x0 27017ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_CMD_ADDR_HIGH 0x04 27027ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL 0x08 27037ec0effdSAtul Deshmukh 27047ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_READ_SIZE (16 * 1024) 27057ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */ 27067ec0effdSAtul Deshmukh 27077ec0effdSAtul Deshmukh static int 27087ec0effdSAtul Deshmukh qla8044_check_dma_engine_state(struct scsi_qla_host *vha) 27097ec0effdSAtul Deshmukh { 27107ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 27117ec0effdSAtul Deshmukh int rval = QLA_SUCCESS; 27127ec0effdSAtul Deshmukh uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 27137ec0effdSAtul Deshmukh uint64_t dma_base_addr = 0; 27147ec0effdSAtul Deshmukh struct qla8044_minidump_template_hdr *tmplt_hdr = NULL; 27157ec0effdSAtul Deshmukh 27167ec0effdSAtul Deshmukh tmplt_hdr = ha->md_tmplt_hdr; 27177ec0effdSAtul Deshmukh dma_eng_num = 27187ec0effdSAtul Deshmukh tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX]; 27197ec0effdSAtul Deshmukh dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS + 27207ec0effdSAtul Deshmukh (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET); 27217ec0effdSAtul Deshmukh 27227ec0effdSAtul Deshmukh /* Read the pex-dma's command-status-and-control register. */ 27237ec0effdSAtul Deshmukh rval = qla8044_rd_reg_indirect(vha, 27247ec0effdSAtul Deshmukh (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL), 27257ec0effdSAtul Deshmukh &cmd_sts_and_cntrl); 27267ec0effdSAtul Deshmukh if (rval) 27277ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 27287ec0effdSAtul Deshmukh 27297ec0effdSAtul Deshmukh /* Check if requested pex-dma engine is available. */ 27307ec0effdSAtul Deshmukh if (cmd_sts_and_cntrl & BIT_31) 27317ec0effdSAtul Deshmukh return QLA_SUCCESS; 27327ec0effdSAtul Deshmukh 27337ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 27347ec0effdSAtul Deshmukh } 27357ec0effdSAtul Deshmukh 27367ec0effdSAtul Deshmukh static int 27377ec0effdSAtul Deshmukh qla8044_start_pex_dma(struct scsi_qla_host *vha, 27387ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr) 27397ec0effdSAtul Deshmukh { 27407ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 27417ec0effdSAtul Deshmukh int rval = QLA_SUCCESS, wait = 0; 27427ec0effdSAtul Deshmukh uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0; 27437ec0effdSAtul Deshmukh uint64_t dma_base_addr = 0; 27447ec0effdSAtul Deshmukh struct qla8044_minidump_template_hdr *tmplt_hdr = NULL; 27457ec0effdSAtul Deshmukh 27467ec0effdSAtul Deshmukh tmplt_hdr = ha->md_tmplt_hdr; 27477ec0effdSAtul Deshmukh dma_eng_num = 27487ec0effdSAtul Deshmukh tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX]; 27497ec0effdSAtul Deshmukh dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS + 27507ec0effdSAtul Deshmukh (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET); 27517ec0effdSAtul Deshmukh 27527ec0effdSAtul Deshmukh rval = qla8044_wr_reg_indirect(vha, 27537ec0effdSAtul Deshmukh dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW, 27547ec0effdSAtul Deshmukh m_hdr->desc_card_addr); 27557ec0effdSAtul Deshmukh if (rval) 27567ec0effdSAtul Deshmukh goto error_exit; 27577ec0effdSAtul Deshmukh 27587ec0effdSAtul Deshmukh rval = qla8044_wr_reg_indirect(vha, 27597ec0effdSAtul Deshmukh dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0); 27607ec0effdSAtul Deshmukh if (rval) 27617ec0effdSAtul Deshmukh goto error_exit; 27627ec0effdSAtul Deshmukh 27637ec0effdSAtul Deshmukh rval = qla8044_wr_reg_indirect(vha, 27647ec0effdSAtul Deshmukh dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL, 27657ec0effdSAtul Deshmukh m_hdr->start_dma_cmd); 27667ec0effdSAtul Deshmukh if (rval) 27677ec0effdSAtul Deshmukh goto error_exit; 27687ec0effdSAtul Deshmukh 27697ec0effdSAtul Deshmukh /* Wait for dma operation to complete. */ 27707ec0effdSAtul Deshmukh for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) { 27717ec0effdSAtul Deshmukh rval = qla8044_rd_reg_indirect(vha, 27727ec0effdSAtul Deshmukh (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL), 27737ec0effdSAtul Deshmukh &cmd_sts_and_cntrl); 27747ec0effdSAtul Deshmukh if (rval) 27757ec0effdSAtul Deshmukh goto error_exit; 27767ec0effdSAtul Deshmukh 27777ec0effdSAtul Deshmukh if ((cmd_sts_and_cntrl & BIT_1) == 0) 27787ec0effdSAtul Deshmukh break; 27797ec0effdSAtul Deshmukh 27807ec0effdSAtul Deshmukh udelay(10); 27817ec0effdSAtul Deshmukh } 27827ec0effdSAtul Deshmukh 27837ec0effdSAtul Deshmukh /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */ 27847ec0effdSAtul Deshmukh if (wait >= ISP8044_PEX_DMA_MAX_WAIT) { 27857ec0effdSAtul Deshmukh rval = QLA_FUNCTION_FAILED; 27867ec0effdSAtul Deshmukh goto error_exit; 27877ec0effdSAtul Deshmukh } 27887ec0effdSAtul Deshmukh 27897ec0effdSAtul Deshmukh error_exit: 27907ec0effdSAtul Deshmukh return rval; 27917ec0effdSAtul Deshmukh } 27927ec0effdSAtul Deshmukh 27937ec0effdSAtul Deshmukh static int 27947ec0effdSAtul Deshmukh qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha, 27957ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr) 27967ec0effdSAtul Deshmukh { 27977ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 27987ec0effdSAtul Deshmukh int rval = QLA_SUCCESS; 27997ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL; 28007ec0effdSAtul Deshmukh uint32_t chunk_size, read_size; 28017ec0effdSAtul Deshmukh uint8_t *data_ptr = (uint8_t *)*d_ptr; 28027ec0effdSAtul Deshmukh void *rdmem_buffer = NULL; 28037ec0effdSAtul Deshmukh dma_addr_t rdmem_dma; 28047ec0effdSAtul Deshmukh struct qla8044_pex_dma_descriptor dma_desc; 28057ec0effdSAtul Deshmukh 28067ec0effdSAtul Deshmukh rval = qla8044_check_dma_engine_state(vha); 28077ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) { 28087ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb147, 28097ec0effdSAtul Deshmukh "DMA engine not available. Fallback to rdmem-read.\n"); 28107ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 28117ec0effdSAtul Deshmukh } 28127ec0effdSAtul Deshmukh 28137ec0effdSAtul Deshmukh m_hdr = (void *)entry_hdr; 28147ec0effdSAtul Deshmukh 28157ec0effdSAtul Deshmukh rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev, 28167ec0effdSAtul Deshmukh ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL); 28177ec0effdSAtul Deshmukh if (!rdmem_buffer) { 28187ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb148, 28197ec0effdSAtul Deshmukh "Unable to allocate rdmem dma buffer\n"); 28207ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 28217ec0effdSAtul Deshmukh } 28227ec0effdSAtul Deshmukh 28237ec0effdSAtul Deshmukh /* Prepare pex-dma descriptor to be written to MS memory. */ 28247ec0effdSAtul Deshmukh /* dma-desc-cmd layout: 28257ec0effdSAtul Deshmukh * 0-3: dma-desc-cmd 0-3 28267ec0effdSAtul Deshmukh * 4-7: pcid function number 28277ec0effdSAtul Deshmukh * 8-15: dma-desc-cmd 8-15 28287ec0effdSAtul Deshmukh * dma_bus_addr: dma buffer address 28297ec0effdSAtul Deshmukh * cmd.read_data_size: amount of data-chunk to be read. 28307ec0effdSAtul Deshmukh */ 28317ec0effdSAtul Deshmukh dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f); 28327ec0effdSAtul Deshmukh dma_desc.cmd.dma_desc_cmd |= 28337ec0effdSAtul Deshmukh ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4); 28347ec0effdSAtul Deshmukh 28357ec0effdSAtul Deshmukh dma_desc.dma_bus_addr = rdmem_dma; 28367ec0effdSAtul Deshmukh dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE; 28377ec0effdSAtul Deshmukh read_size = 0; 28387ec0effdSAtul Deshmukh 28397ec0effdSAtul Deshmukh /* 28407ec0effdSAtul Deshmukh * Perform rdmem operation using pex-dma. 28417ec0effdSAtul Deshmukh * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE. 28427ec0effdSAtul Deshmukh */ 28437ec0effdSAtul Deshmukh while (read_size < m_hdr->read_data_size) { 28447ec0effdSAtul Deshmukh if (m_hdr->read_data_size - read_size < 28457ec0effdSAtul Deshmukh ISP8044_PEX_DMA_READ_SIZE) { 28467ec0effdSAtul Deshmukh chunk_size = (m_hdr->read_data_size - read_size); 28477ec0effdSAtul Deshmukh dma_desc.cmd.read_data_size = chunk_size; 28487ec0effdSAtul Deshmukh } 28497ec0effdSAtul Deshmukh 28507ec0effdSAtul Deshmukh dma_desc.src_addr = m_hdr->read_addr + read_size; 28517ec0effdSAtul Deshmukh 28527ec0effdSAtul Deshmukh /* Prepare: Write pex-dma descriptor to MS memory. */ 28537ec0effdSAtul Deshmukh rval = qla8044_ms_mem_write_128b(vha, 28547ec0effdSAtul Deshmukh m_hdr->desc_card_addr, (void *)&dma_desc, 28557ec0effdSAtul Deshmukh (sizeof(struct qla8044_pex_dma_descriptor)/16)); 28567ec0effdSAtul Deshmukh if (rval) { 28577ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb14a, 28587ec0effdSAtul Deshmukh "%s: Error writing rdmem-dma-init to MS !!!\n", 28597ec0effdSAtul Deshmukh __func__); 28607ec0effdSAtul Deshmukh goto error_exit; 28617ec0effdSAtul Deshmukh } 28627ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb14b, 28637ec0effdSAtul Deshmukh "%s: Dma-descriptor: Instruct for rdmem dma " 28647ec0effdSAtul Deshmukh "(chunk_size 0x%x).\n", __func__, chunk_size); 28657ec0effdSAtul Deshmukh 28667ec0effdSAtul Deshmukh /* Execute: Start pex-dma operation. */ 28677ec0effdSAtul Deshmukh rval = qla8044_start_pex_dma(vha, m_hdr); 28687ec0effdSAtul Deshmukh if (rval) 28697ec0effdSAtul Deshmukh goto error_exit; 28707ec0effdSAtul Deshmukh 28717ec0effdSAtul Deshmukh memcpy(data_ptr, rdmem_buffer, chunk_size); 28727ec0effdSAtul Deshmukh data_ptr += chunk_size; 28737ec0effdSAtul Deshmukh read_size += chunk_size; 28747ec0effdSAtul Deshmukh } 28757ec0effdSAtul Deshmukh 28767ec0effdSAtul Deshmukh *d_ptr = (void *)data_ptr; 28777ec0effdSAtul Deshmukh 28787ec0effdSAtul Deshmukh error_exit: 28797ec0effdSAtul Deshmukh if (rdmem_buffer) 28807ec0effdSAtul Deshmukh dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE, 28817ec0effdSAtul Deshmukh rdmem_buffer, rdmem_dma); 28827ec0effdSAtul Deshmukh 28837ec0effdSAtul Deshmukh return rval; 28847ec0effdSAtul Deshmukh } 28857ec0effdSAtul Deshmukh 28867ec0effdSAtul Deshmukh /* 28877ec0effdSAtul Deshmukh * 28887ec0effdSAtul Deshmukh * qla8044_collect_md_data - Retrieve firmware minidump data. 28897ec0effdSAtul Deshmukh * @ha: pointer to adapter structure 28907ec0effdSAtul Deshmukh **/ 28917ec0effdSAtul Deshmukh int 28927ec0effdSAtul Deshmukh qla8044_collect_md_data(struct scsi_qla_host *vha) 28937ec0effdSAtul Deshmukh { 28947ec0effdSAtul Deshmukh int num_entry_hdr = 0; 28957ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr; 28967ec0effdSAtul Deshmukh struct qla8044_minidump_template_hdr *tmplt_hdr; 28977ec0effdSAtul Deshmukh uint32_t *data_ptr; 28987ec0effdSAtul Deshmukh uint32_t data_collected = 0, f_capture_mask; 28997ec0effdSAtul Deshmukh int i, rval = QLA_FUNCTION_FAILED; 29007ec0effdSAtul Deshmukh uint64_t now; 29017ec0effdSAtul Deshmukh uint32_t timestamp, idc_control; 29027ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 29037ec0effdSAtul Deshmukh 29047ec0effdSAtul Deshmukh if (!ha->md_dump) { 29057ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb101, 29067ec0effdSAtul Deshmukh "%s(%ld) No buffer to dump\n", 29077ec0effdSAtul Deshmukh __func__, vha->host_no); 29087ec0effdSAtul Deshmukh return rval; 29097ec0effdSAtul Deshmukh } 29107ec0effdSAtul Deshmukh 29117ec0effdSAtul Deshmukh if (ha->fw_dumped) { 29127ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb10d, 29137ec0effdSAtul Deshmukh "Firmware has been previously dumped (%p) " 29147ec0effdSAtul Deshmukh "-- ignoring request.\n", ha->fw_dump); 29157ec0effdSAtul Deshmukh goto md_failed; 29167ec0effdSAtul Deshmukh } 29177ec0effdSAtul Deshmukh 29187ec0effdSAtul Deshmukh ha->fw_dumped = 0; 29197ec0effdSAtul Deshmukh 29207ec0effdSAtul Deshmukh if (!ha->md_tmplt_hdr || !ha->md_dump) { 29217ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb10e, 29227ec0effdSAtul Deshmukh "Memory not allocated for minidump capture\n"); 29237ec0effdSAtul Deshmukh goto md_failed; 29247ec0effdSAtul Deshmukh } 29257ec0effdSAtul Deshmukh 29267ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 29277ec0effdSAtul Deshmukh idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 29287ec0effdSAtul Deshmukh if (idc_control & GRACEFUL_RESET_BIT1) { 29297ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb112, 29307ec0effdSAtul Deshmukh "Forced reset from application, " 29317ec0effdSAtul Deshmukh "ignore minidump capture\n"); 29327ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, 29337ec0effdSAtul Deshmukh (idc_control & ~GRACEFUL_RESET_BIT1)); 29347ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 29357ec0effdSAtul Deshmukh 29367ec0effdSAtul Deshmukh goto md_failed; 29377ec0effdSAtul Deshmukh } 29387ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 29397ec0effdSAtul Deshmukh 29407ec0effdSAtul Deshmukh if (qla82xx_validate_template_chksum(vha)) { 29417ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb109, 29427ec0effdSAtul Deshmukh "Template checksum validation error\n"); 29437ec0effdSAtul Deshmukh goto md_failed; 29447ec0effdSAtul Deshmukh } 29457ec0effdSAtul Deshmukh 29467ec0effdSAtul Deshmukh tmplt_hdr = (struct qla8044_minidump_template_hdr *) 29477ec0effdSAtul Deshmukh ha->md_tmplt_hdr; 29487ec0effdSAtul Deshmukh data_ptr = (uint32_t *)((uint8_t *)ha->md_dump); 29497ec0effdSAtul Deshmukh num_entry_hdr = tmplt_hdr->num_of_entries; 29507ec0effdSAtul Deshmukh 29517ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb11a, 29527ec0effdSAtul Deshmukh "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level); 29537ec0effdSAtul Deshmukh 29547ec0effdSAtul Deshmukh f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF; 29557ec0effdSAtul Deshmukh 29567ec0effdSAtul Deshmukh /* Validate whether required debug level is set */ 29577ec0effdSAtul Deshmukh if ((f_capture_mask & 0x3) != 0x3) { 29587ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb10f, 29597ec0effdSAtul Deshmukh "Minimum required capture mask[0x%x] level not set\n", 29607ec0effdSAtul Deshmukh f_capture_mask); 29617ec0effdSAtul Deshmukh 29627ec0effdSAtul Deshmukh } 29637ec0effdSAtul Deshmukh tmplt_hdr->driver_capture_mask = ql2xmdcapmask; 29647ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb102, 29657ec0effdSAtul Deshmukh "[%s]: starting data ptr: %p\n", 29667ec0effdSAtul Deshmukh __func__, data_ptr); 29677ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb10b, 29687ec0effdSAtul Deshmukh "[%s]: no of entry headers in Template: 0x%x\n", 29697ec0effdSAtul Deshmukh __func__, num_entry_hdr); 29707ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb10c, 29717ec0effdSAtul Deshmukh "[%s]: Total_data_size 0x%x, %d obtained\n", 29727ec0effdSAtul Deshmukh __func__, ha->md_dump_size, ha->md_dump_size); 29737ec0effdSAtul Deshmukh 29747ec0effdSAtul Deshmukh /* Update current timestamp before taking dump */ 29757ec0effdSAtul Deshmukh now = get_jiffies_64(); 29767ec0effdSAtul Deshmukh timestamp = (u32)(jiffies_to_msecs(now) / 1000); 29777ec0effdSAtul Deshmukh tmplt_hdr->driver_timestamp = timestamp; 29787ec0effdSAtul Deshmukh 29797ec0effdSAtul Deshmukh entry_hdr = (struct qla8044_minidump_entry_hdr *) 29807ec0effdSAtul Deshmukh (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset); 29817ec0effdSAtul Deshmukh tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] = 29827ec0effdSAtul Deshmukh tmplt_hdr->ocm_window_reg[ha->portnum]; 29837ec0effdSAtul Deshmukh 29847ec0effdSAtul Deshmukh /* Walk through the entry headers - validate/perform required action */ 29857ec0effdSAtul Deshmukh for (i = 0; i < num_entry_hdr; i++) { 29867ec0effdSAtul Deshmukh if (data_collected > ha->md_dump_size) { 29877ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb103, 29887ec0effdSAtul Deshmukh "Data collected: [0x%x], " 29897ec0effdSAtul Deshmukh "Total Dump size: [0x%x]\n", 29907ec0effdSAtul Deshmukh data_collected, ha->md_dump_size); 29917ec0effdSAtul Deshmukh return rval; 29927ec0effdSAtul Deshmukh } 29937ec0effdSAtul Deshmukh 29947ec0effdSAtul Deshmukh if (!(entry_hdr->d_ctrl.entry_capture_mask & 29957ec0effdSAtul Deshmukh ql2xmdcapmask)) { 29967ec0effdSAtul Deshmukh entry_hdr->d_ctrl.driver_flags |= 29977ec0effdSAtul Deshmukh QLA82XX_DBG_SKIPPED_FLAG; 29987ec0effdSAtul Deshmukh goto skip_nxt_entry; 29997ec0effdSAtul Deshmukh } 30007ec0effdSAtul Deshmukh 30017ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb104, 30027ec0effdSAtul Deshmukh "Data collected: [0x%x], Dump size left:[0x%x]\n", 30037ec0effdSAtul Deshmukh data_collected, 30047ec0effdSAtul Deshmukh (ha->md_dump_size - data_collected)); 30057ec0effdSAtul Deshmukh 30067ec0effdSAtul Deshmukh /* Decode the entry type and take required action to capture 30077ec0effdSAtul Deshmukh * debug data 30087ec0effdSAtul Deshmukh */ 30097ec0effdSAtul Deshmukh switch (entry_hdr->entry_type) { 30107ec0effdSAtul Deshmukh case QLA82XX_RDEND: 30117ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, entry_hdr, i); 30127ec0effdSAtul Deshmukh break; 30137ec0effdSAtul Deshmukh case QLA82XX_CNTRL: 30147ec0effdSAtul Deshmukh rval = qla8044_minidump_process_control(vha, 30157ec0effdSAtul Deshmukh entry_hdr); 30167ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) { 30177ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, entry_hdr, i); 30187ec0effdSAtul Deshmukh goto md_failed; 30197ec0effdSAtul Deshmukh } 30207ec0effdSAtul Deshmukh break; 30217ec0effdSAtul Deshmukh case QLA82XX_RDCRB: 30227ec0effdSAtul Deshmukh qla8044_minidump_process_rdcrb(vha, 30237ec0effdSAtul Deshmukh entry_hdr, &data_ptr); 30247ec0effdSAtul Deshmukh break; 30257ec0effdSAtul Deshmukh case QLA82XX_RDMEM: 30267ec0effdSAtul Deshmukh rval = qla8044_minidump_pex_dma_read(vha, 30277ec0effdSAtul Deshmukh entry_hdr, &data_ptr); 30287ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) { 30297ec0effdSAtul Deshmukh rval = qla8044_minidump_process_rdmem(vha, 30307ec0effdSAtul Deshmukh entry_hdr, &data_ptr); 30317ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) { 30327ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, 30337ec0effdSAtul Deshmukh entry_hdr, i); 30347ec0effdSAtul Deshmukh goto md_failed; 30357ec0effdSAtul Deshmukh } 30367ec0effdSAtul Deshmukh } 30377ec0effdSAtul Deshmukh break; 30387ec0effdSAtul Deshmukh case QLA82XX_BOARD: 30397ec0effdSAtul Deshmukh case QLA82XX_RDROM: 30407ec0effdSAtul Deshmukh rval = qla8044_minidump_process_rdrom(vha, 30417ec0effdSAtul Deshmukh entry_hdr, &data_ptr); 30427ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) { 30437ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, 30447ec0effdSAtul Deshmukh entry_hdr, i); 30457ec0effdSAtul Deshmukh } 30467ec0effdSAtul Deshmukh break; 30477ec0effdSAtul Deshmukh case QLA82XX_L2DTG: 30487ec0effdSAtul Deshmukh case QLA82XX_L2ITG: 30497ec0effdSAtul Deshmukh case QLA82XX_L2DAT: 30507ec0effdSAtul Deshmukh case QLA82XX_L2INS: 30517ec0effdSAtul Deshmukh rval = qla8044_minidump_process_l2tag(vha, 30527ec0effdSAtul Deshmukh entry_hdr, &data_ptr); 30537ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) { 30547ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, entry_hdr, i); 30557ec0effdSAtul Deshmukh goto md_failed; 30567ec0effdSAtul Deshmukh } 30577ec0effdSAtul Deshmukh break; 30587ec0effdSAtul Deshmukh case QLA8044_L1DTG: 30597ec0effdSAtul Deshmukh case QLA8044_L1ITG: 30607ec0effdSAtul Deshmukh case QLA82XX_L1DAT: 30617ec0effdSAtul Deshmukh case QLA82XX_L1INS: 30627ec0effdSAtul Deshmukh qla8044_minidump_process_l1cache(vha, 30637ec0effdSAtul Deshmukh entry_hdr, &data_ptr); 30647ec0effdSAtul Deshmukh break; 30657ec0effdSAtul Deshmukh case QLA82XX_RDOCM: 30667ec0effdSAtul Deshmukh qla8044_minidump_process_rdocm(vha, 30677ec0effdSAtul Deshmukh entry_hdr, &data_ptr); 30687ec0effdSAtul Deshmukh break; 30697ec0effdSAtul Deshmukh case QLA82XX_RDMUX: 30707ec0effdSAtul Deshmukh qla8044_minidump_process_rdmux(vha, 30717ec0effdSAtul Deshmukh entry_hdr, &data_ptr); 30727ec0effdSAtul Deshmukh break; 30737ec0effdSAtul Deshmukh case QLA82XX_QUEUE: 30747ec0effdSAtul Deshmukh qla8044_minidump_process_queue(vha, 30757ec0effdSAtul Deshmukh entry_hdr, &data_ptr); 30767ec0effdSAtul Deshmukh break; 30777ec0effdSAtul Deshmukh case QLA8044_POLLRD: 30787ec0effdSAtul Deshmukh rval = qla8044_minidump_process_pollrd(vha, 30797ec0effdSAtul Deshmukh entry_hdr, &data_ptr); 30807ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) 30817ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, entry_hdr, i); 30827ec0effdSAtul Deshmukh break; 30837ec0effdSAtul Deshmukh case QLA8044_RDMUX2: 30847ec0effdSAtul Deshmukh qla8044_minidump_process_rdmux2(vha, 30857ec0effdSAtul Deshmukh entry_hdr, &data_ptr); 30867ec0effdSAtul Deshmukh break; 30877ec0effdSAtul Deshmukh case QLA8044_POLLRDMWR: 30887ec0effdSAtul Deshmukh rval = qla8044_minidump_process_pollrdmwr(vha, 30897ec0effdSAtul Deshmukh entry_hdr, &data_ptr); 30907ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) 30917ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, entry_hdr, i); 30927ec0effdSAtul Deshmukh break; 30937ec0effdSAtul Deshmukh case QLA82XX_RDNOP: 30947ec0effdSAtul Deshmukh default: 30957ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, entry_hdr, i); 30967ec0effdSAtul Deshmukh break; 30977ec0effdSAtul Deshmukh } 30987ec0effdSAtul Deshmukh 30997ec0effdSAtul Deshmukh data_collected = (uint8_t *)data_ptr - 31007ec0effdSAtul Deshmukh (uint8_t *)((uint8_t *)ha->md_dump); 31017ec0effdSAtul Deshmukh skip_nxt_entry: 31027ec0effdSAtul Deshmukh /* 31037ec0effdSAtul Deshmukh * next entry in the template 31047ec0effdSAtul Deshmukh */ 31057ec0effdSAtul Deshmukh entry_hdr = (struct qla8044_minidump_entry_hdr *) 31067ec0effdSAtul Deshmukh (((uint8_t *)entry_hdr) + entry_hdr->entry_size); 31077ec0effdSAtul Deshmukh } 31087ec0effdSAtul Deshmukh 31097ec0effdSAtul Deshmukh if (data_collected != ha->md_dump_size) { 31107ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb105, 31117ec0effdSAtul Deshmukh "Dump data mismatch: Data collected: " 31127ec0effdSAtul Deshmukh "[0x%x], total_data_size:[0x%x]\n", 31137ec0effdSAtul Deshmukh data_collected, ha->md_dump_size); 31147ec0effdSAtul Deshmukh goto md_failed; 31157ec0effdSAtul Deshmukh } 31167ec0effdSAtul Deshmukh 31177ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb110, 31187ec0effdSAtul Deshmukh "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n", 31197ec0effdSAtul Deshmukh vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump); 31207ec0effdSAtul Deshmukh ha->fw_dumped = 1; 31217ec0effdSAtul Deshmukh qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP); 31227ec0effdSAtul Deshmukh 31237ec0effdSAtul Deshmukh 31247ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb106, 31257ec0effdSAtul Deshmukh "Leaving fn: %s Last entry: 0x%x\n", 31267ec0effdSAtul Deshmukh __func__, i); 31277ec0effdSAtul Deshmukh md_failed: 31287ec0effdSAtul Deshmukh return rval; 31297ec0effdSAtul Deshmukh } 31307ec0effdSAtul Deshmukh 31317ec0effdSAtul Deshmukh void 31327ec0effdSAtul Deshmukh qla8044_get_minidump(struct scsi_qla_host *vha) 31337ec0effdSAtul Deshmukh { 31347ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 31357ec0effdSAtul Deshmukh 31367ec0effdSAtul Deshmukh if (!qla8044_collect_md_data(vha)) { 31377ec0effdSAtul Deshmukh ha->fw_dumped = 1; 31387ec0effdSAtul Deshmukh } else { 31397ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0db, 31407ec0effdSAtul Deshmukh "%s: Unable to collect minidump\n", 31417ec0effdSAtul Deshmukh __func__); 31427ec0effdSAtul Deshmukh } 31437ec0effdSAtul Deshmukh } 31447ec0effdSAtul Deshmukh 31457ec0effdSAtul Deshmukh static int 31467ec0effdSAtul Deshmukh qla8044_poll_flash_status_reg(struct scsi_qla_host *vha) 31477ec0effdSAtul Deshmukh { 31487ec0effdSAtul Deshmukh uint32_t flash_status; 31497ec0effdSAtul Deshmukh int retries = QLA8044_FLASH_READ_RETRY_COUNT; 31507ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 31517ec0effdSAtul Deshmukh 31527ec0effdSAtul Deshmukh while (retries--) { 31537ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS, 31547ec0effdSAtul Deshmukh &flash_status); 31557ec0effdSAtul Deshmukh if (ret_val) { 31567ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb120, 31577ec0effdSAtul Deshmukh "%s: Failed to read FLASH_STATUS reg.\n", 31587ec0effdSAtul Deshmukh __func__); 31597ec0effdSAtul Deshmukh break; 31607ec0effdSAtul Deshmukh } 31617ec0effdSAtul Deshmukh if ((flash_status & QLA8044_FLASH_STATUS_READY) == 31627ec0effdSAtul Deshmukh QLA8044_FLASH_STATUS_READY) 31637ec0effdSAtul Deshmukh break; 31647ec0effdSAtul Deshmukh msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY); 31657ec0effdSAtul Deshmukh } 31667ec0effdSAtul Deshmukh 31677ec0effdSAtul Deshmukh if (!retries) 31687ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED; 31697ec0effdSAtul Deshmukh 31707ec0effdSAtul Deshmukh return ret_val; 31717ec0effdSAtul Deshmukh } 31727ec0effdSAtul Deshmukh 31737ec0effdSAtul Deshmukh static int 31747ec0effdSAtul Deshmukh qla8044_write_flash_status_reg(struct scsi_qla_host *vha, 31757ec0effdSAtul Deshmukh uint32_t data) 31767ec0effdSAtul Deshmukh { 31777ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 31787ec0effdSAtul Deshmukh uint32_t cmd; 31797ec0effdSAtul Deshmukh 31807ec0effdSAtul Deshmukh cmd = vha->hw->fdt_wrt_sts_reg_cmd; 31817ec0effdSAtul Deshmukh 31827ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 31837ec0effdSAtul Deshmukh QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd); 31847ec0effdSAtul Deshmukh if (ret_val) { 31857ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb125, 31867ec0effdSAtul Deshmukh "%s: Failed to write to FLASH_ADDR.\n", __func__); 31877ec0effdSAtul Deshmukh goto exit_func; 31887ec0effdSAtul Deshmukh } 31897ec0effdSAtul Deshmukh 31907ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data); 31917ec0effdSAtul Deshmukh if (ret_val) { 31927ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb126, 31937ec0effdSAtul Deshmukh "%s: Failed to write to FLASH_WRDATA.\n", __func__); 31947ec0effdSAtul Deshmukh goto exit_func; 31957ec0effdSAtul Deshmukh } 31967ec0effdSAtul Deshmukh 31977ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 31987ec0effdSAtul Deshmukh QLA8044_FLASH_SECOND_ERASE_MS_VAL); 31997ec0effdSAtul Deshmukh if (ret_val) { 32007ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb127, 32017ec0effdSAtul Deshmukh "%s: Failed to write to FLASH_CONTROL.\n", __func__); 32027ec0effdSAtul Deshmukh goto exit_func; 32037ec0effdSAtul Deshmukh } 32047ec0effdSAtul Deshmukh 32057ec0effdSAtul Deshmukh ret_val = qla8044_poll_flash_status_reg(vha); 32067ec0effdSAtul Deshmukh if (ret_val) 32077ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb128, 32087ec0effdSAtul Deshmukh "%s: Error polling flash status reg.\n", __func__); 32097ec0effdSAtul Deshmukh 32107ec0effdSAtul Deshmukh exit_func: 32117ec0effdSAtul Deshmukh return ret_val; 32127ec0effdSAtul Deshmukh } 32137ec0effdSAtul Deshmukh 32147ec0effdSAtul Deshmukh /* 32157ec0effdSAtul Deshmukh * This function assumes that the flash lock is held. 32167ec0effdSAtul Deshmukh */ 32177ec0effdSAtul Deshmukh static int 32187ec0effdSAtul Deshmukh qla8044_unprotect_flash(scsi_qla_host_t *vha) 32197ec0effdSAtul Deshmukh { 32207ec0effdSAtul Deshmukh int ret_val; 32217ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 32227ec0effdSAtul Deshmukh 32237ec0effdSAtul Deshmukh ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable); 32247ec0effdSAtul Deshmukh if (ret_val) 32257ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb139, 32267ec0effdSAtul Deshmukh "%s: Write flash status failed.\n", __func__); 32277ec0effdSAtul Deshmukh 32287ec0effdSAtul Deshmukh return ret_val; 32297ec0effdSAtul Deshmukh } 32307ec0effdSAtul Deshmukh 32317ec0effdSAtul Deshmukh /* 32327ec0effdSAtul Deshmukh * This function assumes that the flash lock is held. 32337ec0effdSAtul Deshmukh */ 32347ec0effdSAtul Deshmukh static int 32357ec0effdSAtul Deshmukh qla8044_protect_flash(scsi_qla_host_t *vha) 32367ec0effdSAtul Deshmukh { 32377ec0effdSAtul Deshmukh int ret_val; 32387ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 32397ec0effdSAtul Deshmukh 32407ec0effdSAtul Deshmukh ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable); 32417ec0effdSAtul Deshmukh if (ret_val) 32427ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb13b, 32437ec0effdSAtul Deshmukh "%s: Write flash status failed.\n", __func__); 32447ec0effdSAtul Deshmukh 32457ec0effdSAtul Deshmukh return ret_val; 32467ec0effdSAtul Deshmukh } 32477ec0effdSAtul Deshmukh 32487ec0effdSAtul Deshmukh 32497ec0effdSAtul Deshmukh static int 32507ec0effdSAtul Deshmukh qla8044_erase_flash_sector(struct scsi_qla_host *vha, 32517ec0effdSAtul Deshmukh uint32_t sector_start_addr) 32527ec0effdSAtul Deshmukh { 32537ec0effdSAtul Deshmukh uint32_t reversed_addr; 32547ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 32557ec0effdSAtul Deshmukh 32567ec0effdSAtul Deshmukh ret_val = qla8044_poll_flash_status_reg(vha); 32577ec0effdSAtul Deshmukh if (ret_val) { 32587ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb12e, 32597ec0effdSAtul Deshmukh "%s: Poll flash status after erase failed..\n", __func__); 32607ec0effdSAtul Deshmukh } 32617ec0effdSAtul Deshmukh 32627ec0effdSAtul Deshmukh reversed_addr = (((sector_start_addr & 0xFF) << 16) | 32637ec0effdSAtul Deshmukh (sector_start_addr & 0xFF00) | 32647ec0effdSAtul Deshmukh ((sector_start_addr & 0xFF0000) >> 16)); 32657ec0effdSAtul Deshmukh 32667ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, 32677ec0effdSAtul Deshmukh QLA8044_FLASH_WRDATA, reversed_addr); 32687ec0effdSAtul Deshmukh if (ret_val) { 32697ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb12f, 32707ec0effdSAtul Deshmukh "%s: Failed to write to FLASH_WRDATA.\n", __func__); 32717ec0effdSAtul Deshmukh } 32727ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 32737ec0effdSAtul Deshmukh QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd); 32747ec0effdSAtul Deshmukh if (ret_val) { 32757ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb130, 32767ec0effdSAtul Deshmukh "%s: Failed to write to FLASH_ADDR.\n", __func__); 32777ec0effdSAtul Deshmukh } 32787ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 32797ec0effdSAtul Deshmukh QLA8044_FLASH_LAST_ERASE_MS_VAL); 32807ec0effdSAtul Deshmukh if (ret_val) { 32817ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb131, 32827ec0effdSAtul Deshmukh "%s: Failed write to FLASH_CONTROL.\n", __func__); 32837ec0effdSAtul Deshmukh } 32847ec0effdSAtul Deshmukh ret_val = qla8044_poll_flash_status_reg(vha); 32857ec0effdSAtul Deshmukh if (ret_val) { 32867ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb132, 32877ec0effdSAtul Deshmukh "%s: Poll flash status failed.\n", __func__); 32887ec0effdSAtul Deshmukh } 32897ec0effdSAtul Deshmukh 32907ec0effdSAtul Deshmukh 32917ec0effdSAtul Deshmukh return ret_val; 32927ec0effdSAtul Deshmukh } 32937ec0effdSAtul Deshmukh 32947ec0effdSAtul Deshmukh /* 32957ec0effdSAtul Deshmukh * qla8044_flash_write_u32 - Write data to flash 32967ec0effdSAtul Deshmukh * 32977ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure 32987ec0effdSAtul Deshmukh * addr : Flash address to write to 32997ec0effdSAtul Deshmukh * p_data : Data to be written 33007ec0effdSAtul Deshmukh * 33017ec0effdSAtul Deshmukh * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED 33027ec0effdSAtul Deshmukh * 33037ec0effdSAtul Deshmukh * NOTE: Lock should be held on entry 33047ec0effdSAtul Deshmukh */ 33057ec0effdSAtul Deshmukh static int 33067ec0effdSAtul Deshmukh qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr, 33077ec0effdSAtul Deshmukh uint32_t *p_data) 33087ec0effdSAtul Deshmukh { 33097ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS; 33107ec0effdSAtul Deshmukh 33117ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 33127ec0effdSAtul Deshmukh 0x00800000 | (addr >> 2)); 33137ec0effdSAtul Deshmukh if (ret_val) { 33147ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb134, 33157ec0effdSAtul Deshmukh "%s: Failed write to FLASH_ADDR.\n", __func__); 33167ec0effdSAtul Deshmukh goto exit_func; 33177ec0effdSAtul Deshmukh } 33187ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data); 33197ec0effdSAtul Deshmukh if (ret_val) { 33207ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb135, 33217ec0effdSAtul Deshmukh "%s: Failed write to FLASH_WRDATA.\n", __func__); 33227ec0effdSAtul Deshmukh goto exit_func; 33237ec0effdSAtul Deshmukh } 33247ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D); 33257ec0effdSAtul Deshmukh if (ret_val) { 33267ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb136, 33277ec0effdSAtul Deshmukh "%s: Failed write to FLASH_CONTROL.\n", __func__); 33287ec0effdSAtul Deshmukh goto exit_func; 33297ec0effdSAtul Deshmukh } 33307ec0effdSAtul Deshmukh ret_val = qla8044_poll_flash_status_reg(vha); 33317ec0effdSAtul Deshmukh if (ret_val) { 33327ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb137, 33337ec0effdSAtul Deshmukh "%s: Poll flash status failed.\n", __func__); 33347ec0effdSAtul Deshmukh } 33357ec0effdSAtul Deshmukh 33367ec0effdSAtul Deshmukh exit_func: 33377ec0effdSAtul Deshmukh return ret_val; 33387ec0effdSAtul Deshmukh } 33397ec0effdSAtul Deshmukh 33407ec0effdSAtul Deshmukh static int 33417ec0effdSAtul Deshmukh qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr, 33427ec0effdSAtul Deshmukh uint32_t faddr, uint32_t dwords) 33437ec0effdSAtul Deshmukh { 33447ec0effdSAtul Deshmukh int ret = QLA_FUNCTION_FAILED; 33457ec0effdSAtul Deshmukh uint32_t spi_val; 33467ec0effdSAtul Deshmukh 33477ec0effdSAtul Deshmukh if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS || 33487ec0effdSAtul Deshmukh dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) { 33497ec0effdSAtul Deshmukh ql_dbg(ql_dbg_user, vha, 0xb123, 33507ec0effdSAtul Deshmukh "Got unsupported dwords = 0x%x.\n", 33517ec0effdSAtul Deshmukh dwords); 33527ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 33537ec0effdSAtul Deshmukh } 33547ec0effdSAtul Deshmukh 33557ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val); 33567ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, 33577ec0effdSAtul Deshmukh spi_val | QLA8044_FLASH_SPI_CTL); 33587ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 33597ec0effdSAtul Deshmukh QLA8044_FLASH_FIRST_TEMP_VAL); 33607ec0effdSAtul Deshmukh 33617ec0effdSAtul Deshmukh /* First DWORD write to FLASH_WRDATA */ 33627ec0effdSAtul Deshmukh ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, 33637ec0effdSAtul Deshmukh *dwptr++); 33647ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 33657ec0effdSAtul Deshmukh QLA8044_FLASH_FIRST_MS_PATTERN); 33667ec0effdSAtul Deshmukh 33677ec0effdSAtul Deshmukh ret = qla8044_poll_flash_status_reg(vha); 33687ec0effdSAtul Deshmukh if (ret) { 33697ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb124, 33707ec0effdSAtul Deshmukh "%s: Failed.\n", __func__); 33717ec0effdSAtul Deshmukh goto exit_func; 33727ec0effdSAtul Deshmukh } 33737ec0effdSAtul Deshmukh 33747ec0effdSAtul Deshmukh dwords--; 33757ec0effdSAtul Deshmukh 33767ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 33777ec0effdSAtul Deshmukh QLA8044_FLASH_SECOND_TEMP_VAL); 33787ec0effdSAtul Deshmukh 33797ec0effdSAtul Deshmukh 33807ec0effdSAtul Deshmukh /* Second to N-1 DWORDS writes */ 33817ec0effdSAtul Deshmukh while (dwords != 1) { 33827ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++); 33837ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 33847ec0effdSAtul Deshmukh QLA8044_FLASH_SECOND_MS_PATTERN); 33857ec0effdSAtul Deshmukh ret = qla8044_poll_flash_status_reg(vha); 33867ec0effdSAtul Deshmukh if (ret) { 33877ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb129, 33887ec0effdSAtul Deshmukh "%s: Failed.\n", __func__); 33897ec0effdSAtul Deshmukh goto exit_func; 33907ec0effdSAtul Deshmukh } 33917ec0effdSAtul Deshmukh dwords--; 33927ec0effdSAtul Deshmukh } 33937ec0effdSAtul Deshmukh 33947ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR, 33957ec0effdSAtul Deshmukh QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2)); 33967ec0effdSAtul Deshmukh 33977ec0effdSAtul Deshmukh /* Last DWORD write */ 33987ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++); 33997ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 34007ec0effdSAtul Deshmukh QLA8044_FLASH_LAST_MS_PATTERN); 34017ec0effdSAtul Deshmukh ret = qla8044_poll_flash_status_reg(vha); 34027ec0effdSAtul Deshmukh if (ret) { 34037ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb12a, 34047ec0effdSAtul Deshmukh "%s: Failed.\n", __func__); 34057ec0effdSAtul Deshmukh goto exit_func; 34067ec0effdSAtul Deshmukh } 34077ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val); 34087ec0effdSAtul Deshmukh 34097ec0effdSAtul Deshmukh if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) { 34107ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb12b, 34117ec0effdSAtul Deshmukh "%s: Failed.\n", __func__); 34127ec0effdSAtul Deshmukh spi_val = 0; 34137ec0effdSAtul Deshmukh /* Operation failed, clear error bit. */ 34147ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, 34157ec0effdSAtul Deshmukh &spi_val); 34167ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, 34177ec0effdSAtul Deshmukh spi_val | QLA8044_FLASH_SPI_CTL); 34187ec0effdSAtul Deshmukh } 34197ec0effdSAtul Deshmukh exit_func: 34207ec0effdSAtul Deshmukh return ret; 34217ec0effdSAtul Deshmukh } 34227ec0effdSAtul Deshmukh 34237ec0effdSAtul Deshmukh static int 34247ec0effdSAtul Deshmukh qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr, 34257ec0effdSAtul Deshmukh uint32_t faddr, uint32_t dwords) 34267ec0effdSAtul Deshmukh { 34277ec0effdSAtul Deshmukh int ret = QLA_FUNCTION_FAILED; 34287ec0effdSAtul Deshmukh uint32_t liter; 34297ec0effdSAtul Deshmukh 34307ec0effdSAtul Deshmukh for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) { 34317ec0effdSAtul Deshmukh ret = qla8044_flash_write_u32(vha, faddr, dwptr); 34327ec0effdSAtul Deshmukh if (ret) { 34337ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb141, 34347ec0effdSAtul Deshmukh "%s: flash address=%x data=%x.\n", __func__, 34357ec0effdSAtul Deshmukh faddr, *dwptr); 34367ec0effdSAtul Deshmukh break; 34377ec0effdSAtul Deshmukh } 34387ec0effdSAtul Deshmukh } 34397ec0effdSAtul Deshmukh 34407ec0effdSAtul Deshmukh return ret; 34417ec0effdSAtul Deshmukh } 34427ec0effdSAtul Deshmukh 34437ec0effdSAtul Deshmukh int 34447ec0effdSAtul Deshmukh qla8044_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf, 34457ec0effdSAtul Deshmukh uint32_t offset, uint32_t length) 34467ec0effdSAtul Deshmukh { 34477ec0effdSAtul Deshmukh int rval = QLA_FUNCTION_FAILED, i, burst_iter_count; 34487ec0effdSAtul Deshmukh int dword_count, erase_sec_count; 34497ec0effdSAtul Deshmukh uint32_t erase_offset; 34507ec0effdSAtul Deshmukh uint8_t *p_cache, *p_src; 34517ec0effdSAtul Deshmukh 34527ec0effdSAtul Deshmukh erase_offset = offset; 34537ec0effdSAtul Deshmukh 34547ec0effdSAtul Deshmukh p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL); 34557ec0effdSAtul Deshmukh if (!p_cache) 34567ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED; 34577ec0effdSAtul Deshmukh 34587ec0effdSAtul Deshmukh memcpy(p_cache, buf, length); 34597ec0effdSAtul Deshmukh p_src = p_cache; 34607ec0effdSAtul Deshmukh dword_count = length / sizeof(uint32_t); 34617ec0effdSAtul Deshmukh /* Since the offset and legth are sector aligned, it will be always 34627ec0effdSAtul Deshmukh * multiple of burst_iter_count (64) 34637ec0effdSAtul Deshmukh */ 34647ec0effdSAtul Deshmukh burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS; 34657ec0effdSAtul Deshmukh erase_sec_count = length / QLA8044_SECTOR_SIZE; 34667ec0effdSAtul Deshmukh 34677ec0effdSAtul Deshmukh /* Suspend HBA. */ 34687ec0effdSAtul Deshmukh scsi_block_requests(vha->host); 34697ec0effdSAtul Deshmukh /* Lock and enable write for whole operation. */ 34707ec0effdSAtul Deshmukh qla8044_flash_lock(vha); 34717ec0effdSAtul Deshmukh qla8044_unprotect_flash(vha); 34727ec0effdSAtul Deshmukh 34737ec0effdSAtul Deshmukh /* Erasing the sectors */ 34747ec0effdSAtul Deshmukh for (i = 0; i < erase_sec_count; i++) { 34757ec0effdSAtul Deshmukh rval = qla8044_erase_flash_sector(vha, erase_offset); 34767ec0effdSAtul Deshmukh ql_dbg(ql_dbg_user, vha, 0xb138, 34777ec0effdSAtul Deshmukh "Done erase of sector=0x%x.\n", 34787ec0effdSAtul Deshmukh erase_offset); 34797ec0effdSAtul Deshmukh if (rval) { 34807ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb121, 34817ec0effdSAtul Deshmukh "Failed to erase the sector having address: " 34827ec0effdSAtul Deshmukh "0x%x.\n", erase_offset); 34837ec0effdSAtul Deshmukh goto out; 34847ec0effdSAtul Deshmukh } 34857ec0effdSAtul Deshmukh erase_offset += QLA8044_SECTOR_SIZE; 34867ec0effdSAtul Deshmukh } 34877ec0effdSAtul Deshmukh ql_dbg(ql_dbg_user, vha, 0xb139, 34887ec0effdSAtul Deshmukh "Got write for addr = 0x%x length=0x%x.\n", 34897ec0effdSAtul Deshmukh offset, length); 34907ec0effdSAtul Deshmukh 34917ec0effdSAtul Deshmukh for (i = 0; i < burst_iter_count; i++) { 34927ec0effdSAtul Deshmukh 34937ec0effdSAtul Deshmukh /* Go with write. */ 34947ec0effdSAtul Deshmukh rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src, 34957ec0effdSAtul Deshmukh offset, QLA8044_MAX_OPTROM_BURST_DWORDS); 34967ec0effdSAtul Deshmukh if (rval) { 34977ec0effdSAtul Deshmukh /* Buffer Mode failed skip to dword mode */ 34987ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb122, 34997ec0effdSAtul Deshmukh "Failed to write flash in buffer mode, " 35007ec0effdSAtul Deshmukh "Reverting to slow-write.\n"); 35017ec0effdSAtul Deshmukh rval = qla8044_write_flash_dword_mode(vha, 35027ec0effdSAtul Deshmukh (uint32_t *)p_src, offset, 35037ec0effdSAtul Deshmukh QLA8044_MAX_OPTROM_BURST_DWORDS); 35047ec0effdSAtul Deshmukh } 35057ec0effdSAtul Deshmukh p_src += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS; 35067ec0effdSAtul Deshmukh offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS; 35077ec0effdSAtul Deshmukh } 35087ec0effdSAtul Deshmukh ql_dbg(ql_dbg_user, vha, 0xb133, 35097ec0effdSAtul Deshmukh "Done writing.\n"); 35107ec0effdSAtul Deshmukh 35117ec0effdSAtul Deshmukh out: 35127ec0effdSAtul Deshmukh qla8044_protect_flash(vha); 35137ec0effdSAtul Deshmukh qla8044_flash_unlock(vha); 35147ec0effdSAtul Deshmukh scsi_unblock_requests(vha->host); 35157ec0effdSAtul Deshmukh kfree(p_cache); 35167ec0effdSAtul Deshmukh 35177ec0effdSAtul Deshmukh return rval; 35187ec0effdSAtul Deshmukh } 35197ec0effdSAtul Deshmukh 35207ec0effdSAtul Deshmukh #define LEG_INT_PTR_B31 (1 << 31) 35217ec0effdSAtul Deshmukh #define LEG_INT_PTR_B30 (1 << 30) 35227ec0effdSAtul Deshmukh #define PF_BITS_MASK (0xF << 16) 35237ec0effdSAtul Deshmukh /** 35247ec0effdSAtul Deshmukh * qla8044_intr_handler() - Process interrupts for the ISP8044 35257ec0effdSAtul Deshmukh * @irq: 35267ec0effdSAtul Deshmukh * @dev_id: SCSI driver HA context 35277ec0effdSAtul Deshmukh * 35287ec0effdSAtul Deshmukh * Called by system whenever the host adapter generates an interrupt. 35297ec0effdSAtul Deshmukh * 35307ec0effdSAtul Deshmukh * Returns handled flag. 35317ec0effdSAtul Deshmukh */ 35327ec0effdSAtul Deshmukh irqreturn_t 35337ec0effdSAtul Deshmukh qla8044_intr_handler(int irq, void *dev_id) 35347ec0effdSAtul Deshmukh { 35357ec0effdSAtul Deshmukh scsi_qla_host_t *vha; 35367ec0effdSAtul Deshmukh struct qla_hw_data *ha; 35377ec0effdSAtul Deshmukh struct rsp_que *rsp; 35387ec0effdSAtul Deshmukh struct device_reg_82xx __iomem *reg; 35397ec0effdSAtul Deshmukh int status = 0; 35407ec0effdSAtul Deshmukh unsigned long flags; 35417ec0effdSAtul Deshmukh unsigned long iter; 35427ec0effdSAtul Deshmukh uint32_t stat; 35437ec0effdSAtul Deshmukh uint16_t mb[4]; 35447ec0effdSAtul Deshmukh uint32_t leg_int_ptr = 0, pf_bit; 35457ec0effdSAtul Deshmukh 35467ec0effdSAtul Deshmukh rsp = (struct rsp_que *) dev_id; 35477ec0effdSAtul Deshmukh if (!rsp) { 35487ec0effdSAtul Deshmukh ql_log(ql_log_info, NULL, 0xb143, 35497ec0effdSAtul Deshmukh "%s(): NULL response queue pointer\n", __func__); 35507ec0effdSAtul Deshmukh return IRQ_NONE; 35517ec0effdSAtul Deshmukh } 35527ec0effdSAtul Deshmukh ha = rsp->hw; 35537ec0effdSAtul Deshmukh vha = pci_get_drvdata(ha->pdev); 35547ec0effdSAtul Deshmukh 35557ec0effdSAtul Deshmukh if (unlikely(pci_channel_offline(ha->pdev))) 35567ec0effdSAtul Deshmukh return IRQ_HANDLED; 35577ec0effdSAtul Deshmukh 35587ec0effdSAtul Deshmukh leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET); 35597ec0effdSAtul Deshmukh 35607ec0effdSAtul Deshmukh /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */ 35617ec0effdSAtul Deshmukh if (!(leg_int_ptr & (LEG_INT_PTR_B31))) { 35627ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb144, 35637ec0effdSAtul Deshmukh "%s: Legacy Interrupt Bit 31 not set, " 35647ec0effdSAtul Deshmukh "spurious interrupt!\n", __func__); 35657ec0effdSAtul Deshmukh return IRQ_NONE; 35667ec0effdSAtul Deshmukh } 35677ec0effdSAtul Deshmukh 35687ec0effdSAtul Deshmukh pf_bit = ha->portnum << 16; 35697ec0effdSAtul Deshmukh /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */ 35707ec0effdSAtul Deshmukh if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) { 35717ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb145, 35727ec0effdSAtul Deshmukh "%s: Incorrect function ID 0x%x in " 35737ec0effdSAtul Deshmukh "legacy interrupt register, " 35747ec0effdSAtul Deshmukh "ha->pf_bit = 0x%x\n", __func__, 35757ec0effdSAtul Deshmukh (leg_int_ptr & (PF_BITS_MASK)), pf_bit); 35767ec0effdSAtul Deshmukh return IRQ_NONE; 35777ec0effdSAtul Deshmukh } 35787ec0effdSAtul Deshmukh 35797ec0effdSAtul Deshmukh /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger 35807ec0effdSAtul Deshmukh * Control register and poll till Legacy Interrupt Pointer register 35817ec0effdSAtul Deshmukh * bit32 is 0. 35827ec0effdSAtul Deshmukh */ 35837ec0effdSAtul Deshmukh qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0); 35847ec0effdSAtul Deshmukh do { 35857ec0effdSAtul Deshmukh leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET); 35867ec0effdSAtul Deshmukh if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) 35877ec0effdSAtul Deshmukh break; 35887ec0effdSAtul Deshmukh } while (leg_int_ptr & (LEG_INT_PTR_B30)); 35897ec0effdSAtul Deshmukh 35907ec0effdSAtul Deshmukh reg = &ha->iobase->isp82; 35917ec0effdSAtul Deshmukh spin_lock_irqsave(&ha->hardware_lock, flags); 35927ec0effdSAtul Deshmukh for (iter = 1; iter--; ) { 35937ec0effdSAtul Deshmukh 35947ec0effdSAtul Deshmukh if (RD_REG_DWORD(®->host_int)) { 35957ec0effdSAtul Deshmukh stat = RD_REG_DWORD(®->host_status); 35967ec0effdSAtul Deshmukh if ((stat & HSRX_RISC_INT) == 0) 35977ec0effdSAtul Deshmukh break; 35987ec0effdSAtul Deshmukh 35997ec0effdSAtul Deshmukh switch (stat & 0xff) { 36007ec0effdSAtul Deshmukh case 0x1: 36017ec0effdSAtul Deshmukh case 0x2: 36027ec0effdSAtul Deshmukh case 0x10: 36037ec0effdSAtul Deshmukh case 0x11: 36047ec0effdSAtul Deshmukh qla82xx_mbx_completion(vha, MSW(stat)); 36057ec0effdSAtul Deshmukh status |= MBX_INTERRUPT; 36067ec0effdSAtul Deshmukh break; 36077ec0effdSAtul Deshmukh case 0x12: 36087ec0effdSAtul Deshmukh mb[0] = MSW(stat); 36097ec0effdSAtul Deshmukh mb[1] = RD_REG_WORD(®->mailbox_out[1]); 36107ec0effdSAtul Deshmukh mb[2] = RD_REG_WORD(®->mailbox_out[2]); 36117ec0effdSAtul Deshmukh mb[3] = RD_REG_WORD(®->mailbox_out[3]); 36127ec0effdSAtul Deshmukh qla2x00_async_event(vha, rsp, mb); 36137ec0effdSAtul Deshmukh break; 36147ec0effdSAtul Deshmukh case 0x13: 36157ec0effdSAtul Deshmukh qla24xx_process_response_queue(vha, rsp); 36167ec0effdSAtul Deshmukh break; 36177ec0effdSAtul Deshmukh default: 36187ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb146, 36197ec0effdSAtul Deshmukh "Unrecognized interrupt type " 36207ec0effdSAtul Deshmukh "(%d).\n", stat & 0xff); 36217ec0effdSAtul Deshmukh break; 36227ec0effdSAtul Deshmukh } 36237ec0effdSAtul Deshmukh } 36247ec0effdSAtul Deshmukh WRT_REG_DWORD(®->host_int, 0); 36257ec0effdSAtul Deshmukh } 36267ec0effdSAtul Deshmukh 36277ec0effdSAtul Deshmukh qla2x00_handle_mbx_completion(ha, status); 36287ec0effdSAtul Deshmukh spin_unlock_irqrestore(&ha->hardware_lock, flags); 36297ec0effdSAtul Deshmukh 36307ec0effdSAtul Deshmukh return IRQ_HANDLED; 36317ec0effdSAtul Deshmukh } 36327ec0effdSAtul Deshmukh 36337ec0effdSAtul Deshmukh static int 36347ec0effdSAtul Deshmukh qla8044_idc_dontreset(struct qla_hw_data *ha) 36357ec0effdSAtul Deshmukh { 36367ec0effdSAtul Deshmukh uint32_t idc_ctrl; 36377ec0effdSAtul Deshmukh 36387ec0effdSAtul Deshmukh idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL); 36397ec0effdSAtul Deshmukh return idc_ctrl & DONTRESET_BIT0; 36407ec0effdSAtul Deshmukh } 36417ec0effdSAtul Deshmukh 36427ec0effdSAtul Deshmukh static void 36437ec0effdSAtul Deshmukh qla8044_clear_rst_ready(scsi_qla_host_t *vha) 36447ec0effdSAtul Deshmukh { 36457ec0effdSAtul Deshmukh uint32_t drv_state; 36467ec0effdSAtul Deshmukh 36477ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX); 36487ec0effdSAtul Deshmukh 36497ec0effdSAtul Deshmukh /* 36507ec0effdSAtul Deshmukh * For ISP8044, drv_active register has 1 bit per function, 36517ec0effdSAtul Deshmukh * shift 1 by func_num to set a bit for the function. 36527ec0effdSAtul Deshmukh * For ISP82xx, drv_active has 4 bits per function 36537ec0effdSAtul Deshmukh */ 36547ec0effdSAtul Deshmukh drv_state &= ~(1 << vha->hw->portnum); 36557ec0effdSAtul Deshmukh 36567ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb143, 36577ec0effdSAtul Deshmukh "drv_state: 0x%08x\n", drv_state); 36587ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state); 36597ec0effdSAtul Deshmukh } 36607ec0effdSAtul Deshmukh 36617ec0effdSAtul Deshmukh int 36627ec0effdSAtul Deshmukh qla8044_abort_isp(scsi_qla_host_t *vha) 36637ec0effdSAtul Deshmukh { 36647ec0effdSAtul Deshmukh int rval; 36657ec0effdSAtul Deshmukh uint32_t dev_state; 36667ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw; 36677ec0effdSAtul Deshmukh 36687ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 36697ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX); 36707ec0effdSAtul Deshmukh 36717ec0effdSAtul Deshmukh if (ql2xdontresethba) 36727ec0effdSAtul Deshmukh qla8044_set_idc_dontreset(vha); 36737ec0effdSAtul Deshmukh 36747ec0effdSAtul Deshmukh /* If device_state is NEED_RESET, go ahead with 36757ec0effdSAtul Deshmukh * Reset,irrespective of ql2xdontresethba. This is to allow a 36767ec0effdSAtul Deshmukh * non-reset-owner to force a reset. Non-reset-owner sets 36777ec0effdSAtul Deshmukh * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset 36787ec0effdSAtul Deshmukh * and then forces a Reset by setting device_state to 36797ec0effdSAtul Deshmukh * NEED_RESET. */ 36807ec0effdSAtul Deshmukh if (dev_state == QLA8XXX_DEV_READY) { 36817ec0effdSAtul Deshmukh /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset 36827ec0effdSAtul Deshmukh * recovery */ 36837ec0effdSAtul Deshmukh if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) { 36847ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb144, 36857ec0effdSAtul Deshmukh "Reset recovery disabled\n"); 36867ec0effdSAtul Deshmukh rval = QLA_FUNCTION_FAILED; 36877ec0effdSAtul Deshmukh goto exit_isp_reset; 36887ec0effdSAtul Deshmukh } 36897ec0effdSAtul Deshmukh 36907ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb145, 36917ec0effdSAtul Deshmukh "HW State: NEED RESET\n"); 36927ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, 36937ec0effdSAtul Deshmukh QLA8XXX_DEV_NEED_RESET); 36947ec0effdSAtul Deshmukh } 36957ec0effdSAtul Deshmukh 36967ec0effdSAtul Deshmukh /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority 36977ec0effdSAtul Deshmukh * and which drivers are present. Unlike ISP82XX, the function setting 36987ec0effdSAtul Deshmukh * NEED_RESET, may not be the Reset owner. */ 36997ec0effdSAtul Deshmukh qla83xx_reset_ownership(vha); 37007ec0effdSAtul Deshmukh 37017ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 37027ec0effdSAtul Deshmukh rval = qla8044_device_state_handler(vha); 37037ec0effdSAtul Deshmukh qla8044_idc_lock(ha); 37047ec0effdSAtul Deshmukh qla8044_clear_rst_ready(vha); 37057ec0effdSAtul Deshmukh 37067ec0effdSAtul Deshmukh exit_isp_reset: 37077ec0effdSAtul Deshmukh qla8044_idc_unlock(ha); 37087ec0effdSAtul Deshmukh if (rval == QLA_SUCCESS) { 37097ec0effdSAtul Deshmukh ha->flags.isp82xx_fw_hung = 0; 37107ec0effdSAtul Deshmukh ha->flags.nic_core_reset_hdlr_active = 0; 37117ec0effdSAtul Deshmukh rval = qla82xx_restart_isp(vha); 37127ec0effdSAtul Deshmukh } 37137ec0effdSAtul Deshmukh 37147ec0effdSAtul Deshmukh return rval; 37157ec0effdSAtul Deshmukh } 37167ec0effdSAtul Deshmukh 3717