177adf3f0SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
27ec0effdSAtul Deshmukh /*
37ec0effdSAtul Deshmukh * QLogic Fibre Channel HBA Driver
4bd21eaf9SArmen Baloyan * Copyright (c) 2003-2014 QLogic Corporation
57ec0effdSAtul Deshmukh */
67ec0effdSAtul Deshmukh
77ec0effdSAtul Deshmukh #include <linux/vmalloc.h>
850256357SAtul Deshmukh #include <linux/delay.h>
97ec0effdSAtul Deshmukh
107ec0effdSAtul Deshmukh #include "qla_def.h"
117ec0effdSAtul Deshmukh #include "qla_gbl.h"
127ec0effdSAtul Deshmukh
13804df800SPratik Mohanty #define TIMEOUT_100_MS 100
14804df800SPratik Mohanty
1561778a1cSBart Van Assche static const uint32_t qla8044_reg_tbl[] = {
1661778a1cSBart Van Assche QLA8044_PEG_HALT_STATUS1,
1761778a1cSBart Van Assche QLA8044_PEG_HALT_STATUS2,
1861778a1cSBart Van Assche QLA8044_PEG_ALIVE_COUNTER,
1961778a1cSBart Van Assche QLA8044_CRB_DRV_ACTIVE,
2061778a1cSBart Van Assche QLA8044_CRB_DEV_STATE,
2161778a1cSBart Van Assche QLA8044_CRB_DRV_STATE,
2261778a1cSBart Van Assche QLA8044_CRB_DRV_SCRATCH,
2361778a1cSBart Van Assche QLA8044_CRB_DEV_PART_INFO1,
2461778a1cSBart Van Assche QLA8044_CRB_IDC_VER_MAJOR,
2561778a1cSBart Van Assche QLA8044_FW_VER_MAJOR,
2661778a1cSBart Van Assche QLA8044_FW_VER_MINOR,
2761778a1cSBart Van Assche QLA8044_FW_VER_SUB,
2861778a1cSBart Van Assche QLA8044_CMDPEG_STATE,
2961778a1cSBart Van Assche QLA8044_ASIC_TEMP,
3061778a1cSBart Van Assche };
3161778a1cSBart Van Assche
327ec0effdSAtul Deshmukh /* 8044 Flash Read/Write functions */
337ec0effdSAtul Deshmukh uint32_t
qla8044_rd_reg(struct qla_hw_data * ha,ulong addr)347ec0effdSAtul Deshmukh qla8044_rd_reg(struct qla_hw_data *ha, ulong addr)
357ec0effdSAtul Deshmukh {
367ec0effdSAtul Deshmukh return readl((void __iomem *) (ha->nx_pcibase + addr));
377ec0effdSAtul Deshmukh }
387ec0effdSAtul Deshmukh
397ec0effdSAtul Deshmukh void
qla8044_wr_reg(struct qla_hw_data * ha,ulong addr,uint32_t val)407ec0effdSAtul Deshmukh qla8044_wr_reg(struct qla_hw_data *ha, ulong addr, uint32_t val)
417ec0effdSAtul Deshmukh {
427ec0effdSAtul Deshmukh writel(val, (void __iomem *)((ha)->nx_pcibase + addr));
437ec0effdSAtul Deshmukh }
447ec0effdSAtul Deshmukh
457ec0effdSAtul Deshmukh int
qla8044_rd_direct(struct scsi_qla_host * vha,const uint32_t crb_reg)467ec0effdSAtul Deshmukh qla8044_rd_direct(struct scsi_qla_host *vha,
477ec0effdSAtul Deshmukh const uint32_t crb_reg)
487ec0effdSAtul Deshmukh {
497ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
507ec0effdSAtul Deshmukh
517ec0effdSAtul Deshmukh if (crb_reg < CRB_REG_INDEX_MAX)
527ec0effdSAtul Deshmukh return qla8044_rd_reg(ha, qla8044_reg_tbl[crb_reg]);
537ec0effdSAtul Deshmukh else
547ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
557ec0effdSAtul Deshmukh }
567ec0effdSAtul Deshmukh
577ec0effdSAtul Deshmukh void
qla8044_wr_direct(struct scsi_qla_host * vha,const uint32_t crb_reg,const uint32_t value)587ec0effdSAtul Deshmukh qla8044_wr_direct(struct scsi_qla_host *vha,
597ec0effdSAtul Deshmukh const uint32_t crb_reg,
607ec0effdSAtul Deshmukh const uint32_t value)
617ec0effdSAtul Deshmukh {
627ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
637ec0effdSAtul Deshmukh
647ec0effdSAtul Deshmukh if (crb_reg < CRB_REG_INDEX_MAX)
657ec0effdSAtul Deshmukh qla8044_wr_reg(ha, qla8044_reg_tbl[crb_reg], value);
667ec0effdSAtul Deshmukh }
677ec0effdSAtul Deshmukh
687ec0effdSAtul Deshmukh static int
qla8044_set_win_base(scsi_qla_host_t * vha,uint32_t addr)697ec0effdSAtul Deshmukh qla8044_set_win_base(scsi_qla_host_t *vha, uint32_t addr)
707ec0effdSAtul Deshmukh {
717ec0effdSAtul Deshmukh uint32_t val;
727ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
737ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
747ec0effdSAtul Deshmukh
757ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum), addr);
767ec0effdSAtul Deshmukh val = qla8044_rd_reg(ha, QLA8044_CRB_WIN_FUNC(ha->portnum));
777ec0effdSAtul Deshmukh
787ec0effdSAtul Deshmukh if (val != addr) {
797ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb087,
807ec0effdSAtul Deshmukh "%s: Failed to set register window : "
817ec0effdSAtul Deshmukh "addr written 0x%x, read 0x%x!\n",
827ec0effdSAtul Deshmukh __func__, addr, val);
837ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
847ec0effdSAtul Deshmukh }
857ec0effdSAtul Deshmukh return ret_val;
867ec0effdSAtul Deshmukh }
877ec0effdSAtul Deshmukh
887ec0effdSAtul Deshmukh static int
qla8044_rd_reg_indirect(scsi_qla_host_t * vha,uint32_t addr,uint32_t * data)897ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t *data)
907ec0effdSAtul Deshmukh {
917ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
927ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
937ec0effdSAtul Deshmukh
947ec0effdSAtul Deshmukh ret_val = qla8044_set_win_base(vha, addr);
957ec0effdSAtul Deshmukh if (!ret_val)
967ec0effdSAtul Deshmukh *data = qla8044_rd_reg(ha, QLA8044_WILDCARD);
977ec0effdSAtul Deshmukh else
987ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb088,
997ec0effdSAtul Deshmukh "%s: failed read of addr 0x%x!\n", __func__, addr);
1007ec0effdSAtul Deshmukh return ret_val;
1017ec0effdSAtul Deshmukh }
1027ec0effdSAtul Deshmukh
1037ec0effdSAtul Deshmukh static int
qla8044_wr_reg_indirect(scsi_qla_host_t * vha,uint32_t addr,uint32_t data)1047ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(scsi_qla_host_t *vha, uint32_t addr, uint32_t data)
1057ec0effdSAtul Deshmukh {
1067ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
1077ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
1087ec0effdSAtul Deshmukh
1097ec0effdSAtul Deshmukh ret_val = qla8044_set_win_base(vha, addr);
1107ec0effdSAtul Deshmukh if (!ret_val)
1117ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_WILDCARD, data);
1127ec0effdSAtul Deshmukh else
1137ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb089,
1147ec0effdSAtul Deshmukh "%s: failed wrt to addr 0x%x, data 0x%x\n",
1157ec0effdSAtul Deshmukh __func__, addr, data);
1167ec0effdSAtul Deshmukh return ret_val;
1177ec0effdSAtul Deshmukh }
1187ec0effdSAtul Deshmukh
1197ec0effdSAtul Deshmukh /*
1207ec0effdSAtul Deshmukh * qla8044_read_write_crb_reg - Read from raddr and write value to waddr.
1217ec0effdSAtul Deshmukh *
1227ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure
1237ec0effdSAtul Deshmukh * @raddr : CRB address to read from
1247ec0effdSAtul Deshmukh * @waddr : CRB address to write to
1257ec0effdSAtul Deshmukh *
1267ec0effdSAtul Deshmukh */
1277ec0effdSAtul Deshmukh static void
qla8044_read_write_crb_reg(struct scsi_qla_host * vha,uint32_t raddr,uint32_t waddr)1287ec0effdSAtul Deshmukh qla8044_read_write_crb_reg(struct scsi_qla_host *vha,
1297ec0effdSAtul Deshmukh uint32_t raddr, uint32_t waddr)
1307ec0effdSAtul Deshmukh {
1317ec0effdSAtul Deshmukh uint32_t value;
1327ec0effdSAtul Deshmukh
1337ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, raddr, &value);
1347ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, waddr, value);
1357ec0effdSAtul Deshmukh }
1367ec0effdSAtul Deshmukh
137804df800SPratik Mohanty static int
qla8044_poll_wait_for_ready(struct scsi_qla_host * vha,uint32_t addr1,uint32_t mask)138804df800SPratik Mohanty qla8044_poll_wait_for_ready(struct scsi_qla_host *vha, uint32_t addr1,
139804df800SPratik Mohanty uint32_t mask)
140804df800SPratik Mohanty {
141804df800SPratik Mohanty unsigned long timeout;
142aceba54bSArun Easi uint32_t temp = 0;
143804df800SPratik Mohanty
144804df800SPratik Mohanty /* jiffies after 100ms */
145804df800SPratik Mohanty timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
146804df800SPratik Mohanty do {
147804df800SPratik Mohanty qla8044_rd_reg_indirect(vha, addr1, &temp);
148804df800SPratik Mohanty if ((temp & mask) != 0)
149804df800SPratik Mohanty break;
150804df800SPratik Mohanty if (time_after_eq(jiffies, timeout)) {
151804df800SPratik Mohanty ql_log(ql_log_warn, vha, 0xb151,
152804df800SPratik Mohanty "Error in processing rdmdio entry\n");
153804df800SPratik Mohanty return -1;
154804df800SPratik Mohanty }
155804df800SPratik Mohanty } while (1);
156804df800SPratik Mohanty
157804df800SPratik Mohanty return 0;
158804df800SPratik Mohanty }
159804df800SPratik Mohanty
160804df800SPratik Mohanty static uint32_t
qla8044_ipmdio_rd_reg(struct scsi_qla_host * vha,uint32_t addr1,uint32_t addr3,uint32_t mask,uint32_t addr)161804df800SPratik Mohanty qla8044_ipmdio_rd_reg(struct scsi_qla_host *vha,
162804df800SPratik Mohanty uint32_t addr1, uint32_t addr3, uint32_t mask, uint32_t addr)
163804df800SPratik Mohanty {
164804df800SPratik Mohanty uint32_t temp;
165804df800SPratik Mohanty int ret = 0;
166804df800SPratik Mohanty
167804df800SPratik Mohanty ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
168804df800SPratik Mohanty if (ret == -1)
169804df800SPratik Mohanty return -1;
170804df800SPratik Mohanty
171804df800SPratik Mohanty temp = (0x40000000 | addr);
172804df800SPratik Mohanty qla8044_wr_reg_indirect(vha, addr1, temp);
173804df800SPratik Mohanty
174804df800SPratik Mohanty ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
175804df800SPratik Mohanty if (ret == -1)
176804df800SPratik Mohanty return 0;
177804df800SPratik Mohanty
178804df800SPratik Mohanty qla8044_rd_reg_indirect(vha, addr3, &ret);
179804df800SPratik Mohanty
180804df800SPratik Mohanty return ret;
181804df800SPratik Mohanty }
182804df800SPratik Mohanty
183804df800SPratik Mohanty
184804df800SPratik Mohanty static int
qla8044_poll_wait_ipmdio_bus_idle(struct scsi_qla_host * vha,uint32_t addr1,uint32_t addr2,uint32_t addr3,uint32_t mask)185804df800SPratik Mohanty qla8044_poll_wait_ipmdio_bus_idle(struct scsi_qla_host *vha,
186804df800SPratik Mohanty uint32_t addr1, uint32_t addr2, uint32_t addr3, uint32_t mask)
187804df800SPratik Mohanty {
188804df800SPratik Mohanty unsigned long timeout;
189804df800SPratik Mohanty uint32_t temp;
190804df800SPratik Mohanty
191804df800SPratik Mohanty /* jiffies after 100 msecs */
19250a9ff30SJoe Carnuccio timeout = jiffies + msecs_to_jiffies(TIMEOUT_100_MS);
193804df800SPratik Mohanty do {
194804df800SPratik Mohanty temp = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr2);
195804df800SPratik Mohanty if ((temp & 0x1) != 1)
196804df800SPratik Mohanty break;
197804df800SPratik Mohanty if (time_after_eq(jiffies, timeout)) {
198804df800SPratik Mohanty ql_log(ql_log_warn, vha, 0xb152,
199804df800SPratik Mohanty "Error in processing mdiobus idle\n");
200804df800SPratik Mohanty return -1;
201804df800SPratik Mohanty }
20250a9ff30SJoe Carnuccio } while (1);
203804df800SPratik Mohanty
204804df800SPratik Mohanty return 0;
205804df800SPratik Mohanty }
206804df800SPratik Mohanty
207804df800SPratik Mohanty static int
qla8044_ipmdio_wr_reg(struct scsi_qla_host * vha,uint32_t addr1,uint32_t addr3,uint32_t mask,uint32_t addr,uint32_t value)208804df800SPratik Mohanty qla8044_ipmdio_wr_reg(struct scsi_qla_host *vha, uint32_t addr1,
209804df800SPratik Mohanty uint32_t addr3, uint32_t mask, uint32_t addr, uint32_t value)
210804df800SPratik Mohanty {
211804df800SPratik Mohanty int ret = 0;
212804df800SPratik Mohanty
213804df800SPratik Mohanty ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
214804df800SPratik Mohanty if (ret == -1)
215804df800SPratik Mohanty return -1;
216804df800SPratik Mohanty
217804df800SPratik Mohanty qla8044_wr_reg_indirect(vha, addr3, value);
218804df800SPratik Mohanty qla8044_wr_reg_indirect(vha, addr1, addr);
219804df800SPratik Mohanty
220804df800SPratik Mohanty ret = qla8044_poll_wait_for_ready(vha, addr1, mask);
221804df800SPratik Mohanty if (ret == -1)
222804df800SPratik Mohanty return -1;
223804df800SPratik Mohanty
224804df800SPratik Mohanty return 0;
225804df800SPratik Mohanty }
2267ec0effdSAtul Deshmukh /*
2277ec0effdSAtul Deshmukh * qla8044_rmw_crb_reg - Read value from raddr, AND with test_mask,
2287ec0effdSAtul Deshmukh * Shift Left,Right/OR/XOR with values RMW header and write value to waddr.
2297ec0effdSAtul Deshmukh *
2307ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure
2317ec0effdSAtul Deshmukh * @raddr : CRB address to read from
2327ec0effdSAtul Deshmukh * @waddr : CRB address to write to
2337ec0effdSAtul Deshmukh * @p_rmw_hdr : header with shift/or/xor values.
2347ec0effdSAtul Deshmukh *
2357ec0effdSAtul Deshmukh */
2367ec0effdSAtul Deshmukh static void
qla8044_rmw_crb_reg(struct scsi_qla_host * vha,uint32_t raddr,uint32_t waddr,struct qla8044_rmw * p_rmw_hdr)2377ec0effdSAtul Deshmukh qla8044_rmw_crb_reg(struct scsi_qla_host *vha,
2387ec0effdSAtul Deshmukh uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr)
2397ec0effdSAtul Deshmukh {
2407ec0effdSAtul Deshmukh uint32_t value;
2417ec0effdSAtul Deshmukh
2427ec0effdSAtul Deshmukh if (p_rmw_hdr->index_a)
2437ec0effdSAtul Deshmukh value = vha->reset_tmplt.array[p_rmw_hdr->index_a];
2447ec0effdSAtul Deshmukh else
2457ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, raddr, &value);
2467ec0effdSAtul Deshmukh value &= p_rmw_hdr->test_mask;
2477ec0effdSAtul Deshmukh value <<= p_rmw_hdr->shl;
2487ec0effdSAtul Deshmukh value >>= p_rmw_hdr->shr;
2497ec0effdSAtul Deshmukh value |= p_rmw_hdr->or_value;
2507ec0effdSAtul Deshmukh value ^= p_rmw_hdr->xor_value;
2517ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, waddr, value);
2527ec0effdSAtul Deshmukh return;
2537ec0effdSAtul Deshmukh }
2547ec0effdSAtul Deshmukh
2559493c242SChen Gang static inline void
qla8044_set_qsnt_ready(struct scsi_qla_host * vha)2567ec0effdSAtul Deshmukh qla8044_set_qsnt_ready(struct scsi_qla_host *vha)
2577ec0effdSAtul Deshmukh {
2587ec0effdSAtul Deshmukh uint32_t qsnt_state;
2597ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
2607ec0effdSAtul Deshmukh
2617ec0effdSAtul Deshmukh qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
2627ec0effdSAtul Deshmukh qsnt_state |= (1 << ha->portnum);
2637ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
2647ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb08e, "%s(%ld): qsnt_state: 0x%08x\n",
2657ec0effdSAtul Deshmukh __func__, vha->host_no, qsnt_state);
2667ec0effdSAtul Deshmukh }
2677ec0effdSAtul Deshmukh
2687ec0effdSAtul Deshmukh void
qla8044_clear_qsnt_ready(struct scsi_qla_host * vha)2697ec0effdSAtul Deshmukh qla8044_clear_qsnt_ready(struct scsi_qla_host *vha)
2707ec0effdSAtul Deshmukh {
2717ec0effdSAtul Deshmukh uint32_t qsnt_state;
2727ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
2737ec0effdSAtul Deshmukh
2747ec0effdSAtul Deshmukh qsnt_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
2757ec0effdSAtul Deshmukh qsnt_state &= ~(1 << ha->portnum);
2767ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, qsnt_state);
2777ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb08f, "%s(%ld): qsnt_state: 0x%08x\n",
2787ec0effdSAtul Deshmukh __func__, vha->host_no, qsnt_state);
2797ec0effdSAtul Deshmukh }
2807ec0effdSAtul Deshmukh
2817ec0effdSAtul Deshmukh /**
2827ec0effdSAtul Deshmukh * qla8044_lock_recovery - Recovers the idc_lock.
2832db6228dSBart Van Assche * @vha : Pointer to adapter structure
2847ec0effdSAtul Deshmukh *
2857ec0effdSAtul Deshmukh * Lock Recovery Register
2867ec0effdSAtul Deshmukh * 5-2 Lock recovery owner: Function ID of driver doing lock recovery,
2877ec0effdSAtul Deshmukh * valid if bits 1..0 are set by driver doing lock recovery.
2887ec0effdSAtul Deshmukh * 1-0 1 - Driver intends to force unlock the IDC lock.
2897ec0effdSAtul Deshmukh * 2 - Driver is moving forward to unlock the IDC lock. Driver clears
2907ec0effdSAtul Deshmukh * this field after force unlocking the IDC lock.
2917ec0effdSAtul Deshmukh *
2927ec0effdSAtul Deshmukh * Lock Recovery process
2937ec0effdSAtul Deshmukh * a. Read the IDC_LOCK_RECOVERY register. If the value in bits 1..0 is
2947ec0effdSAtul Deshmukh * greater than 0, then wait for the other driver to unlock otherwise
2957ec0effdSAtul Deshmukh * move to the next step.
2967ec0effdSAtul Deshmukh * b. Indicate intent to force-unlock by writing 1h to the IDC_LOCK_RECOVERY
2977ec0effdSAtul Deshmukh * register bits 1..0 and also set the function# in bits 5..2.
2987ec0effdSAtul Deshmukh * c. Read the IDC_LOCK_RECOVERY register again after a delay of 200ms.
2997ec0effdSAtul Deshmukh * Wait for the other driver to perform lock recovery if the function
3007ec0effdSAtul Deshmukh * number in bits 5..2 has changed, otherwise move to the next step.
3017ec0effdSAtul Deshmukh * d. Write a value of 2h to the IDC_LOCK_RECOVERY register bits 1..0
3027ec0effdSAtul Deshmukh * leaving your function# in bits 5..2.
3037ec0effdSAtul Deshmukh * e. Force unlock using the DRIVER_UNLOCK register and immediately clear
3047ec0effdSAtul Deshmukh * the IDC_LOCK_RECOVERY bits 5..0 by writing 0.
3057ec0effdSAtul Deshmukh **/
3067ec0effdSAtul Deshmukh static int
qla8044_lock_recovery(struct scsi_qla_host * vha)3077ec0effdSAtul Deshmukh qla8044_lock_recovery(struct scsi_qla_host *vha)
3087ec0effdSAtul Deshmukh {
3097ec0effdSAtul Deshmukh uint32_t lock = 0, lockid;
3107ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
3117ec0effdSAtul Deshmukh
3127ec0effdSAtul Deshmukh lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
3137ec0effdSAtul Deshmukh
3147ec0effdSAtul Deshmukh /* Check for other Recovery in progress, go wait */
3157ec0effdSAtul Deshmukh if ((lockid & IDC_LOCK_RECOVERY_STATE_MASK) != 0)
3167ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
3177ec0effdSAtul Deshmukh
3187ec0effdSAtul Deshmukh /* Intent to Recover */
3197ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
3207ec0effdSAtul Deshmukh (ha->portnum <<
3217ec0effdSAtul Deshmukh IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) | INTENT_TO_RECOVER);
3227ec0effdSAtul Deshmukh msleep(200);
3237ec0effdSAtul Deshmukh
3247ec0effdSAtul Deshmukh /* Check Intent to Recover is advertised */
3257ec0effdSAtul Deshmukh lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCKRECOVERY);
3267ec0effdSAtul Deshmukh if ((lockid & IDC_LOCK_RECOVERY_OWNER_MASK) != (ha->portnum <<
3277ec0effdSAtul Deshmukh IDC_LOCK_RECOVERY_STATE_SHIFT_BITS))
3287ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
3297ec0effdSAtul Deshmukh
3307ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb08B, "%s:%d: IDC Lock recovery initiated\n"
3317ec0effdSAtul Deshmukh , __func__, ha->portnum);
3327ec0effdSAtul Deshmukh
3337ec0effdSAtul Deshmukh /* Proceed to Recover */
3347ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY,
3357ec0effdSAtul Deshmukh (ha->portnum << IDC_LOCK_RECOVERY_STATE_SHIFT_BITS) |
3367ec0effdSAtul Deshmukh PROCEED_TO_RECOVER);
3377ec0effdSAtul Deshmukh
3387ec0effdSAtul Deshmukh /* Force Unlock() */
3397ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, 0xFF);
3407ec0effdSAtul Deshmukh qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
3417ec0effdSAtul Deshmukh
3427ec0effdSAtul Deshmukh /* Clear bits 0-5 in IDC_RECOVERY register*/
3437ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCKRECOVERY, 0);
3447ec0effdSAtul Deshmukh
3457ec0effdSAtul Deshmukh /* Get lock() */
3467ec0effdSAtul Deshmukh lock = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
3477ec0effdSAtul Deshmukh if (lock) {
3487ec0effdSAtul Deshmukh lockid = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
3497ec0effdSAtul Deshmukh lockid = ((lockid + (1 << 8)) & ~0xFF) | ha->portnum;
3507ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lockid);
3517ec0effdSAtul Deshmukh return QLA_SUCCESS;
3527ec0effdSAtul Deshmukh } else
3537ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
3547ec0effdSAtul Deshmukh }
3557ec0effdSAtul Deshmukh
3567ec0effdSAtul Deshmukh int
qla8044_idc_lock(struct qla_hw_data * ha)3577ec0effdSAtul Deshmukh qla8044_idc_lock(struct qla_hw_data *ha)
3587ec0effdSAtul Deshmukh {
3597ec0effdSAtul Deshmukh uint32_t ret_val = QLA_SUCCESS, timeout = 0, status = 0;
3607ec0effdSAtul Deshmukh uint32_t lock_id, lock_cnt, func_num, tmo_owner = 0, first_owner = 0;
3617ec0effdSAtul Deshmukh scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
3627ec0effdSAtul Deshmukh
3637ec0effdSAtul Deshmukh while (status == 0) {
3647ec0effdSAtul Deshmukh /* acquire semaphore5 from PCI HW block */
3657ec0effdSAtul Deshmukh status = qla8044_rd_reg(ha, QLA8044_DRV_LOCK);
3667ec0effdSAtul Deshmukh
3677ec0effdSAtul Deshmukh if (status) {
3687ec0effdSAtul Deshmukh /* Increment Counter (8-31) and update func_num (0-7) on
3697ec0effdSAtul Deshmukh * getting a successful lock */
3707ec0effdSAtul Deshmukh lock_id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
3717ec0effdSAtul Deshmukh lock_id = ((lock_id + (1 << 8)) & ~0xFF) | ha->portnum;
3727ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, lock_id);
3737ec0effdSAtul Deshmukh break;
3747ec0effdSAtul Deshmukh }
3757ec0effdSAtul Deshmukh
3767ec0effdSAtul Deshmukh if (timeout == 0)
3777ec0effdSAtul Deshmukh first_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
3787ec0effdSAtul Deshmukh
3797ec0effdSAtul Deshmukh if (++timeout >=
3807ec0effdSAtul Deshmukh (QLA8044_DRV_LOCK_TIMEOUT / QLA8044_DRV_LOCK_MSLEEP)) {
3817ec0effdSAtul Deshmukh tmo_owner = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
3827ec0effdSAtul Deshmukh func_num = tmo_owner & 0xFF;
3837ec0effdSAtul Deshmukh lock_cnt = tmo_owner >> 8;
3847ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb114,
3857ec0effdSAtul Deshmukh "%s: Lock by func %d failed after 2s, lock held "
3867ec0effdSAtul Deshmukh "by func %d, lock count %d, first_owner %d\n",
3877ec0effdSAtul Deshmukh __func__, ha->portnum, func_num, lock_cnt,
3887ec0effdSAtul Deshmukh (first_owner & 0xFF));
3897ec0effdSAtul Deshmukh if (first_owner != tmo_owner) {
3907ec0effdSAtul Deshmukh /* Some other driver got lock,
3917ec0effdSAtul Deshmukh * OR same driver got lock again (counter
3927ec0effdSAtul Deshmukh * value changed), when we were waiting for
3937ec0effdSAtul Deshmukh * lock. Retry for another 2 sec */
3947ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb115,
3957ec0effdSAtul Deshmukh "%s: %d: IDC lock failed\n",
3967ec0effdSAtul Deshmukh __func__, ha->portnum);
3977ec0effdSAtul Deshmukh timeout = 0;
3987ec0effdSAtul Deshmukh } else {
3997ec0effdSAtul Deshmukh /* Same driver holding lock > 2sec.
4007ec0effdSAtul Deshmukh * Force Recovery */
4017ec0effdSAtul Deshmukh if (qla8044_lock_recovery(vha) == QLA_SUCCESS) {
4027ec0effdSAtul Deshmukh /* Recovered and got lock */
4037ec0effdSAtul Deshmukh ret_val = QLA_SUCCESS;
4047ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb116,
4057ec0effdSAtul Deshmukh "%s:IDC lock Recovery by %d"
4067ec0effdSAtul Deshmukh "successful...\n", __func__,
4077ec0effdSAtul Deshmukh ha->portnum);
4087ec0effdSAtul Deshmukh }
4097ec0effdSAtul Deshmukh /* Recovery Failed, some other function
4107ec0effdSAtul Deshmukh * has the lock, wait for 2secs
4117ec0effdSAtul Deshmukh * and retry
4127ec0effdSAtul Deshmukh */
4137ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb08a,
4147ec0effdSAtul Deshmukh "%s: IDC lock Recovery by %d "
4159b13494cSMasanari Iida "failed, Retrying timeout\n", __func__,
4167ec0effdSAtul Deshmukh ha->portnum);
4177ec0effdSAtul Deshmukh timeout = 0;
4187ec0effdSAtul Deshmukh }
4197ec0effdSAtul Deshmukh }
4207ec0effdSAtul Deshmukh msleep(QLA8044_DRV_LOCK_MSLEEP);
4217ec0effdSAtul Deshmukh }
4227ec0effdSAtul Deshmukh return ret_val;
4237ec0effdSAtul Deshmukh }
4247ec0effdSAtul Deshmukh
4257ec0effdSAtul Deshmukh void
qla8044_idc_unlock(struct qla_hw_data * ha)4267ec0effdSAtul Deshmukh qla8044_idc_unlock(struct qla_hw_data *ha)
4277ec0effdSAtul Deshmukh {
4287ec0effdSAtul Deshmukh int id;
4297ec0effdSAtul Deshmukh scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
4307ec0effdSAtul Deshmukh
4317ec0effdSAtul Deshmukh id = qla8044_rd_reg(ha, QLA8044_DRV_LOCK_ID);
4327ec0effdSAtul Deshmukh
4337ec0effdSAtul Deshmukh if ((id & 0xFF) != ha->portnum) {
4347ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb118,
4357ec0effdSAtul Deshmukh "%s: IDC Unlock by %d failed, lock owner is %d!\n",
4367ec0effdSAtul Deshmukh __func__, ha->portnum, (id & 0xFF));
4377ec0effdSAtul Deshmukh return;
4387ec0effdSAtul Deshmukh }
4397ec0effdSAtul Deshmukh
4407ec0effdSAtul Deshmukh /* Keep lock counter value, update the ha->func_num to 0xFF */
4417ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_DRV_LOCK_ID, (id | 0xFF));
4427ec0effdSAtul Deshmukh qla8044_rd_reg(ha, QLA8044_DRV_UNLOCK);
4437ec0effdSAtul Deshmukh }
4447ec0effdSAtul Deshmukh
4457ec0effdSAtul Deshmukh /* 8044 Flash Lock/Unlock functions */
4467ec0effdSAtul Deshmukh static int
qla8044_flash_lock(scsi_qla_host_t * vha)4477ec0effdSAtul Deshmukh qla8044_flash_lock(scsi_qla_host_t *vha)
4487ec0effdSAtul Deshmukh {
4497ec0effdSAtul Deshmukh int lock_owner;
4507ec0effdSAtul Deshmukh int timeout = 0;
4517ec0effdSAtul Deshmukh uint32_t lock_status = 0;
4527ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
4537ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
4547ec0effdSAtul Deshmukh
4557ec0effdSAtul Deshmukh while (lock_status == 0) {
4567ec0effdSAtul Deshmukh lock_status = qla8044_rd_reg(ha, QLA8044_FLASH_LOCK);
4577ec0effdSAtul Deshmukh if (lock_status)
4587ec0effdSAtul Deshmukh break;
4597ec0effdSAtul Deshmukh
4607ec0effdSAtul Deshmukh if (++timeout >= QLA8044_FLASH_LOCK_TIMEOUT / 20) {
4617ec0effdSAtul Deshmukh lock_owner = qla8044_rd_reg(ha,
4627ec0effdSAtul Deshmukh QLA8044_FLASH_LOCK_ID);
4637ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb113,
46427f4b72fSAtul Deshmukh "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
4657ec0effdSAtul Deshmukh __func__, ha->portnum, lock_owner);
4667ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
4677ec0effdSAtul Deshmukh break;
4687ec0effdSAtul Deshmukh }
4697ec0effdSAtul Deshmukh msleep(20);
4707ec0effdSAtul Deshmukh }
4717ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, ha->portnum);
4727ec0effdSAtul Deshmukh return ret_val;
4737ec0effdSAtul Deshmukh }
4747ec0effdSAtul Deshmukh
4757ec0effdSAtul Deshmukh static void
qla8044_flash_unlock(scsi_qla_host_t * vha)4767ec0effdSAtul Deshmukh qla8044_flash_unlock(scsi_qla_host_t *vha)
4777ec0effdSAtul Deshmukh {
4787ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
4797ec0effdSAtul Deshmukh
4807ec0effdSAtul Deshmukh /* Reading FLASH_UNLOCK register unlocks the Flash */
4817ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_FLASH_LOCK_ID, 0xFF);
48252c82823SBart Van Assche qla8044_rd_reg(ha, QLA8044_FLASH_UNLOCK);
4837ec0effdSAtul Deshmukh }
4847ec0effdSAtul Deshmukh
4857ec0effdSAtul Deshmukh
4867ec0effdSAtul Deshmukh static
qla8044_flash_lock_recovery(struct scsi_qla_host * vha)4877ec0effdSAtul Deshmukh void qla8044_flash_lock_recovery(struct scsi_qla_host *vha)
4887ec0effdSAtul Deshmukh {
4897ec0effdSAtul Deshmukh
4907ec0effdSAtul Deshmukh if (qla8044_flash_lock(vha)) {
4917ec0effdSAtul Deshmukh /* Someone else is holding the lock. */
4927ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb120, "Resetting flash_lock\n");
4937ec0effdSAtul Deshmukh }
4947ec0effdSAtul Deshmukh
4957ec0effdSAtul Deshmukh /*
4967ec0effdSAtul Deshmukh * Either we got the lock, or someone
4977ec0effdSAtul Deshmukh * else died while holding it.
4987ec0effdSAtul Deshmukh * In either case, unlock.
4997ec0effdSAtul Deshmukh */
5007ec0effdSAtul Deshmukh qla8044_flash_unlock(vha);
5017ec0effdSAtul Deshmukh }
5027ec0effdSAtul Deshmukh
5037ec0effdSAtul Deshmukh /*
5047ec0effdSAtul Deshmukh * Address and length are byte address
5057ec0effdSAtul Deshmukh */
5067ec0effdSAtul Deshmukh static int
qla8044_read_flash_data(scsi_qla_host_t * vha,uint8_t * p_data,uint32_t flash_addr,int u32_word_count)5077ec0effdSAtul Deshmukh qla8044_read_flash_data(scsi_qla_host_t *vha, uint8_t *p_data,
5087ec0effdSAtul Deshmukh uint32_t flash_addr, int u32_word_count)
5097ec0effdSAtul Deshmukh {
5107ec0effdSAtul Deshmukh int i, ret_val = QLA_SUCCESS;
5117ec0effdSAtul Deshmukh uint32_t u32_word;
5127ec0effdSAtul Deshmukh
5137ec0effdSAtul Deshmukh if (qla8044_flash_lock(vha) != QLA_SUCCESS) {
5147ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
5157ec0effdSAtul Deshmukh goto exit_lock_error;
5167ec0effdSAtul Deshmukh }
5177ec0effdSAtul Deshmukh
5187ec0effdSAtul Deshmukh if (flash_addr & 0x03) {
5197ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb117,
5207ec0effdSAtul Deshmukh "%s: Illegal addr = 0x%x\n", __func__, flash_addr);
5217ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
5227ec0effdSAtul Deshmukh goto exit_flash_read;
5237ec0effdSAtul Deshmukh }
5247ec0effdSAtul Deshmukh
5257ec0effdSAtul Deshmukh for (i = 0; i < u32_word_count; i++) {
5267ec0effdSAtul Deshmukh if (qla8044_wr_reg_indirect(vha, QLA8044_FLASH_DIRECT_WINDOW,
5277ec0effdSAtul Deshmukh (flash_addr & 0xFFFF0000))) {
5287ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb119,
5297ec0effdSAtul Deshmukh "%s: failed to write addr 0x%x to "
5307ec0effdSAtul Deshmukh "FLASH_DIRECT_WINDOW\n! ",
5317ec0effdSAtul Deshmukh __func__, flash_addr);
5327ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
5337ec0effdSAtul Deshmukh goto exit_flash_read;
5347ec0effdSAtul Deshmukh }
5357ec0effdSAtul Deshmukh
5367ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha,
5377ec0effdSAtul Deshmukh QLA8044_FLASH_DIRECT_DATA(flash_addr),
5387ec0effdSAtul Deshmukh &u32_word);
5397ec0effdSAtul Deshmukh if (ret_val != QLA_SUCCESS) {
5407ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb08c,
5417ec0effdSAtul Deshmukh "%s: failed to read addr 0x%x!\n",
5427ec0effdSAtul Deshmukh __func__, flash_addr);
5437ec0effdSAtul Deshmukh goto exit_flash_read;
5447ec0effdSAtul Deshmukh }
5457ec0effdSAtul Deshmukh
5467ec0effdSAtul Deshmukh *(uint32_t *)p_data = u32_word;
5477ec0effdSAtul Deshmukh p_data = p_data + 4;
5487ec0effdSAtul Deshmukh flash_addr = flash_addr + 4;
5497ec0effdSAtul Deshmukh }
5507ec0effdSAtul Deshmukh
5517ec0effdSAtul Deshmukh exit_flash_read:
5527ec0effdSAtul Deshmukh qla8044_flash_unlock(vha);
5537ec0effdSAtul Deshmukh
5547ec0effdSAtul Deshmukh exit_lock_error:
5557ec0effdSAtul Deshmukh return ret_val;
5567ec0effdSAtul Deshmukh }
5577ec0effdSAtul Deshmukh
5587ec0effdSAtul Deshmukh /*
5597ec0effdSAtul Deshmukh * Address and length are byte address
5607ec0effdSAtul Deshmukh */
5613695310eSJoe Carnuccio void *
qla8044_read_optrom_data(struct scsi_qla_host * vha,void * buf,uint32_t offset,uint32_t length)5623695310eSJoe Carnuccio qla8044_read_optrom_data(struct scsi_qla_host *vha, void *buf,
5637ec0effdSAtul Deshmukh uint32_t offset, uint32_t length)
5647ec0effdSAtul Deshmukh {
5657ec0effdSAtul Deshmukh scsi_block_requests(vha->host);
5663695310eSJoe Carnuccio if (qla8044_read_flash_data(vha, buf, offset, length / 4)
5677ec0effdSAtul Deshmukh != QLA_SUCCESS) {
5687ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb08d,
5697ec0effdSAtul Deshmukh "%s: Failed to read from flash\n",
5707ec0effdSAtul Deshmukh __func__);
5717ec0effdSAtul Deshmukh }
5727ec0effdSAtul Deshmukh scsi_unblock_requests(vha->host);
5737ec0effdSAtul Deshmukh return buf;
5747ec0effdSAtul Deshmukh }
5757ec0effdSAtul Deshmukh
5762374dd23SBart Van Assche static inline int
qla8044_need_reset(struct scsi_qla_host * vha)5777ec0effdSAtul Deshmukh qla8044_need_reset(struct scsi_qla_host *vha)
5787ec0effdSAtul Deshmukh {
5797ec0effdSAtul Deshmukh uint32_t drv_state, drv_active;
5807ec0effdSAtul Deshmukh int rval;
5817ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
5827ec0effdSAtul Deshmukh
5837ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
5847ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
5857ec0effdSAtul Deshmukh
5867ec0effdSAtul Deshmukh rval = drv_state & (1 << ha->portnum);
5877ec0effdSAtul Deshmukh
5887ec0effdSAtul Deshmukh if (ha->flags.eeh_busy && drv_active)
5897ec0effdSAtul Deshmukh rval = 1;
5907ec0effdSAtul Deshmukh return rval;
5917ec0effdSAtul Deshmukh }
5927ec0effdSAtul Deshmukh
5937ec0effdSAtul Deshmukh /*
5947ec0effdSAtul Deshmukh * qla8044_write_list - Write the value (p_entry->arg2) to address specified
5957ec0effdSAtul Deshmukh * by p_entry->arg1 for all entries in header with delay of p_hdr->delay between
5967ec0effdSAtul Deshmukh * entries.
5977ec0effdSAtul Deshmukh *
5987ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure
5997ec0effdSAtul Deshmukh * @p_hdr : reset_entry header for WRITE_LIST opcode.
6007ec0effdSAtul Deshmukh *
6017ec0effdSAtul Deshmukh */
6027ec0effdSAtul Deshmukh static void
qla8044_write_list(struct scsi_qla_host * vha,struct qla8044_reset_entry_hdr * p_hdr)6037ec0effdSAtul Deshmukh qla8044_write_list(struct scsi_qla_host *vha,
6047ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr)
6057ec0effdSAtul Deshmukh {
6067ec0effdSAtul Deshmukh struct qla8044_entry *p_entry;
6077ec0effdSAtul Deshmukh uint32_t i;
6087ec0effdSAtul Deshmukh
6097ec0effdSAtul Deshmukh p_entry = (struct qla8044_entry *)((char *)p_hdr +
6107ec0effdSAtul Deshmukh sizeof(struct qla8044_reset_entry_hdr));
6117ec0effdSAtul Deshmukh
6127ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) {
6137ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, p_entry->arg1, p_entry->arg2);
6147ec0effdSAtul Deshmukh if (p_hdr->delay)
6157ec0effdSAtul Deshmukh udelay((uint32_t)(p_hdr->delay));
6167ec0effdSAtul Deshmukh }
6177ec0effdSAtul Deshmukh }
6187ec0effdSAtul Deshmukh
6197ec0effdSAtul Deshmukh /*
6207ec0effdSAtul Deshmukh * qla8044_read_write_list - Read from address specified by p_entry->arg1,
6217ec0effdSAtul Deshmukh * write value read to address specified by p_entry->arg2, for all entries in
6227ec0effdSAtul Deshmukh * header with delay of p_hdr->delay between entries.
6237ec0effdSAtul Deshmukh *
6247ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure
6257ec0effdSAtul Deshmukh * @p_hdr : reset_entry header for READ_WRITE_LIST opcode.
6267ec0effdSAtul Deshmukh *
6277ec0effdSAtul Deshmukh */
6287ec0effdSAtul Deshmukh static void
qla8044_read_write_list(struct scsi_qla_host * vha,struct qla8044_reset_entry_hdr * p_hdr)6297ec0effdSAtul Deshmukh qla8044_read_write_list(struct scsi_qla_host *vha,
6307ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr)
6317ec0effdSAtul Deshmukh {
6327ec0effdSAtul Deshmukh struct qla8044_entry *p_entry;
6337ec0effdSAtul Deshmukh uint32_t i;
6347ec0effdSAtul Deshmukh
6357ec0effdSAtul Deshmukh p_entry = (struct qla8044_entry *)((char *)p_hdr +
6367ec0effdSAtul Deshmukh sizeof(struct qla8044_reset_entry_hdr));
6377ec0effdSAtul Deshmukh
6387ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) {
6397ec0effdSAtul Deshmukh qla8044_read_write_crb_reg(vha, p_entry->arg1,
6407ec0effdSAtul Deshmukh p_entry->arg2);
6417ec0effdSAtul Deshmukh if (p_hdr->delay)
6427ec0effdSAtul Deshmukh udelay((uint32_t)(p_hdr->delay));
6437ec0effdSAtul Deshmukh }
6447ec0effdSAtul Deshmukh }
6457ec0effdSAtul Deshmukh
6467ec0effdSAtul Deshmukh /*
6477ec0effdSAtul Deshmukh * qla8044_poll_reg - Poll the given CRB addr for duration msecs till
6487ec0effdSAtul Deshmukh * value read ANDed with test_mask is equal to test_result.
6497ec0effdSAtul Deshmukh *
6507ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure
6517ec0effdSAtul Deshmukh * @addr : CRB register address
6527ec0effdSAtul Deshmukh * @duration : Poll for total of "duration" msecs
6537ec0effdSAtul Deshmukh * @test_mask : Mask value read with "test_mask"
6547ec0effdSAtul Deshmukh * @test_result : Compare (value&test_mask) with test_result.
6557ec0effdSAtul Deshmukh *
6567ec0effdSAtul Deshmukh * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
6577ec0effdSAtul Deshmukh */
6587ec0effdSAtul Deshmukh static int
qla8044_poll_reg(struct scsi_qla_host * vha,uint32_t addr,int duration,uint32_t test_mask,uint32_t test_result)6597ec0effdSAtul Deshmukh qla8044_poll_reg(struct scsi_qla_host *vha, uint32_t addr,
6607ec0effdSAtul Deshmukh int duration, uint32_t test_mask, uint32_t test_result)
6617ec0effdSAtul Deshmukh {
66221a6cd48STom Rix uint32_t value = 0;
6637ec0effdSAtul Deshmukh int timeout_error;
6647ec0effdSAtul Deshmukh uint8_t retries;
6657ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
6667ec0effdSAtul Deshmukh
6677ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
6687ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) {
6697ec0effdSAtul Deshmukh timeout_error = 1;
6707ec0effdSAtul Deshmukh goto exit_poll_reg;
6717ec0effdSAtul Deshmukh }
6727ec0effdSAtul Deshmukh
6737ec0effdSAtul Deshmukh /* poll every 1/10 of the total duration */
6747ec0effdSAtul Deshmukh retries = duration/10;
6757ec0effdSAtul Deshmukh
6767ec0effdSAtul Deshmukh do {
6777ec0effdSAtul Deshmukh if ((value & test_mask) != test_result) {
6787ec0effdSAtul Deshmukh timeout_error = 1;
6797ec0effdSAtul Deshmukh msleep(duration/10);
6807ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha, addr, &value);
6817ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) {
6827ec0effdSAtul Deshmukh timeout_error = 1;
6837ec0effdSAtul Deshmukh goto exit_poll_reg;
6847ec0effdSAtul Deshmukh }
6857ec0effdSAtul Deshmukh } else {
6867ec0effdSAtul Deshmukh timeout_error = 0;
6877ec0effdSAtul Deshmukh break;
6887ec0effdSAtul Deshmukh }
6897ec0effdSAtul Deshmukh } while (retries--);
6907ec0effdSAtul Deshmukh
6917ec0effdSAtul Deshmukh exit_poll_reg:
6927ec0effdSAtul Deshmukh if (timeout_error) {
6937ec0effdSAtul Deshmukh vha->reset_tmplt.seq_error++;
6947ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb090,
6957ec0effdSAtul Deshmukh "%s: Poll Failed: 0x%08x 0x%08x 0x%08x\n",
6967ec0effdSAtul Deshmukh __func__, value, test_mask, test_result);
6977ec0effdSAtul Deshmukh }
6987ec0effdSAtul Deshmukh
6997ec0effdSAtul Deshmukh return timeout_error;
7007ec0effdSAtul Deshmukh }
7017ec0effdSAtul Deshmukh
7027ec0effdSAtul Deshmukh /*
7037ec0effdSAtul Deshmukh * qla8044_poll_list - For all entries in the POLL_LIST header, poll read CRB
7047ec0effdSAtul Deshmukh * register specified by p_entry->arg1 and compare (value AND test_mask) with
7057ec0effdSAtul Deshmukh * test_result to validate it. Wait for p_hdr->delay between processing entries.
7067ec0effdSAtul Deshmukh *
7077ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure
7087ec0effdSAtul Deshmukh * @p_hdr : reset_entry header for POLL_LIST opcode.
7097ec0effdSAtul Deshmukh *
7107ec0effdSAtul Deshmukh */
7117ec0effdSAtul Deshmukh static void
qla8044_poll_list(struct scsi_qla_host * vha,struct qla8044_reset_entry_hdr * p_hdr)7127ec0effdSAtul Deshmukh qla8044_poll_list(struct scsi_qla_host *vha,
7137ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr)
7147ec0effdSAtul Deshmukh {
7157ec0effdSAtul Deshmukh long delay;
7167ec0effdSAtul Deshmukh struct qla8044_entry *p_entry;
7177ec0effdSAtul Deshmukh struct qla8044_poll *p_poll;
7187ec0effdSAtul Deshmukh uint32_t i;
7197ec0effdSAtul Deshmukh uint32_t value;
7207ec0effdSAtul Deshmukh
7217ec0effdSAtul Deshmukh p_poll = (struct qla8044_poll *)
7227ec0effdSAtul Deshmukh ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
7237ec0effdSAtul Deshmukh
7247ec0effdSAtul Deshmukh /* Entries start after 8 byte qla8044_poll, poll header contains
7257ec0effdSAtul Deshmukh * the test_mask, test_value.
7267ec0effdSAtul Deshmukh */
7277ec0effdSAtul Deshmukh p_entry = (struct qla8044_entry *)((char *)p_poll +
7287ec0effdSAtul Deshmukh sizeof(struct qla8044_poll));
7297ec0effdSAtul Deshmukh
7307ec0effdSAtul Deshmukh delay = (long)p_hdr->delay;
7317ec0effdSAtul Deshmukh
7327ec0effdSAtul Deshmukh if (!delay) {
7337ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++)
7347ec0effdSAtul Deshmukh qla8044_poll_reg(vha, p_entry->arg1,
7357ec0effdSAtul Deshmukh delay, p_poll->test_mask, p_poll->test_value);
7367ec0effdSAtul Deshmukh } else {
7377ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) {
7387ec0effdSAtul Deshmukh if (delay) {
7397ec0effdSAtul Deshmukh if (qla8044_poll_reg(vha,
7407ec0effdSAtul Deshmukh p_entry->arg1, delay,
7417ec0effdSAtul Deshmukh p_poll->test_mask,
7427ec0effdSAtul Deshmukh p_poll->test_value)) {
7437ec0effdSAtul Deshmukh /*If
7447ec0effdSAtul Deshmukh * (data_read&test_mask != test_value)
7457ec0effdSAtul Deshmukh * read TIMEOUT_ADDR (arg1) and
7467ec0effdSAtul Deshmukh * ADDR (arg2) registers
7477ec0effdSAtul Deshmukh */
7487ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha,
7497ec0effdSAtul Deshmukh p_entry->arg1, &value);
7507ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha,
7517ec0effdSAtul Deshmukh p_entry->arg2, &value);
7527ec0effdSAtul Deshmukh }
7537ec0effdSAtul Deshmukh }
7547ec0effdSAtul Deshmukh }
7557ec0effdSAtul Deshmukh }
7567ec0effdSAtul Deshmukh }
7577ec0effdSAtul Deshmukh
7587ec0effdSAtul Deshmukh /*
7597ec0effdSAtul Deshmukh * qla8044_poll_write_list - Write dr_value, ar_value to dr_addr/ar_addr,
7607ec0effdSAtul Deshmukh * read ar_addr, if (value& test_mask != test_mask) re-read till timeout
7617ec0effdSAtul Deshmukh * expires.
7627ec0effdSAtul Deshmukh *
7637ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure
7647ec0effdSAtul Deshmukh * @p_hdr : reset entry header for POLL_WRITE_LIST opcode.
7657ec0effdSAtul Deshmukh *
7667ec0effdSAtul Deshmukh */
7677ec0effdSAtul Deshmukh static void
qla8044_poll_write_list(struct scsi_qla_host * vha,struct qla8044_reset_entry_hdr * p_hdr)7687ec0effdSAtul Deshmukh qla8044_poll_write_list(struct scsi_qla_host *vha,
7697ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr)
7707ec0effdSAtul Deshmukh {
7717ec0effdSAtul Deshmukh long delay;
7727ec0effdSAtul Deshmukh struct qla8044_quad_entry *p_entry;
7737ec0effdSAtul Deshmukh struct qla8044_poll *p_poll;
7747ec0effdSAtul Deshmukh uint32_t i;
7757ec0effdSAtul Deshmukh
7767ec0effdSAtul Deshmukh p_poll = (struct qla8044_poll *)((char *)p_hdr +
7777ec0effdSAtul Deshmukh sizeof(struct qla8044_reset_entry_hdr));
7787ec0effdSAtul Deshmukh
7797ec0effdSAtul Deshmukh p_entry = (struct qla8044_quad_entry *)((char *)p_poll +
7807ec0effdSAtul Deshmukh sizeof(struct qla8044_poll));
7817ec0effdSAtul Deshmukh
7827ec0effdSAtul Deshmukh delay = (long)p_hdr->delay;
7837ec0effdSAtul Deshmukh
7847ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) {
7857ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha,
7867ec0effdSAtul Deshmukh p_entry->dr_addr, p_entry->dr_value);
7877ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha,
7887ec0effdSAtul Deshmukh p_entry->ar_addr, p_entry->ar_value);
7897ec0effdSAtul Deshmukh if (delay) {
7907ec0effdSAtul Deshmukh if (qla8044_poll_reg(vha,
7917ec0effdSAtul Deshmukh p_entry->ar_addr, delay,
7927ec0effdSAtul Deshmukh p_poll->test_mask,
7937ec0effdSAtul Deshmukh p_poll->test_value)) {
7947ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb091,
7957ec0effdSAtul Deshmukh "%s: Timeout Error: poll list, ",
7967ec0effdSAtul Deshmukh __func__);
7977ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb092,
7987ec0effdSAtul Deshmukh "item_num %d, entry_num %d\n", i,
7997ec0effdSAtul Deshmukh vha->reset_tmplt.seq_index);
8007ec0effdSAtul Deshmukh }
8017ec0effdSAtul Deshmukh }
8027ec0effdSAtul Deshmukh }
8037ec0effdSAtul Deshmukh }
8047ec0effdSAtul Deshmukh
8057ec0effdSAtul Deshmukh /*
8067ec0effdSAtul Deshmukh * qla8044_read_modify_write - Read value from p_entry->arg1, modify the
8077ec0effdSAtul Deshmukh * value, write value to p_entry->arg2. Process entries with p_hdr->delay
8087ec0effdSAtul Deshmukh * between entries.
8097ec0effdSAtul Deshmukh *
8107ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure
8117ec0effdSAtul Deshmukh * @p_hdr : header with shift/or/xor values.
8127ec0effdSAtul Deshmukh *
8137ec0effdSAtul Deshmukh */
8147ec0effdSAtul Deshmukh static void
qla8044_read_modify_write(struct scsi_qla_host * vha,struct qla8044_reset_entry_hdr * p_hdr)8157ec0effdSAtul Deshmukh qla8044_read_modify_write(struct scsi_qla_host *vha,
8167ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr)
8177ec0effdSAtul Deshmukh {
8187ec0effdSAtul Deshmukh struct qla8044_entry *p_entry;
8197ec0effdSAtul Deshmukh struct qla8044_rmw *p_rmw_hdr;
8207ec0effdSAtul Deshmukh uint32_t i;
8217ec0effdSAtul Deshmukh
8227ec0effdSAtul Deshmukh p_rmw_hdr = (struct qla8044_rmw *)((char *)p_hdr +
8237ec0effdSAtul Deshmukh sizeof(struct qla8044_reset_entry_hdr));
8247ec0effdSAtul Deshmukh
8257ec0effdSAtul Deshmukh p_entry = (struct qla8044_entry *)((char *)p_rmw_hdr +
8267ec0effdSAtul Deshmukh sizeof(struct qla8044_rmw));
8277ec0effdSAtul Deshmukh
8287ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) {
8297ec0effdSAtul Deshmukh qla8044_rmw_crb_reg(vha, p_entry->arg1,
8307ec0effdSAtul Deshmukh p_entry->arg2, p_rmw_hdr);
8317ec0effdSAtul Deshmukh if (p_hdr->delay)
8327ec0effdSAtul Deshmukh udelay((uint32_t)(p_hdr->delay));
8337ec0effdSAtul Deshmukh }
8347ec0effdSAtul Deshmukh }
8357ec0effdSAtul Deshmukh
8367ec0effdSAtul Deshmukh /*
8377ec0effdSAtul Deshmukh * qla8044_pause - Wait for p_hdr->delay msecs, called between processing
8387ec0effdSAtul Deshmukh * two entries of a sequence.
8397ec0effdSAtul Deshmukh *
8407ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure
8417ec0effdSAtul Deshmukh * @p_hdr : Common reset entry header.
8427ec0effdSAtul Deshmukh *
8437ec0effdSAtul Deshmukh */
8447ec0effdSAtul Deshmukh static
qla8044_pause(struct scsi_qla_host * vha,struct qla8044_reset_entry_hdr * p_hdr)8457ec0effdSAtul Deshmukh void qla8044_pause(struct scsi_qla_host *vha,
8467ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr)
8477ec0effdSAtul Deshmukh {
8487ec0effdSAtul Deshmukh if (p_hdr->delay)
8497ec0effdSAtul Deshmukh mdelay((uint32_t)((long)p_hdr->delay));
8507ec0effdSAtul Deshmukh }
8517ec0effdSAtul Deshmukh
8527ec0effdSAtul Deshmukh /*
8537ec0effdSAtul Deshmukh * qla8044_template_end - Indicates end of reset sequence processing.
8547ec0effdSAtul Deshmukh *
8557ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure
8567ec0effdSAtul Deshmukh * @p_hdr : Common reset entry header.
8577ec0effdSAtul Deshmukh *
8587ec0effdSAtul Deshmukh */
8597ec0effdSAtul Deshmukh static void
qla8044_template_end(struct scsi_qla_host * vha,struct qla8044_reset_entry_hdr * p_hdr)8607ec0effdSAtul Deshmukh qla8044_template_end(struct scsi_qla_host *vha,
8617ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr)
8627ec0effdSAtul Deshmukh {
8637ec0effdSAtul Deshmukh vha->reset_tmplt.template_end = 1;
8647ec0effdSAtul Deshmukh
8657ec0effdSAtul Deshmukh if (vha->reset_tmplt.seq_error == 0) {
8667ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb093,
8677ec0effdSAtul Deshmukh "%s: Reset sequence completed SUCCESSFULLY.\n", __func__);
8687ec0effdSAtul Deshmukh } else {
8697ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb094,
8707ec0effdSAtul Deshmukh "%s: Reset sequence completed with some timeout "
8717ec0effdSAtul Deshmukh "errors.\n", __func__);
8727ec0effdSAtul Deshmukh }
8737ec0effdSAtul Deshmukh }
8747ec0effdSAtul Deshmukh
8757ec0effdSAtul Deshmukh /*
8767ec0effdSAtul Deshmukh * qla8044_poll_read_list - Write ar_value to ar_addr register, read ar_addr,
8777ec0effdSAtul Deshmukh * if (value & test_mask != test_value) re-read till timeout value expires,
8787ec0effdSAtul Deshmukh * read dr_addr register and assign to reset_tmplt.array.
8797ec0effdSAtul Deshmukh *
8807ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure
8817ec0effdSAtul Deshmukh * @p_hdr : Common reset entry header.
8827ec0effdSAtul Deshmukh *
8837ec0effdSAtul Deshmukh */
8847ec0effdSAtul Deshmukh static void
qla8044_poll_read_list(struct scsi_qla_host * vha,struct qla8044_reset_entry_hdr * p_hdr)8857ec0effdSAtul Deshmukh qla8044_poll_read_list(struct scsi_qla_host *vha,
8867ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr)
8877ec0effdSAtul Deshmukh {
8887ec0effdSAtul Deshmukh long delay;
8897ec0effdSAtul Deshmukh int index;
8907ec0effdSAtul Deshmukh struct qla8044_quad_entry *p_entry;
8917ec0effdSAtul Deshmukh struct qla8044_poll *p_poll;
8927ec0effdSAtul Deshmukh uint32_t i;
8937ec0effdSAtul Deshmukh uint32_t value;
8947ec0effdSAtul Deshmukh
8957ec0effdSAtul Deshmukh p_poll = (struct qla8044_poll *)
8967ec0effdSAtul Deshmukh ((char *)p_hdr + sizeof(struct qla8044_reset_entry_hdr));
8977ec0effdSAtul Deshmukh
8987ec0effdSAtul Deshmukh p_entry = (struct qla8044_quad_entry *)
8997ec0effdSAtul Deshmukh ((char *)p_poll + sizeof(struct qla8044_poll));
9007ec0effdSAtul Deshmukh
9017ec0effdSAtul Deshmukh delay = (long)p_hdr->delay;
9027ec0effdSAtul Deshmukh
9037ec0effdSAtul Deshmukh for (i = 0; i < p_hdr->count; i++, p_entry++) {
9047ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, p_entry->ar_addr,
9057ec0effdSAtul Deshmukh p_entry->ar_value);
9067ec0effdSAtul Deshmukh if (delay) {
9077ec0effdSAtul Deshmukh if (qla8044_poll_reg(vha, p_entry->ar_addr, delay,
9087ec0effdSAtul Deshmukh p_poll->test_mask, p_poll->test_value)) {
9097ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb095,
9107ec0effdSAtul Deshmukh "%s: Timeout Error: poll "
9117ec0effdSAtul Deshmukh "list, ", __func__);
9127ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb096,
9137ec0effdSAtul Deshmukh "Item_num %d, "
9147ec0effdSAtul Deshmukh "entry_num %d\n", i,
9157ec0effdSAtul Deshmukh vha->reset_tmplt.seq_index);
9167ec0effdSAtul Deshmukh } else {
9177ec0effdSAtul Deshmukh index = vha->reset_tmplt.array_index;
9187ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha,
9197ec0effdSAtul Deshmukh p_entry->dr_addr, &value);
9207ec0effdSAtul Deshmukh vha->reset_tmplt.array[index++] = value;
9217ec0effdSAtul Deshmukh if (index == QLA8044_MAX_RESET_SEQ_ENTRIES)
9227ec0effdSAtul Deshmukh vha->reset_tmplt.array_index = 1;
9237ec0effdSAtul Deshmukh }
9247ec0effdSAtul Deshmukh }
9257ec0effdSAtul Deshmukh }
9267ec0effdSAtul Deshmukh }
9277ec0effdSAtul Deshmukh
9287ec0effdSAtul Deshmukh /*
9297ec0effdSAtul Deshmukh * qla8031_process_reset_template - Process all entries in reset template
9307ec0effdSAtul Deshmukh * till entry with SEQ_END opcode, which indicates end of the reset template
9317ec0effdSAtul Deshmukh * processing. Each entry has a Reset Entry header, entry opcode/command, with
9327ec0effdSAtul Deshmukh * size of the entry, number of entries in sub-sequence and delay in microsecs
9337ec0effdSAtul Deshmukh * or timeout in millisecs.
9347ec0effdSAtul Deshmukh *
9357ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure
9367ec0effdSAtul Deshmukh * @p_buff : Common reset entry header.
9377ec0effdSAtul Deshmukh *
9387ec0effdSAtul Deshmukh */
9397ec0effdSAtul Deshmukh static void
qla8044_process_reset_template(struct scsi_qla_host * vha,char * p_buff)9407ec0effdSAtul Deshmukh qla8044_process_reset_template(struct scsi_qla_host *vha,
9417ec0effdSAtul Deshmukh char *p_buff)
9427ec0effdSAtul Deshmukh {
9437ec0effdSAtul Deshmukh int index, entries;
9447ec0effdSAtul Deshmukh struct qla8044_reset_entry_hdr *p_hdr;
9457ec0effdSAtul Deshmukh char *p_entry = p_buff;
9467ec0effdSAtul Deshmukh
9477ec0effdSAtul Deshmukh vha->reset_tmplt.seq_end = 0;
9487ec0effdSAtul Deshmukh vha->reset_tmplt.template_end = 0;
9497ec0effdSAtul Deshmukh entries = vha->reset_tmplt.hdr->entries;
9507ec0effdSAtul Deshmukh index = vha->reset_tmplt.seq_index;
9517ec0effdSAtul Deshmukh
9527ec0effdSAtul Deshmukh for (; (!vha->reset_tmplt.seq_end) && (index < entries); index++) {
9537ec0effdSAtul Deshmukh p_hdr = (struct qla8044_reset_entry_hdr *)p_entry;
9547ec0effdSAtul Deshmukh switch (p_hdr->cmd) {
9557ec0effdSAtul Deshmukh case OPCODE_NOP:
9567ec0effdSAtul Deshmukh break;
9577ec0effdSAtul Deshmukh case OPCODE_WRITE_LIST:
9587ec0effdSAtul Deshmukh qla8044_write_list(vha, p_hdr);
9597ec0effdSAtul Deshmukh break;
9607ec0effdSAtul Deshmukh case OPCODE_READ_WRITE_LIST:
9617ec0effdSAtul Deshmukh qla8044_read_write_list(vha, p_hdr);
9627ec0effdSAtul Deshmukh break;
9637ec0effdSAtul Deshmukh case OPCODE_POLL_LIST:
9647ec0effdSAtul Deshmukh qla8044_poll_list(vha, p_hdr);
9657ec0effdSAtul Deshmukh break;
9667ec0effdSAtul Deshmukh case OPCODE_POLL_WRITE_LIST:
9677ec0effdSAtul Deshmukh qla8044_poll_write_list(vha, p_hdr);
9687ec0effdSAtul Deshmukh break;
9697ec0effdSAtul Deshmukh case OPCODE_READ_MODIFY_WRITE:
9707ec0effdSAtul Deshmukh qla8044_read_modify_write(vha, p_hdr);
9717ec0effdSAtul Deshmukh break;
9727ec0effdSAtul Deshmukh case OPCODE_SEQ_PAUSE:
9737ec0effdSAtul Deshmukh qla8044_pause(vha, p_hdr);
9747ec0effdSAtul Deshmukh break;
9757ec0effdSAtul Deshmukh case OPCODE_SEQ_END:
9767ec0effdSAtul Deshmukh vha->reset_tmplt.seq_end = 1;
9777ec0effdSAtul Deshmukh break;
9787ec0effdSAtul Deshmukh case OPCODE_TMPL_END:
9797ec0effdSAtul Deshmukh qla8044_template_end(vha, p_hdr);
9807ec0effdSAtul Deshmukh break;
9817ec0effdSAtul Deshmukh case OPCODE_POLL_READ_LIST:
9827ec0effdSAtul Deshmukh qla8044_poll_read_list(vha, p_hdr);
9837ec0effdSAtul Deshmukh break;
9847ec0effdSAtul Deshmukh default:
9857ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb097,
9867ec0effdSAtul Deshmukh "%s: Unknown command ==> 0x%04x on "
9877ec0effdSAtul Deshmukh "entry = %d\n", __func__, p_hdr->cmd, index);
9887ec0effdSAtul Deshmukh break;
9897ec0effdSAtul Deshmukh }
9907ec0effdSAtul Deshmukh /*
9917ec0effdSAtul Deshmukh *Set pointer to next entry in the sequence.
9927ec0effdSAtul Deshmukh */
9937ec0effdSAtul Deshmukh p_entry += p_hdr->size;
9947ec0effdSAtul Deshmukh }
9957ec0effdSAtul Deshmukh vha->reset_tmplt.seq_index = index;
9967ec0effdSAtul Deshmukh }
9977ec0effdSAtul Deshmukh
9987ec0effdSAtul Deshmukh static void
qla8044_process_init_seq(struct scsi_qla_host * vha)9997ec0effdSAtul Deshmukh qla8044_process_init_seq(struct scsi_qla_host *vha)
10007ec0effdSAtul Deshmukh {
10017ec0effdSAtul Deshmukh qla8044_process_reset_template(vha,
10027ec0effdSAtul Deshmukh vha->reset_tmplt.init_offset);
10037ec0effdSAtul Deshmukh if (vha->reset_tmplt.seq_end != 1)
10047ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb098,
10057ec0effdSAtul Deshmukh "%s: Abrupt INIT Sub-Sequence end.\n",
10067ec0effdSAtul Deshmukh __func__);
10077ec0effdSAtul Deshmukh }
10087ec0effdSAtul Deshmukh
10097ec0effdSAtul Deshmukh static void
qla8044_process_stop_seq(struct scsi_qla_host * vha)10107ec0effdSAtul Deshmukh qla8044_process_stop_seq(struct scsi_qla_host *vha)
10117ec0effdSAtul Deshmukh {
10127ec0effdSAtul Deshmukh vha->reset_tmplt.seq_index = 0;
10137ec0effdSAtul Deshmukh qla8044_process_reset_template(vha, vha->reset_tmplt.stop_offset);
10147ec0effdSAtul Deshmukh if (vha->reset_tmplt.seq_end != 1)
10157ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb099,
10167ec0effdSAtul Deshmukh "%s: Abrupt STOP Sub-Sequence end.\n", __func__);
10177ec0effdSAtul Deshmukh }
10187ec0effdSAtul Deshmukh
10197ec0effdSAtul Deshmukh static void
qla8044_process_start_seq(struct scsi_qla_host * vha)10207ec0effdSAtul Deshmukh qla8044_process_start_seq(struct scsi_qla_host *vha)
10217ec0effdSAtul Deshmukh {
10227ec0effdSAtul Deshmukh qla8044_process_reset_template(vha, vha->reset_tmplt.start_offset);
10237ec0effdSAtul Deshmukh if (vha->reset_tmplt.template_end != 1)
10247ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb09a,
10257ec0effdSAtul Deshmukh "%s: Abrupt START Sub-Sequence end.\n",
10267ec0effdSAtul Deshmukh __func__);
10277ec0effdSAtul Deshmukh }
10287ec0effdSAtul Deshmukh
10297ec0effdSAtul Deshmukh static int
qla8044_lockless_flash_read_u32(struct scsi_qla_host * vha,uint32_t flash_addr,uint8_t * p_data,int u32_word_count)10307ec0effdSAtul Deshmukh qla8044_lockless_flash_read_u32(struct scsi_qla_host *vha,
10317ec0effdSAtul Deshmukh uint32_t flash_addr, uint8_t *p_data, int u32_word_count)
10327ec0effdSAtul Deshmukh {
10337ec0effdSAtul Deshmukh uint32_t i;
10347ec0effdSAtul Deshmukh uint32_t u32_word;
10357ec0effdSAtul Deshmukh uint32_t flash_offset;
10367ec0effdSAtul Deshmukh uint32_t addr = flash_addr;
10377ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
10387ec0effdSAtul Deshmukh
10397ec0effdSAtul Deshmukh flash_offset = addr & (QLA8044_FLASH_SECTOR_SIZE - 1);
10407ec0effdSAtul Deshmukh
10417ec0effdSAtul Deshmukh if (addr & 0x3) {
10427ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb09b, "%s: Illegal addr = 0x%x\n",
10437ec0effdSAtul Deshmukh __func__, addr);
10447ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
10457ec0effdSAtul Deshmukh goto exit_lockless_read;
10467ec0effdSAtul Deshmukh }
10477ec0effdSAtul Deshmukh
10487ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha,
10497ec0effdSAtul Deshmukh QLA8044_FLASH_DIRECT_WINDOW, (addr));
10507ec0effdSAtul Deshmukh
10517ec0effdSAtul Deshmukh if (ret_val != QLA_SUCCESS) {
10527ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb09c,
10537ec0effdSAtul Deshmukh "%s: failed to write addr 0x%x to FLASH_DIRECT_WINDOW!\n",
10547ec0effdSAtul Deshmukh __func__, addr);
10557ec0effdSAtul Deshmukh goto exit_lockless_read;
10567ec0effdSAtul Deshmukh }
10577ec0effdSAtul Deshmukh
10587ec0effdSAtul Deshmukh /* Check if data is spread across multiple sectors */
10597ec0effdSAtul Deshmukh if ((flash_offset + (u32_word_count * sizeof(uint32_t))) >
10607ec0effdSAtul Deshmukh (QLA8044_FLASH_SECTOR_SIZE - 1)) {
10617ec0effdSAtul Deshmukh /* Multi sector read */
10627ec0effdSAtul Deshmukh for (i = 0; i < u32_word_count; i++) {
10637ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha,
10647ec0effdSAtul Deshmukh QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
10657ec0effdSAtul Deshmukh if (ret_val != QLA_SUCCESS) {
10667ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb09d,
10677ec0effdSAtul Deshmukh "%s: failed to read addr 0x%x!\n",
10687ec0effdSAtul Deshmukh __func__, addr);
10697ec0effdSAtul Deshmukh goto exit_lockless_read;
10707ec0effdSAtul Deshmukh }
10717ec0effdSAtul Deshmukh *(uint32_t *)p_data = u32_word;
10727ec0effdSAtul Deshmukh p_data = p_data + 4;
10737ec0effdSAtul Deshmukh addr = addr + 4;
10747ec0effdSAtul Deshmukh flash_offset = flash_offset + 4;
10757ec0effdSAtul Deshmukh if (flash_offset > (QLA8044_FLASH_SECTOR_SIZE - 1)) {
10767ec0effdSAtul Deshmukh /* This write is needed once for each sector */
10777ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha,
10787ec0effdSAtul Deshmukh QLA8044_FLASH_DIRECT_WINDOW, (addr));
10797ec0effdSAtul Deshmukh if (ret_val != QLA_SUCCESS) {
10807ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb09f,
10817ec0effdSAtul Deshmukh "%s: failed to write addr "
10827ec0effdSAtul Deshmukh "0x%x to FLASH_DIRECT_WINDOW!\n",
10837ec0effdSAtul Deshmukh __func__, addr);
10847ec0effdSAtul Deshmukh goto exit_lockless_read;
10857ec0effdSAtul Deshmukh }
10867ec0effdSAtul Deshmukh flash_offset = 0;
10877ec0effdSAtul Deshmukh }
10887ec0effdSAtul Deshmukh }
10897ec0effdSAtul Deshmukh } else {
10907ec0effdSAtul Deshmukh /* Single sector read */
10917ec0effdSAtul Deshmukh for (i = 0; i < u32_word_count; i++) {
10927ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha,
10937ec0effdSAtul Deshmukh QLA8044_FLASH_DIRECT_DATA(addr), &u32_word);
10947ec0effdSAtul Deshmukh if (ret_val != QLA_SUCCESS) {
10957ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a0,
10967ec0effdSAtul Deshmukh "%s: failed to read addr 0x%x!\n",
10977ec0effdSAtul Deshmukh __func__, addr);
10987ec0effdSAtul Deshmukh goto exit_lockless_read;
10997ec0effdSAtul Deshmukh }
11007ec0effdSAtul Deshmukh *(uint32_t *)p_data = u32_word;
11017ec0effdSAtul Deshmukh p_data = p_data + 4;
11027ec0effdSAtul Deshmukh addr = addr + 4;
11037ec0effdSAtul Deshmukh }
11047ec0effdSAtul Deshmukh }
11057ec0effdSAtul Deshmukh
11067ec0effdSAtul Deshmukh exit_lockless_read:
11077ec0effdSAtul Deshmukh return ret_val;
11087ec0effdSAtul Deshmukh }
11097ec0effdSAtul Deshmukh
11107ec0effdSAtul Deshmukh /*
11117ec0effdSAtul Deshmukh * qla8044_ms_mem_write_128b - Writes data to MS/off-chip memory
11127ec0effdSAtul Deshmukh *
11137ec0effdSAtul Deshmukh * @vha : Pointer to adapter structure
11147ec0effdSAtul Deshmukh * addr : Flash address to write to
11157ec0effdSAtul Deshmukh * data : Data to be written
11167ec0effdSAtul Deshmukh * count : word_count to be written
11177ec0effdSAtul Deshmukh *
11187ec0effdSAtul Deshmukh * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
11197ec0effdSAtul Deshmukh */
11207ec0effdSAtul Deshmukh static int
qla8044_ms_mem_write_128b(struct scsi_qla_host * vha,uint64_t addr,uint32_t * data,uint32_t count)11217ec0effdSAtul Deshmukh qla8044_ms_mem_write_128b(struct scsi_qla_host *vha,
11227ec0effdSAtul Deshmukh uint64_t addr, uint32_t *data, uint32_t count)
11237ec0effdSAtul Deshmukh {
11247ec0effdSAtul Deshmukh int i, j, ret_val = QLA_SUCCESS;
11257ec0effdSAtul Deshmukh uint32_t agt_ctrl;
11267ec0effdSAtul Deshmukh unsigned long flags;
11277ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
11287ec0effdSAtul Deshmukh
11297ec0effdSAtul Deshmukh /* Only 128-bit aligned access */
11307ec0effdSAtul Deshmukh if (addr & 0xF) {
11317ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
11327ec0effdSAtul Deshmukh goto exit_ms_mem_write;
11337ec0effdSAtul Deshmukh }
11347ec0effdSAtul Deshmukh write_lock_irqsave(&ha->hw_lock, flags);
11357ec0effdSAtul Deshmukh
11367ec0effdSAtul Deshmukh /* Write address */
11377ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, 0);
11387ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) {
11397ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a1,
11407ec0effdSAtul Deshmukh "%s: write to AGT_ADDR_HI failed!\n", __func__);
11417ec0effdSAtul Deshmukh goto exit_ms_mem_write_unlock;
11427ec0effdSAtul Deshmukh }
11437ec0effdSAtul Deshmukh
11447ec0effdSAtul Deshmukh for (i = 0; i < count; i++, addr += 16) {
1145df3f4cd0SBart Van Assche if (!((addr_in_range(addr, QLA8044_ADDR_QDR_NET,
11467ec0effdSAtul Deshmukh QLA8044_ADDR_QDR_NET_MAX)) ||
1147df3f4cd0SBart Van Assche (addr_in_range(addr, QLA8044_ADDR_DDR_NET,
11487ec0effdSAtul Deshmukh QLA8044_ADDR_DDR_NET_MAX)))) {
11497ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
11507ec0effdSAtul Deshmukh goto exit_ms_mem_write_unlock;
11517ec0effdSAtul Deshmukh }
11527ec0effdSAtul Deshmukh
11537ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha,
11547ec0effdSAtul Deshmukh MD_MIU_TEST_AGT_ADDR_LO, addr);
11557ec0effdSAtul Deshmukh
11567ec0effdSAtul Deshmukh /* Write data */
11577ec0effdSAtul Deshmukh ret_val += qla8044_wr_reg_indirect(vha,
11587ec0effdSAtul Deshmukh MD_MIU_TEST_AGT_WRDATA_LO, *data++);
11597ec0effdSAtul Deshmukh ret_val += qla8044_wr_reg_indirect(vha,
11607ec0effdSAtul Deshmukh MD_MIU_TEST_AGT_WRDATA_HI, *data++);
11617ec0effdSAtul Deshmukh ret_val += qla8044_wr_reg_indirect(vha,
11627ec0effdSAtul Deshmukh MD_MIU_TEST_AGT_WRDATA_ULO, *data++);
11637ec0effdSAtul Deshmukh ret_val += qla8044_wr_reg_indirect(vha,
11647ec0effdSAtul Deshmukh MD_MIU_TEST_AGT_WRDATA_UHI, *data++);
11657ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) {
11667ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a2,
11677ec0effdSAtul Deshmukh "%s: write to AGT_WRDATA failed!\n",
11687ec0effdSAtul Deshmukh __func__);
11697ec0effdSAtul Deshmukh goto exit_ms_mem_write_unlock;
11707ec0effdSAtul Deshmukh }
11717ec0effdSAtul Deshmukh
11727ec0effdSAtul Deshmukh /* Check write status */
11737ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
11747ec0effdSAtul Deshmukh MIU_TA_CTL_WRITE_ENABLE);
11757ec0effdSAtul Deshmukh ret_val += qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
11767ec0effdSAtul Deshmukh MIU_TA_CTL_WRITE_START);
11777ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) {
11787ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a3,
11797ec0effdSAtul Deshmukh "%s: write to AGT_CTRL failed!\n", __func__);
11807ec0effdSAtul Deshmukh goto exit_ms_mem_write_unlock;
11817ec0effdSAtul Deshmukh }
11827ec0effdSAtul Deshmukh
11837ec0effdSAtul Deshmukh for (j = 0; j < MAX_CTL_CHECK; j++) {
11847ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha,
11857ec0effdSAtul Deshmukh MD_MIU_TEST_AGT_CTRL, &agt_ctrl);
11867ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) {
11877ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a4,
11887ec0effdSAtul Deshmukh "%s: failed to read "
11897ec0effdSAtul Deshmukh "MD_MIU_TEST_AGT_CTRL!\n", __func__);
11907ec0effdSAtul Deshmukh goto exit_ms_mem_write_unlock;
11917ec0effdSAtul Deshmukh }
11927ec0effdSAtul Deshmukh if ((agt_ctrl & MIU_TA_CTL_BUSY) == 0)
11937ec0effdSAtul Deshmukh break;
11947ec0effdSAtul Deshmukh }
11957ec0effdSAtul Deshmukh
11967ec0effdSAtul Deshmukh /* Status check failed */
11977ec0effdSAtul Deshmukh if (j >= MAX_CTL_CHECK) {
11987ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a5,
11997ec0effdSAtul Deshmukh "%s: MS memory write failed!\n",
12007ec0effdSAtul Deshmukh __func__);
12017ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
12027ec0effdSAtul Deshmukh goto exit_ms_mem_write_unlock;
12037ec0effdSAtul Deshmukh }
12047ec0effdSAtul Deshmukh }
12057ec0effdSAtul Deshmukh
12067ec0effdSAtul Deshmukh exit_ms_mem_write_unlock:
12077ec0effdSAtul Deshmukh write_unlock_irqrestore(&ha->hw_lock, flags);
12087ec0effdSAtul Deshmukh
12097ec0effdSAtul Deshmukh exit_ms_mem_write:
12107ec0effdSAtul Deshmukh return ret_val;
12117ec0effdSAtul Deshmukh }
12127ec0effdSAtul Deshmukh
12137ec0effdSAtul Deshmukh static int
qla8044_copy_bootloader(struct scsi_qla_host * vha)12147ec0effdSAtul Deshmukh qla8044_copy_bootloader(struct scsi_qla_host *vha)
12157ec0effdSAtul Deshmukh {
12167ec0effdSAtul Deshmukh uint8_t *p_cache;
12177ec0effdSAtul Deshmukh uint32_t src, count, size;
12187ec0effdSAtul Deshmukh uint64_t dest;
12197ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
12207ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
12217ec0effdSAtul Deshmukh
12227ec0effdSAtul Deshmukh src = QLA8044_BOOTLOADER_FLASH_ADDR;
12237ec0effdSAtul Deshmukh dest = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_ADDR);
12247ec0effdSAtul Deshmukh size = qla8044_rd_reg(ha, QLA8044_BOOTLOADER_SIZE);
12257ec0effdSAtul Deshmukh
12267ec0effdSAtul Deshmukh /* 128 bit alignment check */
12277ec0effdSAtul Deshmukh if (size & 0xF)
12287ec0effdSAtul Deshmukh size = (size + 16) & ~0xF;
12297ec0effdSAtul Deshmukh
12307ec0effdSAtul Deshmukh /* 16 byte count */
12317ec0effdSAtul Deshmukh count = size/16;
12327ec0effdSAtul Deshmukh
12337ec0effdSAtul Deshmukh p_cache = vmalloc(size);
12347ec0effdSAtul Deshmukh if (p_cache == NULL) {
12357ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a6,
12367ec0effdSAtul Deshmukh "%s: Failed to allocate memory for "
12377ec0effdSAtul Deshmukh "boot loader cache\n", __func__);
12387ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
12397ec0effdSAtul Deshmukh goto exit_copy_bootloader;
12407ec0effdSAtul Deshmukh }
12417ec0effdSAtul Deshmukh
12427ec0effdSAtul Deshmukh ret_val = qla8044_lockless_flash_read_u32(vha, src,
12437ec0effdSAtul Deshmukh p_cache, size/sizeof(uint32_t));
12447ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) {
12457ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a7,
12467ec0effdSAtul Deshmukh "%s: Error reading F/W from flash!!!\n", __func__);
12477ec0effdSAtul Deshmukh goto exit_copy_error;
12487ec0effdSAtul Deshmukh }
12497ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0a8, "%s: Read F/W from flash!\n",
12507ec0effdSAtul Deshmukh __func__);
12517ec0effdSAtul Deshmukh
12527ec0effdSAtul Deshmukh /* 128 bit/16 byte write to MS memory */
12537ec0effdSAtul Deshmukh ret_val = qla8044_ms_mem_write_128b(vha, dest,
12547ec0effdSAtul Deshmukh (uint32_t *)p_cache, count);
12557ec0effdSAtul Deshmukh if (ret_val == QLA_FUNCTION_FAILED) {
12567ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0a9,
12577ec0effdSAtul Deshmukh "%s: Error writing F/W to MS !!!\n", __func__);
12587ec0effdSAtul Deshmukh goto exit_copy_error;
12597ec0effdSAtul Deshmukh }
12607ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0aa,
12617ec0effdSAtul Deshmukh "%s: Wrote F/W (size %d) to MS !!!\n",
12627ec0effdSAtul Deshmukh __func__, size);
12637ec0effdSAtul Deshmukh
12647ec0effdSAtul Deshmukh exit_copy_error:
12657ec0effdSAtul Deshmukh vfree(p_cache);
12667ec0effdSAtul Deshmukh
12677ec0effdSAtul Deshmukh exit_copy_bootloader:
12687ec0effdSAtul Deshmukh return ret_val;
12697ec0effdSAtul Deshmukh }
12707ec0effdSAtul Deshmukh
12717ec0effdSAtul Deshmukh static int
qla8044_restart(struct scsi_qla_host * vha)12727ec0effdSAtul Deshmukh qla8044_restart(struct scsi_qla_host *vha)
12737ec0effdSAtul Deshmukh {
12747ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
12757ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
12767ec0effdSAtul Deshmukh
12777ec0effdSAtul Deshmukh qla8044_process_stop_seq(vha);
12787ec0effdSAtul Deshmukh
12797ec0effdSAtul Deshmukh /* Collect minidump */
12807ec0effdSAtul Deshmukh if (ql2xmdenable)
12817ec0effdSAtul Deshmukh qla8044_get_minidump(vha);
12827ec0effdSAtul Deshmukh else
12837ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb14c,
12847ec0effdSAtul Deshmukh "Minidump disabled.\n");
12857ec0effdSAtul Deshmukh
12867ec0effdSAtul Deshmukh qla8044_process_init_seq(vha);
12877ec0effdSAtul Deshmukh
12887ec0effdSAtul Deshmukh if (qla8044_copy_bootloader(vha)) {
12897ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0ab,
12907ec0effdSAtul Deshmukh "%s: Copy bootloader, firmware restart failed!\n",
12917ec0effdSAtul Deshmukh __func__);
12927ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
12937ec0effdSAtul Deshmukh goto exit_restart;
12947ec0effdSAtul Deshmukh }
12957ec0effdSAtul Deshmukh
12967ec0effdSAtul Deshmukh /*
12977ec0effdSAtul Deshmukh * Loads F/W from flash
12987ec0effdSAtul Deshmukh */
12997ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_FW_IMAGE_VALID, QLA8044_BOOT_FROM_FLASH);
13007ec0effdSAtul Deshmukh
13017ec0effdSAtul Deshmukh qla8044_process_start_seq(vha);
13027ec0effdSAtul Deshmukh
13037ec0effdSAtul Deshmukh exit_restart:
13047ec0effdSAtul Deshmukh return ret_val;
13057ec0effdSAtul Deshmukh }
13067ec0effdSAtul Deshmukh
13077ec0effdSAtul Deshmukh /*
13087ec0effdSAtul Deshmukh * qla8044_check_cmd_peg_status - Check peg status to see if Peg is
13097ec0effdSAtul Deshmukh * initialized.
13107ec0effdSAtul Deshmukh *
13117ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure
13127ec0effdSAtul Deshmukh *
13137ec0effdSAtul Deshmukh * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
13147ec0effdSAtul Deshmukh */
13157ec0effdSAtul Deshmukh static int
qla8044_check_cmd_peg_status(struct scsi_qla_host * vha)13167ec0effdSAtul Deshmukh qla8044_check_cmd_peg_status(struct scsi_qla_host *vha)
13177ec0effdSAtul Deshmukh {
13187ec0effdSAtul Deshmukh uint32_t val, ret_val = QLA_FUNCTION_FAILED;
13197ec0effdSAtul Deshmukh int retries = CRB_CMDPEG_CHECK_RETRY_COUNT;
13207ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
13217ec0effdSAtul Deshmukh
13227ec0effdSAtul Deshmukh do {
13237ec0effdSAtul Deshmukh val = qla8044_rd_reg(ha, QLA8044_CMDPEG_STATE);
13247ec0effdSAtul Deshmukh if (val == PHAN_INITIALIZE_COMPLETE) {
13257ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0ac,
13267ec0effdSAtul Deshmukh "%s: Command Peg initialization "
13277ec0effdSAtul Deshmukh "complete! state=0x%x\n", __func__, val);
13287ec0effdSAtul Deshmukh ret_val = QLA_SUCCESS;
13297ec0effdSAtul Deshmukh break;
13307ec0effdSAtul Deshmukh }
13317ec0effdSAtul Deshmukh msleep(CRB_CMDPEG_CHECK_DELAY);
13327ec0effdSAtul Deshmukh } while (--retries);
13337ec0effdSAtul Deshmukh
13347ec0effdSAtul Deshmukh return ret_val;
13357ec0effdSAtul Deshmukh }
13367ec0effdSAtul Deshmukh
13377ec0effdSAtul Deshmukh static int
qla8044_start_firmware(struct scsi_qla_host * vha)13387ec0effdSAtul Deshmukh qla8044_start_firmware(struct scsi_qla_host *vha)
13397ec0effdSAtul Deshmukh {
13407ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
13417ec0effdSAtul Deshmukh
13427ec0effdSAtul Deshmukh if (qla8044_restart(vha)) {
13437ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0ad,
13447ec0effdSAtul Deshmukh "%s: Restart Error!!!, Need Reset!!!\n",
13457ec0effdSAtul Deshmukh __func__);
13467ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
13477ec0effdSAtul Deshmukh goto exit_start_fw;
13487ec0effdSAtul Deshmukh } else
13497ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0af,
13507ec0effdSAtul Deshmukh "%s: Restart done!\n", __func__);
13517ec0effdSAtul Deshmukh
13527ec0effdSAtul Deshmukh ret_val = qla8044_check_cmd_peg_status(vha);
13537ec0effdSAtul Deshmukh if (ret_val) {
13547ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0b0,
13557ec0effdSAtul Deshmukh "%s: Peg not initialized!\n", __func__);
13567ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
13577ec0effdSAtul Deshmukh }
13587ec0effdSAtul Deshmukh
13597ec0effdSAtul Deshmukh exit_start_fw:
13607ec0effdSAtul Deshmukh return ret_val;
13617ec0effdSAtul Deshmukh }
13627ec0effdSAtul Deshmukh
13637ec0effdSAtul Deshmukh void
qla8044_clear_drv_active(struct qla_hw_data * ha)1364c41afc9aSSaurav Kashyap qla8044_clear_drv_active(struct qla_hw_data *ha)
13657ec0effdSAtul Deshmukh {
13667ec0effdSAtul Deshmukh uint32_t drv_active;
1367c41afc9aSSaurav Kashyap struct scsi_qla_host *vha = pci_get_drvdata(ha->pdev);
13687ec0effdSAtul Deshmukh
13697ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
13707ec0effdSAtul Deshmukh drv_active &= ~(1 << (ha->portnum));
13717ec0effdSAtul Deshmukh
13727ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0b1,
13737ec0effdSAtul Deshmukh "%s(%ld): drv_active: 0x%08x\n",
13747ec0effdSAtul Deshmukh __func__, vha->host_no, drv_active);
13757ec0effdSAtul Deshmukh
13767ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
13777ec0effdSAtul Deshmukh }
13787ec0effdSAtul Deshmukh
13797ec0effdSAtul Deshmukh /*
13807ec0effdSAtul Deshmukh * qla8044_device_bootstrap - Initialize device, set DEV_READY, start fw
13817ec0effdSAtul Deshmukh * @ha: pointer to adapter structure
13827ec0effdSAtul Deshmukh *
13837ec0effdSAtul Deshmukh * Note: IDC lock must be held upon entry
13847ec0effdSAtul Deshmukh **/
13857ec0effdSAtul Deshmukh static int
qla8044_device_bootstrap(struct scsi_qla_host * vha)13867ec0effdSAtul Deshmukh qla8044_device_bootstrap(struct scsi_qla_host *vha)
13877ec0effdSAtul Deshmukh {
13887ec0effdSAtul Deshmukh int rval = QLA_FUNCTION_FAILED;
13897ec0effdSAtul Deshmukh int i;
13907ec0effdSAtul Deshmukh uint32_t old_count = 0, count = 0;
13917ec0effdSAtul Deshmukh int need_reset = 0;
13927ec0effdSAtul Deshmukh uint32_t idc_ctrl;
13937ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
13947ec0effdSAtul Deshmukh
13957ec0effdSAtul Deshmukh need_reset = qla8044_need_reset(vha);
13967ec0effdSAtul Deshmukh
13977ec0effdSAtul Deshmukh if (!need_reset) {
13987ec0effdSAtul Deshmukh old_count = qla8044_rd_direct(vha,
13997ec0effdSAtul Deshmukh QLA8044_PEG_ALIVE_COUNTER_INDEX);
14007ec0effdSAtul Deshmukh
14017ec0effdSAtul Deshmukh for (i = 0; i < 10; i++) {
14027ec0effdSAtul Deshmukh msleep(200);
14037ec0effdSAtul Deshmukh
14047ec0effdSAtul Deshmukh count = qla8044_rd_direct(vha,
14057ec0effdSAtul Deshmukh QLA8044_PEG_ALIVE_COUNTER_INDEX);
14067ec0effdSAtul Deshmukh if (count != old_count) {
14077ec0effdSAtul Deshmukh rval = QLA_SUCCESS;
14087ec0effdSAtul Deshmukh goto dev_ready;
14097ec0effdSAtul Deshmukh }
14107ec0effdSAtul Deshmukh }
14117ec0effdSAtul Deshmukh qla8044_flash_lock_recovery(vha);
14127ec0effdSAtul Deshmukh } else {
14137ec0effdSAtul Deshmukh /* We are trying to perform a recovery here. */
14147ec0effdSAtul Deshmukh if (ha->flags.isp82xx_fw_hung)
14157ec0effdSAtul Deshmukh qla8044_flash_lock_recovery(vha);
14167ec0effdSAtul Deshmukh }
14177ec0effdSAtul Deshmukh
14187ec0effdSAtul Deshmukh /* set to DEV_INITIALIZING */
14197ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0b2,
14207ec0effdSAtul Deshmukh "%s: HW State: INITIALIZING\n", __func__);
14217ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
14227ec0effdSAtul Deshmukh QLA8XXX_DEV_INITIALIZING);
14237ec0effdSAtul Deshmukh
14247ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
14257ec0effdSAtul Deshmukh rval = qla8044_start_firmware(vha);
14267ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
14277ec0effdSAtul Deshmukh
14287ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) {
14297ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0b3,
14307ec0effdSAtul Deshmukh "%s: HW State: FAILED\n", __func__);
1431c41afc9aSSaurav Kashyap qla8044_clear_drv_active(ha);
14327ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
14337ec0effdSAtul Deshmukh QLA8XXX_DEV_FAILED);
14347ec0effdSAtul Deshmukh return rval;
14357ec0effdSAtul Deshmukh }
14367ec0effdSAtul Deshmukh
14377ec0effdSAtul Deshmukh /* For ISP8044, If IDC_CTRL GRACEFUL_RESET_BIT1 is set , reset it after
14387ec0effdSAtul Deshmukh * device goes to INIT state. */
14397ec0effdSAtul Deshmukh idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
14407ec0effdSAtul Deshmukh if (idc_ctrl & GRACEFUL_RESET_BIT1) {
14417ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
14427ec0effdSAtul Deshmukh (idc_ctrl & ~GRACEFUL_RESET_BIT1));
1443dbe6f492SJason Yan ha->fw_dumped = false;
14447ec0effdSAtul Deshmukh }
14457ec0effdSAtul Deshmukh
14467ec0effdSAtul Deshmukh dev_ready:
14477ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0b4,
14487ec0effdSAtul Deshmukh "%s: HW State: READY\n", __func__);
14497ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX, QLA8XXX_DEV_READY);
14507ec0effdSAtul Deshmukh
14517ec0effdSAtul Deshmukh return rval;
14527ec0effdSAtul Deshmukh }
14537ec0effdSAtul Deshmukh
14547ec0effdSAtul Deshmukh /*-------------------------Reset Sequence Functions-----------------------*/
14557ec0effdSAtul Deshmukh static void
qla8044_dump_reset_seq_hdr(struct scsi_qla_host * vha)14567ec0effdSAtul Deshmukh qla8044_dump_reset_seq_hdr(struct scsi_qla_host *vha)
14577ec0effdSAtul Deshmukh {
14587ec0effdSAtul Deshmukh u8 *phdr;
14597ec0effdSAtul Deshmukh
14607ec0effdSAtul Deshmukh if (!vha->reset_tmplt.buff) {
14617ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0b5,
14627ec0effdSAtul Deshmukh "%s: Error Invalid reset_seq_template\n", __func__);
14637ec0effdSAtul Deshmukh return;
14647ec0effdSAtul Deshmukh }
14657ec0effdSAtul Deshmukh
14667ec0effdSAtul Deshmukh phdr = vha->reset_tmplt.buff;
14677ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0b6,
14687ec0effdSAtul Deshmukh "Reset Template :\n\t0x%X 0x%X 0x%X 0x%X"
14697ec0effdSAtul Deshmukh "0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n"
14707ec0effdSAtul Deshmukh "\t0x%X 0x%X 0x%X 0x%X 0x%X 0x%X\n\n",
14717ec0effdSAtul Deshmukh *phdr, *(phdr+1), *(phdr+2), *(phdr+3), *(phdr+4),
14727ec0effdSAtul Deshmukh *(phdr+5), *(phdr+6), *(phdr+7), *(phdr + 8),
14737ec0effdSAtul Deshmukh *(phdr+9), *(phdr+10), *(phdr+11), *(phdr+12),
14747ec0effdSAtul Deshmukh *(phdr+13), *(phdr+14), *(phdr+15));
14757ec0effdSAtul Deshmukh }
14767ec0effdSAtul Deshmukh
14777ec0effdSAtul Deshmukh /*
14787ec0effdSAtul Deshmukh * qla8044_reset_seq_checksum_test - Validate Reset Sequence template.
14797ec0effdSAtul Deshmukh *
14807ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure
14817ec0effdSAtul Deshmukh *
14827ec0effdSAtul Deshmukh * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
14837ec0effdSAtul Deshmukh */
14847ec0effdSAtul Deshmukh static int
qla8044_reset_seq_checksum_test(struct scsi_qla_host * vha)14857ec0effdSAtul Deshmukh qla8044_reset_seq_checksum_test(struct scsi_qla_host *vha)
14867ec0effdSAtul Deshmukh {
14877ec0effdSAtul Deshmukh uint32_t sum = 0;
14887ec0effdSAtul Deshmukh uint16_t *buff = (uint16_t *)vha->reset_tmplt.buff;
14897ec0effdSAtul Deshmukh int u16_count = vha->reset_tmplt.hdr->size / sizeof(uint16_t);
14907ec0effdSAtul Deshmukh
14917ec0effdSAtul Deshmukh while (u16_count-- > 0)
14927ec0effdSAtul Deshmukh sum += *buff++;
14937ec0effdSAtul Deshmukh
14947ec0effdSAtul Deshmukh while (sum >> 16)
14957ec0effdSAtul Deshmukh sum = (sum & 0xFFFF) + (sum >> 16);
14967ec0effdSAtul Deshmukh
14977ec0effdSAtul Deshmukh /* checksum of 0 indicates a valid template */
14987ec0effdSAtul Deshmukh if (~sum) {
14997ec0effdSAtul Deshmukh return QLA_SUCCESS;
15007ec0effdSAtul Deshmukh } else {
15017ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0b7,
15027ec0effdSAtul Deshmukh "%s: Reset seq checksum failed\n", __func__);
15037ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
15047ec0effdSAtul Deshmukh }
15057ec0effdSAtul Deshmukh }
15067ec0effdSAtul Deshmukh
15077ec0effdSAtul Deshmukh /*
15087ec0effdSAtul Deshmukh * qla8044_read_reset_template - Read Reset Template from Flash, validate
15097ec0effdSAtul Deshmukh * the template and store offsets of stop/start/init offsets in ha->reset_tmplt.
15107ec0effdSAtul Deshmukh *
15117ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure
15127ec0effdSAtul Deshmukh */
15137ec0effdSAtul Deshmukh void
qla8044_read_reset_template(struct scsi_qla_host * vha)15147ec0effdSAtul Deshmukh qla8044_read_reset_template(struct scsi_qla_host *vha)
15157ec0effdSAtul Deshmukh {
15167ec0effdSAtul Deshmukh uint8_t *p_buff;
15177ec0effdSAtul Deshmukh uint32_t addr, tmplt_hdr_def_size, tmplt_hdr_size;
15187ec0effdSAtul Deshmukh
15197ec0effdSAtul Deshmukh vha->reset_tmplt.seq_error = 0;
15207ec0effdSAtul Deshmukh vha->reset_tmplt.buff = vmalloc(QLA8044_RESTART_TEMPLATE_SIZE);
15217ec0effdSAtul Deshmukh if (vha->reset_tmplt.buff == NULL) {
15227ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0b8,
15237ec0effdSAtul Deshmukh "%s: Failed to allocate reset template resources\n",
15247ec0effdSAtul Deshmukh __func__);
15257ec0effdSAtul Deshmukh goto exit_read_reset_template;
15267ec0effdSAtul Deshmukh }
15277ec0effdSAtul Deshmukh
15287ec0effdSAtul Deshmukh p_buff = vha->reset_tmplt.buff;
15297ec0effdSAtul Deshmukh addr = QLA8044_RESET_TEMPLATE_ADDR;
15307ec0effdSAtul Deshmukh
15317ec0effdSAtul Deshmukh tmplt_hdr_def_size =
15327ec0effdSAtul Deshmukh sizeof(struct qla8044_reset_template_hdr) / sizeof(uint32_t);
15337ec0effdSAtul Deshmukh
15347ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0b9,
15357ec0effdSAtul Deshmukh "%s: Read template hdr size %d from Flash\n",
15367ec0effdSAtul Deshmukh __func__, tmplt_hdr_def_size);
15377ec0effdSAtul Deshmukh
15387ec0effdSAtul Deshmukh /* Copy template header from flash */
15397ec0effdSAtul Deshmukh if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
15407ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0ba,
15417ec0effdSAtul Deshmukh "%s: Failed to read reset template\n", __func__);
15427ec0effdSAtul Deshmukh goto exit_read_template_error;
15437ec0effdSAtul Deshmukh }
15447ec0effdSAtul Deshmukh
15457ec0effdSAtul Deshmukh vha->reset_tmplt.hdr =
15467ec0effdSAtul Deshmukh (struct qla8044_reset_template_hdr *) vha->reset_tmplt.buff;
15477ec0effdSAtul Deshmukh
15487ec0effdSAtul Deshmukh /* Validate the template header size and signature */
15497ec0effdSAtul Deshmukh tmplt_hdr_size = vha->reset_tmplt.hdr->hdr_size/sizeof(uint32_t);
15507ec0effdSAtul Deshmukh if ((tmplt_hdr_size != tmplt_hdr_def_size) ||
15517ec0effdSAtul Deshmukh (vha->reset_tmplt.hdr->signature != RESET_TMPLT_HDR_SIGNATURE)) {
15527ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0bb,
15537ec0effdSAtul Deshmukh "%s: Template Header size invalid %d "
15547ec0effdSAtul Deshmukh "tmplt_hdr_def_size %d!!!\n", __func__,
15557ec0effdSAtul Deshmukh tmplt_hdr_size, tmplt_hdr_def_size);
15567ec0effdSAtul Deshmukh goto exit_read_template_error;
15577ec0effdSAtul Deshmukh }
15587ec0effdSAtul Deshmukh
15597ec0effdSAtul Deshmukh addr = QLA8044_RESET_TEMPLATE_ADDR + vha->reset_tmplt.hdr->hdr_size;
15607ec0effdSAtul Deshmukh p_buff = vha->reset_tmplt.buff + vha->reset_tmplt.hdr->hdr_size;
15617ec0effdSAtul Deshmukh tmplt_hdr_def_size = (vha->reset_tmplt.hdr->size -
15627ec0effdSAtul Deshmukh vha->reset_tmplt.hdr->hdr_size)/sizeof(uint32_t);
15637ec0effdSAtul Deshmukh
15647ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0bc,
15657ec0effdSAtul Deshmukh "%s: Read rest of the template size %d\n",
15667ec0effdSAtul Deshmukh __func__, vha->reset_tmplt.hdr->size);
15677ec0effdSAtul Deshmukh
15687ec0effdSAtul Deshmukh /* Copy rest of the template */
15697ec0effdSAtul Deshmukh if (qla8044_read_flash_data(vha, p_buff, addr, tmplt_hdr_def_size)) {
15707ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0bd,
15710bf0efa1SColin Ian King "%s: Failed to read reset template\n", __func__);
15727ec0effdSAtul Deshmukh goto exit_read_template_error;
15737ec0effdSAtul Deshmukh }
15747ec0effdSAtul Deshmukh
15757ec0effdSAtul Deshmukh /* Integrity check */
15767ec0effdSAtul Deshmukh if (qla8044_reset_seq_checksum_test(vha)) {
15777ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0be,
15787ec0effdSAtul Deshmukh "%s: Reset Seq checksum failed!\n", __func__);
15797ec0effdSAtul Deshmukh goto exit_read_template_error;
15807ec0effdSAtul Deshmukh }
15817ec0effdSAtul Deshmukh
15827ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0bf,
15837ec0effdSAtul Deshmukh "%s: Reset Seq checksum passed! Get stop, "
15847ec0effdSAtul Deshmukh "start and init seq offsets\n", __func__);
15857ec0effdSAtul Deshmukh
15867ec0effdSAtul Deshmukh /* Get STOP, START, INIT sequence offsets */
15877ec0effdSAtul Deshmukh vha->reset_tmplt.init_offset = vha->reset_tmplt.buff +
15887ec0effdSAtul Deshmukh vha->reset_tmplt.hdr->init_seq_offset;
15897ec0effdSAtul Deshmukh
15907ec0effdSAtul Deshmukh vha->reset_tmplt.start_offset = vha->reset_tmplt.buff +
15917ec0effdSAtul Deshmukh vha->reset_tmplt.hdr->start_seq_offset;
15927ec0effdSAtul Deshmukh
15937ec0effdSAtul Deshmukh vha->reset_tmplt.stop_offset = vha->reset_tmplt.buff +
15947ec0effdSAtul Deshmukh vha->reset_tmplt.hdr->hdr_size;
15957ec0effdSAtul Deshmukh
15967ec0effdSAtul Deshmukh qla8044_dump_reset_seq_hdr(vha);
15977ec0effdSAtul Deshmukh
15987ec0effdSAtul Deshmukh goto exit_read_reset_template;
15997ec0effdSAtul Deshmukh
16007ec0effdSAtul Deshmukh exit_read_template_error:
16017ec0effdSAtul Deshmukh vfree(vha->reset_tmplt.buff);
16027ec0effdSAtul Deshmukh
16037ec0effdSAtul Deshmukh exit_read_reset_template:
16047ec0effdSAtul Deshmukh return;
16057ec0effdSAtul Deshmukh }
16067ec0effdSAtul Deshmukh
16077ec0effdSAtul Deshmukh void
qla8044_set_idc_dontreset(struct scsi_qla_host * vha)16087ec0effdSAtul Deshmukh qla8044_set_idc_dontreset(struct scsi_qla_host *vha)
16097ec0effdSAtul Deshmukh {
16107ec0effdSAtul Deshmukh uint32_t idc_ctrl;
16117ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
16127ec0effdSAtul Deshmukh
16137ec0effdSAtul Deshmukh idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
16147ec0effdSAtul Deshmukh idc_ctrl |= DONTRESET_BIT0;
16157ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0c0,
16167ec0effdSAtul Deshmukh "%s: idc_ctrl = %d\n", __func__, idc_ctrl);
16177ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
16187ec0effdSAtul Deshmukh }
16197ec0effdSAtul Deshmukh
16202374dd23SBart Van Assche static inline void
qla8044_set_rst_ready(struct scsi_qla_host * vha)16217ec0effdSAtul Deshmukh qla8044_set_rst_ready(struct scsi_qla_host *vha)
16227ec0effdSAtul Deshmukh {
16237ec0effdSAtul Deshmukh uint32_t drv_state;
16247ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
16257ec0effdSAtul Deshmukh
16267ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
16277ec0effdSAtul Deshmukh
16287ec0effdSAtul Deshmukh /* For ISP8044, drv_active register has 1 bit per function,
16297ec0effdSAtul Deshmukh * shift 1 by func_num to set a bit for the function.*/
16307ec0effdSAtul Deshmukh drv_state |= (1 << ha->portnum);
16317ec0effdSAtul Deshmukh
16327ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0c1,
16337ec0effdSAtul Deshmukh "%s(%ld): drv_state: 0x%08x\n",
16347ec0effdSAtul Deshmukh __func__, vha->host_no, drv_state);
16357ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
16367ec0effdSAtul Deshmukh }
16377ec0effdSAtul Deshmukh
16387ec0effdSAtul Deshmukh /**
16397ec0effdSAtul Deshmukh * qla8044_need_reset_handler - Code to start reset sequence
16402db6228dSBart Van Assche * @vha: pointer to adapter structure
16417ec0effdSAtul Deshmukh *
16427ec0effdSAtul Deshmukh * Note: IDC lock must be held upon entry
16432db6228dSBart Van Assche */
16447ec0effdSAtul Deshmukh static void
qla8044_need_reset_handler(struct scsi_qla_host * vha)16457ec0effdSAtul Deshmukh qla8044_need_reset_handler(struct scsi_qla_host *vha)
16467ec0effdSAtul Deshmukh {
16477ec0effdSAtul Deshmukh uint32_t dev_state = 0, drv_state, drv_active;
1648a018d8ffSHiral Patel unsigned long reset_timeout;
16497ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
16507ec0effdSAtul Deshmukh
16517ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0c2,
16527ec0effdSAtul Deshmukh "%s: Performing ISP error recovery\n", __func__);
16537ec0effdSAtul Deshmukh
16547ec0effdSAtul Deshmukh if (vha->flags.online) {
16557ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
16567ec0effdSAtul Deshmukh qla2x00_abort_isp_cleanup(vha);
16577ec0effdSAtul Deshmukh ha->isp_ops->get_flash_version(vha, vha->req->ring);
16587ec0effdSAtul Deshmukh ha->isp_ops->nvram_config(vha);
16597ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
16607ec0effdSAtul Deshmukh }
16617ec0effdSAtul Deshmukh
1662a018d8ffSHiral Patel dev_state = qla8044_rd_direct(vha,
1663a018d8ffSHiral Patel QLA8044_CRB_DEV_STATE_INDEX);
16648f476115SSaurav Kashyap drv_state = qla8044_rd_direct(vha,
16658f476115SSaurav Kashyap QLA8044_CRB_DRV_STATE_INDEX);
16668f476115SSaurav Kashyap drv_active = qla8044_rd_direct(vha,
16678f476115SSaurav Kashyap QLA8044_CRB_DRV_ACTIVE_INDEX);
16688f476115SSaurav Kashyap
16698f476115SSaurav Kashyap ql_log(ql_log_info, vha, 0xb0c5,
1670a018d8ffSHiral Patel "%s(%ld): drv_state = 0x%x, drv_active = 0x%x dev_state = 0x%x\n",
1671a018d8ffSHiral Patel __func__, vha->host_no, drv_state, drv_active, dev_state);
16728f476115SSaurav Kashyap
16737ec0effdSAtul Deshmukh qla8044_set_rst_ready(vha);
16747ec0effdSAtul Deshmukh
1675a018d8ffSHiral Patel /* wait for 10 seconds for reset ack from all functions */
1676a018d8ffSHiral Patel reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
16777ec0effdSAtul Deshmukh
16787ec0effdSAtul Deshmukh do {
1679a018d8ffSHiral Patel if (time_after_eq(jiffies, reset_timeout)) {
16807ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0c4,
1681a018d8ffSHiral Patel "%s: Function %d: Reset Ack Timeout!, drv_state: 0x%08x, drv_active: 0x%08x\n",
1682a018d8ffSHiral Patel __func__, ha->portnum, drv_state, drv_active);
16837ec0effdSAtul Deshmukh break;
16847ec0effdSAtul Deshmukh }
16857ec0effdSAtul Deshmukh
16867ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
16877ec0effdSAtul Deshmukh msleep(1000);
16887ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
16897ec0effdSAtul Deshmukh
16907ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha,
16917ec0effdSAtul Deshmukh QLA8044_CRB_DEV_STATE_INDEX);
16927ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha,
16937ec0effdSAtul Deshmukh QLA8044_CRB_DRV_STATE_INDEX);
16947ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha,
16957ec0effdSAtul Deshmukh QLA8044_CRB_DRV_ACTIVE_INDEX);
1696a018d8ffSHiral Patel } while (((drv_state & drv_active) != drv_active) &&
1697a018d8ffSHiral Patel (dev_state == QLA8XXX_DEV_NEED_RESET));
16987ec0effdSAtul Deshmukh
1699a018d8ffSHiral Patel /* Remove IDC participation of functions not acknowledging */
17007ec0effdSAtul Deshmukh if (drv_state != drv_active) {
17017ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0c7,
1702a018d8ffSHiral Patel "%s(%ld): Function %d turning off drv_active of non-acking function 0x%x\n",
1703a018d8ffSHiral Patel __func__, vha->host_no, ha->portnum,
1704a018d8ffSHiral Patel (drv_active ^ drv_state));
17057ec0effdSAtul Deshmukh drv_active = drv_active & drv_state;
17067ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX,
17077ec0effdSAtul Deshmukh drv_active);
1708a018d8ffSHiral Patel } else {
1709a018d8ffSHiral Patel /*
1710a018d8ffSHiral Patel * Reset owner should execute reset recovery,
1711a018d8ffSHiral Patel * if all functions acknowledged
1712a018d8ffSHiral Patel */
1713a018d8ffSHiral Patel if ((ha->flags.nic_core_reset_owner) &&
1714a018d8ffSHiral Patel (dev_state == QLA8XXX_DEV_NEED_RESET)) {
1715a018d8ffSHiral Patel ha->flags.nic_core_reset_owner = 0;
1716a018d8ffSHiral Patel qla8044_device_bootstrap(vha);
1717a018d8ffSHiral Patel return;
1718a018d8ffSHiral Patel }
1719a018d8ffSHiral Patel }
1720a018d8ffSHiral Patel
1721a018d8ffSHiral Patel /* Exit if non active function */
1722a018d8ffSHiral Patel if (!(drv_active & (1 << ha->portnum))) {
1723a018d8ffSHiral Patel ha->flags.nic_core_reset_owner = 0;
1724a018d8ffSHiral Patel return;
17257ec0effdSAtul Deshmukh }
17267ec0effdSAtul Deshmukh
17277ec0effdSAtul Deshmukh /*
1728a018d8ffSHiral Patel * Execute Reset Recovery if Reset Owner or Function 7
1729a018d8ffSHiral Patel * is the only active function
17307ec0effdSAtul Deshmukh */
1731a018d8ffSHiral Patel if (ha->flags.nic_core_reset_owner ||
1732a018d8ffSHiral Patel ((drv_state & drv_active) == QLA8044_FUN7_ACTIVE_INDEX)) {
17337ec0effdSAtul Deshmukh ha->flags.nic_core_reset_owner = 0;
17347ec0effdSAtul Deshmukh qla8044_device_bootstrap(vha);
17357ec0effdSAtul Deshmukh }
17367ec0effdSAtul Deshmukh }
17377ec0effdSAtul Deshmukh
17387ec0effdSAtul Deshmukh static void
qla8044_set_drv_active(struct scsi_qla_host * vha)17397ec0effdSAtul Deshmukh qla8044_set_drv_active(struct scsi_qla_host *vha)
17407ec0effdSAtul Deshmukh {
17417ec0effdSAtul Deshmukh uint32_t drv_active;
17427ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
17437ec0effdSAtul Deshmukh
17447ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
17457ec0effdSAtul Deshmukh
17467ec0effdSAtul Deshmukh /* For ISP8044, drv_active register has 1 bit per function,
17477ec0effdSAtul Deshmukh * shift 1 by func_num to set a bit for the function.*/
17487ec0effdSAtul Deshmukh drv_active |= (1 << ha->portnum);
17497ec0effdSAtul Deshmukh
17507ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0c8,
17517ec0effdSAtul Deshmukh "%s(%ld): drv_active: 0x%08x\n",
17527ec0effdSAtul Deshmukh __func__, vha->host_no, drv_active);
17537ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX, drv_active);
17547ec0effdSAtul Deshmukh }
17557ec0effdSAtul Deshmukh
17564fa0c668SGiridhar Malavali static int
qla8044_check_drv_active(struct scsi_qla_host * vha)17574fa0c668SGiridhar Malavali qla8044_check_drv_active(struct scsi_qla_host *vha)
17584fa0c668SGiridhar Malavali {
17594fa0c668SGiridhar Malavali uint32_t drv_active;
17604fa0c668SGiridhar Malavali struct qla_hw_data *ha = vha->hw;
17614fa0c668SGiridhar Malavali
17624fa0c668SGiridhar Malavali drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
17634fa0c668SGiridhar Malavali if (drv_active & (1 << ha->portnum))
17644fa0c668SGiridhar Malavali return QLA_SUCCESS;
17654fa0c668SGiridhar Malavali else
17664fa0c668SGiridhar Malavali return QLA_TEST_FAILED;
17674fa0c668SGiridhar Malavali }
17684fa0c668SGiridhar Malavali
17697ec0effdSAtul Deshmukh static void
qla8044_clear_idc_dontreset(struct scsi_qla_host * vha)17707ec0effdSAtul Deshmukh qla8044_clear_idc_dontreset(struct scsi_qla_host *vha)
17717ec0effdSAtul Deshmukh {
17727ec0effdSAtul Deshmukh uint32_t idc_ctrl;
17737ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
17747ec0effdSAtul Deshmukh
17757ec0effdSAtul Deshmukh idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
17767ec0effdSAtul Deshmukh idc_ctrl &= ~DONTRESET_BIT0;
17777ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0c9,
17787ec0effdSAtul Deshmukh "%s: idc_ctrl = %d\n", __func__,
17797ec0effdSAtul Deshmukh idc_ctrl);
17807ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL, idc_ctrl);
17817ec0effdSAtul Deshmukh }
17827ec0effdSAtul Deshmukh
17837ec0effdSAtul Deshmukh static int
qla8044_set_idc_ver(struct scsi_qla_host * vha)17847ec0effdSAtul Deshmukh qla8044_set_idc_ver(struct scsi_qla_host *vha)
17857ec0effdSAtul Deshmukh {
17867ec0effdSAtul Deshmukh int idc_ver;
17877ec0effdSAtul Deshmukh uint32_t drv_active;
17887ec0effdSAtul Deshmukh int rval = QLA_SUCCESS;
17897ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
17907ec0effdSAtul Deshmukh
17917ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
17927ec0effdSAtul Deshmukh if (drv_active == (1 << ha->portnum)) {
17937ec0effdSAtul Deshmukh idc_ver = qla8044_rd_direct(vha,
17947ec0effdSAtul Deshmukh QLA8044_CRB_DRV_IDC_VERSION_INDEX);
17957ec0effdSAtul Deshmukh idc_ver &= (~0xFF);
17967ec0effdSAtul Deshmukh idc_ver |= QLA8044_IDC_VER_MAJ_VALUE;
17977ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_IDC_VERSION_INDEX,
17987ec0effdSAtul Deshmukh idc_ver);
17997ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0ca,
18007ec0effdSAtul Deshmukh "%s: IDC version updated to %d\n",
18017ec0effdSAtul Deshmukh __func__, idc_ver);
18027ec0effdSAtul Deshmukh } else {
18037ec0effdSAtul Deshmukh idc_ver = qla8044_rd_direct(vha,
18047ec0effdSAtul Deshmukh QLA8044_CRB_DRV_IDC_VERSION_INDEX);
18057ec0effdSAtul Deshmukh idc_ver &= 0xFF;
18067ec0effdSAtul Deshmukh if (QLA8044_IDC_VER_MAJ_VALUE != idc_ver) {
18077ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0cb,
18087ec0effdSAtul Deshmukh "%s: qla4xxx driver IDC version %d "
18097ec0effdSAtul Deshmukh "is not compatible with IDC version %d "
18107ec0effdSAtul Deshmukh "of other drivers!\n",
18117ec0effdSAtul Deshmukh __func__, QLA8044_IDC_VER_MAJ_VALUE,
18127ec0effdSAtul Deshmukh idc_ver);
18137ec0effdSAtul Deshmukh rval = QLA_FUNCTION_FAILED;
18147ec0effdSAtul Deshmukh goto exit_set_idc_ver;
18157ec0effdSAtul Deshmukh }
18167ec0effdSAtul Deshmukh }
18177ec0effdSAtul Deshmukh
18187ec0effdSAtul Deshmukh /* Update IDC_MINOR_VERSION */
18197ec0effdSAtul Deshmukh idc_ver = qla8044_rd_reg(ha, QLA8044_CRB_IDC_VER_MINOR);
18207ec0effdSAtul Deshmukh idc_ver &= ~(0x03 << (ha->portnum * 2));
18217ec0effdSAtul Deshmukh idc_ver |= (QLA8044_IDC_VER_MIN_VALUE << (ha->portnum * 2));
18227ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_CRB_IDC_VER_MINOR, idc_ver);
18237ec0effdSAtul Deshmukh
18247ec0effdSAtul Deshmukh exit_set_idc_ver:
18257ec0effdSAtul Deshmukh return rval;
18267ec0effdSAtul Deshmukh }
18277ec0effdSAtul Deshmukh
18287ec0effdSAtul Deshmukh static int
qla8044_update_idc_reg(struct scsi_qla_host * vha)18297ec0effdSAtul Deshmukh qla8044_update_idc_reg(struct scsi_qla_host *vha)
18307ec0effdSAtul Deshmukh {
18317ec0effdSAtul Deshmukh uint32_t drv_active;
18327ec0effdSAtul Deshmukh int rval = QLA_SUCCESS;
18337ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
18347ec0effdSAtul Deshmukh
18357ec0effdSAtul Deshmukh if (vha->flags.init_done)
18367ec0effdSAtul Deshmukh goto exit_update_idc_reg;
18377ec0effdSAtul Deshmukh
18387ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
18397ec0effdSAtul Deshmukh qla8044_set_drv_active(vha);
18407ec0effdSAtul Deshmukh
18417ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha,
18427ec0effdSAtul Deshmukh QLA8044_CRB_DRV_ACTIVE_INDEX);
18437ec0effdSAtul Deshmukh
18447ec0effdSAtul Deshmukh /* If we are the first driver to load and
18457ec0effdSAtul Deshmukh * ql2xdontresethba is not set, clear IDC_CTRL BIT0. */
18467ec0effdSAtul Deshmukh if ((drv_active == (1 << ha->portnum)) && !ql2xdontresethba)
18477ec0effdSAtul Deshmukh qla8044_clear_idc_dontreset(vha);
18487ec0effdSAtul Deshmukh
18497ec0effdSAtul Deshmukh rval = qla8044_set_idc_ver(vha);
18507ec0effdSAtul Deshmukh if (rval == QLA_FUNCTION_FAILED)
1851c41afc9aSSaurav Kashyap qla8044_clear_drv_active(ha);
18527ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
18537ec0effdSAtul Deshmukh
18547ec0effdSAtul Deshmukh exit_update_idc_reg:
18557ec0effdSAtul Deshmukh return rval;
18567ec0effdSAtul Deshmukh }
18577ec0effdSAtul Deshmukh
18587ec0effdSAtul Deshmukh /**
18597ec0effdSAtul Deshmukh * qla8044_need_qsnt_handler - Code to start qsnt
18602db6228dSBart Van Assche * @vha: pointer to adapter structure
18612db6228dSBart Van Assche */
18627ec0effdSAtul Deshmukh static void
qla8044_need_qsnt_handler(struct scsi_qla_host * vha)18637ec0effdSAtul Deshmukh qla8044_need_qsnt_handler(struct scsi_qla_host *vha)
18647ec0effdSAtul Deshmukh {
18657ec0effdSAtul Deshmukh unsigned long qsnt_timeout;
18667ec0effdSAtul Deshmukh uint32_t drv_state, drv_active, dev_state;
18677ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
18687ec0effdSAtul Deshmukh
18697ec0effdSAtul Deshmukh if (vha->flags.online)
18707ec0effdSAtul Deshmukh qla2x00_quiesce_io(vha);
18717ec0effdSAtul Deshmukh else
18727ec0effdSAtul Deshmukh return;
18737ec0effdSAtul Deshmukh
18747ec0effdSAtul Deshmukh qla8044_set_qsnt_ready(vha);
18757ec0effdSAtul Deshmukh
18767ec0effdSAtul Deshmukh /* Wait for 30 secs for all functions to ack qsnt mode */
18777ec0effdSAtul Deshmukh qsnt_timeout = jiffies + (QSNT_ACK_TOV * HZ);
18787ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
18797ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha, QLA8044_CRB_DRV_ACTIVE_INDEX);
18807ec0effdSAtul Deshmukh
18817ec0effdSAtul Deshmukh /* Shift drv_active by 1 to match drv_state. As quiescent ready bit
18827ec0effdSAtul Deshmukh position is at bit 1 and drv active is at bit 0 */
18837ec0effdSAtul Deshmukh drv_active = drv_active << 1;
18847ec0effdSAtul Deshmukh
18857ec0effdSAtul Deshmukh while (drv_state != drv_active) {
18867ec0effdSAtul Deshmukh if (time_after_eq(jiffies, qsnt_timeout)) {
18877ec0effdSAtul Deshmukh /* Other functions did not ack, changing state to
18887ec0effdSAtul Deshmukh * DEV_READY
18897ec0effdSAtul Deshmukh */
18907ec0effdSAtul Deshmukh clear_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
18917ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
18927ec0effdSAtul Deshmukh QLA8XXX_DEV_READY);
18937ec0effdSAtul Deshmukh qla8044_clear_qsnt_ready(vha);
18947ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0cc,
18957ec0effdSAtul Deshmukh "Timeout waiting for quiescent ack!!!\n");
18967ec0effdSAtul Deshmukh return;
18977ec0effdSAtul Deshmukh }
18987ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
18997ec0effdSAtul Deshmukh msleep(1000);
19007ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
19017ec0effdSAtul Deshmukh
19027ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha,
19037ec0effdSAtul Deshmukh QLA8044_CRB_DRV_STATE_INDEX);
19047ec0effdSAtul Deshmukh drv_active = qla8044_rd_direct(vha,
19057ec0effdSAtul Deshmukh QLA8044_CRB_DRV_ACTIVE_INDEX);
19067ec0effdSAtul Deshmukh drv_active = drv_active << 1;
19077ec0effdSAtul Deshmukh }
19087ec0effdSAtul Deshmukh
19097ec0effdSAtul Deshmukh /* All functions have Acked. Set quiescent state */
19107ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
19117ec0effdSAtul Deshmukh
19127ec0effdSAtul Deshmukh if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
19137ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
19147ec0effdSAtul Deshmukh QLA8XXX_DEV_QUIESCENT);
19157ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0cd,
19167ec0effdSAtul Deshmukh "%s: HW State: QUIESCENT\n", __func__);
19177ec0effdSAtul Deshmukh }
19187ec0effdSAtul Deshmukh }
19197ec0effdSAtul Deshmukh
19207ec0effdSAtul Deshmukh /*
19217ec0effdSAtul Deshmukh * qla8044_device_state_handler - Adapter state machine
19227ec0effdSAtul Deshmukh * @ha: pointer to host adapter structure.
19237ec0effdSAtul Deshmukh *
19247ec0effdSAtul Deshmukh * Note: IDC lock must be UNLOCKED upon entry
19257ec0effdSAtul Deshmukh **/
19267ec0effdSAtul Deshmukh int
qla8044_device_state_handler(struct scsi_qla_host * vha)19277ec0effdSAtul Deshmukh qla8044_device_state_handler(struct scsi_qla_host *vha)
19287ec0effdSAtul Deshmukh {
19297ec0effdSAtul Deshmukh uint32_t dev_state;
19307ec0effdSAtul Deshmukh int rval = QLA_SUCCESS;
19317ec0effdSAtul Deshmukh unsigned long dev_init_timeout;
19327ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
19337ec0effdSAtul Deshmukh
19347ec0effdSAtul Deshmukh rval = qla8044_update_idc_reg(vha);
19357ec0effdSAtul Deshmukh if (rval == QLA_FUNCTION_FAILED)
19367ec0effdSAtul Deshmukh goto exit_error;
19377ec0effdSAtul Deshmukh
19387ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
19397ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0ce,
19407ec0effdSAtul Deshmukh "Device state is 0x%x = %s\n",
1941*1f652aa0SGleb Chesnokov dev_state, qdev_state(dev_state));
19427ec0effdSAtul Deshmukh
19437ec0effdSAtul Deshmukh /* wait for 30 seconds for device to go ready */
19447ec0effdSAtul Deshmukh dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
19457ec0effdSAtul Deshmukh
19467ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
19477ec0effdSAtul Deshmukh
19487ec0effdSAtul Deshmukh while (1) {
19497ec0effdSAtul Deshmukh if (time_after_eq(jiffies, dev_init_timeout)) {
19504fa0c668SGiridhar Malavali if (qla8044_check_drv_active(vha) == QLA_SUCCESS) {
19517ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb0cf,
19527ec0effdSAtul Deshmukh "%s: Device Init Failed 0x%x = %s\n",
19537ec0effdSAtul Deshmukh QLA2XXX_DRIVER_NAME, dev_state,
1954*1f652aa0SGleb Chesnokov qdev_state(dev_state));
19554fa0c668SGiridhar Malavali qla8044_wr_direct(vha,
19564fa0c668SGiridhar Malavali QLA8044_CRB_DEV_STATE_INDEX,
19577ec0effdSAtul Deshmukh QLA8XXX_DEV_FAILED);
19587ec0effdSAtul Deshmukh }
19594fa0c668SGiridhar Malavali }
19607ec0effdSAtul Deshmukh
19617ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
19627ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0d0,
19637ec0effdSAtul Deshmukh "Device state is 0x%x = %s\n",
1964*1f652aa0SGleb Chesnokov dev_state, qdev_state(dev_state));
19657ec0effdSAtul Deshmukh
19667ec0effdSAtul Deshmukh /* NOTE: Make sure idc unlocked upon exit of switch statement */
19677ec0effdSAtul Deshmukh switch (dev_state) {
19687ec0effdSAtul Deshmukh case QLA8XXX_DEV_READY:
19697ec0effdSAtul Deshmukh ha->flags.nic_core_reset_owner = 0;
19707ec0effdSAtul Deshmukh goto exit;
19717ec0effdSAtul Deshmukh case QLA8XXX_DEV_COLD:
19727ec0effdSAtul Deshmukh rval = qla8044_device_bootstrap(vha);
19733746078fSSawan Chandak break;
19747ec0effdSAtul Deshmukh case QLA8XXX_DEV_INITIALIZING:
19757ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
19767ec0effdSAtul Deshmukh msleep(1000);
19777ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
19787ec0effdSAtul Deshmukh break;
19797ec0effdSAtul Deshmukh case QLA8XXX_DEV_NEED_RESET:
19807ec0effdSAtul Deshmukh /* For ISP8044, if NEED_RESET is set by any driver,
19817ec0effdSAtul Deshmukh * it should be honored, irrespective of IDC_CTRL
19827ec0effdSAtul Deshmukh * DONTRESET_BIT0 */
19837ec0effdSAtul Deshmukh qla8044_need_reset_handler(vha);
19847ec0effdSAtul Deshmukh break;
19857ec0effdSAtul Deshmukh case QLA8XXX_DEV_NEED_QUIESCENT:
19867ec0effdSAtul Deshmukh /* idc locked/unlocked in handler */
19877ec0effdSAtul Deshmukh qla8044_need_qsnt_handler(vha);
19887ec0effdSAtul Deshmukh
19897ec0effdSAtul Deshmukh /* Reset the init timeout after qsnt handler */
19907ec0effdSAtul Deshmukh dev_init_timeout = jiffies +
19917ec0effdSAtul Deshmukh (ha->fcoe_reset_timeout * HZ);
19927ec0effdSAtul Deshmukh break;
19937ec0effdSAtul Deshmukh case QLA8XXX_DEV_QUIESCENT:
19947ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0d1,
19957ec0effdSAtul Deshmukh "HW State: QUIESCENT\n");
19967ec0effdSAtul Deshmukh
19977ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
19987ec0effdSAtul Deshmukh msleep(1000);
19997ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
20007ec0effdSAtul Deshmukh
20017ec0effdSAtul Deshmukh /* Reset the init timeout after qsnt handler */
20027ec0effdSAtul Deshmukh dev_init_timeout = jiffies +
20037ec0effdSAtul Deshmukh (ha->fcoe_reset_timeout * HZ);
20047ec0effdSAtul Deshmukh break;
20057ec0effdSAtul Deshmukh case QLA8XXX_DEV_FAILED:
20067ec0effdSAtul Deshmukh ha->flags.nic_core_reset_owner = 0;
20077ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
20087ec0effdSAtul Deshmukh qla8xxx_dev_failed_handler(vha);
20097ec0effdSAtul Deshmukh rval = QLA_FUNCTION_FAILED;
20107ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
20117ec0effdSAtul Deshmukh goto exit;
20127ec0effdSAtul Deshmukh default:
20137ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
20147ec0effdSAtul Deshmukh qla8xxx_dev_failed_handler(vha);
20157ec0effdSAtul Deshmukh rval = QLA_FUNCTION_FAILED;
20167ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
20177ec0effdSAtul Deshmukh goto exit;
20187ec0effdSAtul Deshmukh }
20197ec0effdSAtul Deshmukh }
20207ec0effdSAtul Deshmukh exit:
20217ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
20227ec0effdSAtul Deshmukh
20237ec0effdSAtul Deshmukh exit_error:
20247ec0effdSAtul Deshmukh return rval;
20257ec0effdSAtul Deshmukh }
20267ec0effdSAtul Deshmukh
20277ec0effdSAtul Deshmukh /**
2028a736e449SLee Jones * qla8044_check_temp - Check the ISP82XX temperature.
20292db6228dSBart Van Assche * @vha: adapter block pointer.
20307ec0effdSAtul Deshmukh *
20317ec0effdSAtul Deshmukh * Note: The caller should not hold the idc lock.
20322db6228dSBart Van Assche */
20337ec0effdSAtul Deshmukh static int
qla8044_check_temp(struct scsi_qla_host * vha)20347ec0effdSAtul Deshmukh qla8044_check_temp(struct scsi_qla_host *vha)
20357ec0effdSAtul Deshmukh {
20367ec0effdSAtul Deshmukh uint32_t temp, temp_state, temp_val;
20377ec0effdSAtul Deshmukh int status = QLA_SUCCESS;
20387ec0effdSAtul Deshmukh
20397ec0effdSAtul Deshmukh temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
20407ec0effdSAtul Deshmukh temp_state = qla82xx_get_temp_state(temp);
20417ec0effdSAtul Deshmukh temp_val = qla82xx_get_temp_val(temp);
20427ec0effdSAtul Deshmukh
20437ec0effdSAtul Deshmukh if (temp_state == QLA82XX_TEMP_PANIC) {
20447ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb0d2,
20457ec0effdSAtul Deshmukh "Device temperature %d degrees C"
20467ec0effdSAtul Deshmukh " exceeds maximum allowed. Hardware has been shut"
20477ec0effdSAtul Deshmukh " down\n", temp_val);
20487ec0effdSAtul Deshmukh status = QLA_FUNCTION_FAILED;
20497ec0effdSAtul Deshmukh return status;
20507ec0effdSAtul Deshmukh } else if (temp_state == QLA82XX_TEMP_WARN) {
20517ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb0d3,
20527ec0effdSAtul Deshmukh "Device temperature %d"
20537ec0effdSAtul Deshmukh " degrees C exceeds operating range."
20547ec0effdSAtul Deshmukh " Immediate action needed.\n", temp_val);
20557ec0effdSAtul Deshmukh }
20567ec0effdSAtul Deshmukh return 0;
20577ec0effdSAtul Deshmukh }
20587ec0effdSAtul Deshmukh
qla8044_read_temperature(scsi_qla_host_t * vha)20591ae47cf3SJoe Carnuccio int qla8044_read_temperature(scsi_qla_host_t *vha)
20601ae47cf3SJoe Carnuccio {
20611ae47cf3SJoe Carnuccio uint32_t temp;
20621ae47cf3SJoe Carnuccio
20631ae47cf3SJoe Carnuccio temp = qla8044_rd_direct(vha, QLA8044_CRB_TEMP_STATE_INDEX);
20641ae47cf3SJoe Carnuccio return qla82xx_get_temp_val(temp);
20651ae47cf3SJoe Carnuccio }
20661ae47cf3SJoe Carnuccio
20677ec0effdSAtul Deshmukh /**
20687ec0effdSAtul Deshmukh * qla8044_check_fw_alive - Check firmware health
20692db6228dSBart Van Assche * @vha: Pointer to host adapter structure.
20707ec0effdSAtul Deshmukh *
20717ec0effdSAtul Deshmukh * Context: Interrupt
20722db6228dSBart Van Assche */
20737ec0effdSAtul Deshmukh int
qla8044_check_fw_alive(struct scsi_qla_host * vha)20747ec0effdSAtul Deshmukh qla8044_check_fw_alive(struct scsi_qla_host *vha)
20757ec0effdSAtul Deshmukh {
20767ec0effdSAtul Deshmukh uint32_t fw_heartbeat_counter;
20777ec0effdSAtul Deshmukh uint32_t halt_status1, halt_status2;
20787ec0effdSAtul Deshmukh int status = QLA_SUCCESS;
20797ec0effdSAtul Deshmukh
20807ec0effdSAtul Deshmukh fw_heartbeat_counter = qla8044_rd_direct(vha,
20817ec0effdSAtul Deshmukh QLA8044_PEG_ALIVE_COUNTER_INDEX);
20827ec0effdSAtul Deshmukh
20837ec0effdSAtul Deshmukh /* If PEG_ALIVE_COUNTER is 0xffffffff, AER/EEH is in progress, ignore */
20847ec0effdSAtul Deshmukh if (fw_heartbeat_counter == 0xffffffff) {
20857ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0d4,
20867ec0effdSAtul Deshmukh "scsi%ld: %s: Device in frozen "
20877ec0effdSAtul Deshmukh "state, QLA82XX_PEG_ALIVE_COUNTER is 0xffffffff\n",
20887ec0effdSAtul Deshmukh vha->host_no, __func__);
20897ec0effdSAtul Deshmukh return status;
20907ec0effdSAtul Deshmukh }
20917ec0effdSAtul Deshmukh
20927ec0effdSAtul Deshmukh if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
20937ec0effdSAtul Deshmukh vha->seconds_since_last_heartbeat++;
20947ec0effdSAtul Deshmukh /* FW not alive after 2 seconds */
20957ec0effdSAtul Deshmukh if (vha->seconds_since_last_heartbeat == 2) {
20967ec0effdSAtul Deshmukh vha->seconds_since_last_heartbeat = 0;
20977ec0effdSAtul Deshmukh halt_status1 = qla8044_rd_direct(vha,
20987ec0effdSAtul Deshmukh QLA8044_PEG_HALT_STATUS1_INDEX);
20997ec0effdSAtul Deshmukh halt_status2 = qla8044_rd_direct(vha,
21007ec0effdSAtul Deshmukh QLA8044_PEG_HALT_STATUS2_INDEX);
21017ec0effdSAtul Deshmukh
21027ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0d5,
21037ec0effdSAtul Deshmukh "scsi(%ld): %s, ISP8044 "
21047ec0effdSAtul Deshmukh "Dumping hw/fw registers:\n"
21057ec0effdSAtul Deshmukh " PEG_HALT_STATUS1: 0x%x, "
21067ec0effdSAtul Deshmukh "PEG_HALT_STATUS2: 0x%x,\n",
21077ec0effdSAtul Deshmukh vha->host_no, __func__, halt_status1,
21087ec0effdSAtul Deshmukh halt_status2);
21097ec0effdSAtul Deshmukh status = QLA_FUNCTION_FAILED;
21107ec0effdSAtul Deshmukh }
21117ec0effdSAtul Deshmukh } else
21127ec0effdSAtul Deshmukh vha->seconds_since_last_heartbeat = 0;
21137ec0effdSAtul Deshmukh
21147ec0effdSAtul Deshmukh vha->fw_heartbeat_counter = fw_heartbeat_counter;
21157ec0effdSAtul Deshmukh return status;
21167ec0effdSAtul Deshmukh }
21177ec0effdSAtul Deshmukh
21187ec0effdSAtul Deshmukh void
qla8044_watchdog(struct scsi_qla_host * vha)21197ec0effdSAtul Deshmukh qla8044_watchdog(struct scsi_qla_host *vha)
21207ec0effdSAtul Deshmukh {
21217ec0effdSAtul Deshmukh uint32_t dev_state, halt_status;
21227ec0effdSAtul Deshmukh int halt_status_unrecoverable = 0;
21237ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
21247ec0effdSAtul Deshmukh
21257ec0effdSAtul Deshmukh /* don't poll if reset is going on or FW hang in quiescent state */
21267ec0effdSAtul Deshmukh if (!(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) ||
21277ec0effdSAtul Deshmukh test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))) {
21287ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
21297ec0effdSAtul Deshmukh
21307012532dSGiridhar Malavali if (qla8044_check_fw_alive(vha)) {
21317012532dSGiridhar Malavali ha->flags.isp82xx_fw_hung = 1;
21327012532dSGiridhar Malavali ql_log(ql_log_warn, vha, 0xb10a,
21337012532dSGiridhar Malavali "Firmware hung.\n");
21347012532dSGiridhar Malavali qla82xx_clear_pending_mbx(vha);
21357012532dSGiridhar Malavali }
21367012532dSGiridhar Malavali
21377ec0effdSAtul Deshmukh if (qla8044_check_temp(vha)) {
21387ec0effdSAtul Deshmukh set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
21397ec0effdSAtul Deshmukh ha->flags.isp82xx_fw_hung = 1;
21407ec0effdSAtul Deshmukh qla2xxx_wake_dpc(vha);
21417ec0effdSAtul Deshmukh } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
21427ec0effdSAtul Deshmukh !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
21437ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0d6,
21447ec0effdSAtul Deshmukh "%s: HW State: NEED RESET!\n",
21457ec0effdSAtul Deshmukh __func__);
21467ec0effdSAtul Deshmukh set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
21477ec0effdSAtul Deshmukh qla2xxx_wake_dpc(vha);
21487ec0effdSAtul Deshmukh } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
21497ec0effdSAtul Deshmukh !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
21507ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0d7,
21517ec0effdSAtul Deshmukh "%s: HW State: NEED QUIES detected!\n",
21527ec0effdSAtul Deshmukh __func__);
21537ec0effdSAtul Deshmukh set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
21547ec0effdSAtul Deshmukh qla2xxx_wake_dpc(vha);
21557ec0effdSAtul Deshmukh } else {
21567ec0effdSAtul Deshmukh /* Check firmware health */
21577012532dSGiridhar Malavali if (ha->flags.isp82xx_fw_hung) {
21587ec0effdSAtul Deshmukh halt_status = qla8044_rd_direct(vha,
21597ec0effdSAtul Deshmukh QLA8044_PEG_HALT_STATUS1_INDEX);
21607ec0effdSAtul Deshmukh if (halt_status &
21617ec0effdSAtul Deshmukh QLA8044_HALT_STATUS_FW_RESET) {
21627ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha,
21637ec0effdSAtul Deshmukh 0xb0d8, "%s: Firmware "
21647ec0effdSAtul Deshmukh "error detected device "
21657ec0effdSAtul Deshmukh "is being reset\n",
21667ec0effdSAtul Deshmukh __func__);
21677ec0effdSAtul Deshmukh } else if (halt_status &
21687ec0effdSAtul Deshmukh QLA8044_HALT_STATUS_UNRECOVERABLE) {
21697ec0effdSAtul Deshmukh halt_status_unrecoverable = 1;
21707ec0effdSAtul Deshmukh }
21717ec0effdSAtul Deshmukh
21727ec0effdSAtul Deshmukh /* Since we cannot change dev_state in interrupt
21737ec0effdSAtul Deshmukh * context, set appropriate DPC flag then wakeup
21747ec0effdSAtul Deshmukh * DPC */
21757ec0effdSAtul Deshmukh if (halt_status_unrecoverable) {
21767ec0effdSAtul Deshmukh set_bit(ISP_UNRECOVERABLE,
21777ec0effdSAtul Deshmukh &vha->dpc_flags);
21787ec0effdSAtul Deshmukh } else {
21797ec0effdSAtul Deshmukh if (dev_state ==
21807ec0effdSAtul Deshmukh QLA8XXX_DEV_QUIESCENT) {
21817ec0effdSAtul Deshmukh set_bit(FCOE_CTX_RESET_NEEDED,
21827ec0effdSAtul Deshmukh &vha->dpc_flags);
21837ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0d9,
21847ec0effdSAtul Deshmukh "%s: FW CONTEXT Reset "
21857ec0effdSAtul Deshmukh "needed!\n", __func__);
21867ec0effdSAtul Deshmukh } else {
21877ec0effdSAtul Deshmukh ql_log(ql_log_info, vha,
21887ec0effdSAtul Deshmukh 0xb0da, "%s: "
21897ec0effdSAtul Deshmukh "detect abort needed\n",
21907ec0effdSAtul Deshmukh __func__);
21917ec0effdSAtul Deshmukh set_bit(ISP_ABORT_NEEDED,
21927ec0effdSAtul Deshmukh &vha->dpc_flags);
21937ec0effdSAtul Deshmukh }
21947ec0effdSAtul Deshmukh }
21957ec0effdSAtul Deshmukh qla2xxx_wake_dpc(vha);
21967ec0effdSAtul Deshmukh }
21977ec0effdSAtul Deshmukh }
21987ec0effdSAtul Deshmukh
21997ec0effdSAtul Deshmukh }
22007ec0effdSAtul Deshmukh }
22017ec0effdSAtul Deshmukh
22027ec0effdSAtul Deshmukh static int
qla8044_minidump_process_control(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr)22037ec0effdSAtul Deshmukh qla8044_minidump_process_control(struct scsi_qla_host *vha,
22047ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr)
22057ec0effdSAtul Deshmukh {
22067ec0effdSAtul Deshmukh struct qla8044_minidump_entry_crb *crb_entry;
22077ec0effdSAtul Deshmukh uint32_t read_value, opcode, poll_time, addr, index;
22087ec0effdSAtul Deshmukh uint32_t crb_addr, rval = QLA_SUCCESS;
22097ec0effdSAtul Deshmukh unsigned long wtime;
22107ec0effdSAtul Deshmukh struct qla8044_minidump_template_hdr *tmplt_hdr;
22117ec0effdSAtul Deshmukh int i;
22127ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
22137ec0effdSAtul Deshmukh
22147ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0dd, "Entering fn: %s\n", __func__);
22157ec0effdSAtul Deshmukh tmplt_hdr = (struct qla8044_minidump_template_hdr *)
22167ec0effdSAtul Deshmukh ha->md_tmplt_hdr;
22177ec0effdSAtul Deshmukh crb_entry = (struct qla8044_minidump_entry_crb *)entry_hdr;
22187ec0effdSAtul Deshmukh
22197ec0effdSAtul Deshmukh crb_addr = crb_entry->addr;
22207ec0effdSAtul Deshmukh for (i = 0; i < crb_entry->op_count; i++) {
22217ec0effdSAtul Deshmukh opcode = crb_entry->crb_ctrl.opcode;
22227ec0effdSAtul Deshmukh
22237ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_WR) {
22247ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, crb_addr,
22257ec0effdSAtul Deshmukh crb_entry->value_1);
22267ec0effdSAtul Deshmukh }
22277ec0effdSAtul Deshmukh
22287ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_RW) {
22297ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
22307ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, crb_addr, read_value);
22317ec0effdSAtul Deshmukh }
22327ec0effdSAtul Deshmukh
22337ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_AND) {
22347ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
22357ec0effdSAtul Deshmukh read_value &= crb_entry->value_2;
22367ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_OR) {
22377ec0effdSAtul Deshmukh read_value |= crb_entry->value_3;
22387ec0effdSAtul Deshmukh opcode &= ~QLA82XX_DBG_OPCODE_OR;
22397ec0effdSAtul Deshmukh }
22407ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, crb_addr, read_value);
22417ec0effdSAtul Deshmukh }
22427ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_OR) {
22437ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
22447ec0effdSAtul Deshmukh read_value |= crb_entry->value_3;
22457ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, crb_addr, read_value);
22467ec0effdSAtul Deshmukh }
22477ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_POLL) {
22487ec0effdSAtul Deshmukh poll_time = crb_entry->crb_strd.poll_timeout;
22497ec0effdSAtul Deshmukh wtime = jiffies + poll_time;
22507ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, crb_addr, &read_value);
22517ec0effdSAtul Deshmukh
22527ec0effdSAtul Deshmukh do {
22537ec0effdSAtul Deshmukh if ((read_value & crb_entry->value_2) ==
22547ec0effdSAtul Deshmukh crb_entry->value_1) {
22557ec0effdSAtul Deshmukh break;
22567ec0effdSAtul Deshmukh } else if (time_after_eq(jiffies, wtime)) {
22577ec0effdSAtul Deshmukh /* capturing dump failed */
22587ec0effdSAtul Deshmukh rval = QLA_FUNCTION_FAILED;
22597ec0effdSAtul Deshmukh break;
22607ec0effdSAtul Deshmukh } else {
22617ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha,
22627ec0effdSAtul Deshmukh crb_addr, &read_value);
22637ec0effdSAtul Deshmukh }
22647ec0effdSAtul Deshmukh } while (1);
22657ec0effdSAtul Deshmukh }
22667ec0effdSAtul Deshmukh
22677ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
22687ec0effdSAtul Deshmukh if (crb_entry->crb_strd.state_index_a) {
22697ec0effdSAtul Deshmukh index = crb_entry->crb_strd.state_index_a;
22707ec0effdSAtul Deshmukh addr = tmplt_hdr->saved_state_array[index];
22717ec0effdSAtul Deshmukh } else {
22727ec0effdSAtul Deshmukh addr = crb_addr;
22737ec0effdSAtul Deshmukh }
22747ec0effdSAtul Deshmukh
22757ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, addr, &read_value);
22767ec0effdSAtul Deshmukh index = crb_entry->crb_ctrl.state_index_v;
22777ec0effdSAtul Deshmukh tmplt_hdr->saved_state_array[index] = read_value;
22787ec0effdSAtul Deshmukh }
22797ec0effdSAtul Deshmukh
22807ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
22817ec0effdSAtul Deshmukh if (crb_entry->crb_strd.state_index_a) {
22827ec0effdSAtul Deshmukh index = crb_entry->crb_strd.state_index_a;
22837ec0effdSAtul Deshmukh addr = tmplt_hdr->saved_state_array[index];
22847ec0effdSAtul Deshmukh } else {
22857ec0effdSAtul Deshmukh addr = crb_addr;
22867ec0effdSAtul Deshmukh }
22877ec0effdSAtul Deshmukh
22887ec0effdSAtul Deshmukh if (crb_entry->crb_ctrl.state_index_v) {
22897ec0effdSAtul Deshmukh index = crb_entry->crb_ctrl.state_index_v;
22907ec0effdSAtul Deshmukh read_value =
22917ec0effdSAtul Deshmukh tmplt_hdr->saved_state_array[index];
22927ec0effdSAtul Deshmukh } else {
22937ec0effdSAtul Deshmukh read_value = crb_entry->value_1;
22947ec0effdSAtul Deshmukh }
22957ec0effdSAtul Deshmukh
22967ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, addr, read_value);
22977ec0effdSAtul Deshmukh }
22987ec0effdSAtul Deshmukh
22997ec0effdSAtul Deshmukh if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
23007ec0effdSAtul Deshmukh index = crb_entry->crb_ctrl.state_index_v;
23017ec0effdSAtul Deshmukh read_value = tmplt_hdr->saved_state_array[index];
23027ec0effdSAtul Deshmukh read_value <<= crb_entry->crb_ctrl.shl;
23037ec0effdSAtul Deshmukh read_value >>= crb_entry->crb_ctrl.shr;
23047ec0effdSAtul Deshmukh if (crb_entry->value_2)
23057ec0effdSAtul Deshmukh read_value &= crb_entry->value_2;
23067ec0effdSAtul Deshmukh read_value |= crb_entry->value_3;
23077ec0effdSAtul Deshmukh read_value += crb_entry->value_1;
23087ec0effdSAtul Deshmukh tmplt_hdr->saved_state_array[index] = read_value;
23097ec0effdSAtul Deshmukh }
23107ec0effdSAtul Deshmukh crb_addr += crb_entry->crb_strd.addr_stride;
23117ec0effdSAtul Deshmukh }
23127ec0effdSAtul Deshmukh return rval;
23137ec0effdSAtul Deshmukh }
23147ec0effdSAtul Deshmukh
23157ec0effdSAtul Deshmukh static void
qla8044_minidump_process_rdcrb(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)23167ec0effdSAtul Deshmukh qla8044_minidump_process_rdcrb(struct scsi_qla_host *vha,
23177ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
23187ec0effdSAtul Deshmukh {
23197ec0effdSAtul Deshmukh uint32_t r_addr, r_stride, loop_cnt, i, r_value;
23207ec0effdSAtul Deshmukh struct qla8044_minidump_entry_crb *crb_hdr;
23217ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr;
23227ec0effdSAtul Deshmukh
23237ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0de, "Entering fn: %s\n", __func__);
23247ec0effdSAtul Deshmukh crb_hdr = (struct qla8044_minidump_entry_crb *)entry_hdr;
23257ec0effdSAtul Deshmukh r_addr = crb_hdr->addr;
23267ec0effdSAtul Deshmukh r_stride = crb_hdr->crb_strd.addr_stride;
23277ec0effdSAtul Deshmukh loop_cnt = crb_hdr->op_count;
23287ec0effdSAtul Deshmukh
23297ec0effdSAtul Deshmukh for (i = 0; i < loop_cnt; i++) {
23307ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, r_addr, &r_value);
23317ec0effdSAtul Deshmukh *data_ptr++ = r_addr;
23327ec0effdSAtul Deshmukh *data_ptr++ = r_value;
23337ec0effdSAtul Deshmukh r_addr += r_stride;
23347ec0effdSAtul Deshmukh }
23357ec0effdSAtul Deshmukh *d_ptr = data_ptr;
23367ec0effdSAtul Deshmukh }
23377ec0effdSAtul Deshmukh
23387ec0effdSAtul Deshmukh static int
qla8044_minidump_process_rdmem(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)23397ec0effdSAtul Deshmukh qla8044_minidump_process_rdmem(struct scsi_qla_host *vha,
23407ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
23417ec0effdSAtul Deshmukh {
23427ec0effdSAtul Deshmukh uint32_t r_addr, r_value, r_data;
23437ec0effdSAtul Deshmukh uint32_t i, j, loop_cnt;
23447ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdmem *m_hdr;
23457ec0effdSAtul Deshmukh unsigned long flags;
23467ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr;
23477ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
23487ec0effdSAtul Deshmukh
23497ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0df, "Entering fn: %s\n", __func__);
23507ec0effdSAtul Deshmukh m_hdr = (struct qla8044_minidump_entry_rdmem *)entry_hdr;
23517ec0effdSAtul Deshmukh r_addr = m_hdr->read_addr;
23527ec0effdSAtul Deshmukh loop_cnt = m_hdr->read_data_size/16;
23537ec0effdSAtul Deshmukh
23547ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f0,
23557ec0effdSAtul Deshmukh "[%s]: Read addr: 0x%x, read_data_size: 0x%x\n",
23567ec0effdSAtul Deshmukh __func__, r_addr, m_hdr->read_data_size);
23577ec0effdSAtul Deshmukh
23587ec0effdSAtul Deshmukh if (r_addr & 0xf) {
23597ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f1,
23608faaaeadSMasanari Iida "[%s]: Read addr 0x%x not 16 bytes aligned\n",
23617ec0effdSAtul Deshmukh __func__, r_addr);
23627ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
23637ec0effdSAtul Deshmukh }
23647ec0effdSAtul Deshmukh
23657ec0effdSAtul Deshmukh if (m_hdr->read_data_size % 16) {
23667ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f2,
23677ec0effdSAtul Deshmukh "[%s]: Read data[0x%x] not multiple of 16 bytes\n",
23687ec0effdSAtul Deshmukh __func__, m_hdr->read_data_size);
23697ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
23707ec0effdSAtul Deshmukh }
23717ec0effdSAtul Deshmukh
23727ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f3,
23737ec0effdSAtul Deshmukh "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
23747ec0effdSAtul Deshmukh __func__, r_addr, m_hdr->read_data_size, loop_cnt);
23757ec0effdSAtul Deshmukh
23767ec0effdSAtul Deshmukh write_lock_irqsave(&ha->hw_lock, flags);
23777ec0effdSAtul Deshmukh for (i = 0; i < loop_cnt; i++) {
23787ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_LO, r_addr);
23797ec0effdSAtul Deshmukh r_value = 0;
23807ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_ADDR_HI, r_value);
23817ec0effdSAtul Deshmukh r_value = MIU_TA_CTL_ENABLE;
23827ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
23837ec0effdSAtul Deshmukh r_value = MIU_TA_CTL_START_ENABLE;
23847ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL, r_value);
23857ec0effdSAtul Deshmukh
23867ec0effdSAtul Deshmukh for (j = 0; j < MAX_CTL_CHECK; j++) {
23877ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_CTRL,
23887ec0effdSAtul Deshmukh &r_value);
23897ec0effdSAtul Deshmukh if ((r_value & MIU_TA_CTL_BUSY) == 0)
23907ec0effdSAtul Deshmukh break;
23917ec0effdSAtul Deshmukh }
23927ec0effdSAtul Deshmukh
23937ec0effdSAtul Deshmukh if (j >= MAX_CTL_CHECK) {
23947ec0effdSAtul Deshmukh write_unlock_irqrestore(&ha->hw_lock, flags);
23957ec0effdSAtul Deshmukh return QLA_SUCCESS;
23967ec0effdSAtul Deshmukh }
23977ec0effdSAtul Deshmukh
23987ec0effdSAtul Deshmukh for (j = 0; j < 4; j++) {
23997ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, MD_MIU_TEST_AGT_RDDATA[j],
24007ec0effdSAtul Deshmukh &r_data);
24017ec0effdSAtul Deshmukh *data_ptr++ = r_data;
24027ec0effdSAtul Deshmukh }
24037ec0effdSAtul Deshmukh
24047ec0effdSAtul Deshmukh r_addr += 16;
24057ec0effdSAtul Deshmukh }
24067ec0effdSAtul Deshmukh write_unlock_irqrestore(&ha->hw_lock, flags);
24077ec0effdSAtul Deshmukh
24087ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f4,
24097ec0effdSAtul Deshmukh "Leaving fn: %s datacount: 0x%x\n",
24107ec0effdSAtul Deshmukh __func__, (loop_cnt * 16));
24117ec0effdSAtul Deshmukh
24127ec0effdSAtul Deshmukh *d_ptr = data_ptr;
24137ec0effdSAtul Deshmukh return QLA_SUCCESS;
24147ec0effdSAtul Deshmukh }
24157ec0effdSAtul Deshmukh
24167ec0effdSAtul Deshmukh /* ISP83xx flash read for _RDROM _BOARD */
24177ec0effdSAtul Deshmukh static uint32_t
qla8044_minidump_process_rdrom(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)24187ec0effdSAtul Deshmukh qla8044_minidump_process_rdrom(struct scsi_qla_host *vha,
24197ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
24207ec0effdSAtul Deshmukh {
24217ec0effdSAtul Deshmukh uint32_t fl_addr, u32_count, rval;
24227ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdrom *rom_hdr;
24237ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr;
24247ec0effdSAtul Deshmukh
24257ec0effdSAtul Deshmukh rom_hdr = (struct qla8044_minidump_entry_rdrom *)entry_hdr;
24267ec0effdSAtul Deshmukh fl_addr = rom_hdr->read_addr;
24277ec0effdSAtul Deshmukh u32_count = (rom_hdr->read_data_size)/sizeof(uint32_t);
24287ec0effdSAtul Deshmukh
24297ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f5, "[%s]: fl_addr: 0x%x, count: 0x%x\n",
24307ec0effdSAtul Deshmukh __func__, fl_addr, u32_count);
24317ec0effdSAtul Deshmukh
24327ec0effdSAtul Deshmukh rval = qla8044_lockless_flash_read_u32(vha, fl_addr,
24337ec0effdSAtul Deshmukh (u8 *)(data_ptr), u32_count);
24347ec0effdSAtul Deshmukh
24357ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) {
24367ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0f6,
24377ec0effdSAtul Deshmukh "%s: Flash Read Error,Count=%d\n", __func__, u32_count);
24387ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
24397ec0effdSAtul Deshmukh } else {
24407ec0effdSAtul Deshmukh data_ptr += u32_count;
24417ec0effdSAtul Deshmukh *d_ptr = data_ptr;
24427ec0effdSAtul Deshmukh return QLA_SUCCESS;
24437ec0effdSAtul Deshmukh }
24447ec0effdSAtul Deshmukh }
24457ec0effdSAtul Deshmukh
24467ec0effdSAtul Deshmukh static void
qla8044_mark_entry_skipped(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,int index)24477ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(struct scsi_qla_host *vha,
24487ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, int index)
24497ec0effdSAtul Deshmukh {
24507ec0effdSAtul Deshmukh entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
24517ec0effdSAtul Deshmukh
24527ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb0f7,
24537ec0effdSAtul Deshmukh "scsi(%ld): Skipping entry[%d]: ETYPE[0x%x]-ELEVEL[0x%x]\n",
24547ec0effdSAtul Deshmukh vha->host_no, index, entry_hdr->entry_type,
24557ec0effdSAtul Deshmukh entry_hdr->d_ctrl.entry_capture_mask);
24567ec0effdSAtul Deshmukh }
24577ec0effdSAtul Deshmukh
24587ec0effdSAtul Deshmukh static int
qla8044_minidump_process_l2tag(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)24597ec0effdSAtul Deshmukh qla8044_minidump_process_l2tag(struct scsi_qla_host *vha,
24607ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr,
24617ec0effdSAtul Deshmukh uint32_t **d_ptr)
24627ec0effdSAtul Deshmukh {
24637ec0effdSAtul Deshmukh uint32_t addr, r_addr, c_addr, t_r_addr;
24647ec0effdSAtul Deshmukh uint32_t i, k, loop_count, t_value, r_cnt, r_value;
24657ec0effdSAtul Deshmukh unsigned long p_wait, w_time, p_mask;
24667ec0effdSAtul Deshmukh uint32_t c_value_w, c_value_r;
24677ec0effdSAtul Deshmukh struct qla8044_minidump_entry_cache *cache_hdr;
24687ec0effdSAtul Deshmukh int rval = QLA_FUNCTION_FAILED;
24697ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr;
24707ec0effdSAtul Deshmukh
24717ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f8, "Entering fn: %s\n", __func__);
24727ec0effdSAtul Deshmukh cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
24737ec0effdSAtul Deshmukh
24747ec0effdSAtul Deshmukh loop_count = cache_hdr->op_count;
24757ec0effdSAtul Deshmukh r_addr = cache_hdr->read_addr;
24767ec0effdSAtul Deshmukh c_addr = cache_hdr->control_addr;
24777ec0effdSAtul Deshmukh c_value_w = cache_hdr->cache_ctrl.write_value;
24787ec0effdSAtul Deshmukh
24797ec0effdSAtul Deshmukh t_r_addr = cache_hdr->tag_reg_addr;
24807ec0effdSAtul Deshmukh t_value = cache_hdr->addr_ctrl.init_tag_value;
24817ec0effdSAtul Deshmukh r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
24827ec0effdSAtul Deshmukh p_wait = cache_hdr->cache_ctrl.poll_wait;
24837ec0effdSAtul Deshmukh p_mask = cache_hdr->cache_ctrl.poll_mask;
24847ec0effdSAtul Deshmukh
24857ec0effdSAtul Deshmukh for (i = 0; i < loop_count; i++) {
24867ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
24877ec0effdSAtul Deshmukh if (c_value_w)
24887ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
24897ec0effdSAtul Deshmukh
24907ec0effdSAtul Deshmukh if (p_mask) {
24917ec0effdSAtul Deshmukh w_time = jiffies + p_wait;
24927ec0effdSAtul Deshmukh do {
24937ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, c_addr,
24947ec0effdSAtul Deshmukh &c_value_r);
24957ec0effdSAtul Deshmukh if ((c_value_r & p_mask) == 0) {
24967ec0effdSAtul Deshmukh break;
24977ec0effdSAtul Deshmukh } else if (time_after_eq(jiffies, w_time)) {
24987ec0effdSAtul Deshmukh /* capturing dump failed */
24997ec0effdSAtul Deshmukh return rval;
25007ec0effdSAtul Deshmukh }
25017ec0effdSAtul Deshmukh } while (1);
25027ec0effdSAtul Deshmukh }
25037ec0effdSAtul Deshmukh
25047ec0effdSAtul Deshmukh addr = r_addr;
25057ec0effdSAtul Deshmukh for (k = 0; k < r_cnt; k++) {
25067ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, addr, &r_value);
25077ec0effdSAtul Deshmukh *data_ptr++ = r_value;
25087ec0effdSAtul Deshmukh addr += cache_hdr->read_ctrl.read_addr_stride;
25097ec0effdSAtul Deshmukh }
25107ec0effdSAtul Deshmukh t_value += cache_hdr->addr_ctrl.tag_value_stride;
25117ec0effdSAtul Deshmukh }
25127ec0effdSAtul Deshmukh *d_ptr = data_ptr;
25137ec0effdSAtul Deshmukh return QLA_SUCCESS;
25147ec0effdSAtul Deshmukh }
25157ec0effdSAtul Deshmukh
25167ec0effdSAtul Deshmukh static void
qla8044_minidump_process_l1cache(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)25177ec0effdSAtul Deshmukh qla8044_minidump_process_l1cache(struct scsi_qla_host *vha,
25187ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
25197ec0effdSAtul Deshmukh {
25207ec0effdSAtul Deshmukh uint32_t addr, r_addr, c_addr, t_r_addr;
25217ec0effdSAtul Deshmukh uint32_t i, k, loop_count, t_value, r_cnt, r_value;
25227ec0effdSAtul Deshmukh uint32_t c_value_w;
25237ec0effdSAtul Deshmukh struct qla8044_minidump_entry_cache *cache_hdr;
25247ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr;
25257ec0effdSAtul Deshmukh
25267ec0effdSAtul Deshmukh cache_hdr = (struct qla8044_minidump_entry_cache *)entry_hdr;
25277ec0effdSAtul Deshmukh loop_count = cache_hdr->op_count;
25287ec0effdSAtul Deshmukh r_addr = cache_hdr->read_addr;
25297ec0effdSAtul Deshmukh c_addr = cache_hdr->control_addr;
25307ec0effdSAtul Deshmukh c_value_w = cache_hdr->cache_ctrl.write_value;
25317ec0effdSAtul Deshmukh
25327ec0effdSAtul Deshmukh t_r_addr = cache_hdr->tag_reg_addr;
25337ec0effdSAtul Deshmukh t_value = cache_hdr->addr_ctrl.init_tag_value;
25347ec0effdSAtul Deshmukh r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
25357ec0effdSAtul Deshmukh
25367ec0effdSAtul Deshmukh for (i = 0; i < loop_count; i++) {
25377ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, t_r_addr, t_value);
25387ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, c_addr, c_value_w);
25397ec0effdSAtul Deshmukh addr = r_addr;
25407ec0effdSAtul Deshmukh for (k = 0; k < r_cnt; k++) {
25417ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, addr, &r_value);
25427ec0effdSAtul Deshmukh *data_ptr++ = r_value;
25437ec0effdSAtul Deshmukh addr += cache_hdr->read_ctrl.read_addr_stride;
25447ec0effdSAtul Deshmukh }
25457ec0effdSAtul Deshmukh t_value += cache_hdr->addr_ctrl.tag_value_stride;
25467ec0effdSAtul Deshmukh }
25477ec0effdSAtul Deshmukh *d_ptr = data_ptr;
25487ec0effdSAtul Deshmukh }
25497ec0effdSAtul Deshmukh
25507ec0effdSAtul Deshmukh static void
qla8044_minidump_process_rdocm(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)25517ec0effdSAtul Deshmukh qla8044_minidump_process_rdocm(struct scsi_qla_host *vha,
25527ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
25537ec0effdSAtul Deshmukh {
25547ec0effdSAtul Deshmukh uint32_t r_addr, r_stride, loop_cnt, i, r_value;
25557ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdocm *ocm_hdr;
25567ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr;
25577ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
25587ec0effdSAtul Deshmukh
25597ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0f9, "Entering fn: %s\n", __func__);
25607ec0effdSAtul Deshmukh
25617ec0effdSAtul Deshmukh ocm_hdr = (struct qla8044_minidump_entry_rdocm *)entry_hdr;
25627ec0effdSAtul Deshmukh r_addr = ocm_hdr->read_addr;
25637ec0effdSAtul Deshmukh r_stride = ocm_hdr->read_addr_stride;
25647ec0effdSAtul Deshmukh loop_cnt = ocm_hdr->op_count;
25657ec0effdSAtul Deshmukh
25667ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0fa,
25677ec0effdSAtul Deshmukh "[%s]: r_addr: 0x%x, r_stride: 0x%x, loop_cnt: 0x%x\n",
25687ec0effdSAtul Deshmukh __func__, r_addr, r_stride, loop_cnt);
25697ec0effdSAtul Deshmukh
25707ec0effdSAtul Deshmukh for (i = 0; i < loop_cnt; i++) {
25717ec0effdSAtul Deshmukh r_value = readl((void __iomem *)(r_addr + ha->nx_pcibase));
25727ec0effdSAtul Deshmukh *data_ptr++ = r_value;
25737ec0effdSAtul Deshmukh r_addr += r_stride;
25747ec0effdSAtul Deshmukh }
25757ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0fb, "Leaving fn: %s datacount: 0x%lx\n",
25767ec0effdSAtul Deshmukh __func__, (long unsigned int) (loop_cnt * sizeof(uint32_t)));
25777ec0effdSAtul Deshmukh
25787ec0effdSAtul Deshmukh *d_ptr = data_ptr;
25797ec0effdSAtul Deshmukh }
25807ec0effdSAtul Deshmukh
25817ec0effdSAtul Deshmukh static void
qla8044_minidump_process_rdmux(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)25827ec0effdSAtul Deshmukh qla8044_minidump_process_rdmux(struct scsi_qla_host *vha,
25837ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr,
25847ec0effdSAtul Deshmukh uint32_t **d_ptr)
25857ec0effdSAtul Deshmukh {
2586aceba54bSArun Easi uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value = 0;
25877ec0effdSAtul Deshmukh struct qla8044_minidump_entry_mux *mux_hdr;
25887ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr;
25897ec0effdSAtul Deshmukh
25907ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0fc, "Entering fn: %s\n", __func__);
25917ec0effdSAtul Deshmukh
25927ec0effdSAtul Deshmukh mux_hdr = (struct qla8044_minidump_entry_mux *)entry_hdr;
25937ec0effdSAtul Deshmukh r_addr = mux_hdr->read_addr;
25947ec0effdSAtul Deshmukh s_addr = mux_hdr->select_addr;
25957ec0effdSAtul Deshmukh s_stride = mux_hdr->select_value_stride;
25967ec0effdSAtul Deshmukh s_value = mux_hdr->select_value;
25977ec0effdSAtul Deshmukh loop_cnt = mux_hdr->op_count;
25987ec0effdSAtul Deshmukh
25997ec0effdSAtul Deshmukh for (i = 0; i < loop_cnt; i++) {
26007ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, s_addr, s_value);
26017ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, r_addr, &r_value);
26027ec0effdSAtul Deshmukh *data_ptr++ = s_value;
26037ec0effdSAtul Deshmukh *data_ptr++ = r_value;
26047ec0effdSAtul Deshmukh s_value += s_stride;
26057ec0effdSAtul Deshmukh }
26067ec0effdSAtul Deshmukh *d_ptr = data_ptr;
26077ec0effdSAtul Deshmukh }
26087ec0effdSAtul Deshmukh
26097ec0effdSAtul Deshmukh static void
qla8044_minidump_process_queue(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)26107ec0effdSAtul Deshmukh qla8044_minidump_process_queue(struct scsi_qla_host *vha,
26117ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr,
26127ec0effdSAtul Deshmukh uint32_t **d_ptr)
26137ec0effdSAtul Deshmukh {
26147ec0effdSAtul Deshmukh uint32_t s_addr, r_addr;
26157ec0effdSAtul Deshmukh uint32_t r_stride, r_value, r_cnt, qid = 0;
26167ec0effdSAtul Deshmukh uint32_t i, k, loop_cnt;
26177ec0effdSAtul Deshmukh struct qla8044_minidump_entry_queue *q_hdr;
26187ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr;
26197ec0effdSAtul Deshmukh
26207ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb0fd, "Entering fn: %s\n", __func__);
26217ec0effdSAtul Deshmukh q_hdr = (struct qla8044_minidump_entry_queue *)entry_hdr;
26227ec0effdSAtul Deshmukh s_addr = q_hdr->select_addr;
26237ec0effdSAtul Deshmukh r_cnt = q_hdr->rd_strd.read_addr_cnt;
26247ec0effdSAtul Deshmukh r_stride = q_hdr->rd_strd.read_addr_stride;
26257ec0effdSAtul Deshmukh loop_cnt = q_hdr->op_count;
26267ec0effdSAtul Deshmukh
26277ec0effdSAtul Deshmukh for (i = 0; i < loop_cnt; i++) {
26287ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, s_addr, qid);
26297ec0effdSAtul Deshmukh r_addr = q_hdr->read_addr;
26307ec0effdSAtul Deshmukh for (k = 0; k < r_cnt; k++) {
26317ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, r_addr, &r_value);
26327ec0effdSAtul Deshmukh *data_ptr++ = r_value;
26337ec0effdSAtul Deshmukh r_addr += r_stride;
26347ec0effdSAtul Deshmukh }
26357ec0effdSAtul Deshmukh qid += q_hdr->q_strd.queue_id_stride;
26367ec0effdSAtul Deshmukh }
26377ec0effdSAtul Deshmukh *d_ptr = data_ptr;
26387ec0effdSAtul Deshmukh }
26397ec0effdSAtul Deshmukh
26407ec0effdSAtul Deshmukh /* ISP83xx functions to process new minidump entries... */
26417ec0effdSAtul Deshmukh static uint32_t
qla8044_minidump_process_pollrd(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)26427ec0effdSAtul Deshmukh qla8044_minidump_process_pollrd(struct scsi_qla_host *vha,
26437ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr,
26447ec0effdSAtul Deshmukh uint32_t **d_ptr)
26457ec0effdSAtul Deshmukh {
26467ec0effdSAtul Deshmukh uint32_t r_addr, s_addr, s_value, r_value, poll_wait, poll_mask;
26477ec0effdSAtul Deshmukh uint16_t s_stride, i;
26487ec0effdSAtul Deshmukh struct qla8044_minidump_entry_pollrd *pollrd_hdr;
26497ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr;
26507ec0effdSAtul Deshmukh
26517ec0effdSAtul Deshmukh pollrd_hdr = (struct qla8044_minidump_entry_pollrd *) entry_hdr;
26527ec0effdSAtul Deshmukh s_addr = pollrd_hdr->select_addr;
26537ec0effdSAtul Deshmukh r_addr = pollrd_hdr->read_addr;
26547ec0effdSAtul Deshmukh s_value = pollrd_hdr->select_value;
26557ec0effdSAtul Deshmukh s_stride = pollrd_hdr->select_value_stride;
26567ec0effdSAtul Deshmukh
26577ec0effdSAtul Deshmukh poll_wait = pollrd_hdr->poll_wait;
26587ec0effdSAtul Deshmukh poll_mask = pollrd_hdr->poll_mask;
26597ec0effdSAtul Deshmukh
26607ec0effdSAtul Deshmukh for (i = 0; i < pollrd_hdr->op_count; i++) {
26617ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, s_addr, s_value);
26627ec0effdSAtul Deshmukh poll_wait = pollrd_hdr->poll_wait;
26637ec0effdSAtul Deshmukh while (1) {
26647ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, s_addr, &r_value);
26657ec0effdSAtul Deshmukh if ((r_value & poll_mask) != 0) {
26667ec0effdSAtul Deshmukh break;
26677ec0effdSAtul Deshmukh } else {
26687ec0effdSAtul Deshmukh usleep_range(1000, 1100);
26697ec0effdSAtul Deshmukh if (--poll_wait == 0) {
26707ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0fe,
26717ec0effdSAtul Deshmukh "%s: TIMEOUT\n", __func__);
26727ec0effdSAtul Deshmukh goto error;
26737ec0effdSAtul Deshmukh }
26747ec0effdSAtul Deshmukh }
26757ec0effdSAtul Deshmukh }
26767ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, r_addr, &r_value);
26777ec0effdSAtul Deshmukh *data_ptr++ = s_value;
26787ec0effdSAtul Deshmukh *data_ptr++ = r_value;
26797ec0effdSAtul Deshmukh
26807ec0effdSAtul Deshmukh s_value += s_stride;
26817ec0effdSAtul Deshmukh }
26827ec0effdSAtul Deshmukh *d_ptr = data_ptr;
26837ec0effdSAtul Deshmukh return QLA_SUCCESS;
26847ec0effdSAtul Deshmukh
26857ec0effdSAtul Deshmukh error:
26867ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
26877ec0effdSAtul Deshmukh }
26887ec0effdSAtul Deshmukh
26897ec0effdSAtul Deshmukh static void
qla8044_minidump_process_rdmux2(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)26907ec0effdSAtul Deshmukh qla8044_minidump_process_rdmux2(struct scsi_qla_host *vha,
26917ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
26927ec0effdSAtul Deshmukh {
26937ec0effdSAtul Deshmukh uint32_t sel_val1, sel_val2, t_sel_val, data, i;
26947ec0effdSAtul Deshmukh uint32_t sel_addr1, sel_addr2, sel_val_mask, read_addr;
26957ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdmux2 *rdmux2_hdr;
26967ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr;
26977ec0effdSAtul Deshmukh
26987ec0effdSAtul Deshmukh rdmux2_hdr = (struct qla8044_minidump_entry_rdmux2 *) entry_hdr;
26997ec0effdSAtul Deshmukh sel_val1 = rdmux2_hdr->select_value_1;
27007ec0effdSAtul Deshmukh sel_val2 = rdmux2_hdr->select_value_2;
27017ec0effdSAtul Deshmukh sel_addr1 = rdmux2_hdr->select_addr_1;
27027ec0effdSAtul Deshmukh sel_addr2 = rdmux2_hdr->select_addr_2;
27037ec0effdSAtul Deshmukh sel_val_mask = rdmux2_hdr->select_value_mask;
27047ec0effdSAtul Deshmukh read_addr = rdmux2_hdr->read_addr;
27057ec0effdSAtul Deshmukh
27067ec0effdSAtul Deshmukh for (i = 0; i < rdmux2_hdr->op_count; i++) {
27077ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, sel_addr1, sel_val1);
27087ec0effdSAtul Deshmukh t_sel_val = sel_val1 & sel_val_mask;
27097ec0effdSAtul Deshmukh *data_ptr++ = t_sel_val;
27107ec0effdSAtul Deshmukh
27117ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
27127ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, read_addr, &data);
27137ec0effdSAtul Deshmukh
27147ec0effdSAtul Deshmukh *data_ptr++ = data;
27157ec0effdSAtul Deshmukh
27167ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, sel_addr1, sel_val2);
27177ec0effdSAtul Deshmukh t_sel_val = sel_val2 & sel_val_mask;
27187ec0effdSAtul Deshmukh *data_ptr++ = t_sel_val;
27197ec0effdSAtul Deshmukh
27207ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, sel_addr2, t_sel_val);
27217ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, read_addr, &data);
27227ec0effdSAtul Deshmukh
27237ec0effdSAtul Deshmukh *data_ptr++ = data;
27247ec0effdSAtul Deshmukh
27257ec0effdSAtul Deshmukh sel_val1 += rdmux2_hdr->select_value_stride;
27267ec0effdSAtul Deshmukh sel_val2 += rdmux2_hdr->select_value_stride;
27277ec0effdSAtul Deshmukh }
27287ec0effdSAtul Deshmukh
27297ec0effdSAtul Deshmukh *d_ptr = data_ptr;
27307ec0effdSAtul Deshmukh }
27317ec0effdSAtul Deshmukh
27327ec0effdSAtul Deshmukh static uint32_t
qla8044_minidump_process_pollrdmwr(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)27337ec0effdSAtul Deshmukh qla8044_minidump_process_pollrdmwr(struct scsi_qla_host *vha,
27347ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr,
27357ec0effdSAtul Deshmukh uint32_t **d_ptr)
27367ec0effdSAtul Deshmukh {
27377ec0effdSAtul Deshmukh uint32_t poll_wait, poll_mask, r_value, data;
27387ec0effdSAtul Deshmukh uint32_t addr_1, addr_2, value_1, value_2;
27397ec0effdSAtul Deshmukh struct qla8044_minidump_entry_pollrdmwr *poll_hdr;
27407ec0effdSAtul Deshmukh uint32_t *data_ptr = *d_ptr;
27417ec0effdSAtul Deshmukh
27427ec0effdSAtul Deshmukh poll_hdr = (struct qla8044_minidump_entry_pollrdmwr *) entry_hdr;
27437ec0effdSAtul Deshmukh addr_1 = poll_hdr->addr_1;
27447ec0effdSAtul Deshmukh addr_2 = poll_hdr->addr_2;
27457ec0effdSAtul Deshmukh value_1 = poll_hdr->value_1;
27467ec0effdSAtul Deshmukh value_2 = poll_hdr->value_2;
27477ec0effdSAtul Deshmukh poll_mask = poll_hdr->poll_mask;
27487ec0effdSAtul Deshmukh
27497ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, addr_1, value_1);
27507ec0effdSAtul Deshmukh
27517ec0effdSAtul Deshmukh poll_wait = poll_hdr->poll_wait;
27527ec0effdSAtul Deshmukh while (1) {
27537ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, addr_1, &r_value);
27547ec0effdSAtul Deshmukh
27557ec0effdSAtul Deshmukh if ((r_value & poll_mask) != 0) {
27567ec0effdSAtul Deshmukh break;
27577ec0effdSAtul Deshmukh } else {
27587ec0effdSAtul Deshmukh usleep_range(1000, 1100);
27597ec0effdSAtul Deshmukh if (--poll_wait == 0) {
27607ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0ff,
27617ec0effdSAtul Deshmukh "%s: TIMEOUT\n", __func__);
27627ec0effdSAtul Deshmukh goto error;
27637ec0effdSAtul Deshmukh }
27647ec0effdSAtul Deshmukh }
27657ec0effdSAtul Deshmukh }
27667ec0effdSAtul Deshmukh
27677ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, addr_2, &data);
27687ec0effdSAtul Deshmukh data &= poll_hdr->modify_mask;
27697ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, addr_2, data);
27707ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, addr_1, value_2);
27717ec0effdSAtul Deshmukh
27727ec0effdSAtul Deshmukh poll_wait = poll_hdr->poll_wait;
27737ec0effdSAtul Deshmukh while (1) {
27747ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, addr_1, &r_value);
27757ec0effdSAtul Deshmukh
27767ec0effdSAtul Deshmukh if ((r_value & poll_mask) != 0) {
27777ec0effdSAtul Deshmukh break;
27787ec0effdSAtul Deshmukh } else {
27797ec0effdSAtul Deshmukh usleep_range(1000, 1100);
27807ec0effdSAtul Deshmukh if (--poll_wait == 0) {
27817ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb100,
27827ec0effdSAtul Deshmukh "%s: TIMEOUT2\n", __func__);
27837ec0effdSAtul Deshmukh goto error;
27847ec0effdSAtul Deshmukh }
27857ec0effdSAtul Deshmukh }
27867ec0effdSAtul Deshmukh }
27877ec0effdSAtul Deshmukh
27887ec0effdSAtul Deshmukh *data_ptr++ = addr_2;
27897ec0effdSAtul Deshmukh *data_ptr++ = data;
27907ec0effdSAtul Deshmukh
27917ec0effdSAtul Deshmukh *d_ptr = data_ptr;
27927ec0effdSAtul Deshmukh
27937ec0effdSAtul Deshmukh return QLA_SUCCESS;
27947ec0effdSAtul Deshmukh
27957ec0effdSAtul Deshmukh error:
27967ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
27977ec0effdSAtul Deshmukh }
27987ec0effdSAtul Deshmukh
27997ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_ENGINE_INDEX 8
28007ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_BASE_ADDRESS 0x77320000
2801f91ff36aSBart Van Assche #define ISP8044_PEX_DMA_NUM_OFFSET 0x10000UL
28027ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_CMD_ADDR_LOW 0x0
28037ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_CMD_ADDR_HIGH 0x04
28047ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_CMD_STS_AND_CNTRL 0x08
28057ec0effdSAtul Deshmukh
28067ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_READ_SIZE (16 * 1024)
28077ec0effdSAtul Deshmukh #define ISP8044_PEX_DMA_MAX_WAIT (100 * 100) /* Max wait of 100 msecs */
28087ec0effdSAtul Deshmukh
28097ec0effdSAtul Deshmukh static int
qla8044_check_dma_engine_state(struct scsi_qla_host * vha)28107ec0effdSAtul Deshmukh qla8044_check_dma_engine_state(struct scsi_qla_host *vha)
28117ec0effdSAtul Deshmukh {
28127ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
28137ec0effdSAtul Deshmukh int rval = QLA_SUCCESS;
28147ec0effdSAtul Deshmukh uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
28157ec0effdSAtul Deshmukh uint64_t dma_base_addr = 0;
28167ec0effdSAtul Deshmukh struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
28177ec0effdSAtul Deshmukh
28187ec0effdSAtul Deshmukh tmplt_hdr = ha->md_tmplt_hdr;
28197ec0effdSAtul Deshmukh dma_eng_num =
28207ec0effdSAtul Deshmukh tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
28217ec0effdSAtul Deshmukh dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
28227ec0effdSAtul Deshmukh (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
28237ec0effdSAtul Deshmukh
28247ec0effdSAtul Deshmukh /* Read the pex-dma's command-status-and-control register. */
28257ec0effdSAtul Deshmukh rval = qla8044_rd_reg_indirect(vha,
28267ec0effdSAtul Deshmukh (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
28277ec0effdSAtul Deshmukh &cmd_sts_and_cntrl);
28287ec0effdSAtul Deshmukh if (rval)
28297ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
28307ec0effdSAtul Deshmukh
28317ec0effdSAtul Deshmukh /* Check if requested pex-dma engine is available. */
28327ec0effdSAtul Deshmukh if (cmd_sts_and_cntrl & BIT_31)
28337ec0effdSAtul Deshmukh return QLA_SUCCESS;
28347ec0effdSAtul Deshmukh
28357ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
28367ec0effdSAtul Deshmukh }
28377ec0effdSAtul Deshmukh
28387ec0effdSAtul Deshmukh static int
qla8044_start_pex_dma(struct scsi_qla_host * vha,struct qla8044_minidump_entry_rdmem_pex_dma * m_hdr)28397ec0effdSAtul Deshmukh qla8044_start_pex_dma(struct scsi_qla_host *vha,
28407ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr)
28417ec0effdSAtul Deshmukh {
28427ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
28437ec0effdSAtul Deshmukh int rval = QLA_SUCCESS, wait = 0;
28447ec0effdSAtul Deshmukh uint32_t dma_eng_num = 0, cmd_sts_and_cntrl = 0;
28457ec0effdSAtul Deshmukh uint64_t dma_base_addr = 0;
28467ec0effdSAtul Deshmukh struct qla8044_minidump_template_hdr *tmplt_hdr = NULL;
28477ec0effdSAtul Deshmukh
28487ec0effdSAtul Deshmukh tmplt_hdr = ha->md_tmplt_hdr;
28497ec0effdSAtul Deshmukh dma_eng_num =
28507ec0effdSAtul Deshmukh tmplt_hdr->saved_state_array[ISP8044_PEX_DMA_ENGINE_INDEX];
28517ec0effdSAtul Deshmukh dma_base_addr = ISP8044_PEX_DMA_BASE_ADDRESS +
28527ec0effdSAtul Deshmukh (dma_eng_num * ISP8044_PEX_DMA_NUM_OFFSET);
28537ec0effdSAtul Deshmukh
28547ec0effdSAtul Deshmukh rval = qla8044_wr_reg_indirect(vha,
28557ec0effdSAtul Deshmukh dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_LOW,
28567ec0effdSAtul Deshmukh m_hdr->desc_card_addr);
28577ec0effdSAtul Deshmukh if (rval)
28587ec0effdSAtul Deshmukh goto error_exit;
28597ec0effdSAtul Deshmukh
28607ec0effdSAtul Deshmukh rval = qla8044_wr_reg_indirect(vha,
28617ec0effdSAtul Deshmukh dma_base_addr + ISP8044_PEX_DMA_CMD_ADDR_HIGH, 0);
28627ec0effdSAtul Deshmukh if (rval)
28637ec0effdSAtul Deshmukh goto error_exit;
28647ec0effdSAtul Deshmukh
28657ec0effdSAtul Deshmukh rval = qla8044_wr_reg_indirect(vha,
28667ec0effdSAtul Deshmukh dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL,
28677ec0effdSAtul Deshmukh m_hdr->start_dma_cmd);
28687ec0effdSAtul Deshmukh if (rval)
28697ec0effdSAtul Deshmukh goto error_exit;
28707ec0effdSAtul Deshmukh
28717ec0effdSAtul Deshmukh /* Wait for dma operation to complete. */
28727ec0effdSAtul Deshmukh for (wait = 0; wait < ISP8044_PEX_DMA_MAX_WAIT; wait++) {
28737ec0effdSAtul Deshmukh rval = qla8044_rd_reg_indirect(vha,
28747ec0effdSAtul Deshmukh (dma_base_addr + ISP8044_PEX_DMA_CMD_STS_AND_CNTRL),
28757ec0effdSAtul Deshmukh &cmd_sts_and_cntrl);
28767ec0effdSAtul Deshmukh if (rval)
28777ec0effdSAtul Deshmukh goto error_exit;
28787ec0effdSAtul Deshmukh
28797ec0effdSAtul Deshmukh if ((cmd_sts_and_cntrl & BIT_1) == 0)
28807ec0effdSAtul Deshmukh break;
28817ec0effdSAtul Deshmukh
28827ec0effdSAtul Deshmukh udelay(10);
28837ec0effdSAtul Deshmukh }
28847ec0effdSAtul Deshmukh
28857ec0effdSAtul Deshmukh /* Wait a max of 100 ms, otherwise fallback to rdmem entry read */
28867ec0effdSAtul Deshmukh if (wait >= ISP8044_PEX_DMA_MAX_WAIT) {
28877ec0effdSAtul Deshmukh rval = QLA_FUNCTION_FAILED;
28887ec0effdSAtul Deshmukh goto error_exit;
28897ec0effdSAtul Deshmukh }
28907ec0effdSAtul Deshmukh
28917ec0effdSAtul Deshmukh error_exit:
28927ec0effdSAtul Deshmukh return rval;
28937ec0effdSAtul Deshmukh }
28947ec0effdSAtul Deshmukh
28957ec0effdSAtul Deshmukh static int
qla8044_minidump_pex_dma_read(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)28967ec0effdSAtul Deshmukh qla8044_minidump_pex_dma_read(struct scsi_qla_host *vha,
28977ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
28987ec0effdSAtul Deshmukh {
28997ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
29007ec0effdSAtul Deshmukh int rval = QLA_SUCCESS;
29017ec0effdSAtul Deshmukh struct qla8044_minidump_entry_rdmem_pex_dma *m_hdr = NULL;
29027ec0effdSAtul Deshmukh uint32_t chunk_size, read_size;
29037ec0effdSAtul Deshmukh uint8_t *data_ptr = (uint8_t *)*d_ptr;
29047ec0effdSAtul Deshmukh void *rdmem_buffer = NULL;
29057ec0effdSAtul Deshmukh dma_addr_t rdmem_dma;
29067ec0effdSAtul Deshmukh struct qla8044_pex_dma_descriptor dma_desc;
29077ec0effdSAtul Deshmukh
29087ec0effdSAtul Deshmukh rval = qla8044_check_dma_engine_state(vha);
29097ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) {
29107ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb147,
29117ec0effdSAtul Deshmukh "DMA engine not available. Fallback to rdmem-read.\n");
29127ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
29137ec0effdSAtul Deshmukh }
29147ec0effdSAtul Deshmukh
29157ec0effdSAtul Deshmukh m_hdr = (void *)entry_hdr;
29167ec0effdSAtul Deshmukh
29177ec0effdSAtul Deshmukh rdmem_buffer = dma_alloc_coherent(&ha->pdev->dev,
29187ec0effdSAtul Deshmukh ISP8044_PEX_DMA_READ_SIZE, &rdmem_dma, GFP_KERNEL);
29197ec0effdSAtul Deshmukh if (!rdmem_buffer) {
29207ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb148,
29217ec0effdSAtul Deshmukh "Unable to allocate rdmem dma buffer\n");
29227ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
29237ec0effdSAtul Deshmukh }
29247ec0effdSAtul Deshmukh
29257ec0effdSAtul Deshmukh /* Prepare pex-dma descriptor to be written to MS memory. */
29267ec0effdSAtul Deshmukh /* dma-desc-cmd layout:
29277ec0effdSAtul Deshmukh * 0-3: dma-desc-cmd 0-3
29287ec0effdSAtul Deshmukh * 4-7: pcid function number
29297ec0effdSAtul Deshmukh * 8-15: dma-desc-cmd 8-15
29307ec0effdSAtul Deshmukh * dma_bus_addr: dma buffer address
29317ec0effdSAtul Deshmukh * cmd.read_data_size: amount of data-chunk to be read.
29327ec0effdSAtul Deshmukh */
29337ec0effdSAtul Deshmukh dma_desc.cmd.dma_desc_cmd = (m_hdr->dma_desc_cmd & 0xff0f);
29347ec0effdSAtul Deshmukh dma_desc.cmd.dma_desc_cmd |=
29357ec0effdSAtul Deshmukh ((PCI_FUNC(ha->pdev->devfn) & 0xf) << 0x4);
29367ec0effdSAtul Deshmukh
29377ec0effdSAtul Deshmukh dma_desc.dma_bus_addr = rdmem_dma;
29387ec0effdSAtul Deshmukh dma_desc.cmd.read_data_size = chunk_size = ISP8044_PEX_DMA_READ_SIZE;
29397ec0effdSAtul Deshmukh read_size = 0;
29407ec0effdSAtul Deshmukh
29417ec0effdSAtul Deshmukh /*
29427ec0effdSAtul Deshmukh * Perform rdmem operation using pex-dma.
29437ec0effdSAtul Deshmukh * Prepare dma in chunks of ISP8044_PEX_DMA_READ_SIZE.
29447ec0effdSAtul Deshmukh */
29457ec0effdSAtul Deshmukh while (read_size < m_hdr->read_data_size) {
29467ec0effdSAtul Deshmukh if (m_hdr->read_data_size - read_size <
29477ec0effdSAtul Deshmukh ISP8044_PEX_DMA_READ_SIZE) {
29487ec0effdSAtul Deshmukh chunk_size = (m_hdr->read_data_size - read_size);
29497ec0effdSAtul Deshmukh dma_desc.cmd.read_data_size = chunk_size;
29507ec0effdSAtul Deshmukh }
29517ec0effdSAtul Deshmukh
29527ec0effdSAtul Deshmukh dma_desc.src_addr = m_hdr->read_addr + read_size;
29537ec0effdSAtul Deshmukh
29547ec0effdSAtul Deshmukh /* Prepare: Write pex-dma descriptor to MS memory. */
29557ec0effdSAtul Deshmukh rval = qla8044_ms_mem_write_128b(vha,
2956ab053c09SBart Van Assche m_hdr->desc_card_addr, (uint32_t *)&dma_desc,
29577ec0effdSAtul Deshmukh (sizeof(struct qla8044_pex_dma_descriptor)/16));
29587ec0effdSAtul Deshmukh if (rval) {
29597ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb14a,
29607ec0effdSAtul Deshmukh "%s: Error writing rdmem-dma-init to MS !!!\n",
29617ec0effdSAtul Deshmukh __func__);
29627ec0effdSAtul Deshmukh goto error_exit;
29637ec0effdSAtul Deshmukh }
29647ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb14b,
29657ec0effdSAtul Deshmukh "%s: Dma-descriptor: Instruct for rdmem dma "
29667ec0effdSAtul Deshmukh "(chunk_size 0x%x).\n", __func__, chunk_size);
29677ec0effdSAtul Deshmukh
29687ec0effdSAtul Deshmukh /* Execute: Start pex-dma operation. */
29697ec0effdSAtul Deshmukh rval = qla8044_start_pex_dma(vha, m_hdr);
29707ec0effdSAtul Deshmukh if (rval)
29717ec0effdSAtul Deshmukh goto error_exit;
29727ec0effdSAtul Deshmukh
29737ec0effdSAtul Deshmukh memcpy(data_ptr, rdmem_buffer, chunk_size);
29747ec0effdSAtul Deshmukh data_ptr += chunk_size;
29757ec0effdSAtul Deshmukh read_size += chunk_size;
29767ec0effdSAtul Deshmukh }
29777ec0effdSAtul Deshmukh
2978ab053c09SBart Van Assche *d_ptr = (uint32_t *)data_ptr;
29797ec0effdSAtul Deshmukh
29807ec0effdSAtul Deshmukh error_exit:
29817ec0effdSAtul Deshmukh if (rdmem_buffer)
29827ec0effdSAtul Deshmukh dma_free_coherent(&ha->pdev->dev, ISP8044_PEX_DMA_READ_SIZE,
29837ec0effdSAtul Deshmukh rdmem_buffer, rdmem_dma);
29847ec0effdSAtul Deshmukh
29857ec0effdSAtul Deshmukh return rval;
29867ec0effdSAtul Deshmukh }
29877ec0effdSAtul Deshmukh
2988804df800SPratik Mohanty static uint32_t
qla8044_minidump_process_rddfe(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)2989804df800SPratik Mohanty qla8044_minidump_process_rddfe(struct scsi_qla_host *vha,
2990804df800SPratik Mohanty struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
2991804df800SPratik Mohanty {
2992804df800SPratik Mohanty int loop_cnt;
2993804df800SPratik Mohanty uint32_t addr1, addr2, value, data, temp, wrVal;
2994804df800SPratik Mohanty uint8_t stride, stride2;
2995804df800SPratik Mohanty uint16_t count;
299652c82823SBart Van Assche uint32_t poll, mask, modify_mask;
2997804df800SPratik Mohanty uint32_t wait_count = 0;
2998804df800SPratik Mohanty uint32_t *data_ptr = *d_ptr;
2999804df800SPratik Mohanty struct qla8044_minidump_entry_rddfe *rddfe;
3000bd432bb5SBart Van Assche
3001804df800SPratik Mohanty rddfe = (struct qla8044_minidump_entry_rddfe *) entry_hdr;
3002804df800SPratik Mohanty
3003804df800SPratik Mohanty addr1 = rddfe->addr_1;
3004804df800SPratik Mohanty value = rddfe->value;
3005804df800SPratik Mohanty stride = rddfe->stride;
3006804df800SPratik Mohanty stride2 = rddfe->stride2;
3007804df800SPratik Mohanty count = rddfe->count;
3008804df800SPratik Mohanty
3009804df800SPratik Mohanty poll = rddfe->poll;
3010804df800SPratik Mohanty mask = rddfe->mask;
3011804df800SPratik Mohanty modify_mask = rddfe->modify_mask;
3012804df800SPratik Mohanty
3013804df800SPratik Mohanty addr2 = addr1 + stride;
3014804df800SPratik Mohanty
3015804df800SPratik Mohanty for (loop_cnt = 0x0; loop_cnt < count; loop_cnt++) {
3016804df800SPratik Mohanty qla8044_wr_reg_indirect(vha, addr1, (0x40000000 | value));
3017804df800SPratik Mohanty
3018804df800SPratik Mohanty wait_count = 0;
3019804df800SPratik Mohanty while (wait_count < poll) {
3020804df800SPratik Mohanty qla8044_rd_reg_indirect(vha, addr1, &temp);
3021804df800SPratik Mohanty if ((temp & mask) != 0)
3022804df800SPratik Mohanty break;
3023804df800SPratik Mohanty wait_count++;
3024804df800SPratik Mohanty }
3025804df800SPratik Mohanty
3026804df800SPratik Mohanty if (wait_count == poll) {
3027804df800SPratik Mohanty ql_log(ql_log_warn, vha, 0xb153,
3028804df800SPratik Mohanty "%s: TIMEOUT\n", __func__);
3029804df800SPratik Mohanty goto error;
3030804df800SPratik Mohanty } else {
3031804df800SPratik Mohanty qla8044_rd_reg_indirect(vha, addr2, &temp);
3032804df800SPratik Mohanty temp = temp & modify_mask;
3033804df800SPratik Mohanty temp = (temp | ((loop_cnt << 16) | loop_cnt));
3034804df800SPratik Mohanty wrVal = ((temp << 16) | temp);
3035804df800SPratik Mohanty
3036804df800SPratik Mohanty qla8044_wr_reg_indirect(vha, addr2, wrVal);
3037804df800SPratik Mohanty qla8044_wr_reg_indirect(vha, addr1, value);
3038804df800SPratik Mohanty
3039804df800SPratik Mohanty wait_count = 0;
3040804df800SPratik Mohanty while (wait_count < poll) {
3041804df800SPratik Mohanty qla8044_rd_reg_indirect(vha, addr1, &temp);
3042804df800SPratik Mohanty if ((temp & mask) != 0)
3043804df800SPratik Mohanty break;
3044804df800SPratik Mohanty wait_count++;
3045804df800SPratik Mohanty }
3046804df800SPratik Mohanty if (wait_count == poll) {
3047804df800SPratik Mohanty ql_log(ql_log_warn, vha, 0xb154,
3048804df800SPratik Mohanty "%s: TIMEOUT\n", __func__);
3049804df800SPratik Mohanty goto error;
3050804df800SPratik Mohanty }
3051804df800SPratik Mohanty
3052804df800SPratik Mohanty qla8044_wr_reg_indirect(vha, addr1,
3053804df800SPratik Mohanty ((0x40000000 | value) + stride2));
3054804df800SPratik Mohanty wait_count = 0;
3055804df800SPratik Mohanty while (wait_count < poll) {
3056804df800SPratik Mohanty qla8044_rd_reg_indirect(vha, addr1, &temp);
3057804df800SPratik Mohanty if ((temp & mask) != 0)
3058804df800SPratik Mohanty break;
3059804df800SPratik Mohanty wait_count++;
3060804df800SPratik Mohanty }
3061804df800SPratik Mohanty
3062804df800SPratik Mohanty if (wait_count == poll) {
3063804df800SPratik Mohanty ql_log(ql_log_warn, vha, 0xb155,
3064804df800SPratik Mohanty "%s: TIMEOUT\n", __func__);
3065804df800SPratik Mohanty goto error;
3066804df800SPratik Mohanty }
3067804df800SPratik Mohanty
3068804df800SPratik Mohanty qla8044_rd_reg_indirect(vha, addr2, &data);
3069804df800SPratik Mohanty
3070804df800SPratik Mohanty *data_ptr++ = wrVal;
3071804df800SPratik Mohanty *data_ptr++ = data;
3072804df800SPratik Mohanty }
3073804df800SPratik Mohanty
3074804df800SPratik Mohanty }
3075804df800SPratik Mohanty
3076804df800SPratik Mohanty *d_ptr = data_ptr;
3077804df800SPratik Mohanty return QLA_SUCCESS;
3078804df800SPratik Mohanty
3079804df800SPratik Mohanty error:
3080804df800SPratik Mohanty return -1;
3081804df800SPratik Mohanty
3082804df800SPratik Mohanty }
3083804df800SPratik Mohanty
3084804df800SPratik Mohanty static uint32_t
qla8044_minidump_process_rdmdio(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)3085804df800SPratik Mohanty qla8044_minidump_process_rdmdio(struct scsi_qla_host *vha,
3086804df800SPratik Mohanty struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
3087804df800SPratik Mohanty {
3088804df800SPratik Mohanty int ret = 0;
3089804df800SPratik Mohanty uint32_t addr1, addr2, value1, value2, data, selVal;
3090804df800SPratik Mohanty uint8_t stride1, stride2;
3091804df800SPratik Mohanty uint32_t addr3, addr4, addr5, addr6, addr7;
3092804df800SPratik Mohanty uint16_t count, loop_cnt;
309352c82823SBart Van Assche uint32_t mask;
3094804df800SPratik Mohanty uint32_t *data_ptr = *d_ptr;
3095804df800SPratik Mohanty
3096804df800SPratik Mohanty struct qla8044_minidump_entry_rdmdio *rdmdio;
3097804df800SPratik Mohanty
3098804df800SPratik Mohanty rdmdio = (struct qla8044_minidump_entry_rdmdio *) entry_hdr;
3099804df800SPratik Mohanty
3100804df800SPratik Mohanty addr1 = rdmdio->addr_1;
3101804df800SPratik Mohanty addr2 = rdmdio->addr_2;
3102804df800SPratik Mohanty value1 = rdmdio->value_1;
3103804df800SPratik Mohanty stride1 = rdmdio->stride_1;
3104804df800SPratik Mohanty stride2 = rdmdio->stride_2;
3105804df800SPratik Mohanty count = rdmdio->count;
3106804df800SPratik Mohanty
3107804df800SPratik Mohanty mask = rdmdio->mask;
3108804df800SPratik Mohanty value2 = rdmdio->value_2;
3109804df800SPratik Mohanty
3110804df800SPratik Mohanty addr3 = addr1 + stride1;
3111804df800SPratik Mohanty
3112804df800SPratik Mohanty for (loop_cnt = 0; loop_cnt < count; loop_cnt++) {
3113804df800SPratik Mohanty ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
3114804df800SPratik Mohanty addr3, mask);
3115804df800SPratik Mohanty if (ret == -1)
3116804df800SPratik Mohanty goto error;
3117804df800SPratik Mohanty
3118804df800SPratik Mohanty addr4 = addr2 - stride1;
3119804df800SPratik Mohanty ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr4,
3120804df800SPratik Mohanty value2);
3121804df800SPratik Mohanty if (ret == -1)
3122804df800SPratik Mohanty goto error;
3123804df800SPratik Mohanty
3124804df800SPratik Mohanty addr5 = addr2 - (2 * stride1);
3125804df800SPratik Mohanty ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask, addr5,
3126804df800SPratik Mohanty value1);
3127804df800SPratik Mohanty if (ret == -1)
3128804df800SPratik Mohanty goto error;
3129804df800SPratik Mohanty
3130804df800SPratik Mohanty addr6 = addr2 - (3 * stride1);
3131804df800SPratik Mohanty ret = qla8044_ipmdio_wr_reg(vha, addr1, addr3, mask,
3132804df800SPratik Mohanty addr6, 0x2);
3133804df800SPratik Mohanty if (ret == -1)
3134804df800SPratik Mohanty goto error;
3135804df800SPratik Mohanty
3136804df800SPratik Mohanty ret = qla8044_poll_wait_ipmdio_bus_idle(vha, addr1, addr2,
3137804df800SPratik Mohanty addr3, mask);
3138804df800SPratik Mohanty if (ret == -1)
3139804df800SPratik Mohanty goto error;
3140804df800SPratik Mohanty
3141804df800SPratik Mohanty addr7 = addr2 - (4 * stride1);
31428d2b21dbSBart Van Assche data = qla8044_ipmdio_rd_reg(vha, addr1, addr3, mask, addr7);
3143804df800SPratik Mohanty if (data == -1)
3144804df800SPratik Mohanty goto error;
3145804df800SPratik Mohanty
3146804df800SPratik Mohanty selVal = (value2 << 18) | (value1 << 2) | 2;
3147804df800SPratik Mohanty
3148804df800SPratik Mohanty stride2 = rdmdio->stride_2;
3149804df800SPratik Mohanty *data_ptr++ = selVal;
3150804df800SPratik Mohanty *data_ptr++ = data;
3151804df800SPratik Mohanty
3152804df800SPratik Mohanty value1 = value1 + stride2;
3153804df800SPratik Mohanty *d_ptr = data_ptr;
3154804df800SPratik Mohanty }
3155804df800SPratik Mohanty
3156804df800SPratik Mohanty return 0;
3157804df800SPratik Mohanty
3158804df800SPratik Mohanty error:
3159804df800SPratik Mohanty return -1;
3160804df800SPratik Mohanty }
3161804df800SPratik Mohanty
qla8044_minidump_process_pollwr(struct scsi_qla_host * vha,struct qla8044_minidump_entry_hdr * entry_hdr,uint32_t ** d_ptr)3162804df800SPratik Mohanty static uint32_t qla8044_minidump_process_pollwr(struct scsi_qla_host *vha,
3163804df800SPratik Mohanty struct qla8044_minidump_entry_hdr *entry_hdr, uint32_t **d_ptr)
3164804df800SPratik Mohanty {
316552c82823SBart Van Assche uint32_t addr1, addr2, value1, value2, poll, r_value;
3166804df800SPratik Mohanty uint32_t wait_count = 0;
3167804df800SPratik Mohanty struct qla8044_minidump_entry_pollwr *pollwr_hdr;
3168804df800SPratik Mohanty
3169804df800SPratik Mohanty pollwr_hdr = (struct qla8044_minidump_entry_pollwr *)entry_hdr;
3170804df800SPratik Mohanty addr1 = pollwr_hdr->addr_1;
3171804df800SPratik Mohanty addr2 = pollwr_hdr->addr_2;
3172804df800SPratik Mohanty value1 = pollwr_hdr->value_1;
3173804df800SPratik Mohanty value2 = pollwr_hdr->value_2;
3174804df800SPratik Mohanty
3175804df800SPratik Mohanty poll = pollwr_hdr->poll;
3176804df800SPratik Mohanty
3177804df800SPratik Mohanty while (wait_count < poll) {
3178804df800SPratik Mohanty qla8044_rd_reg_indirect(vha, addr1, &r_value);
3179804df800SPratik Mohanty
3180804df800SPratik Mohanty if ((r_value & poll) != 0)
3181804df800SPratik Mohanty break;
3182804df800SPratik Mohanty wait_count++;
3183804df800SPratik Mohanty }
3184804df800SPratik Mohanty
3185804df800SPratik Mohanty if (wait_count == poll) {
3186804df800SPratik Mohanty ql_log(ql_log_warn, vha, 0xb156, "%s: TIMEOUT\n", __func__);
3187804df800SPratik Mohanty goto error;
3188804df800SPratik Mohanty }
3189804df800SPratik Mohanty
3190804df800SPratik Mohanty qla8044_wr_reg_indirect(vha, addr2, value2);
3191804df800SPratik Mohanty qla8044_wr_reg_indirect(vha, addr1, value1);
3192804df800SPratik Mohanty
3193804df800SPratik Mohanty wait_count = 0;
3194804df800SPratik Mohanty while (wait_count < poll) {
3195804df800SPratik Mohanty qla8044_rd_reg_indirect(vha, addr1, &r_value);
3196804df800SPratik Mohanty
3197804df800SPratik Mohanty if ((r_value & poll) != 0)
3198804df800SPratik Mohanty break;
3199804df800SPratik Mohanty wait_count++;
3200804df800SPratik Mohanty }
3201804df800SPratik Mohanty
3202804df800SPratik Mohanty return QLA_SUCCESS;
3203804df800SPratik Mohanty
3204804df800SPratik Mohanty error:
3205804df800SPratik Mohanty return -1;
3206804df800SPratik Mohanty }
3207804df800SPratik Mohanty
32087ec0effdSAtul Deshmukh /*
32097ec0effdSAtul Deshmukh *
32107ec0effdSAtul Deshmukh * qla8044_collect_md_data - Retrieve firmware minidump data.
32117ec0effdSAtul Deshmukh * @ha: pointer to adapter structure
32127ec0effdSAtul Deshmukh **/
32137ec0effdSAtul Deshmukh int
qla8044_collect_md_data(struct scsi_qla_host * vha)32147ec0effdSAtul Deshmukh qla8044_collect_md_data(struct scsi_qla_host *vha)
32157ec0effdSAtul Deshmukh {
32167ec0effdSAtul Deshmukh int num_entry_hdr = 0;
32177ec0effdSAtul Deshmukh struct qla8044_minidump_entry_hdr *entry_hdr;
32187ec0effdSAtul Deshmukh struct qla8044_minidump_template_hdr *tmplt_hdr;
32197ec0effdSAtul Deshmukh uint32_t *data_ptr;
32207ec0effdSAtul Deshmukh uint32_t data_collected = 0, f_capture_mask;
32217ec0effdSAtul Deshmukh int i, rval = QLA_FUNCTION_FAILED;
32227ec0effdSAtul Deshmukh uint64_t now;
32237ec0effdSAtul Deshmukh uint32_t timestamp, idc_control;
32247ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
32257ec0effdSAtul Deshmukh
32267ec0effdSAtul Deshmukh if (!ha->md_dump) {
32277ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb101,
32287ec0effdSAtul Deshmukh "%s(%ld) No buffer to dump\n",
32297ec0effdSAtul Deshmukh __func__, vha->host_no);
32307ec0effdSAtul Deshmukh return rval;
32317ec0effdSAtul Deshmukh }
32327ec0effdSAtul Deshmukh
32337ec0effdSAtul Deshmukh if (ha->fw_dumped) {
32347ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb10d,
32357ec0effdSAtul Deshmukh "Firmware has been previously dumped (%p) "
32367ec0effdSAtul Deshmukh "-- ignoring request.\n", ha->fw_dump);
32377ec0effdSAtul Deshmukh goto md_failed;
32387ec0effdSAtul Deshmukh }
32397ec0effdSAtul Deshmukh
3240dbe6f492SJason Yan ha->fw_dumped = false;
32417ec0effdSAtul Deshmukh
32427ec0effdSAtul Deshmukh if (!ha->md_tmplt_hdr || !ha->md_dump) {
32437ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb10e,
32447ec0effdSAtul Deshmukh "Memory not allocated for minidump capture\n");
32457ec0effdSAtul Deshmukh goto md_failed;
32467ec0effdSAtul Deshmukh }
32477ec0effdSAtul Deshmukh
32487ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
32497ec0effdSAtul Deshmukh idc_control = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
32507ec0effdSAtul Deshmukh if (idc_control & GRACEFUL_RESET_BIT1) {
32517ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb112,
32527ec0effdSAtul Deshmukh "Forced reset from application, "
32537ec0effdSAtul Deshmukh "ignore minidump capture\n");
32547ec0effdSAtul Deshmukh qla8044_wr_reg(ha, QLA8044_IDC_DRV_CTRL,
32557ec0effdSAtul Deshmukh (idc_control & ~GRACEFUL_RESET_BIT1));
32567ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
32577ec0effdSAtul Deshmukh
32587ec0effdSAtul Deshmukh goto md_failed;
32597ec0effdSAtul Deshmukh }
32607ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
32617ec0effdSAtul Deshmukh
32627ec0effdSAtul Deshmukh if (qla82xx_validate_template_chksum(vha)) {
32637ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb109,
32647ec0effdSAtul Deshmukh "Template checksum validation error\n");
32657ec0effdSAtul Deshmukh goto md_failed;
32667ec0effdSAtul Deshmukh }
32677ec0effdSAtul Deshmukh
32687ec0effdSAtul Deshmukh tmplt_hdr = (struct qla8044_minidump_template_hdr *)
32697ec0effdSAtul Deshmukh ha->md_tmplt_hdr;
32707ec0effdSAtul Deshmukh data_ptr = (uint32_t *)((uint8_t *)ha->md_dump);
32717ec0effdSAtul Deshmukh num_entry_hdr = tmplt_hdr->num_of_entries;
32727ec0effdSAtul Deshmukh
32737ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb11a,
32747ec0effdSAtul Deshmukh "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
32757ec0effdSAtul Deshmukh
32767ec0effdSAtul Deshmukh f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
32777ec0effdSAtul Deshmukh
32787ec0effdSAtul Deshmukh /* Validate whether required debug level is set */
32797ec0effdSAtul Deshmukh if ((f_capture_mask & 0x3) != 0x3) {
32807ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb10f,
32817ec0effdSAtul Deshmukh "Minimum required capture mask[0x%x] level not set\n",
32827ec0effdSAtul Deshmukh f_capture_mask);
32837ec0effdSAtul Deshmukh
32847ec0effdSAtul Deshmukh }
32857ec0effdSAtul Deshmukh tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
32867ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb102,
32877ec0effdSAtul Deshmukh "[%s]: starting data ptr: %p\n",
32887ec0effdSAtul Deshmukh __func__, data_ptr);
32897ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb10b,
32907ec0effdSAtul Deshmukh "[%s]: no of entry headers in Template: 0x%x\n",
32917ec0effdSAtul Deshmukh __func__, num_entry_hdr);
32927ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb10c,
32937ec0effdSAtul Deshmukh "[%s]: Total_data_size 0x%x, %d obtained\n",
32947ec0effdSAtul Deshmukh __func__, ha->md_dump_size, ha->md_dump_size);
32957ec0effdSAtul Deshmukh
32967ec0effdSAtul Deshmukh /* Update current timestamp before taking dump */
32977ec0effdSAtul Deshmukh now = get_jiffies_64();
32987ec0effdSAtul Deshmukh timestamp = (u32)(jiffies_to_msecs(now) / 1000);
32997ec0effdSAtul Deshmukh tmplt_hdr->driver_timestamp = timestamp;
33007ec0effdSAtul Deshmukh
33017ec0effdSAtul Deshmukh entry_hdr = (struct qla8044_minidump_entry_hdr *)
33027ec0effdSAtul Deshmukh (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
33037ec0effdSAtul Deshmukh tmplt_hdr->saved_state_array[QLA8044_SS_OCM_WNDREG_INDEX] =
33047ec0effdSAtul Deshmukh tmplt_hdr->ocm_window_reg[ha->portnum];
33057ec0effdSAtul Deshmukh
33067ec0effdSAtul Deshmukh /* Walk through the entry headers - validate/perform required action */
33077ec0effdSAtul Deshmukh for (i = 0; i < num_entry_hdr; i++) {
33087ec0effdSAtul Deshmukh if (data_collected > ha->md_dump_size) {
33097ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb103,
33107ec0effdSAtul Deshmukh "Data collected: [0x%x], "
33117ec0effdSAtul Deshmukh "Total Dump size: [0x%x]\n",
33127ec0effdSAtul Deshmukh data_collected, ha->md_dump_size);
33137ec0effdSAtul Deshmukh return rval;
33147ec0effdSAtul Deshmukh }
33157ec0effdSAtul Deshmukh
33167ec0effdSAtul Deshmukh if (!(entry_hdr->d_ctrl.entry_capture_mask &
33177ec0effdSAtul Deshmukh ql2xmdcapmask)) {
33187ec0effdSAtul Deshmukh entry_hdr->d_ctrl.driver_flags |=
33197ec0effdSAtul Deshmukh QLA82XX_DBG_SKIPPED_FLAG;
33207ec0effdSAtul Deshmukh goto skip_nxt_entry;
33217ec0effdSAtul Deshmukh }
33227ec0effdSAtul Deshmukh
33237ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb104,
33247ec0effdSAtul Deshmukh "Data collected: [0x%x], Dump size left:[0x%x]\n",
33257ec0effdSAtul Deshmukh data_collected,
33267ec0effdSAtul Deshmukh (ha->md_dump_size - data_collected));
33277ec0effdSAtul Deshmukh
33287ec0effdSAtul Deshmukh /* Decode the entry type and take required action to capture
33297ec0effdSAtul Deshmukh * debug data
33307ec0effdSAtul Deshmukh */
33317ec0effdSAtul Deshmukh switch (entry_hdr->entry_type) {
33327ec0effdSAtul Deshmukh case QLA82XX_RDEND:
33337ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, entry_hdr, i);
33347ec0effdSAtul Deshmukh break;
33357ec0effdSAtul Deshmukh case QLA82XX_CNTRL:
33367ec0effdSAtul Deshmukh rval = qla8044_minidump_process_control(vha,
33377ec0effdSAtul Deshmukh entry_hdr);
33387ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) {
33397ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, entry_hdr, i);
33407ec0effdSAtul Deshmukh goto md_failed;
33417ec0effdSAtul Deshmukh }
33427ec0effdSAtul Deshmukh break;
33437ec0effdSAtul Deshmukh case QLA82XX_RDCRB:
33447ec0effdSAtul Deshmukh qla8044_minidump_process_rdcrb(vha,
33457ec0effdSAtul Deshmukh entry_hdr, &data_ptr);
33467ec0effdSAtul Deshmukh break;
33477ec0effdSAtul Deshmukh case QLA82XX_RDMEM:
33487ec0effdSAtul Deshmukh rval = qla8044_minidump_pex_dma_read(vha,
33497ec0effdSAtul Deshmukh entry_hdr, &data_ptr);
33507ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) {
33517ec0effdSAtul Deshmukh rval = qla8044_minidump_process_rdmem(vha,
33527ec0effdSAtul Deshmukh entry_hdr, &data_ptr);
33537ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) {
33547ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha,
33557ec0effdSAtul Deshmukh entry_hdr, i);
33567ec0effdSAtul Deshmukh goto md_failed;
33577ec0effdSAtul Deshmukh }
33587ec0effdSAtul Deshmukh }
33597ec0effdSAtul Deshmukh break;
33607ec0effdSAtul Deshmukh case QLA82XX_BOARD:
33617ec0effdSAtul Deshmukh case QLA82XX_RDROM:
33627ec0effdSAtul Deshmukh rval = qla8044_minidump_process_rdrom(vha,
33637ec0effdSAtul Deshmukh entry_hdr, &data_ptr);
33647ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) {
33657ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha,
33667ec0effdSAtul Deshmukh entry_hdr, i);
33677ec0effdSAtul Deshmukh }
33687ec0effdSAtul Deshmukh break;
33697ec0effdSAtul Deshmukh case QLA82XX_L2DTG:
33707ec0effdSAtul Deshmukh case QLA82XX_L2ITG:
33717ec0effdSAtul Deshmukh case QLA82XX_L2DAT:
33727ec0effdSAtul Deshmukh case QLA82XX_L2INS:
33737ec0effdSAtul Deshmukh rval = qla8044_minidump_process_l2tag(vha,
33747ec0effdSAtul Deshmukh entry_hdr, &data_ptr);
33757ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS) {
33767ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, entry_hdr, i);
33777ec0effdSAtul Deshmukh goto md_failed;
33787ec0effdSAtul Deshmukh }
33797ec0effdSAtul Deshmukh break;
33807ec0effdSAtul Deshmukh case QLA8044_L1DTG:
33817ec0effdSAtul Deshmukh case QLA8044_L1ITG:
33827ec0effdSAtul Deshmukh case QLA82XX_L1DAT:
33837ec0effdSAtul Deshmukh case QLA82XX_L1INS:
33847ec0effdSAtul Deshmukh qla8044_minidump_process_l1cache(vha,
33857ec0effdSAtul Deshmukh entry_hdr, &data_ptr);
33867ec0effdSAtul Deshmukh break;
33877ec0effdSAtul Deshmukh case QLA82XX_RDOCM:
33887ec0effdSAtul Deshmukh qla8044_minidump_process_rdocm(vha,
33897ec0effdSAtul Deshmukh entry_hdr, &data_ptr);
33907ec0effdSAtul Deshmukh break;
33917ec0effdSAtul Deshmukh case QLA82XX_RDMUX:
33927ec0effdSAtul Deshmukh qla8044_minidump_process_rdmux(vha,
33937ec0effdSAtul Deshmukh entry_hdr, &data_ptr);
33947ec0effdSAtul Deshmukh break;
33957ec0effdSAtul Deshmukh case QLA82XX_QUEUE:
33967ec0effdSAtul Deshmukh qla8044_minidump_process_queue(vha,
33977ec0effdSAtul Deshmukh entry_hdr, &data_ptr);
33987ec0effdSAtul Deshmukh break;
33997ec0effdSAtul Deshmukh case QLA8044_POLLRD:
34007ec0effdSAtul Deshmukh rval = qla8044_minidump_process_pollrd(vha,
34017ec0effdSAtul Deshmukh entry_hdr, &data_ptr);
34027ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS)
34037ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, entry_hdr, i);
34047ec0effdSAtul Deshmukh break;
34057ec0effdSAtul Deshmukh case QLA8044_RDMUX2:
34067ec0effdSAtul Deshmukh qla8044_minidump_process_rdmux2(vha,
34077ec0effdSAtul Deshmukh entry_hdr, &data_ptr);
34087ec0effdSAtul Deshmukh break;
34097ec0effdSAtul Deshmukh case QLA8044_POLLRDMWR:
34107ec0effdSAtul Deshmukh rval = qla8044_minidump_process_pollrdmwr(vha,
34117ec0effdSAtul Deshmukh entry_hdr, &data_ptr);
34127ec0effdSAtul Deshmukh if (rval != QLA_SUCCESS)
34137ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, entry_hdr, i);
34147ec0effdSAtul Deshmukh break;
3415804df800SPratik Mohanty case QLA8044_RDDFE:
3416804df800SPratik Mohanty rval = qla8044_minidump_process_rddfe(vha, entry_hdr,
3417804df800SPratik Mohanty &data_ptr);
3418804df800SPratik Mohanty if (rval != QLA_SUCCESS)
3419804df800SPratik Mohanty qla8044_mark_entry_skipped(vha, entry_hdr, i);
3420804df800SPratik Mohanty break;
3421804df800SPratik Mohanty case QLA8044_RDMDIO:
3422804df800SPratik Mohanty rval = qla8044_minidump_process_rdmdio(vha, entry_hdr,
3423804df800SPratik Mohanty &data_ptr);
3424804df800SPratik Mohanty if (rval != QLA_SUCCESS)
3425804df800SPratik Mohanty qla8044_mark_entry_skipped(vha, entry_hdr, i);
3426804df800SPratik Mohanty break;
3427804df800SPratik Mohanty case QLA8044_POLLWR:
3428804df800SPratik Mohanty rval = qla8044_minidump_process_pollwr(vha, entry_hdr,
3429804df800SPratik Mohanty &data_ptr);
3430804df800SPratik Mohanty if (rval != QLA_SUCCESS)
3431804df800SPratik Mohanty qla8044_mark_entry_skipped(vha, entry_hdr, i);
3432804df800SPratik Mohanty break;
34337ec0effdSAtul Deshmukh case QLA82XX_RDNOP:
34347ec0effdSAtul Deshmukh default:
34357ec0effdSAtul Deshmukh qla8044_mark_entry_skipped(vha, entry_hdr, i);
34367ec0effdSAtul Deshmukh break;
34377ec0effdSAtul Deshmukh }
34387ec0effdSAtul Deshmukh
34397ec0effdSAtul Deshmukh data_collected = (uint8_t *)data_ptr -
34407ec0effdSAtul Deshmukh (uint8_t *)((uint8_t *)ha->md_dump);
34417ec0effdSAtul Deshmukh skip_nxt_entry:
34427ec0effdSAtul Deshmukh /*
34437ec0effdSAtul Deshmukh * next entry in the template
34447ec0effdSAtul Deshmukh */
34457ec0effdSAtul Deshmukh entry_hdr = (struct qla8044_minidump_entry_hdr *)
34467ec0effdSAtul Deshmukh (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
34477ec0effdSAtul Deshmukh }
34487ec0effdSAtul Deshmukh
34497ec0effdSAtul Deshmukh if (data_collected != ha->md_dump_size) {
34507ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb105,
34517ec0effdSAtul Deshmukh "Dump data mismatch: Data collected: "
34527ec0effdSAtul Deshmukh "[0x%x], total_data_size:[0x%x]\n",
34537ec0effdSAtul Deshmukh data_collected, ha->md_dump_size);
3454edaa5c74SSaurav Kashyap rval = QLA_FUNCTION_FAILED;
34557ec0effdSAtul Deshmukh goto md_failed;
34567ec0effdSAtul Deshmukh }
34577ec0effdSAtul Deshmukh
34587ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb110,
34597ec0effdSAtul Deshmukh "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
34607ec0effdSAtul Deshmukh vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
3461dbe6f492SJason Yan ha->fw_dumped = true;
34627ec0effdSAtul Deshmukh qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
34637ec0effdSAtul Deshmukh
34647ec0effdSAtul Deshmukh
34657ec0effdSAtul Deshmukh ql_log(ql_log_info, vha, 0xb106,
34667ec0effdSAtul Deshmukh "Leaving fn: %s Last entry: 0x%x\n",
34677ec0effdSAtul Deshmukh __func__, i);
34687ec0effdSAtul Deshmukh md_failed:
34697ec0effdSAtul Deshmukh return rval;
34707ec0effdSAtul Deshmukh }
34717ec0effdSAtul Deshmukh
34727ec0effdSAtul Deshmukh void
qla8044_get_minidump(struct scsi_qla_host * vha)34737ec0effdSAtul Deshmukh qla8044_get_minidump(struct scsi_qla_host *vha)
34747ec0effdSAtul Deshmukh {
34757ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
34767ec0effdSAtul Deshmukh
34777ec0effdSAtul Deshmukh if (!qla8044_collect_md_data(vha)) {
3478dbe6f492SJason Yan ha->fw_dumped = true;
3479edaa5c74SSaurav Kashyap ha->prev_minidump_failed = 0;
34807ec0effdSAtul Deshmukh } else {
34817ec0effdSAtul Deshmukh ql_log(ql_log_fatal, vha, 0xb0db,
34827ec0effdSAtul Deshmukh "%s: Unable to collect minidump\n",
34837ec0effdSAtul Deshmukh __func__);
3484edaa5c74SSaurav Kashyap ha->prev_minidump_failed = 1;
34857ec0effdSAtul Deshmukh }
34867ec0effdSAtul Deshmukh }
34877ec0effdSAtul Deshmukh
34887ec0effdSAtul Deshmukh static int
qla8044_poll_flash_status_reg(struct scsi_qla_host * vha)34897ec0effdSAtul Deshmukh qla8044_poll_flash_status_reg(struct scsi_qla_host *vha)
34907ec0effdSAtul Deshmukh {
34917ec0effdSAtul Deshmukh uint32_t flash_status;
34927ec0effdSAtul Deshmukh int retries = QLA8044_FLASH_READ_RETRY_COUNT;
34937ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
34947ec0effdSAtul Deshmukh
34957ec0effdSAtul Deshmukh while (retries--) {
34967ec0effdSAtul Deshmukh ret_val = qla8044_rd_reg_indirect(vha, QLA8044_FLASH_STATUS,
34977ec0effdSAtul Deshmukh &flash_status);
34987ec0effdSAtul Deshmukh if (ret_val) {
34996ddcfef7SSaurav Kashyap ql_log(ql_log_warn, vha, 0xb13c,
35007ec0effdSAtul Deshmukh "%s: Failed to read FLASH_STATUS reg.\n",
35017ec0effdSAtul Deshmukh __func__);
35027ec0effdSAtul Deshmukh break;
35037ec0effdSAtul Deshmukh }
35047ec0effdSAtul Deshmukh if ((flash_status & QLA8044_FLASH_STATUS_READY) ==
35057ec0effdSAtul Deshmukh QLA8044_FLASH_STATUS_READY)
35067ec0effdSAtul Deshmukh break;
35077ec0effdSAtul Deshmukh msleep(QLA8044_FLASH_STATUS_REG_POLL_DELAY);
35087ec0effdSAtul Deshmukh }
35097ec0effdSAtul Deshmukh
35107ec0effdSAtul Deshmukh if (!retries)
35117ec0effdSAtul Deshmukh ret_val = QLA_FUNCTION_FAILED;
35127ec0effdSAtul Deshmukh
35137ec0effdSAtul Deshmukh return ret_val;
35147ec0effdSAtul Deshmukh }
35157ec0effdSAtul Deshmukh
35167ec0effdSAtul Deshmukh static int
qla8044_write_flash_status_reg(struct scsi_qla_host * vha,uint32_t data)35177ec0effdSAtul Deshmukh qla8044_write_flash_status_reg(struct scsi_qla_host *vha,
35187ec0effdSAtul Deshmukh uint32_t data)
35197ec0effdSAtul Deshmukh {
35207ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
35217ec0effdSAtul Deshmukh uint32_t cmd;
35227ec0effdSAtul Deshmukh
35237ec0effdSAtul Deshmukh cmd = vha->hw->fdt_wrt_sts_reg_cmd;
35247ec0effdSAtul Deshmukh
35257ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
35267ec0effdSAtul Deshmukh QLA8044_FLASH_STATUS_WRITE_DEF_SIG | cmd);
35277ec0effdSAtul Deshmukh if (ret_val) {
35287ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb125,
35297ec0effdSAtul Deshmukh "%s: Failed to write to FLASH_ADDR.\n", __func__);
35307ec0effdSAtul Deshmukh goto exit_func;
35317ec0effdSAtul Deshmukh }
35327ec0effdSAtul Deshmukh
35337ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, data);
35347ec0effdSAtul Deshmukh if (ret_val) {
35357ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb126,
35367ec0effdSAtul Deshmukh "%s: Failed to write to FLASH_WRDATA.\n", __func__);
35377ec0effdSAtul Deshmukh goto exit_func;
35387ec0effdSAtul Deshmukh }
35397ec0effdSAtul Deshmukh
35407ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
35417ec0effdSAtul Deshmukh QLA8044_FLASH_SECOND_ERASE_MS_VAL);
35427ec0effdSAtul Deshmukh if (ret_val) {
35437ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb127,
35447ec0effdSAtul Deshmukh "%s: Failed to write to FLASH_CONTROL.\n", __func__);
35457ec0effdSAtul Deshmukh goto exit_func;
35467ec0effdSAtul Deshmukh }
35477ec0effdSAtul Deshmukh
35487ec0effdSAtul Deshmukh ret_val = qla8044_poll_flash_status_reg(vha);
35497ec0effdSAtul Deshmukh if (ret_val)
35507ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb128,
35517ec0effdSAtul Deshmukh "%s: Error polling flash status reg.\n", __func__);
35527ec0effdSAtul Deshmukh
35537ec0effdSAtul Deshmukh exit_func:
35547ec0effdSAtul Deshmukh return ret_val;
35557ec0effdSAtul Deshmukh }
35567ec0effdSAtul Deshmukh
35577ec0effdSAtul Deshmukh /*
35587ec0effdSAtul Deshmukh * This function assumes that the flash lock is held.
35597ec0effdSAtul Deshmukh */
35607ec0effdSAtul Deshmukh static int
qla8044_unprotect_flash(scsi_qla_host_t * vha)35617ec0effdSAtul Deshmukh qla8044_unprotect_flash(scsi_qla_host_t *vha)
35627ec0effdSAtul Deshmukh {
35637ec0effdSAtul Deshmukh int ret_val;
35647ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
35657ec0effdSAtul Deshmukh
35667ec0effdSAtul Deshmukh ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_enable);
35677ec0effdSAtul Deshmukh if (ret_val)
35687ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb139,
35697ec0effdSAtul Deshmukh "%s: Write flash status failed.\n", __func__);
35707ec0effdSAtul Deshmukh
35717ec0effdSAtul Deshmukh return ret_val;
35727ec0effdSAtul Deshmukh }
35737ec0effdSAtul Deshmukh
35747ec0effdSAtul Deshmukh /*
35757ec0effdSAtul Deshmukh * This function assumes that the flash lock is held.
35767ec0effdSAtul Deshmukh */
35777ec0effdSAtul Deshmukh static int
qla8044_protect_flash(scsi_qla_host_t * vha)35787ec0effdSAtul Deshmukh qla8044_protect_flash(scsi_qla_host_t *vha)
35797ec0effdSAtul Deshmukh {
35807ec0effdSAtul Deshmukh int ret_val;
35817ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
35827ec0effdSAtul Deshmukh
35837ec0effdSAtul Deshmukh ret_val = qla8044_write_flash_status_reg(vha, ha->fdt_wrt_disable);
35847ec0effdSAtul Deshmukh if (ret_val)
35857ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb13b,
35867ec0effdSAtul Deshmukh "%s: Write flash status failed.\n", __func__);
35877ec0effdSAtul Deshmukh
35887ec0effdSAtul Deshmukh return ret_val;
35897ec0effdSAtul Deshmukh }
35907ec0effdSAtul Deshmukh
35917ec0effdSAtul Deshmukh
35927ec0effdSAtul Deshmukh static int
qla8044_erase_flash_sector(struct scsi_qla_host * vha,uint32_t sector_start_addr)35937ec0effdSAtul Deshmukh qla8044_erase_flash_sector(struct scsi_qla_host *vha,
35947ec0effdSAtul Deshmukh uint32_t sector_start_addr)
35957ec0effdSAtul Deshmukh {
35967ec0effdSAtul Deshmukh uint32_t reversed_addr;
35977ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
35987ec0effdSAtul Deshmukh
35997ec0effdSAtul Deshmukh ret_val = qla8044_poll_flash_status_reg(vha);
36007ec0effdSAtul Deshmukh if (ret_val) {
36017ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb12e,
36027ec0effdSAtul Deshmukh "%s: Poll flash status after erase failed..\n", __func__);
36037ec0effdSAtul Deshmukh }
36047ec0effdSAtul Deshmukh
36057ec0effdSAtul Deshmukh reversed_addr = (((sector_start_addr & 0xFF) << 16) |
36067ec0effdSAtul Deshmukh (sector_start_addr & 0xFF00) |
36077ec0effdSAtul Deshmukh ((sector_start_addr & 0xFF0000) >> 16));
36087ec0effdSAtul Deshmukh
36097ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha,
36107ec0effdSAtul Deshmukh QLA8044_FLASH_WRDATA, reversed_addr);
36117ec0effdSAtul Deshmukh if (ret_val) {
36127ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb12f,
36137ec0effdSAtul Deshmukh "%s: Failed to write to FLASH_WRDATA.\n", __func__);
36147ec0effdSAtul Deshmukh }
36157ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
36167ec0effdSAtul Deshmukh QLA8044_FLASH_ERASE_SIG | vha->hw->fdt_erase_cmd);
36177ec0effdSAtul Deshmukh if (ret_val) {
36187ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb130,
36197ec0effdSAtul Deshmukh "%s: Failed to write to FLASH_ADDR.\n", __func__);
36207ec0effdSAtul Deshmukh }
36217ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
36227ec0effdSAtul Deshmukh QLA8044_FLASH_LAST_ERASE_MS_VAL);
36237ec0effdSAtul Deshmukh if (ret_val) {
36247ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb131,
36257ec0effdSAtul Deshmukh "%s: Failed write to FLASH_CONTROL.\n", __func__);
36267ec0effdSAtul Deshmukh }
36277ec0effdSAtul Deshmukh ret_val = qla8044_poll_flash_status_reg(vha);
36287ec0effdSAtul Deshmukh if (ret_val) {
36297ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb132,
36307ec0effdSAtul Deshmukh "%s: Poll flash status failed.\n", __func__);
36317ec0effdSAtul Deshmukh }
36327ec0effdSAtul Deshmukh
36337ec0effdSAtul Deshmukh
36347ec0effdSAtul Deshmukh return ret_val;
36357ec0effdSAtul Deshmukh }
36367ec0effdSAtul Deshmukh
36377ec0effdSAtul Deshmukh /*
36387ec0effdSAtul Deshmukh * qla8044_flash_write_u32 - Write data to flash
36397ec0effdSAtul Deshmukh *
36407ec0effdSAtul Deshmukh * @ha : Pointer to adapter structure
36417ec0effdSAtul Deshmukh * addr : Flash address to write to
36427ec0effdSAtul Deshmukh * p_data : Data to be written
36437ec0effdSAtul Deshmukh *
36447ec0effdSAtul Deshmukh * Return Value - QLA_SUCCESS/QLA_FUNCTION_FAILED
36457ec0effdSAtul Deshmukh *
36467ec0effdSAtul Deshmukh * NOTE: Lock should be held on entry
36477ec0effdSAtul Deshmukh */
36487ec0effdSAtul Deshmukh static int
qla8044_flash_write_u32(struct scsi_qla_host * vha,uint32_t addr,uint32_t * p_data)36497ec0effdSAtul Deshmukh qla8044_flash_write_u32(struct scsi_qla_host *vha, uint32_t addr,
36507ec0effdSAtul Deshmukh uint32_t *p_data)
36517ec0effdSAtul Deshmukh {
36527ec0effdSAtul Deshmukh int ret_val = QLA_SUCCESS;
36537ec0effdSAtul Deshmukh
36547ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
36557ec0effdSAtul Deshmukh 0x00800000 | (addr >> 2));
36567ec0effdSAtul Deshmukh if (ret_val) {
36577ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb134,
36587ec0effdSAtul Deshmukh "%s: Failed write to FLASH_ADDR.\n", __func__);
36597ec0effdSAtul Deshmukh goto exit_func;
36607ec0effdSAtul Deshmukh }
36617ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *p_data);
36627ec0effdSAtul Deshmukh if (ret_val) {
36637ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb135,
36647ec0effdSAtul Deshmukh "%s: Failed write to FLASH_WRDATA.\n", __func__);
36657ec0effdSAtul Deshmukh goto exit_func;
36667ec0effdSAtul Deshmukh }
36677ec0effdSAtul Deshmukh ret_val = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL, 0x3D);
36687ec0effdSAtul Deshmukh if (ret_val) {
36697ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb136,
36707ec0effdSAtul Deshmukh "%s: Failed write to FLASH_CONTROL.\n", __func__);
36717ec0effdSAtul Deshmukh goto exit_func;
36727ec0effdSAtul Deshmukh }
36737ec0effdSAtul Deshmukh ret_val = qla8044_poll_flash_status_reg(vha);
36747ec0effdSAtul Deshmukh if (ret_val) {
36757ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb137,
36767ec0effdSAtul Deshmukh "%s: Poll flash status failed.\n", __func__);
36777ec0effdSAtul Deshmukh }
36787ec0effdSAtul Deshmukh
36797ec0effdSAtul Deshmukh exit_func:
36807ec0effdSAtul Deshmukh return ret_val;
36817ec0effdSAtul Deshmukh }
36827ec0effdSAtul Deshmukh
36837ec0effdSAtul Deshmukh static int
qla8044_write_flash_buffer_mode(scsi_qla_host_t * vha,uint32_t * dwptr,uint32_t faddr,uint32_t dwords)36847ec0effdSAtul Deshmukh qla8044_write_flash_buffer_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
36857ec0effdSAtul Deshmukh uint32_t faddr, uint32_t dwords)
36867ec0effdSAtul Deshmukh {
36877ec0effdSAtul Deshmukh int ret = QLA_FUNCTION_FAILED;
36887ec0effdSAtul Deshmukh uint32_t spi_val;
36897ec0effdSAtul Deshmukh
36907ec0effdSAtul Deshmukh if (dwords < QLA8044_MIN_OPTROM_BURST_DWORDS ||
36917ec0effdSAtul Deshmukh dwords > QLA8044_MAX_OPTROM_BURST_DWORDS) {
36927ec0effdSAtul Deshmukh ql_dbg(ql_dbg_user, vha, 0xb123,
36937ec0effdSAtul Deshmukh "Got unsupported dwords = 0x%x.\n",
36947ec0effdSAtul Deshmukh dwords);
36957ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
36967ec0effdSAtul Deshmukh }
36977ec0effdSAtul Deshmukh
36987ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL, &spi_val);
36997ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
37007ec0effdSAtul Deshmukh spi_val | QLA8044_FLASH_SPI_CTL);
37017ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
37027ec0effdSAtul Deshmukh QLA8044_FLASH_FIRST_TEMP_VAL);
37037ec0effdSAtul Deshmukh
37047ec0effdSAtul Deshmukh /* First DWORD write to FLASH_WRDATA */
37057ec0effdSAtul Deshmukh ret = qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA,
37067ec0effdSAtul Deshmukh *dwptr++);
37077ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
37087ec0effdSAtul Deshmukh QLA8044_FLASH_FIRST_MS_PATTERN);
37097ec0effdSAtul Deshmukh
37107ec0effdSAtul Deshmukh ret = qla8044_poll_flash_status_reg(vha);
37117ec0effdSAtul Deshmukh if (ret) {
37127ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb124,
37137ec0effdSAtul Deshmukh "%s: Failed.\n", __func__);
37147ec0effdSAtul Deshmukh goto exit_func;
37157ec0effdSAtul Deshmukh }
37167ec0effdSAtul Deshmukh
37177ec0effdSAtul Deshmukh dwords--;
37187ec0effdSAtul Deshmukh
37197ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
37207ec0effdSAtul Deshmukh QLA8044_FLASH_SECOND_TEMP_VAL);
37217ec0effdSAtul Deshmukh
37227ec0effdSAtul Deshmukh
37237ec0effdSAtul Deshmukh /* Second to N-1 DWORDS writes */
37247ec0effdSAtul Deshmukh while (dwords != 1) {
37257ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
37267ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
37277ec0effdSAtul Deshmukh QLA8044_FLASH_SECOND_MS_PATTERN);
37287ec0effdSAtul Deshmukh ret = qla8044_poll_flash_status_reg(vha);
37297ec0effdSAtul Deshmukh if (ret) {
37307ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb129,
37317ec0effdSAtul Deshmukh "%s: Failed.\n", __func__);
37327ec0effdSAtul Deshmukh goto exit_func;
37337ec0effdSAtul Deshmukh }
37347ec0effdSAtul Deshmukh dwords--;
37357ec0effdSAtul Deshmukh }
37367ec0effdSAtul Deshmukh
37377ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_ADDR,
37387ec0effdSAtul Deshmukh QLA8044_FLASH_FIRST_TEMP_VAL | (faddr >> 2));
37397ec0effdSAtul Deshmukh
37407ec0effdSAtul Deshmukh /* Last DWORD write */
37417ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_WRDATA, *dwptr++);
37427ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_CONTROL,
37437ec0effdSAtul Deshmukh QLA8044_FLASH_LAST_MS_PATTERN);
37447ec0effdSAtul Deshmukh ret = qla8044_poll_flash_status_reg(vha);
37457ec0effdSAtul Deshmukh if (ret) {
37467ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb12a,
37477ec0effdSAtul Deshmukh "%s: Failed.\n", __func__);
37487ec0effdSAtul Deshmukh goto exit_func;
37497ec0effdSAtul Deshmukh }
37507ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_STATUS, &spi_val);
37517ec0effdSAtul Deshmukh
37527ec0effdSAtul Deshmukh if ((spi_val & QLA8044_FLASH_SPI_CTL) == QLA8044_FLASH_SPI_CTL) {
37537ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb12b,
37547ec0effdSAtul Deshmukh "%s: Failed.\n", __func__);
37557ec0effdSAtul Deshmukh spi_val = 0;
37567ec0effdSAtul Deshmukh /* Operation failed, clear error bit. */
37577ec0effdSAtul Deshmukh qla8044_rd_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
37587ec0effdSAtul Deshmukh &spi_val);
37597ec0effdSAtul Deshmukh qla8044_wr_reg_indirect(vha, QLA8044_FLASH_SPI_CONTROL,
37607ec0effdSAtul Deshmukh spi_val | QLA8044_FLASH_SPI_CTL);
37617ec0effdSAtul Deshmukh }
37627ec0effdSAtul Deshmukh exit_func:
37637ec0effdSAtul Deshmukh return ret;
37647ec0effdSAtul Deshmukh }
37657ec0effdSAtul Deshmukh
37667ec0effdSAtul Deshmukh static int
qla8044_write_flash_dword_mode(scsi_qla_host_t * vha,uint32_t * dwptr,uint32_t faddr,uint32_t dwords)37677ec0effdSAtul Deshmukh qla8044_write_flash_dword_mode(scsi_qla_host_t *vha, uint32_t *dwptr,
37687ec0effdSAtul Deshmukh uint32_t faddr, uint32_t dwords)
37697ec0effdSAtul Deshmukh {
37707ec0effdSAtul Deshmukh int ret = QLA_FUNCTION_FAILED;
37717ec0effdSAtul Deshmukh uint32_t liter;
37727ec0effdSAtul Deshmukh
37737ec0effdSAtul Deshmukh for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
37747ec0effdSAtul Deshmukh ret = qla8044_flash_write_u32(vha, faddr, dwptr);
37757ec0effdSAtul Deshmukh if (ret) {
37767ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb141,
37777ec0effdSAtul Deshmukh "%s: flash address=%x data=%x.\n", __func__,
37787ec0effdSAtul Deshmukh faddr, *dwptr);
37797ec0effdSAtul Deshmukh break;
37807ec0effdSAtul Deshmukh }
37817ec0effdSAtul Deshmukh }
37827ec0effdSAtul Deshmukh
37837ec0effdSAtul Deshmukh return ret;
37847ec0effdSAtul Deshmukh }
37857ec0effdSAtul Deshmukh
37867ec0effdSAtul Deshmukh int
qla8044_write_optrom_data(struct scsi_qla_host * vha,void * buf,uint32_t offset,uint32_t length)37873695310eSJoe Carnuccio qla8044_write_optrom_data(struct scsi_qla_host *vha, void *buf,
37887ec0effdSAtul Deshmukh uint32_t offset, uint32_t length)
37897ec0effdSAtul Deshmukh {
37907ec0effdSAtul Deshmukh int rval = QLA_FUNCTION_FAILED, i, burst_iter_count;
37917ec0effdSAtul Deshmukh int dword_count, erase_sec_count;
37927ec0effdSAtul Deshmukh uint32_t erase_offset;
37937ec0effdSAtul Deshmukh uint8_t *p_cache, *p_src;
37947ec0effdSAtul Deshmukh
37957ec0effdSAtul Deshmukh erase_offset = offset;
37967ec0effdSAtul Deshmukh
37977ec0effdSAtul Deshmukh p_cache = kcalloc(length, sizeof(uint8_t), GFP_KERNEL);
37987ec0effdSAtul Deshmukh if (!p_cache)
37997ec0effdSAtul Deshmukh return QLA_FUNCTION_FAILED;
38007ec0effdSAtul Deshmukh
38017ec0effdSAtul Deshmukh memcpy(p_cache, buf, length);
38027ec0effdSAtul Deshmukh p_src = p_cache;
38037ec0effdSAtul Deshmukh dword_count = length / sizeof(uint32_t);
38047ec0effdSAtul Deshmukh /* Since the offset and legth are sector aligned, it will be always
38057ec0effdSAtul Deshmukh * multiple of burst_iter_count (64)
38067ec0effdSAtul Deshmukh */
38077ec0effdSAtul Deshmukh burst_iter_count = dword_count / QLA8044_MAX_OPTROM_BURST_DWORDS;
38087ec0effdSAtul Deshmukh erase_sec_count = length / QLA8044_SECTOR_SIZE;
38097ec0effdSAtul Deshmukh
38107ec0effdSAtul Deshmukh /* Suspend HBA. */
38117ec0effdSAtul Deshmukh scsi_block_requests(vha->host);
38127ec0effdSAtul Deshmukh /* Lock and enable write for whole operation. */
38137ec0effdSAtul Deshmukh qla8044_flash_lock(vha);
38147ec0effdSAtul Deshmukh qla8044_unprotect_flash(vha);
38157ec0effdSAtul Deshmukh
38167ec0effdSAtul Deshmukh /* Erasing the sectors */
38177ec0effdSAtul Deshmukh for (i = 0; i < erase_sec_count; i++) {
38187ec0effdSAtul Deshmukh rval = qla8044_erase_flash_sector(vha, erase_offset);
38197ec0effdSAtul Deshmukh ql_dbg(ql_dbg_user, vha, 0xb138,
38207ec0effdSAtul Deshmukh "Done erase of sector=0x%x.\n",
38217ec0effdSAtul Deshmukh erase_offset);
38227ec0effdSAtul Deshmukh if (rval) {
38237ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb121,
38247ec0effdSAtul Deshmukh "Failed to erase the sector having address: "
38257ec0effdSAtul Deshmukh "0x%x.\n", erase_offset);
38267ec0effdSAtul Deshmukh goto out;
38277ec0effdSAtul Deshmukh }
38287ec0effdSAtul Deshmukh erase_offset += QLA8044_SECTOR_SIZE;
38297ec0effdSAtul Deshmukh }
38306ddcfef7SSaurav Kashyap ql_dbg(ql_dbg_user, vha, 0xb13f,
38317ec0effdSAtul Deshmukh "Got write for addr = 0x%x length=0x%x.\n",
38327ec0effdSAtul Deshmukh offset, length);
38337ec0effdSAtul Deshmukh
38347ec0effdSAtul Deshmukh for (i = 0; i < burst_iter_count; i++) {
38357ec0effdSAtul Deshmukh
38367ec0effdSAtul Deshmukh /* Go with write. */
38377ec0effdSAtul Deshmukh rval = qla8044_write_flash_buffer_mode(vha, (uint32_t *)p_src,
38387ec0effdSAtul Deshmukh offset, QLA8044_MAX_OPTROM_BURST_DWORDS);
38397ec0effdSAtul Deshmukh if (rval) {
38407ec0effdSAtul Deshmukh /* Buffer Mode failed skip to dword mode */
38417ec0effdSAtul Deshmukh ql_log(ql_log_warn, vha, 0xb122,
38427ec0effdSAtul Deshmukh "Failed to write flash in buffer mode, "
38437ec0effdSAtul Deshmukh "Reverting to slow-write.\n");
38447ec0effdSAtul Deshmukh rval = qla8044_write_flash_dword_mode(vha,
38457ec0effdSAtul Deshmukh (uint32_t *)p_src, offset,
38467ec0effdSAtul Deshmukh QLA8044_MAX_OPTROM_BURST_DWORDS);
38477ec0effdSAtul Deshmukh }
38487ec0effdSAtul Deshmukh p_src += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
38497ec0effdSAtul Deshmukh offset += sizeof(uint32_t) * QLA8044_MAX_OPTROM_BURST_DWORDS;
38507ec0effdSAtul Deshmukh }
38517ec0effdSAtul Deshmukh ql_dbg(ql_dbg_user, vha, 0xb133,
38527ec0effdSAtul Deshmukh "Done writing.\n");
38537ec0effdSAtul Deshmukh
38547ec0effdSAtul Deshmukh out:
38557ec0effdSAtul Deshmukh qla8044_protect_flash(vha);
38567ec0effdSAtul Deshmukh qla8044_flash_unlock(vha);
38577ec0effdSAtul Deshmukh scsi_unblock_requests(vha->host);
38587ec0effdSAtul Deshmukh kfree(p_cache);
38597ec0effdSAtul Deshmukh
38607ec0effdSAtul Deshmukh return rval;
38617ec0effdSAtul Deshmukh }
38627ec0effdSAtul Deshmukh
38637ec0effdSAtul Deshmukh #define LEG_INT_PTR_B31 (1 << 31)
38647ec0effdSAtul Deshmukh #define LEG_INT_PTR_B30 (1 << 30)
38657ec0effdSAtul Deshmukh #define PF_BITS_MASK (0xF << 16)
38667ec0effdSAtul Deshmukh /**
38677ec0effdSAtul Deshmukh * qla8044_intr_handler() - Process interrupts for the ISP8044
3868807eb907SBart Van Assche * @irq: interrupt number
38697ec0effdSAtul Deshmukh * @dev_id: SCSI driver HA context
38707ec0effdSAtul Deshmukh *
38717ec0effdSAtul Deshmukh * Called by system whenever the host adapter generates an interrupt.
38727ec0effdSAtul Deshmukh *
38737ec0effdSAtul Deshmukh * Returns handled flag.
38747ec0effdSAtul Deshmukh */
38757ec0effdSAtul Deshmukh irqreturn_t
qla8044_intr_handler(int irq,void * dev_id)38767ec0effdSAtul Deshmukh qla8044_intr_handler(int irq, void *dev_id)
38777ec0effdSAtul Deshmukh {
38787ec0effdSAtul Deshmukh scsi_qla_host_t *vha;
38797ec0effdSAtul Deshmukh struct qla_hw_data *ha;
38807ec0effdSAtul Deshmukh struct rsp_que *rsp;
38817ec0effdSAtul Deshmukh struct device_reg_82xx __iomem *reg;
38827ec0effdSAtul Deshmukh int status = 0;
38837ec0effdSAtul Deshmukh unsigned long flags;
38847ec0effdSAtul Deshmukh unsigned long iter;
38857ec0effdSAtul Deshmukh uint32_t stat;
38860a59cea4SBart Van Assche uint16_t mb[8];
38877ec0effdSAtul Deshmukh uint32_t leg_int_ptr = 0, pf_bit;
38887ec0effdSAtul Deshmukh
38897ec0effdSAtul Deshmukh rsp = (struct rsp_que *) dev_id;
38907ec0effdSAtul Deshmukh if (!rsp) {
38917ec0effdSAtul Deshmukh ql_log(ql_log_info, NULL, 0xb143,
38927ec0effdSAtul Deshmukh "%s(): NULL response queue pointer\n", __func__);
38937ec0effdSAtul Deshmukh return IRQ_NONE;
38947ec0effdSAtul Deshmukh }
38957ec0effdSAtul Deshmukh ha = rsp->hw;
38967ec0effdSAtul Deshmukh vha = pci_get_drvdata(ha->pdev);
38977ec0effdSAtul Deshmukh
38987ec0effdSAtul Deshmukh if (unlikely(pci_channel_offline(ha->pdev)))
38997ec0effdSAtul Deshmukh return IRQ_HANDLED;
39007ec0effdSAtul Deshmukh
39017ec0effdSAtul Deshmukh leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
39027ec0effdSAtul Deshmukh
39037ec0effdSAtul Deshmukh /* Legacy interrupt is valid if bit31 of leg_int_ptr is set */
39047ec0effdSAtul Deshmukh if (!(leg_int_ptr & (LEG_INT_PTR_B31))) {
39057ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb144,
39067ec0effdSAtul Deshmukh "%s: Legacy Interrupt Bit 31 not set, "
39077ec0effdSAtul Deshmukh "spurious interrupt!\n", __func__);
39087ec0effdSAtul Deshmukh return IRQ_NONE;
39097ec0effdSAtul Deshmukh }
39107ec0effdSAtul Deshmukh
39117ec0effdSAtul Deshmukh pf_bit = ha->portnum << 16;
39127ec0effdSAtul Deshmukh /* Validate the PCIE function ID set in leg_int_ptr bits [19..16] */
39137ec0effdSAtul Deshmukh if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit) {
39147ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb145,
39157ec0effdSAtul Deshmukh "%s: Incorrect function ID 0x%x in "
39167ec0effdSAtul Deshmukh "legacy interrupt register, "
39177ec0effdSAtul Deshmukh "ha->pf_bit = 0x%x\n", __func__,
39187ec0effdSAtul Deshmukh (leg_int_ptr & (PF_BITS_MASK)), pf_bit);
39197ec0effdSAtul Deshmukh return IRQ_NONE;
39207ec0effdSAtul Deshmukh }
39217ec0effdSAtul Deshmukh
39227ec0effdSAtul Deshmukh /* To de-assert legacy interrupt, write 0 to Legacy Interrupt Trigger
39237ec0effdSAtul Deshmukh * Control register and poll till Legacy Interrupt Pointer register
39247ec0effdSAtul Deshmukh * bit32 is 0.
39257ec0effdSAtul Deshmukh */
39267ec0effdSAtul Deshmukh qla8044_wr_reg(ha, LEG_INTR_TRIG_OFFSET, 0);
39277ec0effdSAtul Deshmukh do {
39287ec0effdSAtul Deshmukh leg_int_ptr = qla8044_rd_reg(ha, LEG_INTR_PTR_OFFSET);
39297ec0effdSAtul Deshmukh if ((leg_int_ptr & (PF_BITS_MASK)) != pf_bit)
39307ec0effdSAtul Deshmukh break;
39317ec0effdSAtul Deshmukh } while (leg_int_ptr & (LEG_INT_PTR_B30));
39327ec0effdSAtul Deshmukh
39337ec0effdSAtul Deshmukh reg = &ha->iobase->isp82;
39347ec0effdSAtul Deshmukh spin_lock_irqsave(&ha->hardware_lock, flags);
39357ec0effdSAtul Deshmukh for (iter = 1; iter--; ) {
39367ec0effdSAtul Deshmukh
393704474d3aSBart Van Assche if (rd_reg_dword(®->host_int)) {
393804474d3aSBart Van Assche stat = rd_reg_dword(®->host_status);
39397ec0effdSAtul Deshmukh if ((stat & HSRX_RISC_INT) == 0)
39407ec0effdSAtul Deshmukh break;
39417ec0effdSAtul Deshmukh
39427ec0effdSAtul Deshmukh switch (stat & 0xff) {
39437ec0effdSAtul Deshmukh case 0x1:
39447ec0effdSAtul Deshmukh case 0x2:
39457ec0effdSAtul Deshmukh case 0x10:
39467ec0effdSAtul Deshmukh case 0x11:
39477ec0effdSAtul Deshmukh qla82xx_mbx_completion(vha, MSW(stat));
39487ec0effdSAtul Deshmukh status |= MBX_INTERRUPT;
39497ec0effdSAtul Deshmukh break;
39507ec0effdSAtul Deshmukh case 0x12:
39517ec0effdSAtul Deshmukh mb[0] = MSW(stat);
395204474d3aSBart Van Assche mb[1] = rd_reg_word(®->mailbox_out[1]);
395304474d3aSBart Van Assche mb[2] = rd_reg_word(®->mailbox_out[2]);
395404474d3aSBart Van Assche mb[3] = rd_reg_word(®->mailbox_out[3]);
39557ec0effdSAtul Deshmukh qla2x00_async_event(vha, rsp, mb);
39567ec0effdSAtul Deshmukh break;
39577ec0effdSAtul Deshmukh case 0x13:
39587ec0effdSAtul Deshmukh qla24xx_process_response_queue(vha, rsp);
39597ec0effdSAtul Deshmukh break;
39607ec0effdSAtul Deshmukh default:
39617ec0effdSAtul Deshmukh ql_dbg(ql_dbg_p3p, vha, 0xb146,
39627ec0effdSAtul Deshmukh "Unrecognized interrupt type "
39637ec0effdSAtul Deshmukh "(%d).\n", stat & 0xff);
39647ec0effdSAtul Deshmukh break;
39657ec0effdSAtul Deshmukh }
39667ec0effdSAtul Deshmukh }
396704474d3aSBart Van Assche wrt_reg_dword(®->host_int, 0);
39687ec0effdSAtul Deshmukh }
39697ec0effdSAtul Deshmukh
39707ec0effdSAtul Deshmukh qla2x00_handle_mbx_completion(ha, status);
39717ec0effdSAtul Deshmukh spin_unlock_irqrestore(&ha->hardware_lock, flags);
39727ec0effdSAtul Deshmukh
39737ec0effdSAtul Deshmukh return IRQ_HANDLED;
39747ec0effdSAtul Deshmukh }
39757ec0effdSAtul Deshmukh
39767ec0effdSAtul Deshmukh static int
qla8044_idc_dontreset(struct qla_hw_data * ha)39777ec0effdSAtul Deshmukh qla8044_idc_dontreset(struct qla_hw_data *ha)
39787ec0effdSAtul Deshmukh {
39797ec0effdSAtul Deshmukh uint32_t idc_ctrl;
39807ec0effdSAtul Deshmukh
39817ec0effdSAtul Deshmukh idc_ctrl = qla8044_rd_reg(ha, QLA8044_IDC_DRV_CTRL);
39827ec0effdSAtul Deshmukh return idc_ctrl & DONTRESET_BIT0;
39837ec0effdSAtul Deshmukh }
39847ec0effdSAtul Deshmukh
39857ec0effdSAtul Deshmukh static void
qla8044_clear_rst_ready(scsi_qla_host_t * vha)39867ec0effdSAtul Deshmukh qla8044_clear_rst_ready(scsi_qla_host_t *vha)
39877ec0effdSAtul Deshmukh {
39887ec0effdSAtul Deshmukh uint32_t drv_state;
39897ec0effdSAtul Deshmukh
39907ec0effdSAtul Deshmukh drv_state = qla8044_rd_direct(vha, QLA8044_CRB_DRV_STATE_INDEX);
39917ec0effdSAtul Deshmukh
39927ec0effdSAtul Deshmukh /*
39937ec0effdSAtul Deshmukh * For ISP8044, drv_active register has 1 bit per function,
39947ec0effdSAtul Deshmukh * shift 1 by func_num to set a bit for the function.
39957ec0effdSAtul Deshmukh * For ISP82xx, drv_active has 4 bits per function
39967ec0effdSAtul Deshmukh */
39977ec0effdSAtul Deshmukh drv_state &= ~(1 << vha->hw->portnum);
39987ec0effdSAtul Deshmukh
39996ddcfef7SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb13d,
40007ec0effdSAtul Deshmukh "drv_state: 0x%08x\n", drv_state);
40017ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DRV_STATE_INDEX, drv_state);
40027ec0effdSAtul Deshmukh }
40037ec0effdSAtul Deshmukh
40047ec0effdSAtul Deshmukh int
qla8044_abort_isp(scsi_qla_host_t * vha)40057ec0effdSAtul Deshmukh qla8044_abort_isp(scsi_qla_host_t *vha)
40067ec0effdSAtul Deshmukh {
40077ec0effdSAtul Deshmukh int rval;
40087ec0effdSAtul Deshmukh uint32_t dev_state;
40097ec0effdSAtul Deshmukh struct qla_hw_data *ha = vha->hw;
40107ec0effdSAtul Deshmukh
40117ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
40127ec0effdSAtul Deshmukh dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
40137ec0effdSAtul Deshmukh
40147ec0effdSAtul Deshmukh if (ql2xdontresethba)
40157ec0effdSAtul Deshmukh qla8044_set_idc_dontreset(vha);
40167ec0effdSAtul Deshmukh
40177ec0effdSAtul Deshmukh /* If device_state is NEED_RESET, go ahead with
40187ec0effdSAtul Deshmukh * Reset,irrespective of ql2xdontresethba. This is to allow a
40197ec0effdSAtul Deshmukh * non-reset-owner to force a reset. Non-reset-owner sets
40207ec0effdSAtul Deshmukh * the IDC_CTRL BIT0 to prevent Reset-owner from doing a Reset
40217ec0effdSAtul Deshmukh * and then forces a Reset by setting device_state to
40227ec0effdSAtul Deshmukh * NEED_RESET. */
40237ec0effdSAtul Deshmukh if (dev_state == QLA8XXX_DEV_READY) {
40247ec0effdSAtul Deshmukh /* If IDC_CTRL DONTRESETHBA_BIT0 is set don't do reset
40257ec0effdSAtul Deshmukh * recovery */
40267ec0effdSAtul Deshmukh if (qla8044_idc_dontreset(ha) == DONTRESET_BIT0) {
40276ddcfef7SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb13e,
40287ec0effdSAtul Deshmukh "Reset recovery disabled\n");
40297ec0effdSAtul Deshmukh rval = QLA_FUNCTION_FAILED;
40307ec0effdSAtul Deshmukh goto exit_isp_reset;
40317ec0effdSAtul Deshmukh }
40327ec0effdSAtul Deshmukh
40336ddcfef7SSaurav Kashyap ql_dbg(ql_dbg_p3p, vha, 0xb140,
40347ec0effdSAtul Deshmukh "HW State: NEED RESET\n");
40357ec0effdSAtul Deshmukh qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
40367ec0effdSAtul Deshmukh QLA8XXX_DEV_NEED_RESET);
40377ec0effdSAtul Deshmukh }
40387ec0effdSAtul Deshmukh
40397ec0effdSAtul Deshmukh /* For ISP8044, Reset owner is NIC, iSCSI or FCOE based on priority
40407ec0effdSAtul Deshmukh * and which drivers are present. Unlike ISP82XX, the function setting
40417ec0effdSAtul Deshmukh * NEED_RESET, may not be the Reset owner. */
40427ec0effdSAtul Deshmukh qla83xx_reset_ownership(vha);
40437ec0effdSAtul Deshmukh
40447ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
40457ec0effdSAtul Deshmukh rval = qla8044_device_state_handler(vha);
40467ec0effdSAtul Deshmukh qla8044_idc_lock(ha);
40477ec0effdSAtul Deshmukh qla8044_clear_rst_ready(vha);
40487ec0effdSAtul Deshmukh
40497ec0effdSAtul Deshmukh exit_isp_reset:
40507ec0effdSAtul Deshmukh qla8044_idc_unlock(ha);
40517ec0effdSAtul Deshmukh if (rval == QLA_SUCCESS) {
40527ec0effdSAtul Deshmukh ha->flags.isp82xx_fw_hung = 0;
40537ec0effdSAtul Deshmukh ha->flags.nic_core_reset_hdlr_active = 0;
40547ec0effdSAtul Deshmukh rval = qla82xx_restart_isp(vha);
40557ec0effdSAtul Deshmukh }
40567ec0effdSAtul Deshmukh
40577ec0effdSAtul Deshmukh return rval;
40587ec0effdSAtul Deshmukh }
40597ec0effdSAtul Deshmukh
4060a1b23c5aSChad Dupuis void
qla8044_fw_dump(scsi_qla_host_t * vha)40618ae17876SBart Van Assche qla8044_fw_dump(scsi_qla_host_t *vha)
4062a1b23c5aSChad Dupuis {
4063a1b23c5aSChad Dupuis struct qla_hw_data *ha = vha->hw;
4064a1b23c5aSChad Dupuis
4065a1b23c5aSChad Dupuis if (!ha->allow_cna_fw_dump)
4066a1b23c5aSChad Dupuis return;
4067a1b23c5aSChad Dupuis
4068a1b23c5aSChad Dupuis scsi_block_requests(vha->host);
4069a1b23c5aSChad Dupuis ha->flags.isp82xx_no_md_cap = 1;
4070a1b23c5aSChad Dupuis qla8044_idc_lock(ha);
4071a1b23c5aSChad Dupuis qla82xx_set_reset_owner(vha);
4072a1b23c5aSChad Dupuis qla8044_idc_unlock(ha);
4073a1b23c5aSChad Dupuis qla2x00_wait_for_chip_reset(vha);
4074a1b23c5aSChad Dupuis scsi_unblock_requests(vha->host);
4075a1b23c5aSChad Dupuis }
4076