1 /* 2 * PWM driver for Rockchip SoCs 3 * 4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 5 * Copyright (C) 2014 ROCKCHIP, Inc. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/platform_device.h> 18 #include <linux/pwm.h> 19 #include <linux/time.h> 20 21 #define PWM_CTRL_TIMER_EN (1 << 0) 22 #define PWM_CTRL_OUTPUT_EN (1 << 3) 23 24 #define PWM_ENABLE (1 << 0) 25 #define PWM_CONTINUOUS (1 << 1) 26 #define PWM_DUTY_POSITIVE (1 << 3) 27 #define PWM_DUTY_NEGATIVE (0 << 3) 28 #define PWM_INACTIVE_NEGATIVE (0 << 4) 29 #define PWM_INACTIVE_POSITIVE (1 << 4) 30 #define PWM_OUTPUT_LEFT (0 << 5) 31 #define PWM_LP_DISABLE (0 << 8) 32 33 struct rockchip_pwm_chip { 34 struct pwm_chip chip; 35 struct clk *clk; 36 const struct rockchip_pwm_data *data; 37 void __iomem *base; 38 }; 39 40 struct rockchip_pwm_regs { 41 unsigned long duty; 42 unsigned long period; 43 unsigned long cntr; 44 unsigned long ctrl; 45 }; 46 47 struct rockchip_pwm_data { 48 struct rockchip_pwm_regs regs; 49 unsigned int prescaler; 50 bool supports_polarity; 51 const struct pwm_ops *ops; 52 53 void (*set_enable)(struct pwm_chip *chip, 54 struct pwm_device *pwm, bool enable, 55 enum pwm_polarity polarity); 56 void (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm, 57 struct pwm_state *state); 58 }; 59 60 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) 61 { 62 return container_of(c, struct rockchip_pwm_chip, chip); 63 } 64 65 static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip, 66 struct pwm_device *pwm, bool enable, 67 enum pwm_polarity polarity) 68 { 69 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 70 u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; 71 u32 val; 72 73 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 74 75 if (enable) 76 val |= enable_conf; 77 else 78 val &= ~enable_conf; 79 80 writel_relaxed(val, pc->base + pc->data->regs.ctrl); 81 } 82 83 static void rockchip_pwm_get_state_v1(struct pwm_chip *chip, 84 struct pwm_device *pwm, 85 struct pwm_state *state) 86 { 87 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 88 u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; 89 u32 val; 90 91 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 92 if ((val & enable_conf) == enable_conf) 93 state->enabled = true; 94 } 95 96 static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, 97 struct pwm_device *pwm, bool enable, 98 enum pwm_polarity polarity) 99 { 100 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 101 u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 102 PWM_CONTINUOUS; 103 u32 val; 104 105 if (polarity == PWM_POLARITY_INVERSED) 106 enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE; 107 else 108 enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE; 109 110 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 111 112 if (enable) 113 val |= enable_conf; 114 else 115 val &= ~enable_conf; 116 117 writel_relaxed(val, pc->base + pc->data->regs.ctrl); 118 } 119 120 static void rockchip_pwm_get_state_v2(struct pwm_chip *chip, 121 struct pwm_device *pwm, 122 struct pwm_state *state) 123 { 124 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 125 u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 126 PWM_CONTINUOUS; 127 u32 val; 128 129 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 130 if ((val & enable_conf) != enable_conf) 131 return; 132 133 state->enabled = true; 134 135 if (!(val & PWM_DUTY_POSITIVE)) 136 state->polarity = PWM_POLARITY_INVERSED; 137 } 138 139 static void rockchip_pwm_get_state(struct pwm_chip *chip, 140 struct pwm_device *pwm, 141 struct pwm_state *state) 142 { 143 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 144 unsigned long clk_rate; 145 u64 tmp; 146 int ret; 147 148 ret = clk_enable(pc->clk); 149 if (ret) 150 return; 151 152 clk_rate = clk_get_rate(pc->clk); 153 154 tmp = readl_relaxed(pc->base + pc->data->regs.period); 155 tmp *= pc->data->prescaler * NSEC_PER_SEC; 156 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 157 158 tmp = readl_relaxed(pc->base + pc->data->regs.duty); 159 tmp *= pc->data->prescaler * NSEC_PER_SEC; 160 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 161 162 pc->data->get_state(chip, pwm, state); 163 164 clk_disable(pc->clk); 165 } 166 167 static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 168 int duty_ns, int period_ns) 169 { 170 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 171 unsigned long period, duty; 172 u64 clk_rate, div; 173 174 clk_rate = clk_get_rate(pc->clk); 175 176 /* 177 * Since period and duty cycle registers have a width of 32 178 * bits, every possible input period can be obtained using the 179 * default prescaler value for all practical clock rate values. 180 */ 181 div = clk_rate * period_ns; 182 period = DIV_ROUND_CLOSEST_ULL(div, 183 pc->data->prescaler * NSEC_PER_SEC); 184 185 div = clk_rate * duty_ns; 186 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); 187 188 writel(period, pc->base + pc->data->regs.period); 189 writel(duty, pc->base + pc->data->regs.duty); 190 191 return 0; 192 } 193 194 static int rockchip_pwm_enable(struct pwm_chip *chip, 195 struct pwm_device *pwm, 196 bool enable, 197 enum pwm_polarity polarity) 198 { 199 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 200 int ret; 201 202 if (enable) { 203 ret = clk_enable(pc->clk); 204 if (ret) 205 return ret; 206 } 207 208 pc->data->set_enable(chip, pwm, enable, polarity); 209 210 if (!enable) 211 clk_disable(pc->clk); 212 213 return 0; 214 } 215 216 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 217 struct pwm_state *state) 218 { 219 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 220 struct pwm_state curstate; 221 bool enabled; 222 int ret; 223 224 pwm_get_state(pwm, &curstate); 225 enabled = curstate.enabled; 226 227 ret = clk_enable(pc->clk); 228 if (ret) 229 return ret; 230 231 if (state->polarity != curstate.polarity && enabled) { 232 ret = rockchip_pwm_enable(chip, pwm, false, state->polarity); 233 if (ret) 234 goto out; 235 enabled = false; 236 } 237 238 ret = rockchip_pwm_config(chip, pwm, state->duty_cycle, state->period); 239 if (ret) { 240 if (enabled != curstate.enabled) 241 rockchip_pwm_enable(chip, pwm, !enabled, 242 state->polarity); 243 goto out; 244 } 245 246 if (state->enabled != enabled) { 247 ret = rockchip_pwm_enable(chip, pwm, state->enabled, 248 state->polarity); 249 if (ret) 250 goto out; 251 } 252 253 /* 254 * Update the state with the real hardware, which can differ a bit 255 * because of period/duty_cycle approximation. 256 */ 257 rockchip_pwm_get_state(chip, pwm, state); 258 259 out: 260 clk_disable(pc->clk); 261 262 return ret; 263 } 264 265 static const struct pwm_ops rockchip_pwm_ops_v1 = { 266 .get_state = rockchip_pwm_get_state, 267 .apply = rockchip_pwm_apply, 268 .owner = THIS_MODULE, 269 }; 270 271 static const struct pwm_ops rockchip_pwm_ops_v2 = { 272 .get_state = rockchip_pwm_get_state, 273 .apply = rockchip_pwm_apply, 274 .owner = THIS_MODULE, 275 }; 276 277 static const struct rockchip_pwm_data pwm_data_v1 = { 278 .regs = { 279 .duty = 0x04, 280 .period = 0x08, 281 .cntr = 0x00, 282 .ctrl = 0x0c, 283 }, 284 .prescaler = 2, 285 .ops = &rockchip_pwm_ops_v1, 286 .set_enable = rockchip_pwm_set_enable_v1, 287 .get_state = rockchip_pwm_get_state_v1, 288 }; 289 290 static const struct rockchip_pwm_data pwm_data_v2 = { 291 .regs = { 292 .duty = 0x08, 293 .period = 0x04, 294 .cntr = 0x00, 295 .ctrl = 0x0c, 296 }, 297 .prescaler = 1, 298 .supports_polarity = true, 299 .ops = &rockchip_pwm_ops_v2, 300 .set_enable = rockchip_pwm_set_enable_v2, 301 .get_state = rockchip_pwm_get_state_v2, 302 }; 303 304 static const struct rockchip_pwm_data pwm_data_vop = { 305 .regs = { 306 .duty = 0x08, 307 .period = 0x04, 308 .cntr = 0x0c, 309 .ctrl = 0x00, 310 }, 311 .prescaler = 1, 312 .supports_polarity = true, 313 .ops = &rockchip_pwm_ops_v2, 314 .set_enable = rockchip_pwm_set_enable_v2, 315 .get_state = rockchip_pwm_get_state_v2, 316 }; 317 318 static const struct of_device_id rockchip_pwm_dt_ids[] = { 319 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1}, 320 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2}, 321 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop}, 322 { /* sentinel */ } 323 }; 324 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); 325 326 static int rockchip_pwm_probe(struct platform_device *pdev) 327 { 328 const struct of_device_id *id; 329 struct rockchip_pwm_chip *pc; 330 struct resource *r; 331 int ret; 332 333 id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev); 334 if (!id) 335 return -EINVAL; 336 337 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 338 if (!pc) 339 return -ENOMEM; 340 341 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 342 pc->base = devm_ioremap_resource(&pdev->dev, r); 343 if (IS_ERR(pc->base)) 344 return PTR_ERR(pc->base); 345 346 pc->clk = devm_clk_get(&pdev->dev, NULL); 347 if (IS_ERR(pc->clk)) 348 return PTR_ERR(pc->clk); 349 350 ret = clk_prepare_enable(pc->clk); 351 if (ret) 352 return ret; 353 354 platform_set_drvdata(pdev, pc); 355 356 pc->data = id->data; 357 pc->chip.dev = &pdev->dev; 358 pc->chip.ops = pc->data->ops; 359 pc->chip.base = -1; 360 pc->chip.npwm = 1; 361 362 if (pc->data->supports_polarity) { 363 pc->chip.of_xlate = of_pwm_xlate_with_flags; 364 pc->chip.of_pwm_n_cells = 3; 365 } 366 367 ret = pwmchip_add(&pc->chip); 368 if (ret < 0) { 369 clk_unprepare(pc->clk); 370 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 371 } 372 373 /* Keep the PWM clk enabled if the PWM appears to be up and running. */ 374 if (!pwm_is_enabled(pc->chip.pwms)) 375 clk_disable(pc->clk); 376 377 return ret; 378 } 379 380 static int rockchip_pwm_remove(struct platform_device *pdev) 381 { 382 struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev); 383 384 /* 385 * Disable the PWM clk before unpreparing it if the PWM device is still 386 * running. This should only happen when the last PWM user left it 387 * enabled, or when nobody requested a PWM that was previously enabled 388 * by the bootloader. 389 * 390 * FIXME: Maybe the core should disable all PWM devices in 391 * pwmchip_remove(). In this case we'd only have to call 392 * clk_unprepare() after pwmchip_remove(). 393 * 394 */ 395 if (pwm_is_enabled(pc->chip.pwms)) 396 clk_disable(pc->clk); 397 398 clk_unprepare(pc->clk); 399 400 return pwmchip_remove(&pc->chip); 401 } 402 403 static struct platform_driver rockchip_pwm_driver = { 404 .driver = { 405 .name = "rockchip-pwm", 406 .of_match_table = rockchip_pwm_dt_ids, 407 }, 408 .probe = rockchip_pwm_probe, 409 .remove = rockchip_pwm_remove, 410 }; 411 module_platform_driver(rockchip_pwm_driver); 412 413 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); 414 MODULE_DESCRIPTION("Rockchip SoC PWM driver"); 415 MODULE_LICENSE("GPL v2"); 416