1 /* 2 * PWM driver for Rockchip SoCs 3 * 4 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 5 * Copyright (C) 2014 ROCKCHIP, Inc. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_device.h> 17 #include <linux/platform_device.h> 18 #include <linux/pwm.h> 19 #include <linux/time.h> 20 21 #define PWM_CTRL_TIMER_EN (1 << 0) 22 #define PWM_CTRL_OUTPUT_EN (1 << 3) 23 24 #define PWM_ENABLE (1 << 0) 25 #define PWM_CONTINUOUS (1 << 1) 26 #define PWM_DUTY_POSITIVE (1 << 3) 27 #define PWM_DUTY_NEGATIVE (0 << 3) 28 #define PWM_INACTIVE_NEGATIVE (0 << 4) 29 #define PWM_INACTIVE_POSITIVE (1 << 4) 30 #define PWM_OUTPUT_LEFT (0 << 5) 31 #define PWM_LP_DISABLE (0 << 8) 32 33 struct rockchip_pwm_chip { 34 struct pwm_chip chip; 35 struct clk *clk; 36 const struct rockchip_pwm_data *data; 37 void __iomem *base; 38 }; 39 40 struct rockchip_pwm_regs { 41 unsigned long duty; 42 unsigned long period; 43 unsigned long cntr; 44 unsigned long ctrl; 45 }; 46 47 struct rockchip_pwm_data { 48 struct rockchip_pwm_regs regs; 49 unsigned int prescaler; 50 bool supports_polarity; 51 const struct pwm_ops *ops; 52 53 void (*set_enable)(struct pwm_chip *chip, 54 struct pwm_device *pwm, bool enable, 55 enum pwm_polarity polarity); 56 void (*get_state)(struct pwm_chip *chip, struct pwm_device *pwm, 57 struct pwm_state *state); 58 }; 59 60 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) 61 { 62 return container_of(c, struct rockchip_pwm_chip, chip); 63 } 64 65 static void rockchip_pwm_set_enable_v1(struct pwm_chip *chip, 66 struct pwm_device *pwm, bool enable, 67 enum pwm_polarity polarity) 68 { 69 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 70 u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; 71 u32 val; 72 73 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 74 75 if (enable) 76 val |= enable_conf; 77 else 78 val &= ~enable_conf; 79 80 writel_relaxed(val, pc->base + pc->data->regs.ctrl); 81 } 82 83 static void rockchip_pwm_get_state_v1(struct pwm_chip *chip, 84 struct pwm_device *pwm, 85 struct pwm_state *state) 86 { 87 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 88 u32 enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN; 89 u32 val; 90 91 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 92 if ((val & enable_conf) == enable_conf) 93 state->enabled = true; 94 } 95 96 static void rockchip_pwm_set_enable_v2(struct pwm_chip *chip, 97 struct pwm_device *pwm, bool enable, 98 enum pwm_polarity polarity) 99 { 100 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 101 u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 102 PWM_CONTINUOUS; 103 u32 val; 104 105 if (polarity == PWM_POLARITY_INVERSED) 106 enable_conf |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE; 107 else 108 enable_conf |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE; 109 110 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 111 112 if (enable) 113 val |= enable_conf; 114 else 115 val &= ~enable_conf; 116 117 writel_relaxed(val, pc->base + pc->data->regs.ctrl); 118 } 119 120 static void rockchip_pwm_get_state_v2(struct pwm_chip *chip, 121 struct pwm_device *pwm, 122 struct pwm_state *state) 123 { 124 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 125 u32 enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 126 PWM_CONTINUOUS; 127 u32 val; 128 129 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 130 if ((val & enable_conf) != enable_conf) 131 return; 132 133 state->enabled = true; 134 135 if (!(val & PWM_DUTY_POSITIVE)) 136 state->polarity = PWM_POLARITY_INVERSED; 137 } 138 139 static void rockchip_pwm_get_state(struct pwm_chip *chip, 140 struct pwm_device *pwm, 141 struct pwm_state *state) 142 { 143 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 144 unsigned long clk_rate; 145 u64 tmp; 146 int ret; 147 148 ret = clk_enable(pc->clk); 149 if (ret) 150 return; 151 152 clk_rate = clk_get_rate(pc->clk); 153 154 tmp = readl_relaxed(pc->base + pc->data->regs.period); 155 tmp *= pc->data->prescaler * NSEC_PER_SEC; 156 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 157 158 tmp = readl_relaxed(pc->base + pc->data->regs.duty); 159 tmp *= pc->data->prescaler * NSEC_PER_SEC; 160 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 161 162 pc->data->get_state(chip, pwm, state); 163 164 clk_disable(pc->clk); 165 } 166 167 static int rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 168 int duty_ns, int period_ns) 169 { 170 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 171 unsigned long period, duty; 172 u64 clk_rate, div; 173 174 clk_rate = clk_get_rate(pc->clk); 175 176 /* 177 * Since period and duty cycle registers have a width of 32 178 * bits, every possible input period can be obtained using the 179 * default prescaler value for all practical clock rate values. 180 */ 181 div = clk_rate * period_ns; 182 period = DIV_ROUND_CLOSEST_ULL(div, 183 pc->data->prescaler * NSEC_PER_SEC); 184 185 div = clk_rate * duty_ns; 186 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); 187 188 writel(period, pc->base + pc->data->regs.period); 189 writel(duty, pc->base + pc->data->regs.duty); 190 191 return 0; 192 } 193 194 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 195 struct pwm_state *state) 196 { 197 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 198 struct pwm_state curstate; 199 bool enabled; 200 int ret; 201 202 pwm_get_state(pwm, &curstate); 203 enabled = curstate.enabled; 204 205 ret = clk_enable(pc->clk); 206 if (ret) 207 return ret; 208 209 if (state->polarity != curstate.polarity && enabled) { 210 pc->data->set_enable(chip, pwm, false, state->polarity); 211 enabled = false; 212 } 213 214 ret = rockchip_pwm_config(chip, pwm, state->duty_cycle, state->period); 215 if (ret) { 216 if (enabled != curstate.enabled) 217 pc->data->set_enable(chip, pwm, !enabled, 218 state->polarity); 219 220 goto out; 221 } 222 223 if (state->enabled != enabled) 224 pc->data->set_enable(chip, pwm, state->enabled, 225 state->polarity); 226 227 /* 228 * Update the state with the real hardware, which can differ a bit 229 * because of period/duty_cycle approximation. 230 */ 231 rockchip_pwm_get_state(chip, pwm, state); 232 233 out: 234 clk_disable(pc->clk); 235 236 return ret; 237 } 238 239 static const struct pwm_ops rockchip_pwm_ops_v1 = { 240 .get_state = rockchip_pwm_get_state, 241 .apply = rockchip_pwm_apply, 242 .owner = THIS_MODULE, 243 }; 244 245 static const struct pwm_ops rockchip_pwm_ops_v2 = { 246 .get_state = rockchip_pwm_get_state, 247 .apply = rockchip_pwm_apply, 248 .owner = THIS_MODULE, 249 }; 250 251 static const struct rockchip_pwm_data pwm_data_v1 = { 252 .regs = { 253 .duty = 0x04, 254 .period = 0x08, 255 .cntr = 0x00, 256 .ctrl = 0x0c, 257 }, 258 .prescaler = 2, 259 .ops = &rockchip_pwm_ops_v1, 260 .set_enable = rockchip_pwm_set_enable_v1, 261 .get_state = rockchip_pwm_get_state_v1, 262 }; 263 264 static const struct rockchip_pwm_data pwm_data_v2 = { 265 .regs = { 266 .duty = 0x08, 267 .period = 0x04, 268 .cntr = 0x00, 269 .ctrl = 0x0c, 270 }, 271 .prescaler = 1, 272 .supports_polarity = true, 273 .ops = &rockchip_pwm_ops_v2, 274 .set_enable = rockchip_pwm_set_enable_v2, 275 .get_state = rockchip_pwm_get_state_v2, 276 }; 277 278 static const struct rockchip_pwm_data pwm_data_vop = { 279 .regs = { 280 .duty = 0x08, 281 .period = 0x04, 282 .cntr = 0x0c, 283 .ctrl = 0x00, 284 }, 285 .prescaler = 1, 286 .supports_polarity = true, 287 .ops = &rockchip_pwm_ops_v2, 288 .set_enable = rockchip_pwm_set_enable_v2, 289 .get_state = rockchip_pwm_get_state_v2, 290 }; 291 292 static const struct of_device_id rockchip_pwm_dt_ids[] = { 293 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1}, 294 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2}, 295 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop}, 296 { /* sentinel */ } 297 }; 298 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); 299 300 static int rockchip_pwm_probe(struct platform_device *pdev) 301 { 302 const struct of_device_id *id; 303 struct rockchip_pwm_chip *pc; 304 struct resource *r; 305 int ret; 306 307 id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev); 308 if (!id) 309 return -EINVAL; 310 311 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 312 if (!pc) 313 return -ENOMEM; 314 315 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 316 pc->base = devm_ioremap_resource(&pdev->dev, r); 317 if (IS_ERR(pc->base)) 318 return PTR_ERR(pc->base); 319 320 pc->clk = devm_clk_get(&pdev->dev, NULL); 321 if (IS_ERR(pc->clk)) 322 return PTR_ERR(pc->clk); 323 324 ret = clk_prepare_enable(pc->clk); 325 if (ret) 326 return ret; 327 328 platform_set_drvdata(pdev, pc); 329 330 pc->data = id->data; 331 pc->chip.dev = &pdev->dev; 332 pc->chip.ops = pc->data->ops; 333 pc->chip.base = -1; 334 pc->chip.npwm = 1; 335 336 if (pc->data->supports_polarity) { 337 pc->chip.of_xlate = of_pwm_xlate_with_flags; 338 pc->chip.of_pwm_n_cells = 3; 339 } 340 341 ret = pwmchip_add(&pc->chip); 342 if (ret < 0) { 343 clk_unprepare(pc->clk); 344 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 345 } 346 347 /* Keep the PWM clk enabled if the PWM appears to be up and running. */ 348 if (!pwm_is_enabled(pc->chip.pwms)) 349 clk_disable(pc->clk); 350 351 return ret; 352 } 353 354 static int rockchip_pwm_remove(struct platform_device *pdev) 355 { 356 struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev); 357 358 /* 359 * Disable the PWM clk before unpreparing it if the PWM device is still 360 * running. This should only happen when the last PWM user left it 361 * enabled, or when nobody requested a PWM that was previously enabled 362 * by the bootloader. 363 * 364 * FIXME: Maybe the core should disable all PWM devices in 365 * pwmchip_remove(). In this case we'd only have to call 366 * clk_unprepare() after pwmchip_remove(). 367 * 368 */ 369 if (pwm_is_enabled(pc->chip.pwms)) 370 clk_disable(pc->clk); 371 372 clk_unprepare(pc->clk); 373 374 return pwmchip_remove(&pc->chip); 375 } 376 377 static struct platform_driver rockchip_pwm_driver = { 378 .driver = { 379 .name = "rockchip-pwm", 380 .of_match_table = rockchip_pwm_dt_ids, 381 }, 382 .probe = rockchip_pwm_probe, 383 .remove = rockchip_pwm_remove, 384 }; 385 module_platform_driver(rockchip_pwm_driver); 386 387 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); 388 MODULE_DESCRIPTION("Rockchip SoC PWM driver"); 389 MODULE_LICENSE("GPL v2"); 390