1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PWM driver for Rockchip SoCs 4 * 5 * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com> 6 * Copyright (C) 2014 ROCKCHIP, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/platform_device.h> 15 #include <linux/pwm.h> 16 #include <linux/time.h> 17 18 #define PWM_CTRL_TIMER_EN (1 << 0) 19 #define PWM_CTRL_OUTPUT_EN (1 << 3) 20 21 #define PWM_ENABLE (1 << 0) 22 #define PWM_CONTINUOUS (1 << 1) 23 #define PWM_DUTY_POSITIVE (1 << 3) 24 #define PWM_DUTY_NEGATIVE (0 << 3) 25 #define PWM_INACTIVE_NEGATIVE (0 << 4) 26 #define PWM_INACTIVE_POSITIVE (1 << 4) 27 #define PWM_POLARITY_MASK (PWM_DUTY_POSITIVE | PWM_INACTIVE_POSITIVE) 28 #define PWM_OUTPUT_LEFT (0 << 5) 29 #define PWM_LOCK_EN (1 << 6) 30 #define PWM_LP_DISABLE (0 << 8) 31 32 struct rockchip_pwm_chip { 33 struct pwm_chip chip; 34 struct clk *clk; 35 struct clk *pclk; 36 const struct rockchip_pwm_data *data; 37 void __iomem *base; 38 }; 39 40 struct rockchip_pwm_regs { 41 unsigned long duty; 42 unsigned long period; 43 unsigned long cntr; 44 unsigned long ctrl; 45 }; 46 47 struct rockchip_pwm_data { 48 struct rockchip_pwm_regs regs; 49 unsigned int prescaler; 50 bool supports_polarity; 51 bool supports_lock; 52 u32 enable_conf; 53 }; 54 55 static inline struct rockchip_pwm_chip *to_rockchip_pwm_chip(struct pwm_chip *c) 56 { 57 return container_of(c, struct rockchip_pwm_chip, chip); 58 } 59 60 static void rockchip_pwm_get_state(struct pwm_chip *chip, 61 struct pwm_device *pwm, 62 struct pwm_state *state) 63 { 64 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 65 u32 enable_conf = pc->data->enable_conf; 66 unsigned long clk_rate; 67 u64 tmp; 68 u32 val; 69 int ret; 70 71 ret = clk_enable(pc->pclk); 72 if (ret) 73 return; 74 75 clk_rate = clk_get_rate(pc->clk); 76 77 tmp = readl_relaxed(pc->base + pc->data->regs.period); 78 tmp *= pc->data->prescaler * NSEC_PER_SEC; 79 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 80 81 tmp = readl_relaxed(pc->base + pc->data->regs.duty); 82 tmp *= pc->data->prescaler * NSEC_PER_SEC; 83 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate); 84 85 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 86 state->enabled = (val & enable_conf) == enable_conf; 87 88 if (pc->data->supports_polarity && !(val & PWM_DUTY_POSITIVE)) 89 state->polarity = PWM_POLARITY_INVERSED; 90 else 91 state->polarity = PWM_POLARITY_NORMAL; 92 93 clk_disable(pc->pclk); 94 } 95 96 static void rockchip_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, 97 const struct pwm_state *state) 98 { 99 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 100 unsigned long period, duty; 101 u64 clk_rate, div; 102 u32 ctrl; 103 104 clk_rate = clk_get_rate(pc->clk); 105 106 /* 107 * Since period and duty cycle registers have a width of 32 108 * bits, every possible input period can be obtained using the 109 * default prescaler value for all practical clock rate values. 110 */ 111 div = clk_rate * state->period; 112 period = DIV_ROUND_CLOSEST_ULL(div, 113 pc->data->prescaler * NSEC_PER_SEC); 114 115 div = clk_rate * state->duty_cycle; 116 duty = DIV_ROUND_CLOSEST_ULL(div, pc->data->prescaler * NSEC_PER_SEC); 117 118 /* 119 * Lock the period and duty of previous configuration, then 120 * change the duty and period, that would not be effective. 121 */ 122 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); 123 if (pc->data->supports_lock) { 124 ctrl |= PWM_LOCK_EN; 125 writel_relaxed(ctrl, pc->base + pc->data->regs.ctrl); 126 } 127 128 writel(period, pc->base + pc->data->regs.period); 129 writel(duty, pc->base + pc->data->regs.duty); 130 131 if (pc->data->supports_polarity) { 132 ctrl &= ~PWM_POLARITY_MASK; 133 if (state->polarity == PWM_POLARITY_INVERSED) 134 ctrl |= PWM_DUTY_NEGATIVE | PWM_INACTIVE_POSITIVE; 135 else 136 ctrl |= PWM_DUTY_POSITIVE | PWM_INACTIVE_NEGATIVE; 137 } 138 139 /* 140 * Unlock and set polarity at the same time, 141 * the configuration of duty, period and polarity 142 * would be effective together at next period. 143 */ 144 if (pc->data->supports_lock) 145 ctrl &= ~PWM_LOCK_EN; 146 147 writel(ctrl, pc->base + pc->data->regs.ctrl); 148 } 149 150 static int rockchip_pwm_enable(struct pwm_chip *chip, 151 struct pwm_device *pwm, 152 bool enable) 153 { 154 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 155 u32 enable_conf = pc->data->enable_conf; 156 int ret; 157 u32 val; 158 159 if (enable) { 160 ret = clk_enable(pc->clk); 161 if (ret) 162 return ret; 163 } 164 165 val = readl_relaxed(pc->base + pc->data->regs.ctrl); 166 167 if (enable) 168 val |= enable_conf; 169 else 170 val &= ~enable_conf; 171 172 writel_relaxed(val, pc->base + pc->data->regs.ctrl); 173 174 if (!enable) 175 clk_disable(pc->clk); 176 177 return 0; 178 } 179 180 static int rockchip_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 181 const struct pwm_state *state) 182 { 183 struct rockchip_pwm_chip *pc = to_rockchip_pwm_chip(chip); 184 struct pwm_state curstate; 185 bool enabled; 186 int ret = 0; 187 188 ret = clk_enable(pc->pclk); 189 if (ret) 190 return ret; 191 192 pwm_get_state(pwm, &curstate); 193 enabled = curstate.enabled; 194 195 if (state->polarity != curstate.polarity && enabled && 196 !pc->data->supports_lock) { 197 ret = rockchip_pwm_enable(chip, pwm, false); 198 if (ret) 199 goto out; 200 enabled = false; 201 } 202 203 rockchip_pwm_config(chip, pwm, state); 204 if (state->enabled != enabled) { 205 ret = rockchip_pwm_enable(chip, pwm, state->enabled); 206 if (ret) 207 goto out; 208 } 209 210 out: 211 clk_disable(pc->pclk); 212 213 return ret; 214 } 215 216 static const struct pwm_ops rockchip_pwm_ops = { 217 .get_state = rockchip_pwm_get_state, 218 .apply = rockchip_pwm_apply, 219 .owner = THIS_MODULE, 220 }; 221 222 static const struct rockchip_pwm_data pwm_data_v1 = { 223 .regs = { 224 .duty = 0x04, 225 .period = 0x08, 226 .cntr = 0x00, 227 .ctrl = 0x0c, 228 }, 229 .prescaler = 2, 230 .supports_polarity = false, 231 .supports_lock = false, 232 .enable_conf = PWM_CTRL_OUTPUT_EN | PWM_CTRL_TIMER_EN, 233 }; 234 235 static const struct rockchip_pwm_data pwm_data_v2 = { 236 .regs = { 237 .duty = 0x08, 238 .period = 0x04, 239 .cntr = 0x00, 240 .ctrl = 0x0c, 241 }, 242 .prescaler = 1, 243 .supports_polarity = true, 244 .supports_lock = false, 245 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 246 PWM_CONTINUOUS, 247 }; 248 249 static const struct rockchip_pwm_data pwm_data_vop = { 250 .regs = { 251 .duty = 0x08, 252 .period = 0x04, 253 .cntr = 0x0c, 254 .ctrl = 0x00, 255 }, 256 .prescaler = 1, 257 .supports_polarity = true, 258 .supports_lock = false, 259 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 260 PWM_CONTINUOUS, 261 }; 262 263 static const struct rockchip_pwm_data pwm_data_v3 = { 264 .regs = { 265 .duty = 0x08, 266 .period = 0x04, 267 .cntr = 0x00, 268 .ctrl = 0x0c, 269 }, 270 .prescaler = 1, 271 .supports_polarity = true, 272 .supports_lock = true, 273 .enable_conf = PWM_OUTPUT_LEFT | PWM_LP_DISABLE | PWM_ENABLE | 274 PWM_CONTINUOUS, 275 }; 276 277 static const struct of_device_id rockchip_pwm_dt_ids[] = { 278 { .compatible = "rockchip,rk2928-pwm", .data = &pwm_data_v1}, 279 { .compatible = "rockchip,rk3288-pwm", .data = &pwm_data_v2}, 280 { .compatible = "rockchip,vop-pwm", .data = &pwm_data_vop}, 281 { .compatible = "rockchip,rk3328-pwm", .data = &pwm_data_v3}, 282 { /* sentinel */ } 283 }; 284 MODULE_DEVICE_TABLE(of, rockchip_pwm_dt_ids); 285 286 static int rockchip_pwm_probe(struct platform_device *pdev) 287 { 288 const struct of_device_id *id; 289 struct rockchip_pwm_chip *pc; 290 struct resource *r; 291 u32 enable_conf, ctrl; 292 int ret, count; 293 294 id = of_match_device(rockchip_pwm_dt_ids, &pdev->dev); 295 if (!id) 296 return -EINVAL; 297 298 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); 299 if (!pc) 300 return -ENOMEM; 301 302 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 303 pc->base = devm_ioremap_resource(&pdev->dev, r); 304 if (IS_ERR(pc->base)) 305 return PTR_ERR(pc->base); 306 307 pc->clk = devm_clk_get(&pdev->dev, "pwm"); 308 if (IS_ERR(pc->clk)) { 309 pc->clk = devm_clk_get(&pdev->dev, NULL); 310 if (IS_ERR(pc->clk)) { 311 ret = PTR_ERR(pc->clk); 312 if (ret != -EPROBE_DEFER) 313 dev_err(&pdev->dev, "Can't get bus clk: %d\n", 314 ret); 315 return ret; 316 } 317 } 318 319 count = of_count_phandle_with_args(pdev->dev.of_node, 320 "clocks", "#clock-cells"); 321 if (count == 2) 322 pc->pclk = devm_clk_get(&pdev->dev, "pclk"); 323 else 324 pc->pclk = pc->clk; 325 326 if (IS_ERR(pc->pclk)) { 327 ret = PTR_ERR(pc->pclk); 328 if (ret != -EPROBE_DEFER) 329 dev_err(&pdev->dev, "Can't get APB clk: %d\n", ret); 330 return ret; 331 } 332 333 ret = clk_prepare_enable(pc->clk); 334 if (ret) { 335 dev_err(&pdev->dev, "Can't prepare enable bus clk: %d\n", ret); 336 return ret; 337 } 338 339 ret = clk_prepare(pc->pclk); 340 if (ret) { 341 dev_err(&pdev->dev, "Can't prepare APB clk: %d\n", ret); 342 goto err_clk; 343 } 344 345 platform_set_drvdata(pdev, pc); 346 347 pc->data = id->data; 348 pc->chip.dev = &pdev->dev; 349 pc->chip.ops = &rockchip_pwm_ops; 350 pc->chip.base = -1; 351 pc->chip.npwm = 1; 352 353 if (pc->data->supports_polarity) { 354 pc->chip.of_xlate = of_pwm_xlate_with_flags; 355 pc->chip.of_pwm_n_cells = 3; 356 } 357 358 ret = pwmchip_add(&pc->chip); 359 if (ret < 0) { 360 clk_unprepare(pc->clk); 361 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret); 362 goto err_pclk; 363 } 364 365 /* Keep the PWM clk enabled if the PWM appears to be up and running. */ 366 enable_conf = pc->data->enable_conf; 367 ctrl = readl_relaxed(pc->base + pc->data->regs.ctrl); 368 if ((ctrl & enable_conf) != enable_conf) 369 clk_disable(pc->clk); 370 371 return 0; 372 373 err_pclk: 374 clk_unprepare(pc->pclk); 375 err_clk: 376 clk_disable_unprepare(pc->clk); 377 378 return ret; 379 } 380 381 static int rockchip_pwm_remove(struct platform_device *pdev) 382 { 383 struct rockchip_pwm_chip *pc = platform_get_drvdata(pdev); 384 385 /* 386 * Disable the PWM clk before unpreparing it if the PWM device is still 387 * running. This should only happen when the last PWM user left it 388 * enabled, or when nobody requested a PWM that was previously enabled 389 * by the bootloader. 390 * 391 * FIXME: Maybe the core should disable all PWM devices in 392 * pwmchip_remove(). In this case we'd only have to call 393 * clk_unprepare() after pwmchip_remove(). 394 * 395 */ 396 if (pwm_is_enabled(pc->chip.pwms)) 397 clk_disable(pc->clk); 398 399 clk_unprepare(pc->pclk); 400 clk_unprepare(pc->clk); 401 402 return pwmchip_remove(&pc->chip); 403 } 404 405 static struct platform_driver rockchip_pwm_driver = { 406 .driver = { 407 .name = "rockchip-pwm", 408 .of_match_table = rockchip_pwm_dt_ids, 409 }, 410 .probe = rockchip_pwm_probe, 411 .remove = rockchip_pwm_remove, 412 }; 413 module_platform_driver(rockchip_pwm_driver); 414 415 MODULE_AUTHOR("Beniamino Galvani <b.galvani@gmail.com>"); 416 MODULE_DESCRIPTION("Rockchip SoC PWM driver"); 417 MODULE_LICENSE("GPL v2"); 418