16f7f70e3SChiaEn Wu // SPDX-License-Identifier: GPL-2.0-only
26f7f70e3SChiaEn Wu /*
36f7f70e3SChiaEn Wu  * Copyright (C) 2022 Richtek Technology Corp.
46f7f70e3SChiaEn Wu  *
56f7f70e3SChiaEn Wu  * Author: ChiYuan Huang <cy_huang@richtek.com>
66f7f70e3SChiaEn Wu  *         ChiaEn Wu <chiaen_wu@richtek.com>
76f7f70e3SChiaEn Wu  */
86f7f70e3SChiaEn Wu 
96f7f70e3SChiaEn Wu #include <linux/bits.h>
106f7f70e3SChiaEn Wu #include <linux/bitfield.h>
116f7f70e3SChiaEn Wu #include <linux/completion.h>
126f7f70e3SChiaEn Wu #include <linux/delay.h>
136f7f70e3SChiaEn Wu #include <linux/gpio/consumer.h>
146f7f70e3SChiaEn Wu #include <linux/i2c.h>
156f7f70e3SChiaEn Wu #include <linux/interrupt.h>
166f7f70e3SChiaEn Wu #include <linux/kernel.h>
176f7f70e3SChiaEn Wu #include <linux/kstrtox.h>
186f7f70e3SChiaEn Wu #include <linux/linear_range.h>
196f7f70e3SChiaEn Wu #include <linux/module.h>
206f7f70e3SChiaEn Wu #include <linux/mod_devicetable.h>
216f7f70e3SChiaEn Wu #include <linux/mutex.h>
226f7f70e3SChiaEn Wu #include <linux/of.h>
236f7f70e3SChiaEn Wu #include <linux/power_supply.h>
246f7f70e3SChiaEn Wu #include <linux/regmap.h>
256f7f70e3SChiaEn Wu #include <linux/regulator/driver.h>
266f7f70e3SChiaEn Wu #include <linux/units.h>
276f7f70e3SChiaEn Wu #include <linux/sysfs.h>
286f7f70e3SChiaEn Wu 
296f7f70e3SChiaEn Wu #define RT9467_REG_CORE_CTRL0		0x00
306f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL1		0x01
316f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL2		0x02
326f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL3		0x03
336f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL4		0x04
346f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL5		0x05
356f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL6		0x06
366f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL7		0x07
376f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL8		0x08
386f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL9		0x09
396f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL10		0x0A
406f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL12		0x0C
416f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL13		0x0D
426f7f70e3SChiaEn Wu #define RT9467_REG_CHG_CTRL14		0x0E
436f7f70e3SChiaEn Wu #define RT9467_REG_CHG_ADC		0x11
446f7f70e3SChiaEn Wu #define RT9467_REG_CHG_DPDM1		0x12
456f7f70e3SChiaEn Wu #define RT9467_REG_CHG_DPDM2		0x13
466f7f70e3SChiaEn Wu #define RT9467_REG_DEVICE_ID		0x40
476f7f70e3SChiaEn Wu #define RT9467_REG_CHG_STAT		0x42
486f7f70e3SChiaEn Wu #define RT9467_REG_ADC_DATA_H		0x44
496f7f70e3SChiaEn Wu #define RT9467_REG_CHG_STATC		0x50
506f7f70e3SChiaEn Wu #define RT9467_REG_CHG_IRQ1		0x53
516f7f70e3SChiaEn Wu #define RT9467_REG_CHG_STATC_CTRL	0x60
526f7f70e3SChiaEn Wu #define RT9467_REG_CHG_IRQ1_CTRL	0x63
536f7f70e3SChiaEn Wu 
546f7f70e3SChiaEn Wu #define RT9467_MASK_PWR_RDY		BIT(7)
556f7f70e3SChiaEn Wu #define RT9467_MASK_MIVR_STAT		BIT(6)
566f7f70e3SChiaEn Wu #define RT9467_MASK_OTG_CSEL		GENMASK(2, 0)
576f7f70e3SChiaEn Wu #define RT9467_MASK_OTG_VSEL		GENMASK(7, 2)
586f7f70e3SChiaEn Wu #define RT9467_MASK_OTG_EN		BIT(0)
596f7f70e3SChiaEn Wu #define RT9467_MASK_ADC_IN_SEL		GENMASK(7, 4)
606f7f70e3SChiaEn Wu #define RT9467_MASK_ADC_START		BIT(0)
616f7f70e3SChiaEn Wu 
626f7f70e3SChiaEn Wu #define RT9467_NUM_IRQ_REGS		4
636f7f70e3SChiaEn Wu #define RT9467_ICHG_MIN_uA		100000
646f7f70e3SChiaEn Wu #define RT9467_ICHG_MAX_uA		5000000
656f7f70e3SChiaEn Wu #define RT9467_CV_MAX_uV		4710000
666f7f70e3SChiaEn Wu #define RT9467_OTG_MIN_uV		4425000
676f7f70e3SChiaEn Wu #define RT9467_OTG_MAX_uV		5825000
686f7f70e3SChiaEn Wu #define RT9467_OTG_STEP_uV		25000
696f7f70e3SChiaEn Wu #define RT9467_NUM_VOTG			(RT9467_OTG_MAX_uV - RT9467_OTG_MIN_uV + 1)
706f7f70e3SChiaEn Wu #define RT9467_AICLVTH_GAP_uV		200000
716f7f70e3SChiaEn Wu #define RT9467_ADCCONV_TIME_MS		35
726f7f70e3SChiaEn Wu 
736f7f70e3SChiaEn Wu #define RT9466_VID			0x8
746f7f70e3SChiaEn Wu #define RT9467_VID			0x9
756f7f70e3SChiaEn Wu 
766f7f70e3SChiaEn Wu /* IRQ number */
776f7f70e3SChiaEn Wu #define RT9467_IRQ_TS_STATC	0
786f7f70e3SChiaEn Wu #define RT9467_IRQ_CHG_FAULT	1
796f7f70e3SChiaEn Wu #define RT9467_IRQ_CHG_STATC	2
806f7f70e3SChiaEn Wu #define RT9467_IRQ_CHG_TMR	3
816f7f70e3SChiaEn Wu #define RT9467_IRQ_CHG_BATABS	4
826f7f70e3SChiaEn Wu #define RT9467_IRQ_CHG_ADPBAD	5
836f7f70e3SChiaEn Wu #define RT9467_IRQ_CHG_RVP	6
846f7f70e3SChiaEn Wu #define RT9467_IRQ_OTP		7
856f7f70e3SChiaEn Wu 
866f7f70e3SChiaEn Wu #define RT9467_IRQ_CHG_AICLM	8
876f7f70e3SChiaEn Wu #define RT9467_IRQ_CHG_ICHGM	9
886f7f70e3SChiaEn Wu #define RT9467_IRQ_WDTMR	11
896f7f70e3SChiaEn Wu #define RT9467_IRQ_SSFINISH	12
906f7f70e3SChiaEn Wu #define RT9467_IRQ_CHG_RECHG	13
916f7f70e3SChiaEn Wu #define RT9467_IRQ_CHG_TERM	14
926f7f70e3SChiaEn Wu #define RT9467_IRQ_CHG_IEOC	15
936f7f70e3SChiaEn Wu 
946f7f70e3SChiaEn Wu #define RT9467_IRQ_ADC_DONE	16
956f7f70e3SChiaEn Wu #define RT9467_IRQ_PUMPX_DONE	17
966f7f70e3SChiaEn Wu #define RT9467_IRQ_BST_BATUV	21
976f7f70e3SChiaEn Wu #define RT9467_IRQ_BST_MIDOV	22
986f7f70e3SChiaEn Wu #define RT9467_IRQ_BST_OLP	23
996f7f70e3SChiaEn Wu 
1006f7f70e3SChiaEn Wu #define RT9467_IRQ_ATTACH	24
1016f7f70e3SChiaEn Wu #define RT9467_IRQ_DETACH	25
1026f7f70e3SChiaEn Wu #define RT9467_IRQ_HVDCP_DET	29
1036f7f70e3SChiaEn Wu #define RT9467_IRQ_CHGDET	30
1046f7f70e3SChiaEn Wu #define RT9467_IRQ_DCDT		31
1056f7f70e3SChiaEn Wu 
1066f7f70e3SChiaEn Wu enum rt9467_fields {
1076f7f70e3SChiaEn Wu 	/* RT9467_REG_CORE_CTRL0 */
1086f7f70e3SChiaEn Wu 	F_RST = 0,
1096f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_CTRL1 */
1106f7f70e3SChiaEn Wu 	F_HZ, F_OTG_PIN_EN, F_OPA_MODE,
1116f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_CTRL2 */
1126f7f70e3SChiaEn Wu 	F_SHIP_MODE, F_TE, F_IINLMTSEL, F_CFO_EN, F_CHG_EN,
1136f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_CTRL3 */
1146f7f70e3SChiaEn Wu 	F_IAICR, F_ILIM_EN,
1156f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_CTRL4 */
1166f7f70e3SChiaEn Wu 	F_VOREG,
1176f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_CTRL6 */
1186f7f70e3SChiaEn Wu 	F_VMIVR,
1196f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_CTRL7 */
1206f7f70e3SChiaEn Wu 	F_ICHG,
1216f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_CTRL8 */
1226f7f70e3SChiaEn Wu 	F_IPREC,
1236f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_CTRL9 */
1246f7f70e3SChiaEn Wu 	F_IEOC,
1256f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_CTRL12 */
1266f7f70e3SChiaEn Wu 	F_WT_FC,
1276f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_CTRL13 */
1286f7f70e3SChiaEn Wu 	F_OCP,
1296f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_CTRL14 */
1306f7f70e3SChiaEn Wu 	F_AICL_MEAS, F_AICL_VTH,
1316f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_DPDM1 */
1326f7f70e3SChiaEn Wu 	F_USBCHGEN,
1336f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_DPDM2 */
1346f7f70e3SChiaEn Wu 	F_USB_STATUS,
1356f7f70e3SChiaEn Wu 	/* RT9467_REG_DEVICE_ID */
1366f7f70e3SChiaEn Wu 	F_VENDOR,
1376f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_STAT */
1386f7f70e3SChiaEn Wu 	F_CHG_STAT,
1396f7f70e3SChiaEn Wu 	/* RT9467_REG_CHG_STATC */
1406f7f70e3SChiaEn Wu 	F_PWR_RDY, F_CHG_MIVR,
1416f7f70e3SChiaEn Wu 	F_MAX_FIELDS
1426f7f70e3SChiaEn Wu };
1436f7f70e3SChiaEn Wu 
1446f7f70e3SChiaEn Wu static const struct regmap_irq rt9467_irqs[] = {
1456f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_TS_STATC, 8),
1466f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_CHG_FAULT, 8),
1476f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_CHG_STATC, 8),
1486f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_CHG_TMR, 8),
1496f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_CHG_BATABS, 8),
1506f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_CHG_ADPBAD, 8),
1516f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_CHG_RVP, 8),
1526f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_OTP, 8),
1536f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_CHG_AICLM, 8),
1546f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_CHG_ICHGM, 8),
1556f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_WDTMR, 8),
1566f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_SSFINISH, 8),
1576f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_CHG_RECHG, 8),
1586f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_CHG_TERM, 8),
1596f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_CHG_IEOC, 8),
1606f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_ADC_DONE, 8),
1616f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_PUMPX_DONE, 8),
1626f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_BST_BATUV, 8),
1636f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_BST_MIDOV, 8),
1646f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_BST_OLP, 8),
1656f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_ATTACH, 8),
1666f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_DETACH, 8),
1676f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_HVDCP_DET, 8),
1686f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_CHGDET, 8),
1696f7f70e3SChiaEn Wu 	REGMAP_IRQ_REG_LINE(RT9467_IRQ_DCDT, 8)
1706f7f70e3SChiaEn Wu };
1716f7f70e3SChiaEn Wu 
1726f7f70e3SChiaEn Wu static const struct regmap_irq_chip rt9467_irq_chip = {
1736f7f70e3SChiaEn Wu 	.name = "rt9467-irqs",
1746f7f70e3SChiaEn Wu 	.status_base = RT9467_REG_CHG_IRQ1,
1756f7f70e3SChiaEn Wu 	.mask_base = RT9467_REG_CHG_IRQ1_CTRL,
1766f7f70e3SChiaEn Wu 	.num_regs = RT9467_NUM_IRQ_REGS,
1776f7f70e3SChiaEn Wu 	.irqs = rt9467_irqs,
1786f7f70e3SChiaEn Wu 	.num_irqs = ARRAY_SIZE(rt9467_irqs),
1796f7f70e3SChiaEn Wu };
1806f7f70e3SChiaEn Wu 
1816f7f70e3SChiaEn Wu enum rt9467_ranges {
1826f7f70e3SChiaEn Wu 	RT9467_RANGE_IAICR = 0,
1836f7f70e3SChiaEn Wu 	RT9467_RANGE_VOREG,
1846f7f70e3SChiaEn Wu 	RT9467_RANGE_VMIVR,
1856f7f70e3SChiaEn Wu 	RT9467_RANGE_ICHG,
1866f7f70e3SChiaEn Wu 	RT9467_RANGE_IPREC,
1876f7f70e3SChiaEn Wu 	RT9467_RANGE_IEOC,
1886f7f70e3SChiaEn Wu 	RT9467_RANGE_AICL_VTH,
1896f7f70e3SChiaEn Wu 	RT9467_RANGES_MAX
1906f7f70e3SChiaEn Wu };
1916f7f70e3SChiaEn Wu 
1926f7f70e3SChiaEn Wu static const struct linear_range rt9467_ranges[RT9467_RANGES_MAX] = {
1936f7f70e3SChiaEn Wu 	LINEAR_RANGE_IDX(RT9467_RANGE_IAICR, 100000, 0x0, 0x3F, 50000),
1946f7f70e3SChiaEn Wu 	LINEAR_RANGE_IDX(RT9467_RANGE_VOREG, 3900000, 0x0, 0x51, 10000),
1956f7f70e3SChiaEn Wu 	LINEAR_RANGE_IDX(RT9467_RANGE_VMIVR, 3900000, 0x0, 0x5F, 100000),
1966f7f70e3SChiaEn Wu 	LINEAR_RANGE_IDX(RT9467_RANGE_ICHG, 900000, 0x08, 0x31, 100000),
1976f7f70e3SChiaEn Wu 	LINEAR_RANGE_IDX(RT9467_RANGE_IPREC, 100000, 0x0, 0x0F, 50000),
1986f7f70e3SChiaEn Wu 	LINEAR_RANGE_IDX(RT9467_RANGE_IEOC, 100000, 0x0, 0x0F, 50000),
1996f7f70e3SChiaEn Wu 	LINEAR_RANGE_IDX(RT9467_RANGE_AICL_VTH, 4100000, 0x0, 0x7, 100000),
2006f7f70e3SChiaEn Wu };
2016f7f70e3SChiaEn Wu 
2026f7f70e3SChiaEn Wu static const struct reg_field rt9467_chg_fields[] = {
2036f7f70e3SChiaEn Wu 	[F_RST]			= REG_FIELD(RT9467_REG_CORE_CTRL0, 7, 7),
2046f7f70e3SChiaEn Wu 	[F_HZ]			= REG_FIELD(RT9467_REG_CHG_CTRL1, 2, 2),
2056f7f70e3SChiaEn Wu 	[F_OTG_PIN_EN]		= REG_FIELD(RT9467_REG_CHG_CTRL1, 1, 1),
2066f7f70e3SChiaEn Wu 	[F_OPA_MODE]		= REG_FIELD(RT9467_REG_CHG_CTRL1, 0, 0),
2076f7f70e3SChiaEn Wu 	[F_SHIP_MODE]		= REG_FIELD(RT9467_REG_CHG_CTRL2, 7, 7),
2086f7f70e3SChiaEn Wu 	[F_TE]			= REG_FIELD(RT9467_REG_CHG_CTRL2, 4, 4),
2096f7f70e3SChiaEn Wu 	[F_IINLMTSEL]		= REG_FIELD(RT9467_REG_CHG_CTRL2, 2, 3),
2106f7f70e3SChiaEn Wu 	[F_CFO_EN]		= REG_FIELD(RT9467_REG_CHG_CTRL2, 1, 1),
2116f7f70e3SChiaEn Wu 	[F_CHG_EN]		= REG_FIELD(RT9467_REG_CHG_CTRL2, 0, 0),
2126f7f70e3SChiaEn Wu 	[F_IAICR]		= REG_FIELD(RT9467_REG_CHG_CTRL3, 2, 7),
2136f7f70e3SChiaEn Wu 	[F_ILIM_EN]		= REG_FIELD(RT9467_REG_CHG_CTRL3, 0, 0),
2146f7f70e3SChiaEn Wu 	[F_VOREG]		= REG_FIELD(RT9467_REG_CHG_CTRL4, 1, 7),
2156f7f70e3SChiaEn Wu 	[F_VMIVR]		= REG_FIELD(RT9467_REG_CHG_CTRL6, 1, 7),
2166f7f70e3SChiaEn Wu 	[F_ICHG]		= REG_FIELD(RT9467_REG_CHG_CTRL7, 2, 7),
2176f7f70e3SChiaEn Wu 	[F_IPREC]		= REG_FIELD(RT9467_REG_CHG_CTRL8, 0, 3),
2186f7f70e3SChiaEn Wu 	[F_IEOC]		= REG_FIELD(RT9467_REG_CHG_CTRL9, 4, 7),
2196f7f70e3SChiaEn Wu 	[F_WT_FC]		= REG_FIELD(RT9467_REG_CHG_CTRL12, 5, 7),
2206f7f70e3SChiaEn Wu 	[F_OCP]			= REG_FIELD(RT9467_REG_CHG_CTRL13, 2, 2),
2216f7f70e3SChiaEn Wu 	[F_AICL_MEAS]		= REG_FIELD(RT9467_REG_CHG_CTRL14, 7, 7),
2226f7f70e3SChiaEn Wu 	[F_AICL_VTH]		= REG_FIELD(RT9467_REG_CHG_CTRL14, 0, 2),
2236f7f70e3SChiaEn Wu 	[F_USBCHGEN]		= REG_FIELD(RT9467_REG_CHG_DPDM1, 7, 7),
2246f7f70e3SChiaEn Wu 	[F_USB_STATUS]		= REG_FIELD(RT9467_REG_CHG_DPDM2, 0, 2),
2256f7f70e3SChiaEn Wu 	[F_VENDOR]		= REG_FIELD(RT9467_REG_DEVICE_ID, 4, 7),
2266f7f70e3SChiaEn Wu 	[F_CHG_STAT]		= REG_FIELD(RT9467_REG_CHG_STAT, 6, 7),
2276f7f70e3SChiaEn Wu 	[F_PWR_RDY]		= REG_FIELD(RT9467_REG_CHG_STATC, 7, 7),
2286f7f70e3SChiaEn Wu 	[F_CHG_MIVR]		= REG_FIELD(RT9467_REG_CHG_STATC, 6, 6),
2296f7f70e3SChiaEn Wu };
2306f7f70e3SChiaEn Wu 
2316f7f70e3SChiaEn Wu enum {
2326f7f70e3SChiaEn Wu 	RT9467_STAT_READY = 0,
2336f7f70e3SChiaEn Wu 	RT9467_STAT_PROGRESS,
2346f7f70e3SChiaEn Wu 	RT9467_STAT_CHARGE_DONE,
2356f7f70e3SChiaEn Wu 	RT9467_STAT_FAULT
2366f7f70e3SChiaEn Wu };
2376f7f70e3SChiaEn Wu 
2386f7f70e3SChiaEn Wu enum rt9467_adc_chan {
2396f7f70e3SChiaEn Wu 	RT9467_ADC_VBUS_DIV5 = 0,
2406f7f70e3SChiaEn Wu 	RT9467_ADC_VBUS_DIV2,
2416f7f70e3SChiaEn Wu 	RT9467_ADC_VSYS,
2426f7f70e3SChiaEn Wu 	RT9467_ADC_VBAT,
2436f7f70e3SChiaEn Wu 	RT9467_ADC_TS_BAT,
2446f7f70e3SChiaEn Wu 	RT9467_ADC_IBUS,
2456f7f70e3SChiaEn Wu 	RT9467_ADC_IBAT,
2466f7f70e3SChiaEn Wu 	RT9467_ADC_REGN,
2476f7f70e3SChiaEn Wu 	RT9467_ADC_TEMP_JC
2486f7f70e3SChiaEn Wu };
2496f7f70e3SChiaEn Wu 
2506f7f70e3SChiaEn Wu enum rt9467_chg_type {
2516f7f70e3SChiaEn Wu 	RT9467_CHG_TYPE_NOVBUS = 0,
2526f7f70e3SChiaEn Wu 	RT9467_CHG_TYPE_UNDER_GOING,
2536f7f70e3SChiaEn Wu 	RT9467_CHG_TYPE_SDP,
2546f7f70e3SChiaEn Wu 	RT9467_CHG_TYPE_SDPNSTD,
2556f7f70e3SChiaEn Wu 	RT9467_CHG_TYPE_DCP,
2566f7f70e3SChiaEn Wu 	RT9467_CHG_TYPE_CDP,
2576f7f70e3SChiaEn Wu 	RT9467_CHG_TYPE_MAX
2586f7f70e3SChiaEn Wu };
2596f7f70e3SChiaEn Wu 
2606f7f70e3SChiaEn Wu enum rt9467_iin_limit_sel {
2616f7f70e3SChiaEn Wu 	RT9467_IINLMTSEL_3_2A = 0,
2626f7f70e3SChiaEn Wu 	RT9467_IINLMTSEL_CHG_TYP,
2636f7f70e3SChiaEn Wu 	RT9467_IINLMTSEL_AICR,
2646f7f70e3SChiaEn Wu 	RT9467_IINLMTSEL_LOWER_LEVEL, /* lower of above three */
2656f7f70e3SChiaEn Wu };
2666f7f70e3SChiaEn Wu 
2676f7f70e3SChiaEn Wu struct rt9467_chg_data {
2686f7f70e3SChiaEn Wu 	struct device *dev;
2696f7f70e3SChiaEn Wu 	struct regmap *regmap;
2706f7f70e3SChiaEn Wu 	struct regmap_field *rm_field[F_MAX_FIELDS];
2716f7f70e3SChiaEn Wu 	struct regmap_irq_chip_data *irq_chip_data;
2726f7f70e3SChiaEn Wu 	struct power_supply *psy;
2736f7f70e3SChiaEn Wu 	struct mutex adc_lock;
2746f7f70e3SChiaEn Wu 	struct mutex attach_lock;
2756f7f70e3SChiaEn Wu 	struct mutex ichg_ieoc_lock;
2766f7f70e3SChiaEn Wu 	struct regulator_dev *rdev;
2776f7f70e3SChiaEn Wu 	struct completion aicl_done;
2786f7f70e3SChiaEn Wu 	enum power_supply_usb_type psy_usb_type;
2796f7f70e3SChiaEn Wu 	unsigned int old_stat;
2806f7f70e3SChiaEn Wu 	unsigned int vid;
2816f7f70e3SChiaEn Wu 	int ichg_ua;
2826f7f70e3SChiaEn Wu 	int ieoc_ua;
2836f7f70e3SChiaEn Wu };
2846f7f70e3SChiaEn Wu 
rt9467_otg_of_parse_cb(struct device_node * of,const struct regulator_desc * desc,struct regulator_config * cfg)2856f7f70e3SChiaEn Wu static int rt9467_otg_of_parse_cb(struct device_node *of,
2866f7f70e3SChiaEn Wu 				  const struct regulator_desc *desc,
2876f7f70e3SChiaEn Wu 				  struct regulator_config *cfg)
2886f7f70e3SChiaEn Wu {
2896f7f70e3SChiaEn Wu 	struct rt9467_chg_data *data = cfg->driver_data;
2906f7f70e3SChiaEn Wu 
2916f7f70e3SChiaEn Wu 	cfg->ena_gpiod = fwnode_gpiod_get_index(of_fwnode_handle(of),
2926f7f70e3SChiaEn Wu 						"enable", 0, GPIOD_OUT_LOW |
2936f7f70e3SChiaEn Wu 						GPIOD_FLAGS_BIT_NONEXCLUSIVE,
2946f7f70e3SChiaEn Wu 						desc->name);
2956f7f70e3SChiaEn Wu 	if (IS_ERR(cfg->ena_gpiod)) {
2966f7f70e3SChiaEn Wu 		cfg->ena_gpiod = NULL;
2976f7f70e3SChiaEn Wu 		return 0;
2986f7f70e3SChiaEn Wu 	}
2996f7f70e3SChiaEn Wu 
3006f7f70e3SChiaEn Wu 	return regmap_field_write(data->rm_field[F_OTG_PIN_EN], 1);
3016f7f70e3SChiaEn Wu }
3026f7f70e3SChiaEn Wu 
3036f7f70e3SChiaEn Wu static const struct regulator_ops rt9467_otg_regulator_ops = {
3046f7f70e3SChiaEn Wu 	.enable = regulator_enable_regmap,
3056f7f70e3SChiaEn Wu 	.disable = regulator_disable_regmap,
3066f7f70e3SChiaEn Wu 	.is_enabled = regulator_is_enabled_regmap,
3076f7f70e3SChiaEn Wu 	.list_voltage = regulator_list_voltage_linear,
3086f7f70e3SChiaEn Wu 	.set_voltage_sel = regulator_set_voltage_sel_regmap,
3096f7f70e3SChiaEn Wu 	.get_voltage_sel = regulator_get_voltage_sel_regmap,
3106f7f70e3SChiaEn Wu 	.set_current_limit = regulator_set_current_limit_regmap,
3116f7f70e3SChiaEn Wu 	.get_current_limit = regulator_get_current_limit_regmap,
3126f7f70e3SChiaEn Wu };
3136f7f70e3SChiaEn Wu 
3146f7f70e3SChiaEn Wu static const u32 rt9467_otg_microamp[] = {
3156f7f70e3SChiaEn Wu 	500000, 700000, 1100000, 1300000, 1800000, 2100000, 2400000, 3000000
3166f7f70e3SChiaEn Wu };
3176f7f70e3SChiaEn Wu 
3186f7f70e3SChiaEn Wu static const struct regulator_desc rt9467_otg_desc = {
3196f7f70e3SChiaEn Wu 	.name = "rt9476-usb-otg-vbus",
3206f7f70e3SChiaEn Wu 	.of_match = "usb-otg-vbus-regulator",
3216f7f70e3SChiaEn Wu 	.of_parse_cb = rt9467_otg_of_parse_cb,
3226f7f70e3SChiaEn Wu 	.type = REGULATOR_VOLTAGE,
3236f7f70e3SChiaEn Wu 	.owner = THIS_MODULE,
3246f7f70e3SChiaEn Wu 	.min_uV = RT9467_OTG_MIN_uV,
3256f7f70e3SChiaEn Wu 	.uV_step = RT9467_OTG_STEP_uV,
3266f7f70e3SChiaEn Wu 	.n_voltages = RT9467_NUM_VOTG,
3276f7f70e3SChiaEn Wu 	.curr_table = rt9467_otg_microamp,
3286f7f70e3SChiaEn Wu 	.n_current_limits = ARRAY_SIZE(rt9467_otg_microamp),
3296f7f70e3SChiaEn Wu 	.csel_reg = RT9467_REG_CHG_CTRL10,
3306f7f70e3SChiaEn Wu 	.csel_mask = RT9467_MASK_OTG_CSEL,
3316f7f70e3SChiaEn Wu 	.vsel_reg = RT9467_REG_CHG_CTRL5,
3326f7f70e3SChiaEn Wu 	.vsel_mask = RT9467_MASK_OTG_VSEL,
3336f7f70e3SChiaEn Wu 	.enable_reg = RT9467_REG_CHG_CTRL1,
3346f7f70e3SChiaEn Wu 	.enable_mask = RT9467_MASK_OTG_EN,
3356f7f70e3SChiaEn Wu 	.ops = &rt9467_otg_regulator_ops,
3366f7f70e3SChiaEn Wu };
3376f7f70e3SChiaEn Wu 
rt9467_register_otg_regulator(struct rt9467_chg_data * data)3386f7f70e3SChiaEn Wu static int rt9467_register_otg_regulator(struct rt9467_chg_data *data)
3396f7f70e3SChiaEn Wu {
3406f7f70e3SChiaEn Wu 	struct regulator_config cfg = {
3416f7f70e3SChiaEn Wu 		.dev = data->dev,
3426f7f70e3SChiaEn Wu 		.regmap = data->regmap,
3436f7f70e3SChiaEn Wu 		.driver_data = data,
3446f7f70e3SChiaEn Wu 	};
3456f7f70e3SChiaEn Wu 
3466f7f70e3SChiaEn Wu 	data->rdev = devm_regulator_register(data->dev, &rt9467_otg_desc, &cfg);
3476f7f70e3SChiaEn Wu 	return PTR_ERR_OR_ZERO(data->rdev);
3486f7f70e3SChiaEn Wu }
3496f7f70e3SChiaEn Wu 
rt9467_get_value_from_ranges(struct rt9467_chg_data * data,enum rt9467_fields field,enum rt9467_ranges rsel,int * value)3506f7f70e3SChiaEn Wu static int rt9467_get_value_from_ranges(struct rt9467_chg_data *data,
3516f7f70e3SChiaEn Wu 					enum rt9467_fields field,
3526f7f70e3SChiaEn Wu 					enum rt9467_ranges rsel,
3536f7f70e3SChiaEn Wu 					int *value)
3546f7f70e3SChiaEn Wu {
3556f7f70e3SChiaEn Wu 	const struct linear_range *range = rt9467_ranges + rsel;
3566f7f70e3SChiaEn Wu 	unsigned int sel;
3576f7f70e3SChiaEn Wu 	int ret;
3586f7f70e3SChiaEn Wu 
3596f7f70e3SChiaEn Wu 	ret = regmap_field_read(data->rm_field[field], &sel);
3606f7f70e3SChiaEn Wu 	if (ret)
3616f7f70e3SChiaEn Wu 		return ret;
3626f7f70e3SChiaEn Wu 
3636f7f70e3SChiaEn Wu 	return linear_range_get_value(range, sel, value);
3646f7f70e3SChiaEn Wu }
3656f7f70e3SChiaEn Wu 
rt9467_set_value_from_ranges(struct rt9467_chg_data * data,enum rt9467_fields field,enum rt9467_ranges rsel,int value)3666f7f70e3SChiaEn Wu static int rt9467_set_value_from_ranges(struct rt9467_chg_data *data,
3676f7f70e3SChiaEn Wu 					enum rt9467_fields field,
3686f7f70e3SChiaEn Wu 					enum rt9467_ranges rsel,
3696f7f70e3SChiaEn Wu 					int value)
3706f7f70e3SChiaEn Wu {
3716f7f70e3SChiaEn Wu 	const struct linear_range *range = rt9467_ranges + rsel;
3726f7f70e3SChiaEn Wu 	unsigned int sel;
3736f7f70e3SChiaEn Wu 	bool found;
3746f7f70e3SChiaEn Wu 	int ret;
3756f7f70e3SChiaEn Wu 
3766f7f70e3SChiaEn Wu 	if (rsel == RT9467_RANGE_VMIVR) {
3776f7f70e3SChiaEn Wu 		ret = linear_range_get_selector_high(range, value, &sel, &found);
3786f7f70e3SChiaEn Wu 		if (ret)
3796f7f70e3SChiaEn Wu 			value = range->max_sel;
3806f7f70e3SChiaEn Wu 	} else {
3816f7f70e3SChiaEn Wu 		linear_range_get_selector_within(range, value, &sel);
3826f7f70e3SChiaEn Wu 	}
3836f7f70e3SChiaEn Wu 
3846f7f70e3SChiaEn Wu 	return regmap_field_write(data->rm_field[field], sel);
3856f7f70e3SChiaEn Wu }
3866f7f70e3SChiaEn Wu 
rt9467_get_adc_sel(enum rt9467_adc_chan chan,int * sel)3876f7f70e3SChiaEn Wu static int rt9467_get_adc_sel(enum rt9467_adc_chan chan, int *sel)
3886f7f70e3SChiaEn Wu {
3896f7f70e3SChiaEn Wu 	switch (chan) {
3906f7f70e3SChiaEn Wu 	case RT9467_ADC_VBUS_DIV5:
3916f7f70e3SChiaEn Wu 	case RT9467_ADC_VBUS_DIV2:
3926f7f70e3SChiaEn Wu 	case RT9467_ADC_VSYS:
3936f7f70e3SChiaEn Wu 	case RT9467_ADC_VBAT:
3946f7f70e3SChiaEn Wu 		*sel = chan + 1;
3956f7f70e3SChiaEn Wu 		return 0;
3966f7f70e3SChiaEn Wu 	case RT9467_ADC_TS_BAT:
3976f7f70e3SChiaEn Wu 		*sel = chan + 2;
3986f7f70e3SChiaEn Wu 		return 0;
3996f7f70e3SChiaEn Wu 	case RT9467_ADC_IBUS:
4006f7f70e3SChiaEn Wu 	case RT9467_ADC_IBAT:
4016f7f70e3SChiaEn Wu 		*sel = chan + 3;
4026f7f70e3SChiaEn Wu 		return 0;
4036f7f70e3SChiaEn Wu 	case RT9467_ADC_REGN:
4046f7f70e3SChiaEn Wu 	case RT9467_ADC_TEMP_JC:
4056f7f70e3SChiaEn Wu 		*sel = chan + 4;
4066f7f70e3SChiaEn Wu 		return 0;
4076f7f70e3SChiaEn Wu 	default:
4086f7f70e3SChiaEn Wu 		return -EINVAL;
4096f7f70e3SChiaEn Wu 	}
4106f7f70e3SChiaEn Wu }
4116f7f70e3SChiaEn Wu 
rt9467_get_adc_raw_data(struct rt9467_chg_data * data,enum rt9467_adc_chan chan,int * val)4126f7f70e3SChiaEn Wu static int rt9467_get_adc_raw_data(struct rt9467_chg_data *data,
4136f7f70e3SChiaEn Wu 				   enum rt9467_adc_chan chan, int *val)
4146f7f70e3SChiaEn Wu {
4156f7f70e3SChiaEn Wu 	unsigned int adc_stat, reg_val, adc_sel;
4166f7f70e3SChiaEn Wu 	__be16 chan_raw_data;
4176f7f70e3SChiaEn Wu 	int ret;
4186f7f70e3SChiaEn Wu 
4196f7f70e3SChiaEn Wu 	mutex_lock(&data->adc_lock);
4206f7f70e3SChiaEn Wu 
4216f7f70e3SChiaEn Wu 	ret = rt9467_get_adc_sel(chan, &adc_sel);
4226f7f70e3SChiaEn Wu 	if (ret)
4236f7f70e3SChiaEn Wu 		goto adc_unlock;
4246f7f70e3SChiaEn Wu 
4256f7f70e3SChiaEn Wu 	ret = regmap_write(data->regmap, RT9467_REG_CHG_ADC, 0);
4266f7f70e3SChiaEn Wu 	if (ret) {
4276f7f70e3SChiaEn Wu 		dev_err(data->dev, "Failed to clear ADC enable\n");
4286f7f70e3SChiaEn Wu 		goto adc_unlock;
4296f7f70e3SChiaEn Wu 	}
4306f7f70e3SChiaEn Wu 
4316f7f70e3SChiaEn Wu 	reg_val = RT9467_MASK_ADC_START | FIELD_PREP(RT9467_MASK_ADC_IN_SEL, adc_sel);
4326f7f70e3SChiaEn Wu 	ret = regmap_write(data->regmap, RT9467_REG_CHG_ADC, reg_val);
4336f7f70e3SChiaEn Wu 	if (ret)
4346f7f70e3SChiaEn Wu 		goto adc_unlock;
4356f7f70e3SChiaEn Wu 
4366f7f70e3SChiaEn Wu 	/* Minimum wait time for one channel processing */
4376f7f70e3SChiaEn Wu 	msleep(RT9467_ADCCONV_TIME_MS);
4386f7f70e3SChiaEn Wu 
4396f7f70e3SChiaEn Wu 	ret = regmap_read_poll_timeout(data->regmap, RT9467_REG_CHG_ADC,
4406f7f70e3SChiaEn Wu 				       adc_stat,
4416f7f70e3SChiaEn Wu 				       !(adc_stat & RT9467_MASK_ADC_START),
4426f7f70e3SChiaEn Wu 				       MILLI, RT9467_ADCCONV_TIME_MS * MILLI);
4436f7f70e3SChiaEn Wu 	if (ret) {
4446f7f70e3SChiaEn Wu 		dev_err(data->dev, "Failed to wait ADC conversion, chan = %d\n", chan);
4456f7f70e3SChiaEn Wu 		goto adc_unlock;
4466f7f70e3SChiaEn Wu 	}
4476f7f70e3SChiaEn Wu 
4486f7f70e3SChiaEn Wu 	ret = regmap_raw_read(data->regmap, RT9467_REG_ADC_DATA_H,
4496f7f70e3SChiaEn Wu 			      &chan_raw_data, sizeof(chan_raw_data));
4506f7f70e3SChiaEn Wu 	if (ret)
4516f7f70e3SChiaEn Wu 		goto adc_unlock;
4526f7f70e3SChiaEn Wu 
4536f7f70e3SChiaEn Wu 	*val = be16_to_cpu(chan_raw_data);
4546f7f70e3SChiaEn Wu 
4556f7f70e3SChiaEn Wu adc_unlock:
4566f7f70e3SChiaEn Wu 	mutex_unlock(&data->adc_lock);
4576f7f70e3SChiaEn Wu 	return ret;
4586f7f70e3SChiaEn Wu }
4596f7f70e3SChiaEn Wu 
rt9467_get_adc(struct rt9467_chg_data * data,enum rt9467_adc_chan chan,int * val)4606f7f70e3SChiaEn Wu static int rt9467_get_adc(struct rt9467_chg_data *data,
4616f7f70e3SChiaEn Wu 			  enum rt9467_adc_chan chan, int *val)
4626f7f70e3SChiaEn Wu {
4636f7f70e3SChiaEn Wu 	unsigned int aicr_ua, ichg_ua;
4646f7f70e3SChiaEn Wu 	int ret;
4656f7f70e3SChiaEn Wu 
4666f7f70e3SChiaEn Wu 	ret = rt9467_get_adc_raw_data(data, chan, val);
4676f7f70e3SChiaEn Wu 	if (ret)
4686f7f70e3SChiaEn Wu 		return ret;
4696f7f70e3SChiaEn Wu 
4706f7f70e3SChiaEn Wu 	switch (chan) {
4716f7f70e3SChiaEn Wu 	case RT9467_ADC_VBUS_DIV5:
4726f7f70e3SChiaEn Wu 		*val *= 25000;
4736f7f70e3SChiaEn Wu 		return 0;
4746f7f70e3SChiaEn Wu 	case RT9467_ADC_VBUS_DIV2:
4756f7f70e3SChiaEn Wu 		*val *= 10000;
4766f7f70e3SChiaEn Wu 		return 0;
4776f7f70e3SChiaEn Wu 	case RT9467_ADC_VBAT:
4786f7f70e3SChiaEn Wu 	case RT9467_ADC_VSYS:
4796f7f70e3SChiaEn Wu 	case RT9467_ADC_REGN:
4806f7f70e3SChiaEn Wu 		*val *= 5000;
4816f7f70e3SChiaEn Wu 		return 0;
4826f7f70e3SChiaEn Wu 	case RT9467_ADC_TS_BAT:
4836f7f70e3SChiaEn Wu 		*val /= 400;
4846f7f70e3SChiaEn Wu 		return 0;
4856f7f70e3SChiaEn Wu 	case RT9467_ADC_IBUS:
4866f7f70e3SChiaEn Wu 		/* UUG MOS turn-on ratio will affect the IBUS adc scale */
4876f7f70e3SChiaEn Wu 		ret = rt9467_get_value_from_ranges(data, F_IAICR,
4886f7f70e3SChiaEn Wu 						   RT9467_RANGE_IAICR, &aicr_ua);
4896f7f70e3SChiaEn Wu 		if (ret)
4906f7f70e3SChiaEn Wu 			return ret;
4916f7f70e3SChiaEn Wu 
4926f7f70e3SChiaEn Wu 		*val *= aicr_ua < 400000 ? 29480 : 50000;
4936f7f70e3SChiaEn Wu 		return 0;
4946f7f70e3SChiaEn Wu 	case RT9467_ADC_IBAT:
4956f7f70e3SChiaEn Wu 		/* PP MOS turn-on ratio will affect the ICHG adc scale */
4966f7f70e3SChiaEn Wu 		ret = rt9467_get_value_from_ranges(data, F_ICHG,
4976f7f70e3SChiaEn Wu 						   RT9467_RANGE_ICHG, &ichg_ua);
4986f7f70e3SChiaEn Wu 		if (ret)
4996f7f70e3SChiaEn Wu 			return ret;
5006f7f70e3SChiaEn Wu 
5016f7f70e3SChiaEn Wu 		*val *= ichg_ua <= 400000 ? 28500 :
5026f7f70e3SChiaEn Wu 			ichg_ua <= 800000 ? 31500 : 500000;
5036f7f70e3SChiaEn Wu 		return 0;
5046f7f70e3SChiaEn Wu 	case RT9467_ADC_TEMP_JC:
5056f7f70e3SChiaEn Wu 		*val = ((*val * 2) - 40) * 10;
5066f7f70e3SChiaEn Wu 		return 0;
5076f7f70e3SChiaEn Wu 	default:
5086f7f70e3SChiaEn Wu 		return -EINVAL;
5096f7f70e3SChiaEn Wu 	}
5106f7f70e3SChiaEn Wu }
5116f7f70e3SChiaEn Wu 
rt9467_psy_get_status(struct rt9467_chg_data * data,int * state)5126f7f70e3SChiaEn Wu static int rt9467_psy_get_status(struct rt9467_chg_data *data, int *state)
5136f7f70e3SChiaEn Wu {
5146f7f70e3SChiaEn Wu 	unsigned int status;
5156f7f70e3SChiaEn Wu 	int ret;
5166f7f70e3SChiaEn Wu 
5176f7f70e3SChiaEn Wu 	ret = regmap_field_read(data->rm_field[F_CHG_STAT], &status);
5186f7f70e3SChiaEn Wu 	if (ret)
5196f7f70e3SChiaEn Wu 		return ret;
5206f7f70e3SChiaEn Wu 
5216f7f70e3SChiaEn Wu 	switch (status) {
5226f7f70e3SChiaEn Wu 	case RT9467_STAT_READY:
5236f7f70e3SChiaEn Wu 		*state = POWER_SUPPLY_STATUS_NOT_CHARGING;
5246f7f70e3SChiaEn Wu 		return 0;
5256f7f70e3SChiaEn Wu 	case RT9467_STAT_PROGRESS:
5266f7f70e3SChiaEn Wu 		*state = POWER_SUPPLY_STATUS_CHARGING;
5276f7f70e3SChiaEn Wu 		return 0;
5286f7f70e3SChiaEn Wu 	case RT9467_STAT_CHARGE_DONE:
5296f7f70e3SChiaEn Wu 		*state = POWER_SUPPLY_STATUS_FULL;
5306f7f70e3SChiaEn Wu 		return 0;
5316f7f70e3SChiaEn Wu 	default:
5326f7f70e3SChiaEn Wu 		*state = POWER_SUPPLY_STATUS_UNKNOWN;
5336f7f70e3SChiaEn Wu 		return 0;
5346f7f70e3SChiaEn Wu 	}
5356f7f70e3SChiaEn Wu }
5366f7f70e3SChiaEn Wu 
rt9467_psy_set_ichg(struct rt9467_chg_data * data,int microamp)5376f7f70e3SChiaEn Wu static int rt9467_psy_set_ichg(struct rt9467_chg_data *data, int microamp)
5386f7f70e3SChiaEn Wu {
5396f7f70e3SChiaEn Wu 	int ret;
5406f7f70e3SChiaEn Wu 
5416f7f70e3SChiaEn Wu 	mutex_lock(&data->ichg_ieoc_lock);
5426f7f70e3SChiaEn Wu 
5436f7f70e3SChiaEn Wu 	if (microamp < 500000) {
5446f7f70e3SChiaEn Wu 		dev_err(data->dev, "Minimum value must be 500mA\n");
5456f7f70e3SChiaEn Wu 		microamp = 500000;
5466f7f70e3SChiaEn Wu 	}
5476f7f70e3SChiaEn Wu 
5486f7f70e3SChiaEn Wu 	ret = rt9467_set_value_from_ranges(data, F_ICHG, RT9467_RANGE_ICHG, microamp);
5496f7f70e3SChiaEn Wu 	if (ret)
5506f7f70e3SChiaEn Wu 		goto out;
5516f7f70e3SChiaEn Wu 
5526f7f70e3SChiaEn Wu 	ret = rt9467_get_value_from_ranges(data, F_ICHG, RT9467_RANGE_ICHG,
5536f7f70e3SChiaEn Wu 					   &data->ichg_ua);
5546f7f70e3SChiaEn Wu 	if (ret)
5556f7f70e3SChiaEn Wu 		goto out;
5566f7f70e3SChiaEn Wu 
5576f7f70e3SChiaEn Wu out:
5586f7f70e3SChiaEn Wu 	mutex_unlock(&data->ichg_ieoc_lock);
5596f7f70e3SChiaEn Wu 	return ret;
5606f7f70e3SChiaEn Wu }
5616f7f70e3SChiaEn Wu 
rt9467_run_aicl(struct rt9467_chg_data * data)5626f7f70e3SChiaEn Wu static int rt9467_run_aicl(struct rt9467_chg_data *data)
5636f7f70e3SChiaEn Wu {
5646f7f70e3SChiaEn Wu 	unsigned int statc, aicl_vth;
5656f7f70e3SChiaEn Wu 	int mivr_vth, aicr_get;
5666f7f70e3SChiaEn Wu 	int ret = 0;
5676f7f70e3SChiaEn Wu 
5686f7f70e3SChiaEn Wu 
5696f7f70e3SChiaEn Wu 	ret = regmap_read(data->regmap, RT9467_REG_CHG_STATC, &statc);
5706f7f70e3SChiaEn Wu 	if (ret) {
5716f7f70e3SChiaEn Wu 		dev_err(data->dev, "Failed to read status\n");
5726f7f70e3SChiaEn Wu 		return ret;
5736f7f70e3SChiaEn Wu 	}
5746f7f70e3SChiaEn Wu 
5756f7f70e3SChiaEn Wu 	if (!(statc & RT9467_MASK_PWR_RDY) || !(statc & RT9467_MASK_MIVR_STAT)) {
5766f7f70e3SChiaEn Wu 		dev_info(data->dev, "Condition not matched %d\n", statc);
5776f7f70e3SChiaEn Wu 		return 0;
5786f7f70e3SChiaEn Wu 	}
5796f7f70e3SChiaEn Wu 
5806f7f70e3SChiaEn Wu 	ret = rt9467_get_value_from_ranges(data, F_VMIVR, RT9467_RANGE_VMIVR,
5816f7f70e3SChiaEn Wu 					   &mivr_vth);
5826f7f70e3SChiaEn Wu 	if (ret) {
5836f7f70e3SChiaEn Wu 		dev_err(data->dev, "Failed to get mivr\n");
5846f7f70e3SChiaEn Wu 		return ret;
5856f7f70e3SChiaEn Wu 	}
5866f7f70e3SChiaEn Wu 
5876f7f70e3SChiaEn Wu 	/* AICL_VTH = MIVR_VTH + 200mV */
5886f7f70e3SChiaEn Wu 	aicl_vth = mivr_vth + RT9467_AICLVTH_GAP_uV;
5896f7f70e3SChiaEn Wu 	ret = rt9467_set_value_from_ranges(data, F_AICL_VTH,
5906f7f70e3SChiaEn Wu 					   RT9467_RANGE_AICL_VTH, aicl_vth);
5916f7f70e3SChiaEn Wu 
5926f7f70e3SChiaEn Wu 	/* Trigger AICL function */
5936f7f70e3SChiaEn Wu 	ret = regmap_field_write(data->rm_field[F_AICL_MEAS], 1);
5946f7f70e3SChiaEn Wu 	if (ret) {
5956f7f70e3SChiaEn Wu 		dev_err(data->dev, "Failed to set aicl measurement\n");
5966f7f70e3SChiaEn Wu 		return ret;
5976f7f70e3SChiaEn Wu 	}
5986f7f70e3SChiaEn Wu 
5996f7f70e3SChiaEn Wu 	reinit_completion(&data->aicl_done);
6006f7f70e3SChiaEn Wu 	ret = wait_for_completion_timeout(&data->aicl_done, msecs_to_jiffies(3500));
601*cba32040SChristophe JAILLET 	if (ret == 0)
602*cba32040SChristophe JAILLET 		return -ETIMEDOUT;
6036f7f70e3SChiaEn Wu 
6046f7f70e3SChiaEn Wu 	ret = rt9467_get_value_from_ranges(data, F_IAICR, RT9467_RANGE_IAICR, &aicr_get);
6056f7f70e3SChiaEn Wu 	if (ret) {
6066f7f70e3SChiaEn Wu 		dev_err(data->dev, "Failed to get aicr\n");
6076f7f70e3SChiaEn Wu 		return ret;
6086f7f70e3SChiaEn Wu 	}
6096f7f70e3SChiaEn Wu 
6106f7f70e3SChiaEn Wu 	dev_info(data->dev, "aicr get = %d uA\n", aicr_get);
6116f7f70e3SChiaEn Wu 	return 0;
6126f7f70e3SChiaEn Wu }
6136f7f70e3SChiaEn Wu 
rt9467_psy_set_ieoc(struct rt9467_chg_data * data,int microamp)6146f7f70e3SChiaEn Wu static int rt9467_psy_set_ieoc(struct rt9467_chg_data *data, int microamp)
6156f7f70e3SChiaEn Wu {
6166f7f70e3SChiaEn Wu 	int ret;
6176f7f70e3SChiaEn Wu 
6186f7f70e3SChiaEn Wu 	mutex_lock(&data->ichg_ieoc_lock);
6196f7f70e3SChiaEn Wu 
6206f7f70e3SChiaEn Wu 	ret = rt9467_set_value_from_ranges(data, F_IEOC, RT9467_RANGE_IEOC, microamp);
6216f7f70e3SChiaEn Wu 	if (ret)
6226f7f70e3SChiaEn Wu 		goto out;
6236f7f70e3SChiaEn Wu 
6246f7f70e3SChiaEn Wu 	ret = rt9467_get_value_from_ranges(data, F_IEOC, RT9467_RANGE_IEOC, &data->ieoc_ua);
6256f7f70e3SChiaEn Wu 	if (ret)
6266f7f70e3SChiaEn Wu 		goto out;
6276f7f70e3SChiaEn Wu 
6286f7f70e3SChiaEn Wu out:
6296f7f70e3SChiaEn Wu 	mutex_unlock(&data->ichg_ieoc_lock);
6306f7f70e3SChiaEn Wu 	return ret;
6316f7f70e3SChiaEn Wu }
6326f7f70e3SChiaEn Wu 
6336f7f70e3SChiaEn Wu static const enum power_supply_usb_type rt9467_chg_usb_types[] = {
6346f7f70e3SChiaEn Wu 	POWER_SUPPLY_USB_TYPE_UNKNOWN,
6356f7f70e3SChiaEn Wu 	POWER_SUPPLY_USB_TYPE_SDP,
6366f7f70e3SChiaEn Wu 	POWER_SUPPLY_USB_TYPE_DCP,
6376f7f70e3SChiaEn Wu 	POWER_SUPPLY_USB_TYPE_CDP,
6386f7f70e3SChiaEn Wu };
6396f7f70e3SChiaEn Wu 
6406f7f70e3SChiaEn Wu static const enum power_supply_property rt9467_chg_properties[] = {
6416f7f70e3SChiaEn Wu 	POWER_SUPPLY_PROP_STATUS,
6426f7f70e3SChiaEn Wu 	POWER_SUPPLY_PROP_ONLINE,
6436f7f70e3SChiaEn Wu 	POWER_SUPPLY_PROP_CURRENT_MAX,
6446f7f70e3SChiaEn Wu 	POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT,
6456f7f70e3SChiaEn Wu 	POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX,
6466f7f70e3SChiaEn Wu 	POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE,
6476f7f70e3SChiaEn Wu 	POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX,
6486f7f70e3SChiaEn Wu 	POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT,
6496f7f70e3SChiaEn Wu 	POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT,
6506f7f70e3SChiaEn Wu 	POWER_SUPPLY_PROP_USB_TYPE,
6516f7f70e3SChiaEn Wu 	POWER_SUPPLY_PROP_PRECHARGE_CURRENT,
6526f7f70e3SChiaEn Wu 	POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT,
6536f7f70e3SChiaEn Wu };
6546f7f70e3SChiaEn Wu 
rt9467_psy_get_property(struct power_supply * psy,enum power_supply_property psp,union power_supply_propval * val)6556f7f70e3SChiaEn Wu static int rt9467_psy_get_property(struct power_supply *psy,
6566f7f70e3SChiaEn Wu 				   enum power_supply_property psp,
6576f7f70e3SChiaEn Wu 				   union power_supply_propval *val)
6586f7f70e3SChiaEn Wu {
6596f7f70e3SChiaEn Wu 	struct rt9467_chg_data *data = power_supply_get_drvdata(psy);
6606f7f70e3SChiaEn Wu 
6616f7f70e3SChiaEn Wu 	switch (psp) {
6626f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_STATUS:
6636f7f70e3SChiaEn Wu 		return rt9467_psy_get_status(data, &val->intval);
6646f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_ONLINE:
6656f7f70e3SChiaEn Wu 		return regmap_field_read(data->rm_field[F_PWR_RDY], &val->intval);
6666f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_CURRENT_MAX:
6676f7f70e3SChiaEn Wu 		mutex_lock(&data->attach_lock);
6686f7f70e3SChiaEn Wu 		if (data->psy_usb_type == POWER_SUPPLY_USB_TYPE_UNKNOWN ||
6696f7f70e3SChiaEn Wu 		    data->psy_usb_type == POWER_SUPPLY_USB_TYPE_SDP)
6706f7f70e3SChiaEn Wu 			val->intval = 500000;
6716f7f70e3SChiaEn Wu 		else
6726f7f70e3SChiaEn Wu 			val->intval = 1500000;
6736f7f70e3SChiaEn Wu 		mutex_unlock(&data->attach_lock);
6746f7f70e3SChiaEn Wu 		return 0;
6756f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
6766f7f70e3SChiaEn Wu 		mutex_lock(&data->ichg_ieoc_lock);
6776f7f70e3SChiaEn Wu 		val->intval = data->ichg_ua;
6786f7f70e3SChiaEn Wu 		mutex_unlock(&data->ichg_ieoc_lock);
6796f7f70e3SChiaEn Wu 		return 0;
6806f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX:
6816f7f70e3SChiaEn Wu 		val->intval = RT9467_ICHG_MAX_uA;
6826f7f70e3SChiaEn Wu 		return 0;
6836f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
6846f7f70e3SChiaEn Wu 		return rt9467_get_value_from_ranges(data, F_VOREG,
6856f7f70e3SChiaEn Wu 						    RT9467_RANGE_VOREG,
6866f7f70e3SChiaEn Wu 						    &val->intval);
6876f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE_MAX:
6886f7f70e3SChiaEn Wu 		val->intval = RT9467_CV_MAX_uV;
6896f7f70e3SChiaEn Wu 		return 0;
6906f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
6916f7f70e3SChiaEn Wu 		return rt9467_get_value_from_ranges(data, F_IAICR,
6926f7f70e3SChiaEn Wu 						    RT9467_RANGE_IAICR,
6936f7f70e3SChiaEn Wu 						    &val->intval);
6946f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT:
6956f7f70e3SChiaEn Wu 		return rt9467_get_value_from_ranges(data, F_VMIVR,
6966f7f70e3SChiaEn Wu 						    RT9467_RANGE_VMIVR,
6976f7f70e3SChiaEn Wu 						    &val->intval);
6986f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_USB_TYPE:
6996f7f70e3SChiaEn Wu 		mutex_lock(&data->attach_lock);
7006f7f70e3SChiaEn Wu 		val->intval = data->psy_usb_type;
7016f7f70e3SChiaEn Wu 		mutex_unlock(&data->attach_lock);
7026f7f70e3SChiaEn Wu 		return 0;
7036f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_PRECHARGE_CURRENT:
7046f7f70e3SChiaEn Wu 		return rt9467_get_value_from_ranges(data, F_IPREC,
7056f7f70e3SChiaEn Wu 						    RT9467_RANGE_IPREC,
7066f7f70e3SChiaEn Wu 						    &val->intval);
7076f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT:
7086f7f70e3SChiaEn Wu 		mutex_lock(&data->ichg_ieoc_lock);
7096f7f70e3SChiaEn Wu 		val->intval = data->ieoc_ua;
7106f7f70e3SChiaEn Wu 		mutex_unlock(&data->ichg_ieoc_lock);
7116f7f70e3SChiaEn Wu 		return 0;
7126f7f70e3SChiaEn Wu 	default:
7136f7f70e3SChiaEn Wu 		return -ENODATA;
7146f7f70e3SChiaEn Wu 	}
7156f7f70e3SChiaEn Wu }
7166f7f70e3SChiaEn Wu 
rt9467_psy_set_property(struct power_supply * psy,enum power_supply_property psp,const union power_supply_propval * val)7176f7f70e3SChiaEn Wu static int rt9467_psy_set_property(struct power_supply *psy,
7186f7f70e3SChiaEn Wu 				   enum power_supply_property psp,
7196f7f70e3SChiaEn Wu 				   const union power_supply_propval *val)
7206f7f70e3SChiaEn Wu {
7216f7f70e3SChiaEn Wu 	struct rt9467_chg_data *data = power_supply_get_drvdata(psy);
7226f7f70e3SChiaEn Wu 
7236f7f70e3SChiaEn Wu 	switch (psp) {
7246f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_STATUS:
7256f7f70e3SChiaEn Wu 		return regmap_field_write(data->rm_field[F_CHG_EN], val->intval);
7266f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_ONLINE:
7276f7f70e3SChiaEn Wu 		return regmap_field_write(data->rm_field[F_HZ], val->intval);
7286f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
7296f7f70e3SChiaEn Wu 		return rt9467_psy_set_ichg(data, val->intval);
7306f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
7316f7f70e3SChiaEn Wu 		return rt9467_set_value_from_ranges(data, F_VOREG,
7326f7f70e3SChiaEn Wu 						    RT9467_RANGE_VOREG, val->intval);
7336f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
7346f7f70e3SChiaEn Wu 		if (val->intval == -1)
7356f7f70e3SChiaEn Wu 			return rt9467_run_aicl(data);
7366f7f70e3SChiaEn Wu 		else
7376f7f70e3SChiaEn Wu 			return rt9467_set_value_from_ranges(data, F_IAICR,
7386f7f70e3SChiaEn Wu 							    RT9467_RANGE_IAICR,
7396f7f70e3SChiaEn Wu 							    val->intval);
7406f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT:
7416f7f70e3SChiaEn Wu 		return rt9467_set_value_from_ranges(data, F_VMIVR,
7426f7f70e3SChiaEn Wu 						    RT9467_RANGE_VMIVR, val->intval);
7436f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_PRECHARGE_CURRENT:
7446f7f70e3SChiaEn Wu 		return rt9467_set_value_from_ranges(data, F_IPREC,
7456f7f70e3SChiaEn Wu 						    RT9467_RANGE_IPREC, val->intval);
7466f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT:
7476f7f70e3SChiaEn Wu 		return rt9467_psy_set_ieoc(data, val->intval);
7486f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_USB_TYPE:
7496f7f70e3SChiaEn Wu 		return regmap_field_write(data->rm_field[F_USBCHGEN], val->intval);
7506f7f70e3SChiaEn Wu 	default:
7516f7f70e3SChiaEn Wu 		return -EINVAL;
7526f7f70e3SChiaEn Wu 	}
7536f7f70e3SChiaEn Wu }
7546f7f70e3SChiaEn Wu 
rt9467_chg_prop_is_writeable(struct power_supply * psy,enum power_supply_property psp)7556f7f70e3SChiaEn Wu static int rt9467_chg_prop_is_writeable(struct power_supply *psy,
7566f7f70e3SChiaEn Wu 					enum power_supply_property psp)
7576f7f70e3SChiaEn Wu {
7586f7f70e3SChiaEn Wu 	switch (psp) {
7596f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_STATUS:
7606f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_ONLINE:
7616f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT:
7626f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_CONSTANT_CHARGE_VOLTAGE:
7636f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:
7646f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_INPUT_VOLTAGE_LIMIT:
7656f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_CHARGE_TERM_CURRENT:
7666f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_PRECHARGE_CURRENT:
7676f7f70e3SChiaEn Wu 	case POWER_SUPPLY_PROP_USB_TYPE:
7686f7f70e3SChiaEn Wu 		return 1;
7696f7f70e3SChiaEn Wu 	default:
7706f7f70e3SChiaEn Wu 		return 0;
7716f7f70e3SChiaEn Wu 	}
7726f7f70e3SChiaEn Wu }
7736f7f70e3SChiaEn Wu 
7746f7f70e3SChiaEn Wu static const struct power_supply_desc rt9467_chg_psy_desc = {
7756f7f70e3SChiaEn Wu 	.name = "rt9467-charger",
7766f7f70e3SChiaEn Wu 	.type = POWER_SUPPLY_TYPE_USB,
7776f7f70e3SChiaEn Wu 	.usb_types = rt9467_chg_usb_types,
7786f7f70e3SChiaEn Wu 	.num_usb_types = ARRAY_SIZE(rt9467_chg_usb_types),
7796f7f70e3SChiaEn Wu 	.properties = rt9467_chg_properties,
7806f7f70e3SChiaEn Wu 	.num_properties = ARRAY_SIZE(rt9467_chg_properties),
7816f7f70e3SChiaEn Wu 	.property_is_writeable = rt9467_chg_prop_is_writeable,
7826f7f70e3SChiaEn Wu 	.get_property = rt9467_psy_get_property,
7836f7f70e3SChiaEn Wu 	.set_property = rt9467_psy_set_property,
7846f7f70e3SChiaEn Wu };
7856f7f70e3SChiaEn Wu 
psy_device_to_chip(struct device * dev)7866f7f70e3SChiaEn Wu static inline struct rt9467_chg_data *psy_device_to_chip(struct device *dev)
7876f7f70e3SChiaEn Wu {
7886f7f70e3SChiaEn Wu 	return power_supply_get_drvdata(to_power_supply(dev));
7896f7f70e3SChiaEn Wu }
7906f7f70e3SChiaEn Wu 
sysoff_enable_show(struct device * dev,struct device_attribute * attr,char * buf)7916f7f70e3SChiaEn Wu static ssize_t sysoff_enable_show(struct device *dev,
7926f7f70e3SChiaEn Wu 				  struct device_attribute *attr, char *buf)
7936f7f70e3SChiaEn Wu {
7946f7f70e3SChiaEn Wu 	struct rt9467_chg_data *data = psy_device_to_chip(dev);
7956f7f70e3SChiaEn Wu 	unsigned int sysoff_enable;
7966f7f70e3SChiaEn Wu 	int ret;
7976f7f70e3SChiaEn Wu 
7986f7f70e3SChiaEn Wu 	ret = regmap_field_read(data->rm_field[F_SHIP_MODE], &sysoff_enable);
7996f7f70e3SChiaEn Wu 	if (ret)
8006f7f70e3SChiaEn Wu 		return ret;
8016f7f70e3SChiaEn Wu 
8026f7f70e3SChiaEn Wu 	return sysfs_emit(buf, "%d\n", sysoff_enable);
8036f7f70e3SChiaEn Wu }
8046f7f70e3SChiaEn Wu 
sysoff_enable_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)8056f7f70e3SChiaEn Wu static ssize_t sysoff_enable_store(struct device *dev,
8066f7f70e3SChiaEn Wu 				   struct device_attribute *attr,
8076f7f70e3SChiaEn Wu 				   const char *buf, size_t count)
8086f7f70e3SChiaEn Wu {
8096f7f70e3SChiaEn Wu 	struct rt9467_chg_data *data = psy_device_to_chip(dev);
8106f7f70e3SChiaEn Wu 	unsigned int tmp;
8116f7f70e3SChiaEn Wu 	int ret;
8126f7f70e3SChiaEn Wu 
8136f7f70e3SChiaEn Wu 	ret = kstrtouint(buf, 10, &tmp);
8146f7f70e3SChiaEn Wu 	if (ret)
8156f7f70e3SChiaEn Wu 		return ret;
8166f7f70e3SChiaEn Wu 
8176f7f70e3SChiaEn Wu 	ret = regmap_field_write(data->rm_field[F_SHIP_MODE], !!tmp);
8186f7f70e3SChiaEn Wu 	if (ret)
8196f7f70e3SChiaEn Wu 		return ret;
8206f7f70e3SChiaEn Wu 
8216f7f70e3SChiaEn Wu 	return count;
8226f7f70e3SChiaEn Wu }
8236f7f70e3SChiaEn Wu 
8246f7f70e3SChiaEn Wu static DEVICE_ATTR_RW(sysoff_enable);
8256f7f70e3SChiaEn Wu 
8266f7f70e3SChiaEn Wu static struct attribute *rt9467_sysfs_attrs[] = {
8276f7f70e3SChiaEn Wu 	&dev_attr_sysoff_enable.attr,
8286f7f70e3SChiaEn Wu 	NULL
8296f7f70e3SChiaEn Wu };
8306f7f70e3SChiaEn Wu 
8316f7f70e3SChiaEn Wu ATTRIBUTE_GROUPS(rt9467_sysfs);
8326f7f70e3SChiaEn Wu 
rt9467_register_psy(struct rt9467_chg_data * data)8336f7f70e3SChiaEn Wu static int rt9467_register_psy(struct rt9467_chg_data *data)
8346f7f70e3SChiaEn Wu {
8356f7f70e3SChiaEn Wu 	struct power_supply_config cfg = {
8366f7f70e3SChiaEn Wu 		.drv_data = data,
8376f7f70e3SChiaEn Wu 		.of_node = dev_of_node(data->dev),
8386f7f70e3SChiaEn Wu 		.attr_grp = rt9467_sysfs_groups,
8396f7f70e3SChiaEn Wu 	};
8406f7f70e3SChiaEn Wu 
8416f7f70e3SChiaEn Wu 	data->psy = devm_power_supply_register(data->dev, &rt9467_chg_psy_desc,
8426f7f70e3SChiaEn Wu 					       &cfg);
8436f7f70e3SChiaEn Wu 	return PTR_ERR_OR_ZERO(data->psy);
8446f7f70e3SChiaEn Wu }
8456f7f70e3SChiaEn Wu 
rt9467_mivr_handler(struct rt9467_chg_data * data)8466f7f70e3SChiaEn Wu static int rt9467_mivr_handler(struct rt9467_chg_data *data)
8476f7f70e3SChiaEn Wu {
8486f7f70e3SChiaEn Wu 	unsigned int mivr_act;
8496f7f70e3SChiaEn Wu 	int ret, ibus_ma;
8506f7f70e3SChiaEn Wu 
8516f7f70e3SChiaEn Wu 	/*
8526f7f70e3SChiaEn Wu 	 * back-boost workaround
8536f7f70e3SChiaEn Wu 	 * If (mivr_active & ibus < 100mA), toggle cfo bit
8546f7f70e3SChiaEn Wu 	 */
8556f7f70e3SChiaEn Wu 	ret = regmap_field_read(data->rm_field[F_CHG_MIVR], &mivr_act);
8566f7f70e3SChiaEn Wu 	if (ret) {
8576f7f70e3SChiaEn Wu 		dev_err(data->dev, "Failed to read MIVR stat\n");
8586f7f70e3SChiaEn Wu 		return ret;
8596f7f70e3SChiaEn Wu 	}
8606f7f70e3SChiaEn Wu 
8616f7f70e3SChiaEn Wu 	if (!mivr_act)
8626f7f70e3SChiaEn Wu 		return 0;
8636f7f70e3SChiaEn Wu 
8646f7f70e3SChiaEn Wu 	ret = rt9467_get_adc(data, RT9467_ADC_IBUS, &ibus_ma);
8656f7f70e3SChiaEn Wu 	if (ret) {
8666f7f70e3SChiaEn Wu 		dev_err(data->dev, "Failed to get IBUS\n");
8676f7f70e3SChiaEn Wu 		return ret;
8686f7f70e3SChiaEn Wu 	}
8696f7f70e3SChiaEn Wu 
8706f7f70e3SChiaEn Wu 	if (ibus_ma < 100000) {
8716f7f70e3SChiaEn Wu 		ret = regmap_field_write(data->rm_field[F_CFO_EN], 0);
8726f7f70e3SChiaEn Wu 		ret |= regmap_field_write(data->rm_field[F_CFO_EN], 1);
8736f7f70e3SChiaEn Wu 		if (ret)
8746f7f70e3SChiaEn Wu 			dev_err(data->dev, "Failed to toggle cfo\n");
8756f7f70e3SChiaEn Wu 	}
8766f7f70e3SChiaEn Wu 
8776f7f70e3SChiaEn Wu 	return ret;
8786f7f70e3SChiaEn Wu }
8796f7f70e3SChiaEn Wu 
rt9467_statc_handler(int irq,void * priv)8806f7f70e3SChiaEn Wu static irqreturn_t rt9467_statc_handler(int irq, void *priv)
8816f7f70e3SChiaEn Wu {
8826f7f70e3SChiaEn Wu 	struct rt9467_chg_data *data = priv;
8836f7f70e3SChiaEn Wu 	unsigned int new_stat, evts = 0;
8846f7f70e3SChiaEn Wu 	int ret;
8856f7f70e3SChiaEn Wu 
8866f7f70e3SChiaEn Wu 	ret = regmap_read(data->regmap, RT9467_REG_CHG_STATC, &new_stat);
8876f7f70e3SChiaEn Wu 	if (ret) {
8886f7f70e3SChiaEn Wu 		dev_err(data->dev, "Failed to read chg_statc\n");
8896f7f70e3SChiaEn Wu 		return IRQ_NONE;
8906f7f70e3SChiaEn Wu 	}
8916f7f70e3SChiaEn Wu 
8926f7f70e3SChiaEn Wu 	evts = data->old_stat ^ new_stat;
8936f7f70e3SChiaEn Wu 	data->old_stat = new_stat;
8946f7f70e3SChiaEn Wu 
8956f7f70e3SChiaEn Wu 	if ((evts & new_stat) & RT9467_MASK_MIVR_STAT) {
8966f7f70e3SChiaEn Wu 		ret = rt9467_mivr_handler(data);
8976f7f70e3SChiaEn Wu 		if (ret)
8986f7f70e3SChiaEn Wu 			dev_err(data->dev, "Failed to handle mivr stat\n");
8996f7f70e3SChiaEn Wu 	}
9006f7f70e3SChiaEn Wu 
9016f7f70e3SChiaEn Wu 	return IRQ_HANDLED;
9026f7f70e3SChiaEn Wu }
9036f7f70e3SChiaEn Wu 
rt9467_wdt_handler(int irq,void * priv)9046f7f70e3SChiaEn Wu static irqreturn_t rt9467_wdt_handler(int irq, void *priv)
9056f7f70e3SChiaEn Wu {
9066f7f70e3SChiaEn Wu 	struct rt9467_chg_data *data = priv;
9076f7f70e3SChiaEn Wu 	unsigned int dev_id;
9086f7f70e3SChiaEn Wu 	int ret;
9096f7f70e3SChiaEn Wu 
9106f7f70e3SChiaEn Wu 	/* Any i2c communication can kick watchdog timer */
9116f7f70e3SChiaEn Wu 	ret = regmap_read(data->regmap, RT9467_REG_DEVICE_ID, &dev_id);
9126f7f70e3SChiaEn Wu 	if (ret) {
9136f7f70e3SChiaEn Wu 		dev_err(data->dev, "Failed to kick wdt (%d)\n", ret);
9146f7f70e3SChiaEn Wu 		return IRQ_NONE;
9156f7f70e3SChiaEn Wu 	}
9166f7f70e3SChiaEn Wu 
9176f7f70e3SChiaEn Wu 	return IRQ_HANDLED;
9186f7f70e3SChiaEn Wu }
9196f7f70e3SChiaEn Wu 
rt9467_report_usb_state(struct rt9467_chg_data * data)9206f7f70e3SChiaEn Wu static int rt9467_report_usb_state(struct rt9467_chg_data *data)
9216f7f70e3SChiaEn Wu {
9226f7f70e3SChiaEn Wu 	unsigned int usb_stat, power_ready;
9236f7f70e3SChiaEn Wu 	bool psy_changed = true;
9246f7f70e3SChiaEn Wu 	int ret;
9256f7f70e3SChiaEn Wu 
9266f7f70e3SChiaEn Wu 	ret = regmap_field_read(data->rm_field[F_USB_STATUS], &usb_stat);
9276f7f70e3SChiaEn Wu 	ret |= regmap_field_read(data->rm_field[F_PWR_RDY], &power_ready);
9286f7f70e3SChiaEn Wu 	if (ret)
9296f7f70e3SChiaEn Wu 		return ret;
9306f7f70e3SChiaEn Wu 
9316f7f70e3SChiaEn Wu 	if (!power_ready)
9326f7f70e3SChiaEn Wu 		usb_stat = RT9467_CHG_TYPE_NOVBUS;
9336f7f70e3SChiaEn Wu 
9346f7f70e3SChiaEn Wu 	mutex_lock(&data->attach_lock);
9356f7f70e3SChiaEn Wu 
9366f7f70e3SChiaEn Wu 	switch (usb_stat) {
9376f7f70e3SChiaEn Wu 	case RT9467_CHG_TYPE_NOVBUS:
9386f7f70e3SChiaEn Wu 		data->psy_usb_type = POWER_SUPPLY_USB_TYPE_UNKNOWN;
9396f7f70e3SChiaEn Wu 		break;
9406f7f70e3SChiaEn Wu 	case RT9467_CHG_TYPE_SDP:
9416f7f70e3SChiaEn Wu 		data->psy_usb_type = POWER_SUPPLY_USB_TYPE_SDP;
9426f7f70e3SChiaEn Wu 		break;
9436f7f70e3SChiaEn Wu 	case RT9467_CHG_TYPE_SDPNSTD:
9446f7f70e3SChiaEn Wu 		data->psy_usb_type = POWER_SUPPLY_USB_TYPE_DCP;
9456f7f70e3SChiaEn Wu 		break;
9466f7f70e3SChiaEn Wu 	case RT9467_CHG_TYPE_DCP:
9476f7f70e3SChiaEn Wu 		data->psy_usb_type = POWER_SUPPLY_USB_TYPE_DCP;
9486f7f70e3SChiaEn Wu 		break;
9496f7f70e3SChiaEn Wu 	case RT9467_CHG_TYPE_CDP:
9506f7f70e3SChiaEn Wu 		data->psy_usb_type = POWER_SUPPLY_USB_TYPE_CDP;
9516f7f70e3SChiaEn Wu 		break;
9526f7f70e3SChiaEn Wu 	case RT9467_CHG_TYPE_UNDER_GOING:
9536f7f70e3SChiaEn Wu 	default:
9546f7f70e3SChiaEn Wu 		psy_changed = false;
9556f7f70e3SChiaEn Wu 		break;
9566f7f70e3SChiaEn Wu 	}
9576f7f70e3SChiaEn Wu 
9586f7f70e3SChiaEn Wu 	mutex_unlock(&data->attach_lock);
9596f7f70e3SChiaEn Wu 
9606f7f70e3SChiaEn Wu 	if (psy_changed)
9616f7f70e3SChiaEn Wu 		power_supply_changed(data->psy);
9626f7f70e3SChiaEn Wu 
9636f7f70e3SChiaEn Wu 	return 0;
9646f7f70e3SChiaEn Wu }
9656f7f70e3SChiaEn Wu 
rt9467_usb_state_handler(int irq,void * priv)9666f7f70e3SChiaEn Wu static irqreturn_t rt9467_usb_state_handler(int irq, void *priv)
9676f7f70e3SChiaEn Wu {
9686f7f70e3SChiaEn Wu 	struct rt9467_chg_data *data = priv;
9696f7f70e3SChiaEn Wu 	int ret;
9706f7f70e3SChiaEn Wu 
9716f7f70e3SChiaEn Wu 	ret = rt9467_report_usb_state(data);
9726f7f70e3SChiaEn Wu 	if (ret) {
973469bb609SColin Ian King 		dev_err(data->dev, "Failed to report attach type (%d)\n", ret);
9746f7f70e3SChiaEn Wu 		return IRQ_NONE;
9756f7f70e3SChiaEn Wu 	}
9766f7f70e3SChiaEn Wu 
9776f7f70e3SChiaEn Wu 	return IRQ_HANDLED;
9786f7f70e3SChiaEn Wu }
9796f7f70e3SChiaEn Wu 
rt9467_aiclmeas_handler(int irq,void * priv)9806f7f70e3SChiaEn Wu static irqreturn_t rt9467_aiclmeas_handler(int irq, void *priv)
9816f7f70e3SChiaEn Wu {
9826f7f70e3SChiaEn Wu 	struct rt9467_chg_data *data = priv;
9836f7f70e3SChiaEn Wu 
9846f7f70e3SChiaEn Wu 	complete(&data->aicl_done);
9856f7f70e3SChiaEn Wu 	return IRQ_HANDLED;
9866f7f70e3SChiaEn Wu }
9876f7f70e3SChiaEn Wu 
9886f7f70e3SChiaEn Wu #define RT9467_IRQ_DESC(_name, _handler_func, _hwirq)		\
9896f7f70e3SChiaEn Wu {								\
9906f7f70e3SChiaEn Wu 	.name = #_name,						\
9916f7f70e3SChiaEn Wu 	.handler = rt9467_##_handler_func##_handler,		\
9926f7f70e3SChiaEn Wu 	.hwirq = _hwirq,					\
9936f7f70e3SChiaEn Wu }
9946f7f70e3SChiaEn Wu 
rt9467_request_interrupt(struct rt9467_chg_data * data)9956f7f70e3SChiaEn Wu static int rt9467_request_interrupt(struct rt9467_chg_data *data)
9966f7f70e3SChiaEn Wu {
9976f7f70e3SChiaEn Wu 	struct device *dev = data->dev;
9986f7f70e3SChiaEn Wu 	static const struct {
9996f7f70e3SChiaEn Wu 		const char *name;
10006f7f70e3SChiaEn Wu 		int hwirq;
10016f7f70e3SChiaEn Wu 		irq_handler_t handler;
10026f7f70e3SChiaEn Wu 	} rt9467_exclusive_irqs[] = {
10036f7f70e3SChiaEn Wu 		RT9467_IRQ_DESC(statc, statc, RT9467_IRQ_TS_STATC),
10046f7f70e3SChiaEn Wu 		RT9467_IRQ_DESC(wdt, wdt, RT9467_IRQ_WDTMR),
10056f7f70e3SChiaEn Wu 		RT9467_IRQ_DESC(attach, usb_state, RT9467_IRQ_ATTACH),
10066f7f70e3SChiaEn Wu 		RT9467_IRQ_DESC(detach,	usb_state, RT9467_IRQ_DETACH),
10076f7f70e3SChiaEn Wu 		RT9467_IRQ_DESC(aiclmeas, aiclmeas, RT9467_IRQ_CHG_AICLM),
10086f7f70e3SChiaEn Wu 	}, rt9466_exclusive_irqs[] = {
10096f7f70e3SChiaEn Wu 		RT9467_IRQ_DESC(statc, statc, RT9467_IRQ_TS_STATC),
10106f7f70e3SChiaEn Wu 		RT9467_IRQ_DESC(wdt, wdt, RT9467_IRQ_WDTMR),
10116f7f70e3SChiaEn Wu 		RT9467_IRQ_DESC(aiclmeas, aiclmeas, RT9467_IRQ_CHG_AICLM),
10126f7f70e3SChiaEn Wu 	}, *chg_irqs;
10136f7f70e3SChiaEn Wu 	int num_chg_irqs, i, virq, ret;
10146f7f70e3SChiaEn Wu 
10156f7f70e3SChiaEn Wu 	if (data->vid == RT9466_VID) {
10166f7f70e3SChiaEn Wu 		chg_irqs = rt9466_exclusive_irqs;
10176f7f70e3SChiaEn Wu 		num_chg_irqs = ARRAY_SIZE(rt9466_exclusive_irqs);
10186f7f70e3SChiaEn Wu 	} else {
10196f7f70e3SChiaEn Wu 		chg_irqs = rt9467_exclusive_irqs;
10206f7f70e3SChiaEn Wu 		num_chg_irqs = ARRAY_SIZE(rt9467_exclusive_irqs);
10216f7f70e3SChiaEn Wu 	}
10226f7f70e3SChiaEn Wu 
10236f7f70e3SChiaEn Wu 	for (i = 0; i < num_chg_irqs; i++) {
10246f7f70e3SChiaEn Wu 		virq = regmap_irq_get_virq(data->irq_chip_data, chg_irqs[i].hwirq);
10256f7f70e3SChiaEn Wu 		if (virq <= 0)
1026bc97139fSChiaEn Wu 			return dev_err_probe(dev, -EINVAL, "Failed to get (%s) irq\n",
10276f7f70e3SChiaEn Wu 					     chg_irqs[i].name);
10286f7f70e3SChiaEn Wu 
10296f7f70e3SChiaEn Wu 		ret = devm_request_threaded_irq(dev, virq, NULL, chg_irqs[i].handler,
10306f7f70e3SChiaEn Wu 						IRQF_ONESHOT, chg_irqs[i].name, data);
10316f7f70e3SChiaEn Wu 		if (ret)
10326f7f70e3SChiaEn Wu 			return dev_err_probe(dev, ret, "Failed to request (%s) irq\n",
10336f7f70e3SChiaEn Wu 					     chg_irqs[i].name);
10346f7f70e3SChiaEn Wu 	}
10356f7f70e3SChiaEn Wu 
10366f7f70e3SChiaEn Wu 	return 0;
10376f7f70e3SChiaEn Wu }
10386f7f70e3SChiaEn Wu 
rt9467_do_charger_init(struct rt9467_chg_data * data)10396f7f70e3SChiaEn Wu static int rt9467_do_charger_init(struct rt9467_chg_data *data)
10406f7f70e3SChiaEn Wu {
10416f7f70e3SChiaEn Wu 	struct device *dev = data->dev;
10426f7f70e3SChiaEn Wu 	int ret;
10436f7f70e3SChiaEn Wu 
10446f7f70e3SChiaEn Wu 	ret = regmap_write(data->regmap, RT9467_REG_CHG_ADC, 0);
10456f7f70e3SChiaEn Wu 	if (ret)
10466f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to reset ADC\n");
10476f7f70e3SChiaEn Wu 
10486f7f70e3SChiaEn Wu 	ret = rt9467_get_value_from_ranges(data, F_ICHG, RT9467_RANGE_ICHG,
10496f7f70e3SChiaEn Wu 					   &data->ichg_ua);
10506f7f70e3SChiaEn Wu 	ret |= rt9467_get_value_from_ranges(data, F_IEOC, RT9467_RANGE_IEOC,
10516f7f70e3SChiaEn Wu 					    &data->ieoc_ua);
10526f7f70e3SChiaEn Wu 	if (ret)
10536f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to init ichg/ieoc value\n");
10546f7f70e3SChiaEn Wu 
10556f7f70e3SChiaEn Wu 	ret = regmap_update_bits(data->regmap, RT9467_REG_CHG_STATC_CTRL,
10566f7f70e3SChiaEn Wu 				 RT9467_MASK_PWR_RDY | RT9467_MASK_MIVR_STAT, 0);
10576f7f70e3SChiaEn Wu 	if (ret)
10586f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to make statc unmask\n");
10596f7f70e3SChiaEn Wu 
10606f7f70e3SChiaEn Wu 	/* Select IINLMTSEL to use AICR */
10616f7f70e3SChiaEn Wu 	ret = regmap_field_write(data->rm_field[F_IINLMTSEL],
10626f7f70e3SChiaEn Wu 				 RT9467_IINLMTSEL_AICR);
10636f7f70e3SChiaEn Wu 	if (ret)
10646f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to set iinlmtsel to AICR\n");
10656f7f70e3SChiaEn Wu 
10666f7f70e3SChiaEn Wu 	/* Wait for AICR Rampping */
10676f7f70e3SChiaEn Wu 	msleep(150);
10686f7f70e3SChiaEn Wu 
10696f7f70e3SChiaEn Wu 	/* Disable hardware ILIM */
10706f7f70e3SChiaEn Wu 	ret = regmap_field_write(data->rm_field[F_ILIM_EN], 0);
10716f7f70e3SChiaEn Wu 	if (ret)
10726f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to disable hardware ILIM\n");
10736f7f70e3SChiaEn Wu 
10746f7f70e3SChiaEn Wu 	/* Set inductor OCP to high level */
10756f7f70e3SChiaEn Wu 	ret = regmap_field_write(data->rm_field[F_OCP], 1);
10766f7f70e3SChiaEn Wu 	if (ret)
10776f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to set higher inductor OCP level\n");
10786f7f70e3SChiaEn Wu 
10796f7f70e3SChiaEn Wu 	/* Set charge termination default enable */
10806f7f70e3SChiaEn Wu 	ret = regmap_field_write(data->rm_field[F_TE], 1);
10816f7f70e3SChiaEn Wu 	if (ret)
10826f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to set TE=1\n");
10836f7f70e3SChiaEn Wu 
10846f7f70e3SChiaEn Wu 	/* Set 12hrs fast charger timer */
10856f7f70e3SChiaEn Wu 	ret = regmap_field_write(data->rm_field[F_WT_FC], 4);
10866f7f70e3SChiaEn Wu 	if (ret)
10876f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to set WT_FC\n");
10886f7f70e3SChiaEn Wu 
10896f7f70e3SChiaEn Wu 	/* Toggle BC12 function */
10906f7f70e3SChiaEn Wu 	ret = regmap_field_write(data->rm_field[F_USBCHGEN], 0);
10916f7f70e3SChiaEn Wu 	if (ret)
10926f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to disable BC12\n");
10936f7f70e3SChiaEn Wu 
10946f7f70e3SChiaEn Wu 	return regmap_field_write(data->rm_field[F_USBCHGEN], 1);
10956f7f70e3SChiaEn Wu }
10966f7f70e3SChiaEn Wu 
rt9467_is_accessible_reg(struct device * dev,unsigned int reg)10976f7f70e3SChiaEn Wu static bool rt9467_is_accessible_reg(struct device *dev, unsigned int reg)
10986f7f70e3SChiaEn Wu {
10996f7f70e3SChiaEn Wu 	switch (reg) {
11006f7f70e3SChiaEn Wu 	case 0x00 ... 0x1A:
11016f7f70e3SChiaEn Wu 	case 0x20 ... 0x38:
11026f7f70e3SChiaEn Wu 	case 0x40 ... 0x49:
11036f7f70e3SChiaEn Wu 	case 0x50 ... 0x57:
11046f7f70e3SChiaEn Wu 	case 0x60 ... 0x67:
11056f7f70e3SChiaEn Wu 	case 0x70 ... 0x79:
11066f7f70e3SChiaEn Wu 	case 0x82 ... 0x85:
11076f7f70e3SChiaEn Wu 		return true;
11086f7f70e3SChiaEn Wu 	default:
11096f7f70e3SChiaEn Wu 		return false;
11106f7f70e3SChiaEn Wu 	}
11116f7f70e3SChiaEn Wu }
11126f7f70e3SChiaEn Wu 
11136f7f70e3SChiaEn Wu static const struct regmap_config rt9467_regmap_config = {
11146f7f70e3SChiaEn Wu 	.reg_bits = 8,
11156f7f70e3SChiaEn Wu 	.val_bits = 8,
11166f7f70e3SChiaEn Wu 	.max_register = 0x85,
11176f7f70e3SChiaEn Wu 	.writeable_reg = rt9467_is_accessible_reg,
11186f7f70e3SChiaEn Wu 	.readable_reg = rt9467_is_accessible_reg,
11196f7f70e3SChiaEn Wu };
11206f7f70e3SChiaEn Wu 
rt9467_check_vendor_info(struct rt9467_chg_data * data)11216f7f70e3SChiaEn Wu static int rt9467_check_vendor_info(struct rt9467_chg_data *data)
11226f7f70e3SChiaEn Wu {
11236f7f70e3SChiaEn Wu 	unsigned int vid;
11246f7f70e3SChiaEn Wu 	int ret;
11256f7f70e3SChiaEn Wu 
11266f7f70e3SChiaEn Wu 	ret = regmap_field_read(data->rm_field[F_VENDOR], &vid);
11276f7f70e3SChiaEn Wu 	if (ret) {
11286f7f70e3SChiaEn Wu 		dev_err(data->dev, "Failed to get vid\n");
11296f7f70e3SChiaEn Wu 		return ret;
11306f7f70e3SChiaEn Wu 	}
11316f7f70e3SChiaEn Wu 
11326f7f70e3SChiaEn Wu 	if ((vid != RT9466_VID) && (vid != RT9467_VID))
11336f7f70e3SChiaEn Wu 		return dev_err_probe(data->dev, -ENODEV,
11346f7f70e3SChiaEn Wu 				     "VID not correct [0x%02X]\n", vid);
11356f7f70e3SChiaEn Wu 
11366f7f70e3SChiaEn Wu 	data->vid = vid;
11376f7f70e3SChiaEn Wu 	return 0;
11386f7f70e3SChiaEn Wu }
11396f7f70e3SChiaEn Wu 
rt9467_reset_chip(struct rt9467_chg_data * data)11406f7f70e3SChiaEn Wu static int rt9467_reset_chip(struct rt9467_chg_data *data)
11416f7f70e3SChiaEn Wu {
11426f7f70e3SChiaEn Wu 	int ret;
11436f7f70e3SChiaEn Wu 
11446f7f70e3SChiaEn Wu 	/* Disable HZ before reset chip */
11456f7f70e3SChiaEn Wu 	ret = regmap_field_write(data->rm_field[F_HZ], 0);
11466f7f70e3SChiaEn Wu 	if (ret)
11476f7f70e3SChiaEn Wu 		return ret;
11486f7f70e3SChiaEn Wu 
11496f7f70e3SChiaEn Wu 	return regmap_field_write(data->rm_field[F_RST], 1);
11506f7f70e3SChiaEn Wu }
11516f7f70e3SChiaEn Wu 
rt9467_chg_destroy_adc_lock(void * data)11526f7f70e3SChiaEn Wu static void rt9467_chg_destroy_adc_lock(void *data)
11536f7f70e3SChiaEn Wu {
11546f7f70e3SChiaEn Wu 	struct mutex *adc_lock = data;
11556f7f70e3SChiaEn Wu 
11566f7f70e3SChiaEn Wu 	mutex_destroy(adc_lock);
11576f7f70e3SChiaEn Wu }
11586f7f70e3SChiaEn Wu 
rt9467_chg_destroy_attach_lock(void * data)11596f7f70e3SChiaEn Wu static void rt9467_chg_destroy_attach_lock(void *data)
11606f7f70e3SChiaEn Wu {
11616f7f70e3SChiaEn Wu 	struct mutex *attach_lock = data;
11626f7f70e3SChiaEn Wu 
11636f7f70e3SChiaEn Wu 	mutex_destroy(attach_lock);
11646f7f70e3SChiaEn Wu }
11656f7f70e3SChiaEn Wu 
rt9467_chg_destroy_ichg_ieoc_lock(void * data)11666f7f70e3SChiaEn Wu static void rt9467_chg_destroy_ichg_ieoc_lock(void *data)
11676f7f70e3SChiaEn Wu {
11686f7f70e3SChiaEn Wu 	struct mutex *ichg_ieoc_lock = data;
11696f7f70e3SChiaEn Wu 
11706f7f70e3SChiaEn Wu 	mutex_destroy(ichg_ieoc_lock);
11716f7f70e3SChiaEn Wu }
11726f7f70e3SChiaEn Wu 
rt9467_chg_complete_aicl_done(void * data)11736f7f70e3SChiaEn Wu static void rt9467_chg_complete_aicl_done(void *data)
11746f7f70e3SChiaEn Wu {
11756f7f70e3SChiaEn Wu 	struct completion *aicl_done = data;
11766f7f70e3SChiaEn Wu 
11776f7f70e3SChiaEn Wu 	complete(aicl_done);
11786f7f70e3SChiaEn Wu }
11796f7f70e3SChiaEn Wu 
rt9467_charger_probe(struct i2c_client * i2c)11806f7f70e3SChiaEn Wu static int rt9467_charger_probe(struct i2c_client *i2c)
11816f7f70e3SChiaEn Wu {
11826f7f70e3SChiaEn Wu 	struct device *dev = &i2c->dev;
11836f7f70e3SChiaEn Wu 	struct rt9467_chg_data *data;
11846f7f70e3SChiaEn Wu 	struct gpio_desc *ceb_gpio;
11856f7f70e3SChiaEn Wu 	int ret;
11866f7f70e3SChiaEn Wu 
11876f7f70e3SChiaEn Wu 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
11886f7f70e3SChiaEn Wu 	if (!data)
11896f7f70e3SChiaEn Wu 		return -ENOMEM;
11906f7f70e3SChiaEn Wu 
11916f7f70e3SChiaEn Wu 	data->dev = &i2c->dev;
11926f7f70e3SChiaEn Wu 	i2c_set_clientdata(i2c, data);
11936f7f70e3SChiaEn Wu 
11946f7f70e3SChiaEn Wu 	/* Default pull charge enable gpio to make 'CHG_EN' by SW control only */
11955d80a86aSChiYuan Huang 	ceb_gpio = devm_gpiod_get_optional(dev, "charge-enable", GPIOD_OUT_HIGH);
11966f7f70e3SChiaEn Wu 	if (IS_ERR(ceb_gpio))
11976f7f70e3SChiaEn Wu 		return dev_err_probe(dev, PTR_ERR(ceb_gpio),
11986f7f70e3SChiaEn Wu 				     "Failed to config charge enable gpio\n");
11996f7f70e3SChiaEn Wu 
12006f7f70e3SChiaEn Wu 	data->regmap = devm_regmap_init_i2c(i2c, &rt9467_regmap_config);
12016f7f70e3SChiaEn Wu 	if (IS_ERR(data->regmap))
12026f7f70e3SChiaEn Wu 		return dev_err_probe(dev, PTR_ERR(data->regmap),
12036f7f70e3SChiaEn Wu 				     "Failed to init regmap\n");
12046f7f70e3SChiaEn Wu 
12056f7f70e3SChiaEn Wu 	ret = devm_regmap_field_bulk_alloc(dev, data->regmap,
12066f7f70e3SChiaEn Wu 					   data->rm_field, rt9467_chg_fields,
12076f7f70e3SChiaEn Wu 					   ARRAY_SIZE(rt9467_chg_fields));
12086f7f70e3SChiaEn Wu 	if (ret)
12096f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to alloc regmap fields\n");
12106f7f70e3SChiaEn Wu 
12116f7f70e3SChiaEn Wu 	ret = rt9467_check_vendor_info(data);
12126f7f70e3SChiaEn Wu 	if (ret)
12136f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to check vendor info");
12146f7f70e3SChiaEn Wu 
12156f7f70e3SChiaEn Wu 	ret = rt9467_reset_chip(data);
12166f7f70e3SChiaEn Wu 	if (ret)
12176f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to reset chip\n");
12186f7f70e3SChiaEn Wu 
12196f7f70e3SChiaEn Wu 	ret = devm_regmap_add_irq_chip(dev, data->regmap, i2c->irq,
12206f7f70e3SChiaEn Wu 				       IRQF_TRIGGER_LOW | IRQF_ONESHOT, 0,
12216f7f70e3SChiaEn Wu 				       &rt9467_irq_chip, &data->irq_chip_data);
12226f7f70e3SChiaEn Wu 	if (ret)
12236f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to add irq chip\n");
12246f7f70e3SChiaEn Wu 
12256f7f70e3SChiaEn Wu 	mutex_init(&data->adc_lock);
12266f7f70e3SChiaEn Wu 	ret = devm_add_action_or_reset(dev, rt9467_chg_destroy_adc_lock,
12276f7f70e3SChiaEn Wu 				       &data->adc_lock);
12286f7f70e3SChiaEn Wu 	if (ret)
12296f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to init ADC lock\n");
12306f7f70e3SChiaEn Wu 
12316f7f70e3SChiaEn Wu 	mutex_init(&data->attach_lock);
12326f7f70e3SChiaEn Wu 	ret = devm_add_action_or_reset(dev, rt9467_chg_destroy_attach_lock,
12336f7f70e3SChiaEn Wu 				       &data->attach_lock);
12346f7f70e3SChiaEn Wu 	if (ret)
12356f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to init attach lock\n");
12366f7f70e3SChiaEn Wu 
12376f7f70e3SChiaEn Wu 	mutex_init(&data->ichg_ieoc_lock);
12386f7f70e3SChiaEn Wu 	ret = devm_add_action_or_reset(dev, rt9467_chg_destroy_ichg_ieoc_lock,
12396f7f70e3SChiaEn Wu 				       &data->ichg_ieoc_lock);
12406f7f70e3SChiaEn Wu 	if (ret)
12416f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to init ICHG/IEOC lock\n");
12426f7f70e3SChiaEn Wu 
12436f7f70e3SChiaEn Wu 	init_completion(&data->aicl_done);
12446f7f70e3SChiaEn Wu 	ret = devm_add_action_or_reset(dev, rt9467_chg_complete_aicl_done,
12456f7f70e3SChiaEn Wu 				       &data->aicl_done);
12466f7f70e3SChiaEn Wu 	if (ret)
12476f7f70e3SChiaEn Wu 		return dev_err_probe(dev, ret, "Failed to init AICL done completion\n");
12486f7f70e3SChiaEn Wu 
12496f7f70e3SChiaEn Wu 	ret = rt9467_do_charger_init(data);
12506f7f70e3SChiaEn Wu 	if (ret)
12516f7f70e3SChiaEn Wu 		return ret;
12526f7f70e3SChiaEn Wu 
12536f7f70e3SChiaEn Wu 	ret = rt9467_register_otg_regulator(data);
12546f7f70e3SChiaEn Wu 	if (ret)
12556f7f70e3SChiaEn Wu 		return ret;
12566f7f70e3SChiaEn Wu 
12576f7f70e3SChiaEn Wu 	ret = rt9467_register_psy(data);
12586f7f70e3SChiaEn Wu 	if (ret)
12596f7f70e3SChiaEn Wu 		return ret;
12606f7f70e3SChiaEn Wu 
12616f7f70e3SChiaEn Wu 	return rt9467_request_interrupt(data);
12626f7f70e3SChiaEn Wu }
12636f7f70e3SChiaEn Wu 
12646f7f70e3SChiaEn Wu static const struct of_device_id rt9467_charger_of_match_table[] = {
12656f7f70e3SChiaEn Wu 	{ .compatible = "richtek,rt9467", },
12666f7f70e3SChiaEn Wu 	{}
12676f7f70e3SChiaEn Wu };
12686f7f70e3SChiaEn Wu MODULE_DEVICE_TABLE(of, rt9467_charger_of_match_table);
12696f7f70e3SChiaEn Wu 
12706f7f70e3SChiaEn Wu static struct i2c_driver rt9467_charger_driver = {
12716f7f70e3SChiaEn Wu 	.driver = {
12726f7f70e3SChiaEn Wu 		.name = "rt9467-charger",
12736f7f70e3SChiaEn Wu 		.of_match_table = rt9467_charger_of_match_table,
12746f7f70e3SChiaEn Wu 	},
1275fe20b1dcSUwe Kleine-König 	.probe = rt9467_charger_probe,
12766f7f70e3SChiaEn Wu };
12776f7f70e3SChiaEn Wu module_i2c_driver(rt9467_charger_driver);
12786f7f70e3SChiaEn Wu 
12796f7f70e3SChiaEn Wu MODULE_DESCRIPTION("Richtek RT9467 Charger Driver");
12806f7f70e3SChiaEn Wu MODULE_AUTHOR("ChiYuan Huang <cy_huang@richtek.com>");
12816f7f70e3SChiaEn Wu MODULE_AUTHOR("ChiaEn Wu <chiaen_wu@richtek.com>");
12826f7f70e3SChiaEn Wu MODULE_LICENSE("GPL");
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