1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R-Car SYSC Power management support
4 *
5 * Copyright (C) 2014 Magnus Damm
6 * Copyright (C) 2015-2017 Glider bvba
7 */
8
9 #include <linux/clk/renesas.h>
10 #include <linux/delay.h>
11 #include <linux/err.h>
12 #include <linux/mm.h>
13 #include <linux/of_address.h>
14 #include <linux/pm_domain.h>
15 #include <linux/slab.h>
16 #include <linux/spinlock.h>
17 #include <linux/io.h>
18 #include <linux/iopoll.h>
19 #include <linux/soc/renesas/rcar-sysc.h>
20
21 #include "rcar-sysc.h"
22
23 /* SYSC Common */
24 #define SYSCSR 0x00 /* SYSC Status Register */
25 #define SYSCISR 0x04 /* Interrupt Status Register */
26 #define SYSCISCR 0x08 /* Interrupt Status Clear Register */
27 #define SYSCIER 0x0c /* Interrupt Enable Register */
28 #define SYSCIMR 0x10 /* Interrupt Mask Register */
29
30 /* SYSC Status Register */
31 #define SYSCSR_PONENB 1 /* Ready for power resume requests */
32 #define SYSCSR_POFFENB 0 /* Ready for power shutoff requests */
33
34 /*
35 * Power Control Register Offsets inside the register block for each domain
36 * Note: The "CR" registers for ARM cores exist on H1 only
37 * Use WFI to power off, CPG/APMU to resume ARM cores on R-Car Gen2
38 * Use PSCI on R-Car Gen3
39 */
40 #define PWRSR_OFFS 0x00 /* Power Status Register */
41 #define PWROFFCR_OFFS 0x04 /* Power Shutoff Control Register */
42 #define PWROFFSR_OFFS 0x08 /* Power Shutoff Status Register */
43 #define PWRONCR_OFFS 0x0c /* Power Resume Control Register */
44 #define PWRONSR_OFFS 0x10 /* Power Resume Status Register */
45 #define PWRER_OFFS 0x14 /* Power Shutoff/Resume Error */
46
47
48 #define SYSCSR_TIMEOUT 100
49 #define SYSCSR_DELAY_US 1
50
51 #define PWRER_RETRIES 100
52 #define PWRER_DELAY_US 1
53
54 #define SYSCISR_TIMEOUT 1000
55 #define SYSCISR_DELAY_US 1
56
57 #define RCAR_PD_ALWAYS_ON 32 /* Always-on power area */
58
59 struct rcar_sysc_ch {
60 u16 chan_offs;
61 u8 chan_bit;
62 u8 isr_bit;
63 };
64
65 static void __iomem *rcar_sysc_base;
66 static DEFINE_SPINLOCK(rcar_sysc_lock); /* SMP CPUs + I/O devices */
67 static u32 rcar_sysc_extmask_offs, rcar_sysc_extmask_val;
68
rcar_sysc_pwr_on_off(const struct rcar_sysc_ch * sysc_ch,bool on)69 static int rcar_sysc_pwr_on_off(const struct rcar_sysc_ch *sysc_ch, bool on)
70 {
71 unsigned int sr_bit, reg_offs;
72 u32 val;
73 int ret;
74
75 if (on) {
76 sr_bit = SYSCSR_PONENB;
77 reg_offs = PWRONCR_OFFS;
78 } else {
79 sr_bit = SYSCSR_POFFENB;
80 reg_offs = PWROFFCR_OFFS;
81 }
82
83 /* Wait until SYSC is ready to accept a power request */
84 ret = readl_poll_timeout_atomic(rcar_sysc_base + SYSCSR, val,
85 val & BIT(sr_bit), SYSCSR_DELAY_US,
86 SYSCSR_TIMEOUT);
87 if (ret)
88 return -EAGAIN;
89
90 /* Submit power shutoff or power resume request */
91 iowrite32(BIT(sysc_ch->chan_bit),
92 rcar_sysc_base + sysc_ch->chan_offs + reg_offs);
93
94 return 0;
95 }
96
rcar_sysc_power(const struct rcar_sysc_ch * sysc_ch,bool on)97 static int rcar_sysc_power(const struct rcar_sysc_ch *sysc_ch, bool on)
98 {
99 unsigned int isr_mask = BIT(sysc_ch->isr_bit);
100 unsigned int chan_mask = BIT(sysc_ch->chan_bit);
101 unsigned int status, k;
102 unsigned long flags;
103 int ret;
104
105 spin_lock_irqsave(&rcar_sysc_lock, flags);
106
107 /*
108 * Mask external power requests for CPU or 3DG domains
109 */
110 if (rcar_sysc_extmask_val) {
111 iowrite32(rcar_sysc_extmask_val,
112 rcar_sysc_base + rcar_sysc_extmask_offs);
113 }
114
115 /*
116 * The interrupt source needs to be enabled, but masked, to prevent the
117 * CPU from receiving it.
118 */
119 iowrite32(ioread32(rcar_sysc_base + SYSCIMR) | isr_mask,
120 rcar_sysc_base + SYSCIMR);
121 iowrite32(ioread32(rcar_sysc_base + SYSCIER) | isr_mask,
122 rcar_sysc_base + SYSCIER);
123
124 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
125
126 /* Submit power shutoff or resume request until it was accepted */
127 for (k = 0; k < PWRER_RETRIES; k++) {
128 ret = rcar_sysc_pwr_on_off(sysc_ch, on);
129 if (ret)
130 goto out;
131
132 status = ioread32(rcar_sysc_base +
133 sysc_ch->chan_offs + PWRER_OFFS);
134 if (!(status & chan_mask))
135 break;
136
137 udelay(PWRER_DELAY_US);
138 }
139
140 if (k == PWRER_RETRIES) {
141 ret = -EIO;
142 goto out;
143 }
144
145 /* Wait until the power shutoff or resume request has completed * */
146 ret = readl_poll_timeout_atomic(rcar_sysc_base + SYSCISR, status,
147 status & isr_mask, SYSCISR_DELAY_US,
148 SYSCISR_TIMEOUT);
149 if (ret)
150 ret = -EIO;
151
152 iowrite32(isr_mask, rcar_sysc_base + SYSCISCR);
153
154 out:
155 if (rcar_sysc_extmask_val)
156 iowrite32(0, rcar_sysc_base + rcar_sysc_extmask_offs);
157
158 spin_unlock_irqrestore(&rcar_sysc_lock, flags);
159
160 pr_debug("sysc power %s domain %d: %08x -> %d\n", on ? "on" : "off",
161 sysc_ch->isr_bit, ioread32(rcar_sysc_base + SYSCISR), ret);
162 return ret;
163 }
164
rcar_sysc_power_is_off(const struct rcar_sysc_ch * sysc_ch)165 static bool rcar_sysc_power_is_off(const struct rcar_sysc_ch *sysc_ch)
166 {
167 unsigned int st;
168
169 st = ioread32(rcar_sysc_base + sysc_ch->chan_offs + PWRSR_OFFS);
170 if (st & BIT(sysc_ch->chan_bit))
171 return true;
172
173 return false;
174 }
175
176 struct rcar_sysc_pd {
177 struct generic_pm_domain genpd;
178 struct rcar_sysc_ch ch;
179 unsigned int flags;
180 char name[];
181 };
182
to_rcar_pd(struct generic_pm_domain * d)183 static inline struct rcar_sysc_pd *to_rcar_pd(struct generic_pm_domain *d)
184 {
185 return container_of(d, struct rcar_sysc_pd, genpd);
186 }
187
rcar_sysc_pd_power_off(struct generic_pm_domain * genpd)188 static int rcar_sysc_pd_power_off(struct generic_pm_domain *genpd)
189 {
190 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
191
192 pr_debug("%s: %s\n", __func__, genpd->name);
193 return rcar_sysc_power(&pd->ch, false);
194 }
195
rcar_sysc_pd_power_on(struct generic_pm_domain * genpd)196 static int rcar_sysc_pd_power_on(struct generic_pm_domain *genpd)
197 {
198 struct rcar_sysc_pd *pd = to_rcar_pd(genpd);
199
200 pr_debug("%s: %s\n", __func__, genpd->name);
201 return rcar_sysc_power(&pd->ch, true);
202 }
203
204 static bool has_cpg_mstp;
205
rcar_sysc_pd_setup(struct rcar_sysc_pd * pd)206 static int __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
207 {
208 struct generic_pm_domain *genpd = &pd->genpd;
209 const char *name = pd->genpd.name;
210 int error;
211
212 if (pd->flags & PD_CPU) {
213 /*
214 * This domain contains a CPU core and therefore it should
215 * only be turned off if the CPU is not in use.
216 */
217 pr_debug("PM domain %s contains %s\n", name, "CPU");
218 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
219 } else if (pd->flags & PD_SCU) {
220 /*
221 * This domain contains an SCU and cache-controller, and
222 * therefore it should only be turned off if the CPU cores are
223 * not in use.
224 */
225 pr_debug("PM domain %s contains %s\n", name, "SCU");
226 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
227 } else if (pd->flags & PD_NO_CR) {
228 /*
229 * This domain cannot be turned off.
230 */
231 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
232 }
233
234 if (!(pd->flags & (PD_CPU | PD_SCU))) {
235 /* Enable Clock Domain for I/O devices */
236 genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
237 if (has_cpg_mstp) {
238 genpd->attach_dev = cpg_mstp_attach_dev;
239 genpd->detach_dev = cpg_mstp_detach_dev;
240 } else {
241 genpd->attach_dev = cpg_mssr_attach_dev;
242 genpd->detach_dev = cpg_mssr_detach_dev;
243 }
244 }
245
246 genpd->power_off = rcar_sysc_pd_power_off;
247 genpd->power_on = rcar_sysc_pd_power_on;
248
249 if (pd->flags & (PD_CPU | PD_NO_CR)) {
250 /* Skip CPUs (handled by SMP code) and areas without control */
251 pr_debug("%s: Not touching %s\n", __func__, genpd->name);
252 goto finalize;
253 }
254
255 if (!rcar_sysc_power_is_off(&pd->ch)) {
256 pr_debug("%s: %s is already powered\n", __func__, genpd->name);
257 goto finalize;
258 }
259
260 rcar_sysc_power(&pd->ch, true);
261
262 finalize:
263 error = pm_genpd_init(genpd, &simple_qos_governor, false);
264 if (error)
265 pr_err("Failed to init PM domain %s: %d\n", name, error);
266
267 return error;
268 }
269
270 static const struct of_device_id rcar_sysc_matches[] __initconst = {
271 #ifdef CONFIG_SYSC_R8A7742
272 { .compatible = "renesas,r8a7742-sysc", .data = &r8a7742_sysc_info },
273 #endif
274 #ifdef CONFIG_SYSC_R8A7743
275 { .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
276 /* RZ/G1N is identical to RZ/G2M w.r.t. power domains. */
277 { .compatible = "renesas,r8a7744-sysc", .data = &r8a7743_sysc_info },
278 #endif
279 #ifdef CONFIG_SYSC_R8A7745
280 { .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
281 #endif
282 #ifdef CONFIG_SYSC_R8A77470
283 { .compatible = "renesas,r8a77470-sysc", .data = &r8a77470_sysc_info },
284 #endif
285 #ifdef CONFIG_SYSC_R8A774A1
286 { .compatible = "renesas,r8a774a1-sysc", .data = &r8a774a1_sysc_info },
287 #endif
288 #ifdef CONFIG_SYSC_R8A774B1
289 { .compatible = "renesas,r8a774b1-sysc", .data = &r8a774b1_sysc_info },
290 #endif
291 #ifdef CONFIG_SYSC_R8A774C0
292 { .compatible = "renesas,r8a774c0-sysc", .data = &r8a774c0_sysc_info },
293 #endif
294 #ifdef CONFIG_SYSC_R8A774E1
295 { .compatible = "renesas,r8a774e1-sysc", .data = &r8a774e1_sysc_info },
296 #endif
297 #ifdef CONFIG_SYSC_R8A7779
298 { .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
299 #endif
300 #ifdef CONFIG_SYSC_R8A7790
301 { .compatible = "renesas,r8a7790-sysc", .data = &r8a7790_sysc_info },
302 #endif
303 #ifdef CONFIG_SYSC_R8A7791
304 { .compatible = "renesas,r8a7791-sysc", .data = &r8a7791_sysc_info },
305 /* R-Car M2-N is identical to R-Car M2-W w.r.t. power domains. */
306 { .compatible = "renesas,r8a7793-sysc", .data = &r8a7791_sysc_info },
307 #endif
308 #ifdef CONFIG_SYSC_R8A7792
309 { .compatible = "renesas,r8a7792-sysc", .data = &r8a7792_sysc_info },
310 #endif
311 #ifdef CONFIG_SYSC_R8A7794
312 { .compatible = "renesas,r8a7794-sysc", .data = &r8a7794_sysc_info },
313 #endif
314 #ifdef CONFIG_SYSC_R8A7795
315 { .compatible = "renesas,r8a7795-sysc", .data = &r8a7795_sysc_info },
316 #endif
317 #ifdef CONFIG_SYSC_R8A77960
318 { .compatible = "renesas,r8a7796-sysc", .data = &r8a77960_sysc_info },
319 #endif
320 #ifdef CONFIG_SYSC_R8A77961
321 { .compatible = "renesas,r8a77961-sysc", .data = &r8a77961_sysc_info },
322 #endif
323 #ifdef CONFIG_SYSC_R8A77965
324 { .compatible = "renesas,r8a77965-sysc", .data = &r8a77965_sysc_info },
325 #endif
326 #ifdef CONFIG_SYSC_R8A77970
327 { .compatible = "renesas,r8a77970-sysc", .data = &r8a77970_sysc_info },
328 #endif
329 #ifdef CONFIG_SYSC_R8A77980
330 { .compatible = "renesas,r8a77980-sysc", .data = &r8a77980_sysc_info },
331 #endif
332 #ifdef CONFIG_SYSC_R8A77990
333 { .compatible = "renesas,r8a77990-sysc", .data = &r8a77990_sysc_info },
334 #endif
335 #ifdef CONFIG_SYSC_R8A77995
336 { .compatible = "renesas,r8a77995-sysc", .data = &r8a77995_sysc_info },
337 #endif
338 { /* sentinel */ }
339 };
340
341 struct rcar_pm_domains {
342 struct genpd_onecell_data onecell_data;
343 struct generic_pm_domain *domains[RCAR_PD_ALWAYS_ON + 1];
344 };
345
346 static struct genpd_onecell_data *rcar_sysc_onecell_data;
347
rcar_sysc_pd_init(void)348 static int __init rcar_sysc_pd_init(void)
349 {
350 const struct rcar_sysc_info *info;
351 const struct of_device_id *match;
352 struct rcar_pm_domains *domains;
353 struct device_node *np;
354 void __iomem *base;
355 unsigned int i;
356 int error;
357
358 np = of_find_matching_node_and_match(NULL, rcar_sysc_matches, &match);
359 if (!np)
360 return -ENODEV;
361
362 info = match->data;
363
364 if (info->init) {
365 error = info->init();
366 if (error)
367 goto out_put;
368 }
369
370 has_cpg_mstp = of_find_compatible_node(NULL, NULL,
371 "renesas,cpg-mstp-clocks");
372
373 base = of_iomap(np, 0);
374 if (!base) {
375 pr_warn("%pOF: Cannot map regs\n", np);
376 error = -ENOMEM;
377 goto out_put;
378 }
379
380 rcar_sysc_base = base;
381
382 /* Optional External Request Mask Register */
383 rcar_sysc_extmask_offs = info->extmask_offs;
384 rcar_sysc_extmask_val = info->extmask_val;
385
386 domains = kzalloc(sizeof(*domains), GFP_KERNEL);
387 if (!domains) {
388 error = -ENOMEM;
389 goto out_put;
390 }
391
392 domains->onecell_data.domains = domains->domains;
393 domains->onecell_data.num_domains = ARRAY_SIZE(domains->domains);
394 rcar_sysc_onecell_data = &domains->onecell_data;
395
396 for (i = 0; i < info->num_areas; i++) {
397 const struct rcar_sysc_area *area = &info->areas[i];
398 struct rcar_sysc_pd *pd;
399 size_t n;
400
401 if (!area->name) {
402 /* Skip NULLified area */
403 continue;
404 }
405
406 n = strlen(area->name) + 1;
407 pd = kzalloc(sizeof(*pd) + n, GFP_KERNEL);
408 if (!pd) {
409 error = -ENOMEM;
410 goto out_put;
411 }
412
413 memcpy(pd->name, area->name, n);
414 pd->genpd.name = pd->name;
415 pd->ch.chan_offs = area->chan_offs;
416 pd->ch.chan_bit = area->chan_bit;
417 pd->ch.isr_bit = area->isr_bit;
418 pd->flags = area->flags;
419
420 error = rcar_sysc_pd_setup(pd);
421 if (error)
422 goto out_put;
423
424 domains->domains[area->isr_bit] = &pd->genpd;
425
426 if (area->parent < 0)
427 continue;
428
429 error = pm_genpd_add_subdomain(domains->domains[area->parent],
430 &pd->genpd);
431 if (error) {
432 pr_warn("Failed to add PM subdomain %s to parent %u\n",
433 area->name, area->parent);
434 goto out_put;
435 }
436 }
437
438 error = of_genpd_add_provider_onecell(np, &domains->onecell_data);
439 if (!error)
440 fwnode_dev_initialized(of_fwnode_handle(np), true);
441
442 out_put:
443 of_node_put(np);
444 return error;
445 }
446 early_initcall(rcar_sysc_pd_init);
447
rcar_sysc_nullify(struct rcar_sysc_area * areas,unsigned int num_areas,u8 id)448 void __init rcar_sysc_nullify(struct rcar_sysc_area *areas,
449 unsigned int num_areas, u8 id)
450 {
451 unsigned int i;
452
453 for (i = 0; i < num_areas; i++)
454 if (areas[i].isr_bit == id) {
455 areas[i].name = NULL;
456 return;
457 }
458 }
459
460 #ifdef CONFIG_ARCH_R8A7779
rcar_sysc_power_cpu(unsigned int idx,bool on)461 static int rcar_sysc_power_cpu(unsigned int idx, bool on)
462 {
463 struct generic_pm_domain *genpd;
464 struct rcar_sysc_pd *pd;
465 unsigned int i;
466
467 if (!rcar_sysc_onecell_data)
468 return -ENODEV;
469
470 for (i = 0; i < rcar_sysc_onecell_data->num_domains; i++) {
471 genpd = rcar_sysc_onecell_data->domains[i];
472 if (!genpd)
473 continue;
474
475 pd = to_rcar_pd(genpd);
476 if (!(pd->flags & PD_CPU) || pd->ch.chan_bit != idx)
477 continue;
478
479 return rcar_sysc_power(&pd->ch, on);
480 }
481
482 return -ENOENT;
483 }
484
rcar_sysc_power_down_cpu(unsigned int cpu)485 int rcar_sysc_power_down_cpu(unsigned int cpu)
486 {
487 return rcar_sysc_power_cpu(cpu, false);
488 }
489
rcar_sysc_power_up_cpu(unsigned int cpu)490 int rcar_sysc_power_up_cpu(unsigned int cpu)
491 {
492 return rcar_sysc_power_cpu(cpu, true);
493 }
494 #endif /* CONFIG_ARCH_R8A7779 */
495