1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Intel Atom SOC Power Management Controller Driver 4 * Copyright (c) 2014, Intel Corporation. 5 */ 6 7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 8 9 #include <linux/debugfs.h> 10 #include <linux/device.h> 11 #include <linux/dmi.h> 12 #include <linux/init.h> 13 #include <linux/io.h> 14 #include <linux/platform_data/x86/clk-pmc-atom.h> 15 #include <linux/platform_data/x86/pmc_atom.h> 16 #include <linux/platform_data/x86/simatic-ipc.h> 17 #include <linux/platform_device.h> 18 #include <linux/pci.h> 19 #include <linux/seq_file.h> 20 21 struct pmc_bit_map { 22 const char *name; 23 u32 bit_mask; 24 }; 25 26 struct pmc_reg_map { 27 const struct pmc_bit_map *d3_sts_0; 28 const struct pmc_bit_map *d3_sts_1; 29 const struct pmc_bit_map *func_dis; 30 const struct pmc_bit_map *func_dis_2; 31 const struct pmc_bit_map *pss; 32 }; 33 34 struct pmc_data { 35 const struct pmc_reg_map *map; 36 const struct pmc_clk *clks; 37 }; 38 39 struct pmc_dev { 40 u32 base_addr; 41 void __iomem *regmap; 42 const struct pmc_reg_map *map; 43 #ifdef CONFIG_DEBUG_FS 44 struct dentry *dbgfs_dir; 45 #endif /* CONFIG_DEBUG_FS */ 46 bool init; 47 }; 48 49 static struct pmc_dev pmc_device; 50 static u32 acpi_base_addr; 51 52 static const struct pmc_clk byt_clks[] = { 53 { 54 .name = "xtal", 55 .freq = 25000000, 56 .parent_name = NULL, 57 }, 58 { 59 .name = "pll", 60 .freq = 19200000, 61 .parent_name = "xtal", 62 }, 63 {}, 64 }; 65 66 static const struct pmc_clk cht_clks[] = { 67 { 68 .name = "xtal", 69 .freq = 19200000, 70 .parent_name = NULL, 71 }, 72 {}, 73 }; 74 75 static const struct pmc_bit_map d3_sts_0_map[] = { 76 {"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA}, 77 {"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1}, 78 {"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2}, 79 {"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1}, 80 {"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2}, 81 {"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI}, 82 {"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX}, 83 {"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX}, 84 {"SCC_EMMC", BIT_SCC_EMMC}, 85 {"SCC_SDIO", BIT_SCC_SDIO}, 86 {"SCC_SDCARD", BIT_SCC_SDCARD}, 87 {"SCC_MIPI", BIT_SCC_MIPI}, 88 {"HDA", BIT_HDA}, 89 {"LPE", BIT_LPE}, 90 {"OTG", BIT_OTG}, 91 {"USH", BIT_USH}, 92 {"GBE", BIT_GBE}, 93 {"SATA", BIT_SATA}, 94 {"USB_EHCI", BIT_USB_EHCI}, 95 {"SEC", BIT_SEC}, 96 {"PCIE_PORT0", BIT_PCIE_PORT0}, 97 {"PCIE_PORT1", BIT_PCIE_PORT1}, 98 {"PCIE_PORT2", BIT_PCIE_PORT2}, 99 {"PCIE_PORT3", BIT_PCIE_PORT3}, 100 {"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA}, 101 {"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1}, 102 {"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2}, 103 {"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3}, 104 {"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4}, 105 {"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5}, 106 {"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6}, 107 {"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7}, 108 {}, 109 }; 110 111 static struct pmc_bit_map byt_d3_sts_1_map[] = { 112 {"SMB", BIT_SMB}, 113 {"OTG_SS_PHY", BIT_OTG_SS_PHY}, 114 {"USH_SS_PHY", BIT_USH_SS_PHY}, 115 {"DFX", BIT_DFX}, 116 {}, 117 }; 118 119 static struct pmc_bit_map cht_d3_sts_1_map[] = { 120 {"SMB", BIT_SMB}, 121 {"GMM", BIT_STS_GMM}, 122 {"ISH", BIT_STS_ISH}, 123 {}, 124 }; 125 126 static struct pmc_bit_map cht_func_dis_2_map[] = { 127 {"SMB", BIT_SMB}, 128 {"GMM", BIT_FD_GMM}, 129 {"ISH", BIT_FD_ISH}, 130 {}, 131 }; 132 133 static const struct pmc_bit_map byt_pss_map[] = { 134 {"GBE", PMC_PSS_BIT_GBE}, 135 {"SATA", PMC_PSS_BIT_SATA}, 136 {"HDA", PMC_PSS_BIT_HDA}, 137 {"SEC", PMC_PSS_BIT_SEC}, 138 {"PCIE", PMC_PSS_BIT_PCIE}, 139 {"LPSS", PMC_PSS_BIT_LPSS}, 140 {"LPE", PMC_PSS_BIT_LPE}, 141 {"DFX", PMC_PSS_BIT_DFX}, 142 {"USH_CTRL", PMC_PSS_BIT_USH_CTRL}, 143 {"USH_SUS", PMC_PSS_BIT_USH_SUS}, 144 {"USH_VCCS", PMC_PSS_BIT_USH_VCCS}, 145 {"USH_VCCA", PMC_PSS_BIT_USH_VCCA}, 146 {"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL}, 147 {"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS}, 148 {"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK}, 149 {"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA}, 150 {"USB", PMC_PSS_BIT_USB}, 151 {"USB_SUS", PMC_PSS_BIT_USB_SUS}, 152 {}, 153 }; 154 155 static const struct pmc_bit_map cht_pss_map[] = { 156 {"SATA", PMC_PSS_BIT_SATA}, 157 {"HDA", PMC_PSS_BIT_HDA}, 158 {"SEC", PMC_PSS_BIT_SEC}, 159 {"PCIE", PMC_PSS_BIT_PCIE}, 160 {"LPSS", PMC_PSS_BIT_LPSS}, 161 {"LPE", PMC_PSS_BIT_LPE}, 162 {"UFS", PMC_PSS_BIT_CHT_UFS}, 163 {"UXD", PMC_PSS_BIT_CHT_UXD}, 164 {"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD}, 165 {"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG}, 166 {"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS}, 167 {"GMM", PMC_PSS_BIT_CHT_GMM}, 168 {"ISH", PMC_PSS_BIT_CHT_ISH}, 169 {"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER}, 170 {"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1}, 171 {"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2}, 172 {"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3}, 173 {"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4}, 174 {"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5}, 175 {}, 176 }; 177 178 static const struct pmc_reg_map byt_reg_map = { 179 .d3_sts_0 = d3_sts_0_map, 180 .d3_sts_1 = byt_d3_sts_1_map, 181 .func_dis = d3_sts_0_map, 182 .func_dis_2 = byt_d3_sts_1_map, 183 .pss = byt_pss_map, 184 }; 185 186 static const struct pmc_reg_map cht_reg_map = { 187 .d3_sts_0 = d3_sts_0_map, 188 .d3_sts_1 = cht_d3_sts_1_map, 189 .func_dis = d3_sts_0_map, 190 .func_dis_2 = cht_func_dis_2_map, 191 .pss = cht_pss_map, 192 }; 193 194 static const struct pmc_data byt_data = { 195 .map = &byt_reg_map, 196 .clks = byt_clks, 197 }; 198 199 static const struct pmc_data cht_data = { 200 .map = &cht_reg_map, 201 .clks = cht_clks, 202 }; 203 204 static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset) 205 { 206 return readl(pmc->regmap + reg_offset); 207 } 208 209 static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val) 210 { 211 writel(val, pmc->regmap + reg_offset); 212 } 213 214 int pmc_atom_read(int offset, u32 *value) 215 { 216 struct pmc_dev *pmc = &pmc_device; 217 218 if (!pmc->init) 219 return -ENODEV; 220 221 *value = pmc_reg_read(pmc, offset); 222 return 0; 223 } 224 EXPORT_SYMBOL_GPL(pmc_atom_read); 225 226 int pmc_atom_write(int offset, u32 value) 227 { 228 struct pmc_dev *pmc = &pmc_device; 229 230 if (!pmc->init) 231 return -ENODEV; 232 233 pmc_reg_write(pmc, offset, value); 234 return 0; 235 } 236 EXPORT_SYMBOL_GPL(pmc_atom_write); 237 238 static void pmc_power_off(void) 239 { 240 u16 pm1_cnt_port; 241 u32 pm1_cnt_value; 242 243 pr_info("Preparing to enter system sleep state S5\n"); 244 245 pm1_cnt_port = acpi_base_addr + PM1_CNT; 246 247 pm1_cnt_value = inl(pm1_cnt_port); 248 pm1_cnt_value &= SLEEP_TYPE_MASK; 249 pm1_cnt_value |= SLEEP_TYPE_S5; 250 pm1_cnt_value |= SLEEP_ENABLE; 251 252 outl(pm1_cnt_value, pm1_cnt_port); 253 } 254 255 static void pmc_hw_reg_setup(struct pmc_dev *pmc) 256 { 257 /* 258 * Disable PMC S0IX_WAKE_EN events coming from: 259 * - LPC clock run 260 * - GPIO_SUS ored dedicated IRQs 261 * - GPIO_SCORE ored dedicated IRQs 262 * - GPIO_SUS shared IRQ 263 * - GPIO_SCORE shared IRQ 264 */ 265 pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING); 266 } 267 268 #ifdef CONFIG_DEBUG_FS 269 static void pmc_dev_state_print(struct seq_file *s, int reg_index, 270 u32 sts, const struct pmc_bit_map *sts_map, 271 u32 fd, const struct pmc_bit_map *fd_map) 272 { 273 int offset = PMC_REG_BIT_WIDTH * reg_index; 274 int index; 275 276 for (index = 0; sts_map[index].name; index++) { 277 seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n", 278 offset + index, sts_map[index].name, 279 fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ", 280 sts_map[index].bit_mask & sts ? "D3" : "D0"); 281 } 282 } 283 284 static int pmc_dev_state_show(struct seq_file *s, void *unused) 285 { 286 struct pmc_dev *pmc = s->private; 287 const struct pmc_reg_map *m = pmc->map; 288 u32 func_dis, func_dis_2; 289 u32 d3_sts_0, d3_sts_1; 290 291 func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS); 292 func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2); 293 d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0); 294 d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1); 295 296 /* Low part */ 297 pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis); 298 299 /* High part */ 300 pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2); 301 302 return 0; 303 } 304 305 DEFINE_SHOW_ATTRIBUTE(pmc_dev_state); 306 307 static int pmc_pss_state_show(struct seq_file *s, void *unused) 308 { 309 struct pmc_dev *pmc = s->private; 310 const struct pmc_bit_map *map = pmc->map->pss; 311 u32 pss = pmc_reg_read(pmc, PMC_PSS); 312 int index; 313 314 for (index = 0; map[index].name; index++) { 315 seq_printf(s, "Island: %-2d - %-32s\tState: %s\n", 316 index, map[index].name, 317 map[index].bit_mask & pss ? "Off" : "On"); 318 } 319 return 0; 320 } 321 322 DEFINE_SHOW_ATTRIBUTE(pmc_pss_state); 323 324 static int pmc_sleep_tmr_show(struct seq_file *s, void *unused) 325 { 326 struct pmc_dev *pmc = s->private; 327 u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr; 328 329 s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT; 330 s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT; 331 s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT; 332 s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT; 333 s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT; 334 335 seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr); 336 seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr); 337 seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr); 338 seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr); 339 seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr); 340 return 0; 341 } 342 343 DEFINE_SHOW_ATTRIBUTE(pmc_sleep_tmr); 344 345 static void pmc_dbgfs_register(struct pmc_dev *pmc) 346 { 347 struct dentry *dir; 348 349 dir = debugfs_create_dir("pmc_atom", NULL); 350 351 pmc->dbgfs_dir = dir; 352 353 debugfs_create_file("dev_state", S_IFREG | S_IRUGO, dir, pmc, 354 &pmc_dev_state_fops); 355 debugfs_create_file("pss_state", S_IFREG | S_IRUGO, dir, pmc, 356 &pmc_pss_state_fops); 357 debugfs_create_file("sleep_state", S_IFREG | S_IRUGO, dir, pmc, 358 &pmc_sleep_tmr_fops); 359 } 360 #else 361 static void pmc_dbgfs_register(struct pmc_dev *pmc) 362 { 363 } 364 #endif /* CONFIG_DEBUG_FS */ 365 366 static bool pmc_clk_is_critical = true; 367 368 static int dmi_callback(const struct dmi_system_id *d) 369 { 370 pr_info("%s critclks quirk enabled\n", d->ident); 371 372 return 1; 373 } 374 375 static int dmi_callback_siemens(const struct dmi_system_id *d) 376 { 377 u32 st_id; 378 379 if (dmi_walk(simatic_ipc_find_dmi_entry_helper, &st_id)) 380 goto out; 381 382 if (st_id == SIMATIC_IPC_IPC227E || st_id == SIMATIC_IPC_IPC277E) 383 return dmi_callback(d); 384 385 out: 386 pmc_clk_is_critical = false; 387 return 1; 388 } 389 390 /* 391 * Some systems need one or more of their pmc_plt_clks to be 392 * marked as critical. 393 */ 394 static const struct dmi_system_id critclk_systems[] = { 395 { 396 /* pmc_plt_clk0 is used for an external HSIC USB HUB */ 397 .ident = "MPL CEC1x", 398 .callback = dmi_callback, 399 .matches = { 400 DMI_MATCH(DMI_SYS_VENDOR, "MPL AG"), 401 DMI_MATCH(DMI_PRODUCT_NAME, "CEC10 Family"), 402 }, 403 }, 404 { 405 /* pmc_plt_clk0 - 3 are used for the 4 ethernet controllers */ 406 .ident = "Lex 3I380D", 407 .callback = dmi_callback, 408 .matches = { 409 DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"), 410 DMI_MATCH(DMI_PRODUCT_NAME, "3I380D"), 411 }, 412 }, 413 { 414 /* pmc_plt_clk* - are used for ethernet controllers */ 415 .ident = "Lex 2I385SW", 416 .callback = dmi_callback, 417 .matches = { 418 DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"), 419 DMI_MATCH(DMI_PRODUCT_NAME, "2I385SW"), 420 }, 421 }, 422 { 423 /* pmc_plt_clk* - are used for ethernet controllers */ 424 .ident = "Beckhoff Baytrail", 425 .callback = dmi_callback, 426 .matches = { 427 DMI_MATCH(DMI_SYS_VENDOR, "Beckhoff Automation"), 428 DMI_MATCH(DMI_PRODUCT_FAMILY, "CBxx63"), 429 }, 430 }, 431 { 432 .ident = "SIEMENS AG", 433 .callback = dmi_callback_siemens, 434 .matches = { 435 DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"), 436 }, 437 }, 438 439 { /*sentinel*/ } 440 }; 441 442 static int pmc_setup_clks(struct pci_dev *pdev, void __iomem *pmc_regmap, 443 const struct pmc_data *pmc_data) 444 { 445 struct platform_device *clkdev; 446 struct pmc_clk_data *clk_data; 447 448 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL); 449 if (!clk_data) 450 return -ENOMEM; 451 452 clk_data->base = pmc_regmap; /* offset is added by client */ 453 clk_data->clks = pmc_data->clks; 454 if (dmi_check_system(critclk_systems)) 455 clk_data->critical = pmc_clk_is_critical; 456 457 clkdev = platform_device_register_data(&pdev->dev, "clk-pmc-atom", 458 PLATFORM_DEVID_NONE, 459 clk_data, sizeof(*clk_data)); 460 if (IS_ERR(clkdev)) { 461 kfree(clk_data); 462 return PTR_ERR(clkdev); 463 } 464 465 kfree(clk_data); 466 467 return 0; 468 } 469 470 static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent) 471 { 472 struct pmc_dev *pmc = &pmc_device; 473 const struct pmc_data *data = (struct pmc_data *)ent->driver_data; 474 const struct pmc_reg_map *map = data->map; 475 int ret; 476 477 /* Obtain ACPI base address */ 478 pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr); 479 acpi_base_addr &= ACPI_BASE_ADDR_MASK; 480 481 /* Install power off function */ 482 if (acpi_base_addr != 0 && pm_power_off == NULL) 483 pm_power_off = pmc_power_off; 484 485 pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr); 486 pmc->base_addr &= PMC_BASE_ADDR_MASK; 487 488 pmc->regmap = ioremap(pmc->base_addr, PMC_MMIO_REG_LEN); 489 if (!pmc->regmap) { 490 dev_err(&pdev->dev, "error: ioremap failed\n"); 491 return -ENOMEM; 492 } 493 494 pmc->map = map; 495 496 /* PMC hardware registers setup */ 497 pmc_hw_reg_setup(pmc); 498 499 pmc_dbgfs_register(pmc); 500 501 /* Register platform clocks - PMC_PLT_CLK [0..5] */ 502 ret = pmc_setup_clks(pdev, pmc->regmap, data); 503 if (ret) 504 dev_warn(&pdev->dev, "platform clocks register failed: %d\n", 505 ret); 506 507 pmc->init = true; 508 return ret; 509 } 510 511 /* 512 * Data for PCI driver interface 513 * 514 * used by pci_match_id() call below. 515 */ 516 static const struct pci_device_id pmc_pci_ids[] = { 517 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_data }, 518 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_data }, 519 { 0, }, 520 }; 521 522 static int __init pmc_atom_init(void) 523 { 524 struct pci_dev *pdev = NULL; 525 const struct pci_device_id *ent; 526 527 /* We look for our device - PCU PMC 528 * we assume that there is max. one device. 529 * 530 * We can't use plain pci_driver mechanism, 531 * as the device is really a multiple function device, 532 * main driver that binds to the pci_device is lpc_ich 533 * and have to find & bind to the device this way. 534 */ 535 for_each_pci_dev(pdev) { 536 ent = pci_match_id(pmc_pci_ids, pdev); 537 if (ent) 538 return pmc_setup_dev(pdev, ent); 539 } 540 /* Device not found. */ 541 return -ENODEV; 542 } 543 544 device_initcall(pmc_atom_init); 545 546 /* 547 MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>"); 548 MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface"); 549 MODULE_LICENSE("GPL v2"); 550 */ 551