xref: /openbmc/linux/drivers/platform/x86/pmc_atom.c (revision 5a88ace4)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Intel Atom SoC Power Management Controller Driver
4  * Copyright (c) 2014-2015,2017,2022 Intel Corporation.
5  */
6 
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
8 
9 #include <linux/debugfs.h>
10 #include <linux/device.h>
11 #include <linux/dmi.h>
12 #include <linux/init.h>
13 #include <linux/io.h>
14 #include <linux/platform_data/x86/clk-pmc-atom.h>
15 #include <linux/platform_data/x86/pmc_atom.h>
16 #include <linux/platform_data/x86/simatic-ipc.h>
17 #include <linux/platform_device.h>
18 #include <linux/pci.h>
19 #include <linux/seq_file.h>
20 
21 struct pmc_bit_map {
22 	const char *name;
23 	u32 bit_mask;
24 };
25 
26 struct pmc_reg_map {
27 	const struct pmc_bit_map *d3_sts_0;
28 	const struct pmc_bit_map *d3_sts_1;
29 	const struct pmc_bit_map *func_dis;
30 	const struct pmc_bit_map *func_dis_2;
31 	const struct pmc_bit_map *pss;
32 };
33 
34 struct pmc_data {
35 	const struct pmc_reg_map *map;
36 	const struct pmc_clk *clks;
37 };
38 
39 struct pmc_dev {
40 	u32 base_addr;
41 	void __iomem *regmap;
42 	const struct pmc_reg_map *map;
43 #ifdef CONFIG_DEBUG_FS
44 	struct dentry *dbgfs_dir;
45 #endif /* CONFIG_DEBUG_FS */
46 	bool init;
47 };
48 
49 static struct pmc_dev pmc_device;
50 static u32 acpi_base_addr;
51 
52 static const struct pmc_clk byt_clks[] = {
53 	{
54 		.name = "xtal",
55 		.freq = 25000000,
56 		.parent_name = NULL,
57 	},
58 	{
59 		.name = "pll",
60 		.freq = 19200000,
61 		.parent_name = "xtal",
62 	},
63 	{}
64 };
65 
66 static const struct pmc_clk cht_clks[] = {
67 	{
68 		.name = "xtal",
69 		.freq = 19200000,
70 		.parent_name = NULL,
71 	},
72 	{}
73 };
74 
75 static const struct pmc_bit_map d3_sts_0_map[] = {
76 	{"LPSS1_F0_DMA",	BIT_LPSS1_F0_DMA},
77 	{"LPSS1_F1_PWM1",	BIT_LPSS1_F1_PWM1},
78 	{"LPSS1_F2_PWM2",	BIT_LPSS1_F2_PWM2},
79 	{"LPSS1_F3_HSUART1",	BIT_LPSS1_F3_HSUART1},
80 	{"LPSS1_F4_HSUART2",	BIT_LPSS1_F4_HSUART2},
81 	{"LPSS1_F5_SPI",	BIT_LPSS1_F5_SPI},
82 	{"LPSS1_F6_Reserved",	BIT_LPSS1_F6_XXX},
83 	{"LPSS1_F7_Reserved",	BIT_LPSS1_F7_XXX},
84 	{"SCC_EMMC",		BIT_SCC_EMMC},
85 	{"SCC_SDIO",		BIT_SCC_SDIO},
86 	{"SCC_SDCARD",		BIT_SCC_SDCARD},
87 	{"SCC_MIPI",		BIT_SCC_MIPI},
88 	{"HDA",			BIT_HDA},
89 	{"LPE",			BIT_LPE},
90 	{"OTG",			BIT_OTG},
91 	{"USH",			BIT_USH},
92 	{"GBE",			BIT_GBE},
93 	{"SATA",		BIT_SATA},
94 	{"USB_EHCI",		BIT_USB_EHCI},
95 	{"SEC",			BIT_SEC},
96 	{"PCIE_PORT0",		BIT_PCIE_PORT0},
97 	{"PCIE_PORT1",		BIT_PCIE_PORT1},
98 	{"PCIE_PORT2",		BIT_PCIE_PORT2},
99 	{"PCIE_PORT3",		BIT_PCIE_PORT3},
100 	{"LPSS2_F0_DMA",	BIT_LPSS2_F0_DMA},
101 	{"LPSS2_F1_I2C1",	BIT_LPSS2_F1_I2C1},
102 	{"LPSS2_F2_I2C2",	BIT_LPSS2_F2_I2C2},
103 	{"LPSS2_F3_I2C3",	BIT_LPSS2_F3_I2C3},
104 	{"LPSS2_F3_I2C4",	BIT_LPSS2_F4_I2C4},
105 	{"LPSS2_F5_I2C5",	BIT_LPSS2_F5_I2C5},
106 	{"LPSS2_F6_I2C6",	BIT_LPSS2_F6_I2C6},
107 	{"LPSS2_F7_I2C7",	BIT_LPSS2_F7_I2C7},
108 	{}
109 };
110 
111 static struct pmc_bit_map byt_d3_sts_1_map[] = {
112 	{"SMB",			BIT_SMB},
113 	{"OTG_SS_PHY",		BIT_OTG_SS_PHY},
114 	{"USH_SS_PHY",		BIT_USH_SS_PHY},
115 	{"DFX",			BIT_DFX},
116 	{}
117 };
118 
119 static struct pmc_bit_map cht_d3_sts_1_map[] = {
120 	{"SMB",			BIT_SMB},
121 	{"GMM",			BIT_STS_GMM},
122 	{"ISH",			BIT_STS_ISH},
123 	{}
124 };
125 
126 static struct pmc_bit_map cht_func_dis_2_map[] = {
127 	{"SMB",			BIT_SMB},
128 	{"GMM",			BIT_FD_GMM},
129 	{"ISH",			BIT_FD_ISH},
130 	{}
131 };
132 
133 static const struct pmc_bit_map byt_pss_map[] = {
134 	{"GBE",			PMC_PSS_BIT_GBE},
135 	{"SATA",		PMC_PSS_BIT_SATA},
136 	{"HDA",			PMC_PSS_BIT_HDA},
137 	{"SEC",			PMC_PSS_BIT_SEC},
138 	{"PCIE",		PMC_PSS_BIT_PCIE},
139 	{"LPSS",		PMC_PSS_BIT_LPSS},
140 	{"LPE",			PMC_PSS_BIT_LPE},
141 	{"DFX",			PMC_PSS_BIT_DFX},
142 	{"USH_CTRL",		PMC_PSS_BIT_USH_CTRL},
143 	{"USH_SUS",		PMC_PSS_BIT_USH_SUS},
144 	{"USH_VCCS",		PMC_PSS_BIT_USH_VCCS},
145 	{"USH_VCCA",		PMC_PSS_BIT_USH_VCCA},
146 	{"OTG_CTRL",		PMC_PSS_BIT_OTG_CTRL},
147 	{"OTG_VCCS",		PMC_PSS_BIT_OTG_VCCS},
148 	{"OTG_VCCA_CLK",	PMC_PSS_BIT_OTG_VCCA_CLK},
149 	{"OTG_VCCA",		PMC_PSS_BIT_OTG_VCCA},
150 	{"USB",			PMC_PSS_BIT_USB},
151 	{"USB_SUS",		PMC_PSS_BIT_USB_SUS},
152 	{}
153 };
154 
155 static const struct pmc_bit_map cht_pss_map[] = {
156 	{"SATA",		PMC_PSS_BIT_SATA},
157 	{"HDA",			PMC_PSS_BIT_HDA},
158 	{"SEC",			PMC_PSS_BIT_SEC},
159 	{"PCIE",		PMC_PSS_BIT_PCIE},
160 	{"LPSS",		PMC_PSS_BIT_LPSS},
161 	{"LPE",			PMC_PSS_BIT_LPE},
162 	{"UFS",			PMC_PSS_BIT_CHT_UFS},
163 	{"UXD",			PMC_PSS_BIT_CHT_UXD},
164 	{"UXD_FD",		PMC_PSS_BIT_CHT_UXD_FD},
165 	{"UX_ENG",		PMC_PSS_BIT_CHT_UX_ENG},
166 	{"USB_SUS",		PMC_PSS_BIT_CHT_USB_SUS},
167 	{"GMM",			PMC_PSS_BIT_CHT_GMM},
168 	{"ISH",			PMC_PSS_BIT_CHT_ISH},
169 	{"DFX_MASTER",		PMC_PSS_BIT_CHT_DFX_MASTER},
170 	{"DFX_CLUSTER1",	PMC_PSS_BIT_CHT_DFX_CLUSTER1},
171 	{"DFX_CLUSTER2",	PMC_PSS_BIT_CHT_DFX_CLUSTER2},
172 	{"DFX_CLUSTER3",	PMC_PSS_BIT_CHT_DFX_CLUSTER3},
173 	{"DFX_CLUSTER4",	PMC_PSS_BIT_CHT_DFX_CLUSTER4},
174 	{"DFX_CLUSTER5",	PMC_PSS_BIT_CHT_DFX_CLUSTER5},
175 	{}
176 };
177 
178 static const struct pmc_reg_map byt_reg_map = {
179 	.d3_sts_0	= d3_sts_0_map,
180 	.d3_sts_1	= byt_d3_sts_1_map,
181 	.func_dis	= d3_sts_0_map,
182 	.func_dis_2	= byt_d3_sts_1_map,
183 	.pss		= byt_pss_map,
184 };
185 
186 static const struct pmc_reg_map cht_reg_map = {
187 	.d3_sts_0	= d3_sts_0_map,
188 	.d3_sts_1	= cht_d3_sts_1_map,
189 	.func_dis	= d3_sts_0_map,
190 	.func_dis_2	= cht_func_dis_2_map,
191 	.pss		= cht_pss_map,
192 };
193 
194 static const struct pmc_data byt_data = {
195 	.map = &byt_reg_map,
196 	.clks = byt_clks,
197 };
198 
199 static const struct pmc_data cht_data = {
200 	.map = &cht_reg_map,
201 	.clks = cht_clks,
202 };
203 
pmc_reg_read(struct pmc_dev * pmc,int reg_offset)204 static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
205 {
206 	return readl(pmc->regmap + reg_offset);
207 }
208 
pmc_reg_write(struct pmc_dev * pmc,int reg_offset,u32 val)209 static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
210 {
211 	writel(val, pmc->regmap + reg_offset);
212 }
213 
pmc_atom_read(int offset,u32 * value)214 int pmc_atom_read(int offset, u32 *value)
215 {
216 	struct pmc_dev *pmc = &pmc_device;
217 
218 	if (!pmc->init)
219 		return -ENODEV;
220 
221 	*value = pmc_reg_read(pmc, offset);
222 	return 0;
223 }
224 
pmc_power_off(void)225 static void pmc_power_off(void)
226 {
227 	u16	pm1_cnt_port;
228 	u32	pm1_cnt_value;
229 
230 	pr_info("Preparing to enter system sleep state S5\n");
231 
232 	pm1_cnt_port = acpi_base_addr + PM1_CNT;
233 
234 	pm1_cnt_value = inl(pm1_cnt_port);
235 	pm1_cnt_value &= ~SLEEP_TYPE_MASK;
236 	pm1_cnt_value |= SLEEP_TYPE_S5;
237 	pm1_cnt_value |= SLEEP_ENABLE;
238 
239 	outl(pm1_cnt_value, pm1_cnt_port);
240 }
241 
pmc_hw_reg_setup(struct pmc_dev * pmc)242 static void pmc_hw_reg_setup(struct pmc_dev *pmc)
243 {
244 	/*
245 	 * Disable PMC S0IX_WAKE_EN events coming from:
246 	 * - LPC clock run
247 	 * - GPIO_SUS ored dedicated IRQs
248 	 * - GPIO_SCORE ored dedicated IRQs
249 	 * - GPIO_SUS shared IRQ
250 	 * - GPIO_SCORE shared IRQ
251 	 */
252 	pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
253 }
254 
255 #ifdef CONFIG_DEBUG_FS
pmc_dev_state_print(struct seq_file * s,int reg_index,u32 sts,const struct pmc_bit_map * sts_map,u32 fd,const struct pmc_bit_map * fd_map)256 static void pmc_dev_state_print(struct seq_file *s, int reg_index,
257 				u32 sts, const struct pmc_bit_map *sts_map,
258 				u32 fd, const struct pmc_bit_map *fd_map)
259 {
260 	int offset = PMC_REG_BIT_WIDTH * reg_index;
261 	int index;
262 
263 	for (index = 0; sts_map[index].name; index++) {
264 		seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
265 			offset + index, sts_map[index].name,
266 			fd_map[index].bit_mask & fd ?  "Disabled" : "Enabled ",
267 			sts_map[index].bit_mask & sts ?  "D3" : "D0");
268 	}
269 }
270 
pmc_dev_state_show(struct seq_file * s,void * unused)271 static int pmc_dev_state_show(struct seq_file *s, void *unused)
272 {
273 	struct pmc_dev *pmc = s->private;
274 	const struct pmc_reg_map *m = pmc->map;
275 	u32 func_dis, func_dis_2;
276 	u32 d3_sts_0, d3_sts_1;
277 
278 	func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
279 	func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
280 	d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
281 	d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
282 
283 	/* Low part */
284 	pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
285 
286 	/* High part */
287 	pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
288 
289 	return 0;
290 }
291 
292 DEFINE_SHOW_ATTRIBUTE(pmc_dev_state);
293 
pmc_pss_state_show(struct seq_file * s,void * unused)294 static int pmc_pss_state_show(struct seq_file *s, void *unused)
295 {
296 	struct pmc_dev *pmc = s->private;
297 	const struct pmc_bit_map *map = pmc->map->pss;
298 	u32 pss = pmc_reg_read(pmc, PMC_PSS);
299 	int index;
300 
301 	for (index = 0; map[index].name; index++) {
302 		seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
303 			index, map[index].name,
304 			map[index].bit_mask & pss ? "Off" : "On");
305 	}
306 	return 0;
307 }
308 
309 DEFINE_SHOW_ATTRIBUTE(pmc_pss_state);
310 
pmc_sleep_tmr_show(struct seq_file * s,void * unused)311 static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
312 {
313 	struct pmc_dev *pmc = s->private;
314 	u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
315 
316 	s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
317 	s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
318 	s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
319 	s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
320 	s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
321 
322 	seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
323 	seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
324 	seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
325 	seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
326 	seq_printf(s, "S0   Residency:\t%lldus\n", s0_tmr);
327 	return 0;
328 }
329 
330 DEFINE_SHOW_ATTRIBUTE(pmc_sleep_tmr);
331 
pmc_dbgfs_register(struct pmc_dev * pmc)332 static void pmc_dbgfs_register(struct pmc_dev *pmc)
333 {
334 	struct dentry *dir;
335 
336 	dir = debugfs_create_dir("pmc_atom", NULL);
337 
338 	pmc->dbgfs_dir = dir;
339 
340 	debugfs_create_file("dev_state", S_IFREG | S_IRUGO, dir, pmc,
341 			    &pmc_dev_state_fops);
342 	debugfs_create_file("pss_state", S_IFREG | S_IRUGO, dir, pmc,
343 			    &pmc_pss_state_fops);
344 	debugfs_create_file("sleep_state", S_IFREG | S_IRUGO, dir, pmc,
345 			    &pmc_sleep_tmr_fops);
346 }
347 #else
pmc_dbgfs_register(struct pmc_dev * pmc)348 static void pmc_dbgfs_register(struct pmc_dev *pmc)
349 {
350 }
351 #endif /* CONFIG_DEBUG_FS */
352 
353 static bool pmc_clk_is_critical = true;
354 
dmi_callback(const struct dmi_system_id * d)355 static int dmi_callback(const struct dmi_system_id *d)
356 {
357 	pr_info("%s: PMC critical clocks quirk enabled\n", d->ident);
358 
359 	return 1;
360 }
361 
dmi_callback_siemens(const struct dmi_system_id * d)362 static int dmi_callback_siemens(const struct dmi_system_id *d)
363 {
364 	u32 st_id;
365 
366 	if (dmi_walk(simatic_ipc_find_dmi_entry_helper, &st_id))
367 		goto out;
368 
369 	if (st_id == SIMATIC_IPC_IPC227E || st_id == SIMATIC_IPC_IPC277E)
370 		return dmi_callback(d);
371 
372 out:
373 	pmc_clk_is_critical = false;
374 	return 1;
375 }
376 
377 /*
378  * Some systems need one or more of their pmc_plt_clks to be
379  * marked as critical.
380  */
381 static const struct dmi_system_id critclk_systems[] = {
382 	{
383 		/* pmc_plt_clk0 is used for an external HSIC USB HUB */
384 		.ident = "MPL CEC1x",
385 		.callback = dmi_callback,
386 		.matches = {
387 			DMI_MATCH(DMI_SYS_VENDOR, "MPL AG"),
388 			DMI_MATCH(DMI_PRODUCT_NAME, "CEC10 Family"),
389 		},
390 	},
391 	{
392 		/*
393 		 * Lex System / Lex Computech Co. makes a lot of Bay Trail
394 		 * based embedded boards which often come with multiple
395 		 * ethernet controllers using multiple pmc_plt_clks. See:
396 		 * https://www.lex.com.tw/products/embedded-ipc-board/
397 		 */
398 		.ident = "Lex BayTrail",
399 		.callback = dmi_callback,
400 		.matches = {
401 			DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
402 		},
403 	},
404 	{
405 		/* pmc_plt_clk* - are used for ethernet controllers */
406 		.ident = "Beckhoff Baytrail",
407 		.callback = dmi_callback,
408 		.matches = {
409 			DMI_MATCH(DMI_SYS_VENDOR, "Beckhoff Automation"),
410 			DMI_MATCH(DMI_PRODUCT_FAMILY, "CBxx63"),
411 		},
412 	},
413 	{
414 		.ident = "SIEMENS AG",
415 		.callback = dmi_callback_siemens,
416 		.matches = {
417 			DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
418 		},
419 	},
420 	{}
421 };
422 
pmc_setup_clks(struct pci_dev * pdev,void __iomem * pmc_regmap,const struct pmc_data * pmc_data)423 static int pmc_setup_clks(struct pci_dev *pdev, void __iomem *pmc_regmap,
424 			  const struct pmc_data *pmc_data)
425 {
426 	struct platform_device *clkdev;
427 	struct pmc_clk_data *clk_data;
428 
429 	clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
430 	if (!clk_data)
431 		return -ENOMEM;
432 
433 	clk_data->base = pmc_regmap; /* offset is added by client */
434 	clk_data->clks = pmc_data->clks;
435 	if (dmi_check_system(critclk_systems))
436 		clk_data->critical = pmc_clk_is_critical;
437 
438 	clkdev = platform_device_register_data(&pdev->dev, "clk-pmc-atom",
439 					       PLATFORM_DEVID_NONE,
440 					       clk_data, sizeof(*clk_data));
441 	if (IS_ERR(clkdev)) {
442 		kfree(clk_data);
443 		return PTR_ERR(clkdev);
444 	}
445 
446 	kfree(clk_data);
447 
448 	return 0;
449 }
450 
pmc_setup_dev(struct pci_dev * pdev,const struct pci_device_id * ent)451 static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
452 {
453 	struct pmc_dev *pmc = &pmc_device;
454 	const struct pmc_data *data = (struct pmc_data *)ent->driver_data;
455 	const struct pmc_reg_map *map = data->map;
456 	int ret;
457 
458 	/* Obtain ACPI base address */
459 	pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
460 	acpi_base_addr &= ACPI_BASE_ADDR_MASK;
461 
462 	/* Install power off function */
463 	if (acpi_base_addr != 0 && pm_power_off == NULL)
464 		pm_power_off = pmc_power_off;
465 
466 	pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
467 	pmc->base_addr &= PMC_BASE_ADDR_MASK;
468 
469 	pmc->regmap = ioremap(pmc->base_addr, PMC_MMIO_REG_LEN);
470 	if (!pmc->regmap) {
471 		dev_err(&pdev->dev, "error: ioremap failed\n");
472 		return -ENOMEM;
473 	}
474 
475 	pmc->map = map;
476 
477 	/* PMC hardware registers setup */
478 	pmc_hw_reg_setup(pmc);
479 
480 	pmc_dbgfs_register(pmc);
481 
482 	/* Register platform clocks - PMC_PLT_CLK [0..5] */
483 	ret = pmc_setup_clks(pdev, pmc->regmap, data);
484 	if (ret)
485 		dev_warn(&pdev->dev, "platform clocks register failed: %d\n",
486 			 ret);
487 
488 	pmc->init = true;
489 	return ret;
490 }
491 
492 /* Data for PCI driver interface used by pci_match_id() call below */
493 static const struct pci_device_id pmc_pci_ids[] = {
494 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_data },
495 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_data },
496 	{}
497 };
498 
pmc_atom_init(void)499 static int __init pmc_atom_init(void)
500 {
501 	struct pci_dev *pdev = NULL;
502 	const struct pci_device_id *ent;
503 
504 	/*
505 	 * We look for our device - PCU PMC.
506 	 * We assume that there is maximum one device.
507 	 *
508 	 * We can't use plain pci_driver mechanism,
509 	 * as the device is really a multiple function device,
510 	 * main driver that binds to the pci_device is lpc_ich
511 	 * and have to find & bind to the device this way.
512 	 */
513 	for_each_pci_dev(pdev) {
514 		ent = pci_match_id(pmc_pci_ids, pdev);
515 		if (ent)
516 			return pmc_setup_dev(pdev, ent);
517 	}
518 	/* Device not found */
519 	return -ENODEV;
520 }
521 
522 device_initcall(pmc_atom_init);
523 
524 /*
525 MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
526 MODULE_DESCRIPTION("Intel Atom SoC Power Management Controller Interface");
527 MODULE_LICENSE("GPL v2");
528 */
529