xref: /openbmc/linux/drivers/platform/x86/pmc_atom.c (revision b995dcca)
180a7581fSIrina Tirdea /*
280a7581fSIrina Tirdea  * Intel Atom SOC Power Management Controller Driver
380a7581fSIrina Tirdea  * Copyright (c) 2014, Intel Corporation.
480a7581fSIrina Tirdea  *
580a7581fSIrina Tirdea  * This program is free software; you can redistribute it and/or modify it
680a7581fSIrina Tirdea  * under the terms and conditions of the GNU General Public License,
780a7581fSIrina Tirdea  * version 2, as published by the Free Software Foundation.
880a7581fSIrina Tirdea  *
980a7581fSIrina Tirdea  * This program is distributed in the hope it will be useful, but WITHOUT
1080a7581fSIrina Tirdea  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
1180a7581fSIrina Tirdea  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
1280a7581fSIrina Tirdea  * more details.
1380a7581fSIrina Tirdea  *
1480a7581fSIrina Tirdea  */
1580a7581fSIrina Tirdea 
1680a7581fSIrina Tirdea #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
1780a7581fSIrina Tirdea 
1880a7581fSIrina Tirdea #include <linux/debugfs.h>
1980a7581fSIrina Tirdea #include <linux/device.h>
207c2e0713SDavid Müller #include <linux/dmi.h>
2180a7581fSIrina Tirdea #include <linux/init.h>
2280a7581fSIrina Tirdea #include <linux/io.h>
23282a4e4cSIrina Tirdea #include <linux/platform_data/x86/clk-pmc-atom.h>
2480a7581fSIrina Tirdea #include <linux/platform_data/x86/pmc_atom.h>
25282a4e4cSIrina Tirdea #include <linux/platform_device.h>
2680a7581fSIrina Tirdea #include <linux/pci.h>
2780a7581fSIrina Tirdea #include <linux/seq_file.h>
2880a7581fSIrina Tirdea 
2980a7581fSIrina Tirdea struct pmc_bit_map {
3080a7581fSIrina Tirdea 	const char *name;
3180a7581fSIrina Tirdea 	u32 bit_mask;
3280a7581fSIrina Tirdea };
3380a7581fSIrina Tirdea 
3480a7581fSIrina Tirdea struct pmc_reg_map {
3580a7581fSIrina Tirdea 	const struct pmc_bit_map *d3_sts_0;
3680a7581fSIrina Tirdea 	const struct pmc_bit_map *d3_sts_1;
3780a7581fSIrina Tirdea 	const struct pmc_bit_map *func_dis;
3880a7581fSIrina Tirdea 	const struct pmc_bit_map *func_dis_2;
3980a7581fSIrina Tirdea 	const struct pmc_bit_map *pss;
4080a7581fSIrina Tirdea };
4180a7581fSIrina Tirdea 
42282a4e4cSIrina Tirdea struct pmc_data {
43282a4e4cSIrina Tirdea 	const struct pmc_reg_map *map;
44282a4e4cSIrina Tirdea 	const struct pmc_clk *clks;
45282a4e4cSIrina Tirdea };
46282a4e4cSIrina Tirdea 
4780a7581fSIrina Tirdea struct pmc_dev {
4880a7581fSIrina Tirdea 	u32 base_addr;
4980a7581fSIrina Tirdea 	void __iomem *regmap;
5080a7581fSIrina Tirdea 	const struct pmc_reg_map *map;
5180a7581fSIrina Tirdea #ifdef CONFIG_DEBUG_FS
5280a7581fSIrina Tirdea 	struct dentry *dbgfs_dir;
5380a7581fSIrina Tirdea #endif /* CONFIG_DEBUG_FS */
5480a7581fSIrina Tirdea 	bool init;
5580a7581fSIrina Tirdea };
5680a7581fSIrina Tirdea 
5780a7581fSIrina Tirdea static struct pmc_dev pmc_device;
5880a7581fSIrina Tirdea static u32 acpi_base_addr;
5980a7581fSIrina Tirdea 
60282a4e4cSIrina Tirdea static const struct pmc_clk byt_clks[] = {
61282a4e4cSIrina Tirdea 	{
62282a4e4cSIrina Tirdea 		.name = "xtal",
63282a4e4cSIrina Tirdea 		.freq = 25000000,
64282a4e4cSIrina Tirdea 		.parent_name = NULL,
65282a4e4cSIrina Tirdea 	},
66282a4e4cSIrina Tirdea 	{
67282a4e4cSIrina Tirdea 		.name = "pll",
68282a4e4cSIrina Tirdea 		.freq = 19200000,
69282a4e4cSIrina Tirdea 		.parent_name = "xtal",
70282a4e4cSIrina Tirdea 	},
71282a4e4cSIrina Tirdea 	{},
72282a4e4cSIrina Tirdea };
73282a4e4cSIrina Tirdea 
74282a4e4cSIrina Tirdea static const struct pmc_clk cht_clks[] = {
75282a4e4cSIrina Tirdea 	{
76282a4e4cSIrina Tirdea 		.name = "xtal",
77282a4e4cSIrina Tirdea 		.freq = 19200000,
78282a4e4cSIrina Tirdea 		.parent_name = NULL,
79282a4e4cSIrina Tirdea 	},
80282a4e4cSIrina Tirdea 	{},
81282a4e4cSIrina Tirdea };
82282a4e4cSIrina Tirdea 
8380a7581fSIrina Tirdea static const struct pmc_bit_map d3_sts_0_map[] = {
8480a7581fSIrina Tirdea 	{"LPSS1_F0_DMA",	BIT_LPSS1_F0_DMA},
8580a7581fSIrina Tirdea 	{"LPSS1_F1_PWM1",	BIT_LPSS1_F1_PWM1},
8680a7581fSIrina Tirdea 	{"LPSS1_F2_PWM2",	BIT_LPSS1_F2_PWM2},
8780a7581fSIrina Tirdea 	{"LPSS1_F3_HSUART1",	BIT_LPSS1_F3_HSUART1},
8880a7581fSIrina Tirdea 	{"LPSS1_F4_HSUART2",	BIT_LPSS1_F4_HSUART2},
8980a7581fSIrina Tirdea 	{"LPSS1_F5_SPI",	BIT_LPSS1_F5_SPI},
9080a7581fSIrina Tirdea 	{"LPSS1_F6_Reserved",	BIT_LPSS1_F6_XXX},
9180a7581fSIrina Tirdea 	{"LPSS1_F7_Reserved",	BIT_LPSS1_F7_XXX},
9280a7581fSIrina Tirdea 	{"SCC_EMMC",		BIT_SCC_EMMC},
9380a7581fSIrina Tirdea 	{"SCC_SDIO",		BIT_SCC_SDIO},
9480a7581fSIrina Tirdea 	{"SCC_SDCARD",		BIT_SCC_SDCARD},
9580a7581fSIrina Tirdea 	{"SCC_MIPI",		BIT_SCC_MIPI},
9680a7581fSIrina Tirdea 	{"HDA",			BIT_HDA},
9780a7581fSIrina Tirdea 	{"LPE",			BIT_LPE},
9880a7581fSIrina Tirdea 	{"OTG",			BIT_OTG},
9980a7581fSIrina Tirdea 	{"USH",			BIT_USH},
10080a7581fSIrina Tirdea 	{"GBE",			BIT_GBE},
10180a7581fSIrina Tirdea 	{"SATA",		BIT_SATA},
10280a7581fSIrina Tirdea 	{"USB_EHCI",		BIT_USB_EHCI},
10380a7581fSIrina Tirdea 	{"SEC",			BIT_SEC},
10480a7581fSIrina Tirdea 	{"PCIE_PORT0",		BIT_PCIE_PORT0},
10580a7581fSIrina Tirdea 	{"PCIE_PORT1",		BIT_PCIE_PORT1},
10680a7581fSIrina Tirdea 	{"PCIE_PORT2",		BIT_PCIE_PORT2},
10780a7581fSIrina Tirdea 	{"PCIE_PORT3",		BIT_PCIE_PORT3},
10880a7581fSIrina Tirdea 	{"LPSS2_F0_DMA",	BIT_LPSS2_F0_DMA},
10980a7581fSIrina Tirdea 	{"LPSS2_F1_I2C1",	BIT_LPSS2_F1_I2C1},
11080a7581fSIrina Tirdea 	{"LPSS2_F2_I2C2",	BIT_LPSS2_F2_I2C2},
11180a7581fSIrina Tirdea 	{"LPSS2_F3_I2C3",	BIT_LPSS2_F3_I2C3},
11280a7581fSIrina Tirdea 	{"LPSS2_F3_I2C4",	BIT_LPSS2_F4_I2C4},
11380a7581fSIrina Tirdea 	{"LPSS2_F5_I2C5",	BIT_LPSS2_F5_I2C5},
11480a7581fSIrina Tirdea 	{"LPSS2_F6_I2C6",	BIT_LPSS2_F6_I2C6},
11580a7581fSIrina Tirdea 	{"LPSS2_F7_I2C7",	BIT_LPSS2_F7_I2C7},
11680a7581fSIrina Tirdea 	{},
11780a7581fSIrina Tirdea };
11880a7581fSIrina Tirdea 
11980a7581fSIrina Tirdea static struct pmc_bit_map byt_d3_sts_1_map[] = {
12080a7581fSIrina Tirdea 	{"SMB",			BIT_SMB},
12180a7581fSIrina Tirdea 	{"OTG_SS_PHY",		BIT_OTG_SS_PHY},
12280a7581fSIrina Tirdea 	{"USH_SS_PHY",		BIT_USH_SS_PHY},
12380a7581fSIrina Tirdea 	{"DFX",			BIT_DFX},
12480a7581fSIrina Tirdea 	{},
12580a7581fSIrina Tirdea };
12680a7581fSIrina Tirdea 
12780a7581fSIrina Tirdea static struct pmc_bit_map cht_d3_sts_1_map[] = {
12880a7581fSIrina Tirdea 	{"SMB",			BIT_SMB},
12980a7581fSIrina Tirdea 	{"GMM",			BIT_STS_GMM},
13080a7581fSIrina Tirdea 	{"ISH",			BIT_STS_ISH},
13180a7581fSIrina Tirdea 	{},
13280a7581fSIrina Tirdea };
13380a7581fSIrina Tirdea 
13480a7581fSIrina Tirdea static struct pmc_bit_map cht_func_dis_2_map[] = {
13580a7581fSIrina Tirdea 	{"SMB",			BIT_SMB},
13680a7581fSIrina Tirdea 	{"GMM",			BIT_FD_GMM},
13780a7581fSIrina Tirdea 	{"ISH",			BIT_FD_ISH},
13880a7581fSIrina Tirdea 	{},
13980a7581fSIrina Tirdea };
14080a7581fSIrina Tirdea 
14180a7581fSIrina Tirdea static const struct pmc_bit_map byt_pss_map[] = {
14280a7581fSIrina Tirdea 	{"GBE",			PMC_PSS_BIT_GBE},
14380a7581fSIrina Tirdea 	{"SATA",		PMC_PSS_BIT_SATA},
14480a7581fSIrina Tirdea 	{"HDA",			PMC_PSS_BIT_HDA},
14580a7581fSIrina Tirdea 	{"SEC",			PMC_PSS_BIT_SEC},
14680a7581fSIrina Tirdea 	{"PCIE",		PMC_PSS_BIT_PCIE},
14780a7581fSIrina Tirdea 	{"LPSS",		PMC_PSS_BIT_LPSS},
14880a7581fSIrina Tirdea 	{"LPE",			PMC_PSS_BIT_LPE},
14980a7581fSIrina Tirdea 	{"DFX",			PMC_PSS_BIT_DFX},
15080a7581fSIrina Tirdea 	{"USH_CTRL",		PMC_PSS_BIT_USH_CTRL},
15180a7581fSIrina Tirdea 	{"USH_SUS",		PMC_PSS_BIT_USH_SUS},
15280a7581fSIrina Tirdea 	{"USH_VCCS",		PMC_PSS_BIT_USH_VCCS},
15380a7581fSIrina Tirdea 	{"USH_VCCA",		PMC_PSS_BIT_USH_VCCA},
15480a7581fSIrina Tirdea 	{"OTG_CTRL",		PMC_PSS_BIT_OTG_CTRL},
15580a7581fSIrina Tirdea 	{"OTG_VCCS",		PMC_PSS_BIT_OTG_VCCS},
15680a7581fSIrina Tirdea 	{"OTG_VCCA_CLK",	PMC_PSS_BIT_OTG_VCCA_CLK},
15780a7581fSIrina Tirdea 	{"OTG_VCCA",		PMC_PSS_BIT_OTG_VCCA},
15880a7581fSIrina Tirdea 	{"USB",			PMC_PSS_BIT_USB},
15980a7581fSIrina Tirdea 	{"USB_SUS",		PMC_PSS_BIT_USB_SUS},
16080a7581fSIrina Tirdea 	{},
16180a7581fSIrina Tirdea };
16280a7581fSIrina Tirdea 
16380a7581fSIrina Tirdea static const struct pmc_bit_map cht_pss_map[] = {
16480a7581fSIrina Tirdea 	{"SATA",		PMC_PSS_BIT_SATA},
16580a7581fSIrina Tirdea 	{"HDA",			PMC_PSS_BIT_HDA},
16680a7581fSIrina Tirdea 	{"SEC",			PMC_PSS_BIT_SEC},
16780a7581fSIrina Tirdea 	{"PCIE",		PMC_PSS_BIT_PCIE},
16880a7581fSIrina Tirdea 	{"LPSS",		PMC_PSS_BIT_LPSS},
16980a7581fSIrina Tirdea 	{"LPE",			PMC_PSS_BIT_LPE},
17080a7581fSIrina Tirdea 	{"UFS",			PMC_PSS_BIT_CHT_UFS},
17180a7581fSIrina Tirdea 	{"UXD",			PMC_PSS_BIT_CHT_UXD},
17280a7581fSIrina Tirdea 	{"UXD_FD",		PMC_PSS_BIT_CHT_UXD_FD},
17380a7581fSIrina Tirdea 	{"UX_ENG",		PMC_PSS_BIT_CHT_UX_ENG},
17480a7581fSIrina Tirdea 	{"USB_SUS",		PMC_PSS_BIT_CHT_USB_SUS},
17580a7581fSIrina Tirdea 	{"GMM",			PMC_PSS_BIT_CHT_GMM},
17680a7581fSIrina Tirdea 	{"ISH",			PMC_PSS_BIT_CHT_ISH},
17780a7581fSIrina Tirdea 	{"DFX_MASTER",		PMC_PSS_BIT_CHT_DFX_MASTER},
17880a7581fSIrina Tirdea 	{"DFX_CLUSTER1",	PMC_PSS_BIT_CHT_DFX_CLUSTER1},
17980a7581fSIrina Tirdea 	{"DFX_CLUSTER2",	PMC_PSS_BIT_CHT_DFX_CLUSTER2},
18080a7581fSIrina Tirdea 	{"DFX_CLUSTER3",	PMC_PSS_BIT_CHT_DFX_CLUSTER3},
18180a7581fSIrina Tirdea 	{"DFX_CLUSTER4",	PMC_PSS_BIT_CHT_DFX_CLUSTER4},
18280a7581fSIrina Tirdea 	{"DFX_CLUSTER5",	PMC_PSS_BIT_CHT_DFX_CLUSTER5},
18380a7581fSIrina Tirdea 	{},
18480a7581fSIrina Tirdea };
18580a7581fSIrina Tirdea 
18680a7581fSIrina Tirdea static const struct pmc_reg_map byt_reg_map = {
18780a7581fSIrina Tirdea 	.d3_sts_0	= d3_sts_0_map,
18880a7581fSIrina Tirdea 	.d3_sts_1	= byt_d3_sts_1_map,
18980a7581fSIrina Tirdea 	.func_dis	= d3_sts_0_map,
19080a7581fSIrina Tirdea 	.func_dis_2	= byt_d3_sts_1_map,
19180a7581fSIrina Tirdea 	.pss		= byt_pss_map,
19280a7581fSIrina Tirdea };
19380a7581fSIrina Tirdea 
19480a7581fSIrina Tirdea static const struct pmc_reg_map cht_reg_map = {
19580a7581fSIrina Tirdea 	.d3_sts_0	= d3_sts_0_map,
19680a7581fSIrina Tirdea 	.d3_sts_1	= cht_d3_sts_1_map,
19780a7581fSIrina Tirdea 	.func_dis	= d3_sts_0_map,
19880a7581fSIrina Tirdea 	.func_dis_2	= cht_func_dis_2_map,
19980a7581fSIrina Tirdea 	.pss		= cht_pss_map,
20080a7581fSIrina Tirdea };
20180a7581fSIrina Tirdea 
202282a4e4cSIrina Tirdea static const struct pmc_data byt_data = {
203282a4e4cSIrina Tirdea 	.map = &byt_reg_map,
204282a4e4cSIrina Tirdea 	.clks = byt_clks,
205282a4e4cSIrina Tirdea };
206282a4e4cSIrina Tirdea 
207282a4e4cSIrina Tirdea static const struct pmc_data cht_data = {
208282a4e4cSIrina Tirdea 	.map = &cht_reg_map,
209282a4e4cSIrina Tirdea 	.clks = cht_clks,
210282a4e4cSIrina Tirdea };
211282a4e4cSIrina Tirdea 
21280a7581fSIrina Tirdea static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
21380a7581fSIrina Tirdea {
21480a7581fSIrina Tirdea 	return readl(pmc->regmap + reg_offset);
21580a7581fSIrina Tirdea }
21680a7581fSIrina Tirdea 
21780a7581fSIrina Tirdea static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
21880a7581fSIrina Tirdea {
21980a7581fSIrina Tirdea 	writel(val, pmc->regmap + reg_offset);
22080a7581fSIrina Tirdea }
22180a7581fSIrina Tirdea 
22280a7581fSIrina Tirdea int pmc_atom_read(int offset, u32 *value)
22380a7581fSIrina Tirdea {
22480a7581fSIrina Tirdea 	struct pmc_dev *pmc = &pmc_device;
22580a7581fSIrina Tirdea 
22680a7581fSIrina Tirdea 	if (!pmc->init)
22780a7581fSIrina Tirdea 		return -ENODEV;
22880a7581fSIrina Tirdea 
22980a7581fSIrina Tirdea 	*value = pmc_reg_read(pmc, offset);
23080a7581fSIrina Tirdea 	return 0;
23180a7581fSIrina Tirdea }
23280a7581fSIrina Tirdea EXPORT_SYMBOL_GPL(pmc_atom_read);
23380a7581fSIrina Tirdea 
23480a7581fSIrina Tirdea int pmc_atom_write(int offset, u32 value)
23580a7581fSIrina Tirdea {
23680a7581fSIrina Tirdea 	struct pmc_dev *pmc = &pmc_device;
23780a7581fSIrina Tirdea 
23880a7581fSIrina Tirdea 	if (!pmc->init)
23980a7581fSIrina Tirdea 		return -ENODEV;
24080a7581fSIrina Tirdea 
24180a7581fSIrina Tirdea 	pmc_reg_write(pmc, offset, value);
24280a7581fSIrina Tirdea 	return 0;
24380a7581fSIrina Tirdea }
24480a7581fSIrina Tirdea EXPORT_SYMBOL_GPL(pmc_atom_write);
24580a7581fSIrina Tirdea 
24680a7581fSIrina Tirdea static void pmc_power_off(void)
24780a7581fSIrina Tirdea {
24880a7581fSIrina Tirdea 	u16	pm1_cnt_port;
24980a7581fSIrina Tirdea 	u32	pm1_cnt_value;
25080a7581fSIrina Tirdea 
25180a7581fSIrina Tirdea 	pr_info("Preparing to enter system sleep state S5\n");
25280a7581fSIrina Tirdea 
25380a7581fSIrina Tirdea 	pm1_cnt_port = acpi_base_addr + PM1_CNT;
25480a7581fSIrina Tirdea 
25580a7581fSIrina Tirdea 	pm1_cnt_value = inl(pm1_cnt_port);
25680a7581fSIrina Tirdea 	pm1_cnt_value &= SLEEP_TYPE_MASK;
25780a7581fSIrina Tirdea 	pm1_cnt_value |= SLEEP_TYPE_S5;
25880a7581fSIrina Tirdea 	pm1_cnt_value |= SLEEP_ENABLE;
25980a7581fSIrina Tirdea 
26080a7581fSIrina Tirdea 	outl(pm1_cnt_value, pm1_cnt_port);
26180a7581fSIrina Tirdea }
26280a7581fSIrina Tirdea 
26380a7581fSIrina Tirdea static void pmc_hw_reg_setup(struct pmc_dev *pmc)
26480a7581fSIrina Tirdea {
26580a7581fSIrina Tirdea 	/*
26680a7581fSIrina Tirdea 	 * Disable PMC S0IX_WAKE_EN events coming from:
26780a7581fSIrina Tirdea 	 * - LPC clock run
26880a7581fSIrina Tirdea 	 * - GPIO_SUS ored dedicated IRQs
26980a7581fSIrina Tirdea 	 * - GPIO_SCORE ored dedicated IRQs
27080a7581fSIrina Tirdea 	 * - GPIO_SUS shared IRQ
27180a7581fSIrina Tirdea 	 * - GPIO_SCORE shared IRQ
27280a7581fSIrina Tirdea 	 */
27380a7581fSIrina Tirdea 	pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
27480a7581fSIrina Tirdea }
27580a7581fSIrina Tirdea 
27680a7581fSIrina Tirdea #ifdef CONFIG_DEBUG_FS
27780a7581fSIrina Tirdea static void pmc_dev_state_print(struct seq_file *s, int reg_index,
27880a7581fSIrina Tirdea 				u32 sts, const struct pmc_bit_map *sts_map,
27980a7581fSIrina Tirdea 				u32 fd, const struct pmc_bit_map *fd_map)
28080a7581fSIrina Tirdea {
28180a7581fSIrina Tirdea 	int offset = PMC_REG_BIT_WIDTH * reg_index;
28280a7581fSIrina Tirdea 	int index;
28380a7581fSIrina Tirdea 
28480a7581fSIrina Tirdea 	for (index = 0; sts_map[index].name; index++) {
28580a7581fSIrina Tirdea 		seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
28680a7581fSIrina Tirdea 			offset + index, sts_map[index].name,
28780a7581fSIrina Tirdea 			fd_map[index].bit_mask & fd ?  "Disabled" : "Enabled ",
28880a7581fSIrina Tirdea 			sts_map[index].bit_mask & sts ?  "D3" : "D0");
28980a7581fSIrina Tirdea 	}
29080a7581fSIrina Tirdea }
29180a7581fSIrina Tirdea 
29280a7581fSIrina Tirdea static int pmc_dev_state_show(struct seq_file *s, void *unused)
29380a7581fSIrina Tirdea {
29480a7581fSIrina Tirdea 	struct pmc_dev *pmc = s->private;
29580a7581fSIrina Tirdea 	const struct pmc_reg_map *m = pmc->map;
29680a7581fSIrina Tirdea 	u32 func_dis, func_dis_2;
29780a7581fSIrina Tirdea 	u32 d3_sts_0, d3_sts_1;
29880a7581fSIrina Tirdea 
29980a7581fSIrina Tirdea 	func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
30080a7581fSIrina Tirdea 	func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
30180a7581fSIrina Tirdea 	d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
30280a7581fSIrina Tirdea 	d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
30380a7581fSIrina Tirdea 
30480a7581fSIrina Tirdea 	/* Low part */
30580a7581fSIrina Tirdea 	pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
30680a7581fSIrina Tirdea 
30780a7581fSIrina Tirdea 	/* High part */
30880a7581fSIrina Tirdea 	pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
30980a7581fSIrina Tirdea 
31080a7581fSIrina Tirdea 	return 0;
31180a7581fSIrina Tirdea }
31280a7581fSIrina Tirdea 
3131ea74a56SAndy Shevchenko DEFINE_SHOW_ATTRIBUTE(pmc_dev_state);
31480a7581fSIrina Tirdea 
31580a7581fSIrina Tirdea static int pmc_pss_state_show(struct seq_file *s, void *unused)
31680a7581fSIrina Tirdea {
31780a7581fSIrina Tirdea 	struct pmc_dev *pmc = s->private;
31880a7581fSIrina Tirdea 	const struct pmc_bit_map *map = pmc->map->pss;
31980a7581fSIrina Tirdea 	u32 pss = pmc_reg_read(pmc, PMC_PSS);
32080a7581fSIrina Tirdea 	int index;
32180a7581fSIrina Tirdea 
32280a7581fSIrina Tirdea 	for (index = 0; map[index].name; index++) {
32380a7581fSIrina Tirdea 		seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
32480a7581fSIrina Tirdea 			index, map[index].name,
32580a7581fSIrina Tirdea 			map[index].bit_mask & pss ? "Off" : "On");
32680a7581fSIrina Tirdea 	}
32780a7581fSIrina Tirdea 	return 0;
32880a7581fSIrina Tirdea }
32980a7581fSIrina Tirdea 
3301ea74a56SAndy Shevchenko DEFINE_SHOW_ATTRIBUTE(pmc_pss_state);
33180a7581fSIrina Tirdea 
33280a7581fSIrina Tirdea static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
33380a7581fSIrina Tirdea {
33480a7581fSIrina Tirdea 	struct pmc_dev *pmc = s->private;
33580a7581fSIrina Tirdea 	u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
33680a7581fSIrina Tirdea 
33780a7581fSIrina Tirdea 	s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
33880a7581fSIrina Tirdea 	s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
33980a7581fSIrina Tirdea 	s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
34080a7581fSIrina Tirdea 	s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
34180a7581fSIrina Tirdea 	s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
34280a7581fSIrina Tirdea 
34380a7581fSIrina Tirdea 	seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
34480a7581fSIrina Tirdea 	seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
34580a7581fSIrina Tirdea 	seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
34680a7581fSIrina Tirdea 	seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
34780a7581fSIrina Tirdea 	seq_printf(s, "S0   Residency:\t%lldus\n", s0_tmr);
34880a7581fSIrina Tirdea 	return 0;
34980a7581fSIrina Tirdea }
35080a7581fSIrina Tirdea 
3511ea74a56SAndy Shevchenko DEFINE_SHOW_ATTRIBUTE(pmc_sleep_tmr);
35280a7581fSIrina Tirdea 
35380a7581fSIrina Tirdea static void pmc_dbgfs_unregister(struct pmc_dev *pmc)
35480a7581fSIrina Tirdea {
35580a7581fSIrina Tirdea 	debugfs_remove_recursive(pmc->dbgfs_dir);
35680a7581fSIrina Tirdea }
35780a7581fSIrina Tirdea 
35880a7581fSIrina Tirdea static int pmc_dbgfs_register(struct pmc_dev *pmc)
35980a7581fSIrina Tirdea {
36080a7581fSIrina Tirdea 	struct dentry *dir, *f;
36180a7581fSIrina Tirdea 
36280a7581fSIrina Tirdea 	dir = debugfs_create_dir("pmc_atom", NULL);
36380a7581fSIrina Tirdea 	if (!dir)
36480a7581fSIrina Tirdea 		return -ENOMEM;
36580a7581fSIrina Tirdea 
36680a7581fSIrina Tirdea 	pmc->dbgfs_dir = dir;
36780a7581fSIrina Tirdea 
36880a7581fSIrina Tirdea 	f = debugfs_create_file("dev_state", S_IFREG | S_IRUGO,
3691ea74a56SAndy Shevchenko 				dir, pmc, &pmc_dev_state_fops);
37080a7581fSIrina Tirdea 	if (!f)
37180a7581fSIrina Tirdea 		goto err;
37280a7581fSIrina Tirdea 
37380a7581fSIrina Tirdea 	f = debugfs_create_file("pss_state", S_IFREG | S_IRUGO,
3741ea74a56SAndy Shevchenko 				dir, pmc, &pmc_pss_state_fops);
37580a7581fSIrina Tirdea 	if (!f)
37680a7581fSIrina Tirdea 		goto err;
37780a7581fSIrina Tirdea 
37880a7581fSIrina Tirdea 	f = debugfs_create_file("sleep_state", S_IFREG | S_IRUGO,
3791ea74a56SAndy Shevchenko 				dir, pmc, &pmc_sleep_tmr_fops);
38080a7581fSIrina Tirdea 	if (!f)
38180a7581fSIrina Tirdea 		goto err;
38280a7581fSIrina Tirdea 
38380a7581fSIrina Tirdea 	return 0;
38480a7581fSIrina Tirdea err:
38580a7581fSIrina Tirdea 	pmc_dbgfs_unregister(pmc);
38680a7581fSIrina Tirdea 	return -ENODEV;
38780a7581fSIrina Tirdea }
38880a7581fSIrina Tirdea #else
38980a7581fSIrina Tirdea static int pmc_dbgfs_register(struct pmc_dev *pmc)
39080a7581fSIrina Tirdea {
39180a7581fSIrina Tirdea 	return 0;
39280a7581fSIrina Tirdea }
39380a7581fSIrina Tirdea #endif /* CONFIG_DEBUG_FS */
39480a7581fSIrina Tirdea 
3957c2e0713SDavid Müller /*
3967c2e0713SDavid Müller  * Some systems need one or more of their pmc_plt_clks to be
3977c2e0713SDavid Müller  * marked as critical.
3987c2e0713SDavid Müller  */
399b995dccaSStephen Boyd static const struct dmi_system_id critclk_systems[] = {
4007c2e0713SDavid Müller 	{
4017c2e0713SDavid Müller 		.ident = "MPL CEC1x",
4027c2e0713SDavid Müller 		.matches = {
4037c2e0713SDavid Müller 			DMI_MATCH(DMI_SYS_VENDOR, "MPL AG"),
4047c2e0713SDavid Müller 			DMI_MATCH(DMI_PRODUCT_NAME, "CEC10 Family"),
4057c2e0713SDavid Müller 		},
4067c2e0713SDavid Müller 	},
4077c2e0713SDavid Müller 	{ /*sentinel*/ }
4087c2e0713SDavid Müller };
4097c2e0713SDavid Müller 
410282a4e4cSIrina Tirdea static int pmc_setup_clks(struct pci_dev *pdev, void __iomem *pmc_regmap,
411282a4e4cSIrina Tirdea 			  const struct pmc_data *pmc_data)
412282a4e4cSIrina Tirdea {
413282a4e4cSIrina Tirdea 	struct platform_device *clkdev;
414282a4e4cSIrina Tirdea 	struct pmc_clk_data *clk_data;
4157c2e0713SDavid Müller 	const struct dmi_system_id *d = dmi_first_match(critclk_systems);
416282a4e4cSIrina Tirdea 
417282a4e4cSIrina Tirdea 	clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
418282a4e4cSIrina Tirdea 	if (!clk_data)
419282a4e4cSIrina Tirdea 		return -ENOMEM;
420282a4e4cSIrina Tirdea 
421282a4e4cSIrina Tirdea 	clk_data->base = pmc_regmap; /* offset is added by client */
422282a4e4cSIrina Tirdea 	clk_data->clks = pmc_data->clks;
4237c2e0713SDavid Müller 	if (d) {
4247c2e0713SDavid Müller 		clk_data->critical = true;
4257c2e0713SDavid Müller 		pr_info("%s critclks quirk enabled\n", d->ident);
4267c2e0713SDavid Müller 	}
427282a4e4cSIrina Tirdea 
428282a4e4cSIrina Tirdea 	clkdev = platform_device_register_data(&pdev->dev, "clk-pmc-atom",
429282a4e4cSIrina Tirdea 					       PLATFORM_DEVID_NONE,
430282a4e4cSIrina Tirdea 					       clk_data, sizeof(*clk_data));
431282a4e4cSIrina Tirdea 	if (IS_ERR(clkdev)) {
432282a4e4cSIrina Tirdea 		kfree(clk_data);
433282a4e4cSIrina Tirdea 		return PTR_ERR(clkdev);
434282a4e4cSIrina Tirdea 	}
435282a4e4cSIrina Tirdea 
436282a4e4cSIrina Tirdea 	kfree(clk_data);
437282a4e4cSIrina Tirdea 
438282a4e4cSIrina Tirdea 	return 0;
439282a4e4cSIrina Tirdea }
440282a4e4cSIrina Tirdea 
44180a7581fSIrina Tirdea static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
44280a7581fSIrina Tirdea {
44380a7581fSIrina Tirdea 	struct pmc_dev *pmc = &pmc_device;
444282a4e4cSIrina Tirdea 	const struct pmc_data *data = (struct pmc_data *)ent->driver_data;
445282a4e4cSIrina Tirdea 	const struct pmc_reg_map *map = data->map;
44680a7581fSIrina Tirdea 	int ret;
44780a7581fSIrina Tirdea 
44880a7581fSIrina Tirdea 	/* Obtain ACPI base address */
44980a7581fSIrina Tirdea 	pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
45080a7581fSIrina Tirdea 	acpi_base_addr &= ACPI_BASE_ADDR_MASK;
45180a7581fSIrina Tirdea 
45280a7581fSIrina Tirdea 	/* Install power off function */
45380a7581fSIrina Tirdea 	if (acpi_base_addr != 0 && pm_power_off == NULL)
45480a7581fSIrina Tirdea 		pm_power_off = pmc_power_off;
45580a7581fSIrina Tirdea 
45680a7581fSIrina Tirdea 	pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
45780a7581fSIrina Tirdea 	pmc->base_addr &= PMC_BASE_ADDR_MASK;
45880a7581fSIrina Tirdea 
45980a7581fSIrina Tirdea 	pmc->regmap = ioremap_nocache(pmc->base_addr, PMC_MMIO_REG_LEN);
46080a7581fSIrina Tirdea 	if (!pmc->regmap) {
46180a7581fSIrina Tirdea 		dev_err(&pdev->dev, "error: ioremap failed\n");
46280a7581fSIrina Tirdea 		return -ENOMEM;
46380a7581fSIrina Tirdea 	}
46480a7581fSIrina Tirdea 
46580a7581fSIrina Tirdea 	pmc->map = map;
46680a7581fSIrina Tirdea 
46780a7581fSIrina Tirdea 	/* PMC hardware registers setup */
46880a7581fSIrina Tirdea 	pmc_hw_reg_setup(pmc);
46980a7581fSIrina Tirdea 
47080a7581fSIrina Tirdea 	ret = pmc_dbgfs_register(pmc);
47180a7581fSIrina Tirdea 	if (ret)
47280a7581fSIrina Tirdea 		dev_warn(&pdev->dev, "debugfs register failed\n");
47380a7581fSIrina Tirdea 
474282a4e4cSIrina Tirdea 	/* Register platform clocks - PMC_PLT_CLK [0..5] */
475282a4e4cSIrina Tirdea 	ret = pmc_setup_clks(pdev, pmc->regmap, data);
476282a4e4cSIrina Tirdea 	if (ret)
477282a4e4cSIrina Tirdea 		dev_warn(&pdev->dev, "platform clocks register failed: %d\n",
478282a4e4cSIrina Tirdea 			 ret);
479282a4e4cSIrina Tirdea 
48080a7581fSIrina Tirdea 	pmc->init = true;
48180a7581fSIrina Tirdea 	return ret;
48280a7581fSIrina Tirdea }
48380a7581fSIrina Tirdea 
48480a7581fSIrina Tirdea /*
48580a7581fSIrina Tirdea  * Data for PCI driver interface
48680a7581fSIrina Tirdea  *
48780a7581fSIrina Tirdea  * used by pci_match_id() call below.
48880a7581fSIrina Tirdea  */
48980a7581fSIrina Tirdea static const struct pci_device_id pmc_pci_ids[] = {
490282a4e4cSIrina Tirdea 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_data },
491282a4e4cSIrina Tirdea 	{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_data },
49280a7581fSIrina Tirdea 	{ 0, },
49380a7581fSIrina Tirdea };
49480a7581fSIrina Tirdea 
49580a7581fSIrina Tirdea static int __init pmc_atom_init(void)
49680a7581fSIrina Tirdea {
49780a7581fSIrina Tirdea 	struct pci_dev *pdev = NULL;
49880a7581fSIrina Tirdea 	const struct pci_device_id *ent;
49980a7581fSIrina Tirdea 
50080a7581fSIrina Tirdea 	/* We look for our device - PCU PMC
50180a7581fSIrina Tirdea 	 * we assume that there is max. one device.
50280a7581fSIrina Tirdea 	 *
50380a7581fSIrina Tirdea 	 * We can't use plain pci_driver mechanism,
50480a7581fSIrina Tirdea 	 * as the device is really a multiple function device,
50580a7581fSIrina Tirdea 	 * main driver that binds to the pci_device is lpc_ich
50680a7581fSIrina Tirdea 	 * and have to find & bind to the device this way.
50780a7581fSIrina Tirdea 	 */
50880a7581fSIrina Tirdea 	for_each_pci_dev(pdev) {
50980a7581fSIrina Tirdea 		ent = pci_match_id(pmc_pci_ids, pdev);
51080a7581fSIrina Tirdea 		if (ent)
51180a7581fSIrina Tirdea 			return pmc_setup_dev(pdev, ent);
51280a7581fSIrina Tirdea 	}
51380a7581fSIrina Tirdea 	/* Device not found. */
51480a7581fSIrina Tirdea 	return -ENODEV;
51580a7581fSIrina Tirdea }
51680a7581fSIrina Tirdea 
51780a7581fSIrina Tirdea device_initcall(pmc_atom_init);
51880a7581fSIrina Tirdea 
51980a7581fSIrina Tirdea /*
52080a7581fSIrina Tirdea MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
52180a7581fSIrina Tirdea MODULE_DESCRIPTION("Intel Atom SOC Power Management Controller Interface");
52280a7581fSIrina Tirdea MODULE_LICENSE("GPL v2");
52380a7581fSIrina Tirdea */
524