12025cf9eSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
280a7581fSIrina Tirdea /*
3*5a88ace4SAndy Shevchenko * Intel Atom SoC Power Management Controller Driver
4*5a88ace4SAndy Shevchenko * Copyright (c) 2014-2015,2017,2022 Intel Corporation.
580a7581fSIrina Tirdea */
680a7581fSIrina Tirdea
780a7581fSIrina Tirdea #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
880a7581fSIrina Tirdea
980a7581fSIrina Tirdea #include <linux/debugfs.h>
1080a7581fSIrina Tirdea #include <linux/device.h>
117c2e0713SDavid Müller #include <linux/dmi.h>
1280a7581fSIrina Tirdea #include <linux/init.h>
1380a7581fSIrina Tirdea #include <linux/io.h>
14282a4e4cSIrina Tirdea #include <linux/platform_data/x86/clk-pmc-atom.h>
1580a7581fSIrina Tirdea #include <linux/platform_data/x86/pmc_atom.h>
164ba0b818SHenning Schild #include <linux/platform_data/x86/simatic-ipc.h>
17282a4e4cSIrina Tirdea #include <linux/platform_device.h>
1880a7581fSIrina Tirdea #include <linux/pci.h>
1980a7581fSIrina Tirdea #include <linux/seq_file.h>
2080a7581fSIrina Tirdea
2180a7581fSIrina Tirdea struct pmc_bit_map {
2280a7581fSIrina Tirdea const char *name;
2380a7581fSIrina Tirdea u32 bit_mask;
2480a7581fSIrina Tirdea };
2580a7581fSIrina Tirdea
2680a7581fSIrina Tirdea struct pmc_reg_map {
2780a7581fSIrina Tirdea const struct pmc_bit_map *d3_sts_0;
2880a7581fSIrina Tirdea const struct pmc_bit_map *d3_sts_1;
2980a7581fSIrina Tirdea const struct pmc_bit_map *func_dis;
3080a7581fSIrina Tirdea const struct pmc_bit_map *func_dis_2;
3180a7581fSIrina Tirdea const struct pmc_bit_map *pss;
3280a7581fSIrina Tirdea };
3380a7581fSIrina Tirdea
34282a4e4cSIrina Tirdea struct pmc_data {
35282a4e4cSIrina Tirdea const struct pmc_reg_map *map;
36282a4e4cSIrina Tirdea const struct pmc_clk *clks;
37282a4e4cSIrina Tirdea };
38282a4e4cSIrina Tirdea
3980a7581fSIrina Tirdea struct pmc_dev {
4080a7581fSIrina Tirdea u32 base_addr;
4180a7581fSIrina Tirdea void __iomem *regmap;
4280a7581fSIrina Tirdea const struct pmc_reg_map *map;
4380a7581fSIrina Tirdea #ifdef CONFIG_DEBUG_FS
4480a7581fSIrina Tirdea struct dentry *dbgfs_dir;
4580a7581fSIrina Tirdea #endif /* CONFIG_DEBUG_FS */
4680a7581fSIrina Tirdea bool init;
4780a7581fSIrina Tirdea };
4880a7581fSIrina Tirdea
4980a7581fSIrina Tirdea static struct pmc_dev pmc_device;
5080a7581fSIrina Tirdea static u32 acpi_base_addr;
5180a7581fSIrina Tirdea
52282a4e4cSIrina Tirdea static const struct pmc_clk byt_clks[] = {
53282a4e4cSIrina Tirdea {
54282a4e4cSIrina Tirdea .name = "xtal",
55282a4e4cSIrina Tirdea .freq = 25000000,
56282a4e4cSIrina Tirdea .parent_name = NULL,
57282a4e4cSIrina Tirdea },
58282a4e4cSIrina Tirdea {
59282a4e4cSIrina Tirdea .name = "pll",
60282a4e4cSIrina Tirdea .freq = 19200000,
61282a4e4cSIrina Tirdea .parent_name = "xtal",
62282a4e4cSIrina Tirdea },
6327526525SAndy Shevchenko {}
64282a4e4cSIrina Tirdea };
65282a4e4cSIrina Tirdea
66282a4e4cSIrina Tirdea static const struct pmc_clk cht_clks[] = {
67282a4e4cSIrina Tirdea {
68282a4e4cSIrina Tirdea .name = "xtal",
69282a4e4cSIrina Tirdea .freq = 19200000,
70282a4e4cSIrina Tirdea .parent_name = NULL,
71282a4e4cSIrina Tirdea },
7227526525SAndy Shevchenko {}
73282a4e4cSIrina Tirdea };
74282a4e4cSIrina Tirdea
7580a7581fSIrina Tirdea static const struct pmc_bit_map d3_sts_0_map[] = {
7680a7581fSIrina Tirdea {"LPSS1_F0_DMA", BIT_LPSS1_F0_DMA},
7780a7581fSIrina Tirdea {"LPSS1_F1_PWM1", BIT_LPSS1_F1_PWM1},
7880a7581fSIrina Tirdea {"LPSS1_F2_PWM2", BIT_LPSS1_F2_PWM2},
7980a7581fSIrina Tirdea {"LPSS1_F3_HSUART1", BIT_LPSS1_F3_HSUART1},
8080a7581fSIrina Tirdea {"LPSS1_F4_HSUART2", BIT_LPSS1_F4_HSUART2},
8180a7581fSIrina Tirdea {"LPSS1_F5_SPI", BIT_LPSS1_F5_SPI},
8280a7581fSIrina Tirdea {"LPSS1_F6_Reserved", BIT_LPSS1_F6_XXX},
8380a7581fSIrina Tirdea {"LPSS1_F7_Reserved", BIT_LPSS1_F7_XXX},
8480a7581fSIrina Tirdea {"SCC_EMMC", BIT_SCC_EMMC},
8580a7581fSIrina Tirdea {"SCC_SDIO", BIT_SCC_SDIO},
8680a7581fSIrina Tirdea {"SCC_SDCARD", BIT_SCC_SDCARD},
8780a7581fSIrina Tirdea {"SCC_MIPI", BIT_SCC_MIPI},
8880a7581fSIrina Tirdea {"HDA", BIT_HDA},
8980a7581fSIrina Tirdea {"LPE", BIT_LPE},
9080a7581fSIrina Tirdea {"OTG", BIT_OTG},
9180a7581fSIrina Tirdea {"USH", BIT_USH},
9280a7581fSIrina Tirdea {"GBE", BIT_GBE},
9380a7581fSIrina Tirdea {"SATA", BIT_SATA},
9480a7581fSIrina Tirdea {"USB_EHCI", BIT_USB_EHCI},
9580a7581fSIrina Tirdea {"SEC", BIT_SEC},
9680a7581fSIrina Tirdea {"PCIE_PORT0", BIT_PCIE_PORT0},
9780a7581fSIrina Tirdea {"PCIE_PORT1", BIT_PCIE_PORT1},
9880a7581fSIrina Tirdea {"PCIE_PORT2", BIT_PCIE_PORT2},
9980a7581fSIrina Tirdea {"PCIE_PORT3", BIT_PCIE_PORT3},
10080a7581fSIrina Tirdea {"LPSS2_F0_DMA", BIT_LPSS2_F0_DMA},
10180a7581fSIrina Tirdea {"LPSS2_F1_I2C1", BIT_LPSS2_F1_I2C1},
10280a7581fSIrina Tirdea {"LPSS2_F2_I2C2", BIT_LPSS2_F2_I2C2},
10380a7581fSIrina Tirdea {"LPSS2_F3_I2C3", BIT_LPSS2_F3_I2C3},
10480a7581fSIrina Tirdea {"LPSS2_F3_I2C4", BIT_LPSS2_F4_I2C4},
10580a7581fSIrina Tirdea {"LPSS2_F5_I2C5", BIT_LPSS2_F5_I2C5},
10680a7581fSIrina Tirdea {"LPSS2_F6_I2C6", BIT_LPSS2_F6_I2C6},
10780a7581fSIrina Tirdea {"LPSS2_F7_I2C7", BIT_LPSS2_F7_I2C7},
10827526525SAndy Shevchenko {}
10980a7581fSIrina Tirdea };
11080a7581fSIrina Tirdea
11180a7581fSIrina Tirdea static struct pmc_bit_map byt_d3_sts_1_map[] = {
11280a7581fSIrina Tirdea {"SMB", BIT_SMB},
11380a7581fSIrina Tirdea {"OTG_SS_PHY", BIT_OTG_SS_PHY},
11480a7581fSIrina Tirdea {"USH_SS_PHY", BIT_USH_SS_PHY},
11580a7581fSIrina Tirdea {"DFX", BIT_DFX},
11627526525SAndy Shevchenko {}
11780a7581fSIrina Tirdea };
11880a7581fSIrina Tirdea
11980a7581fSIrina Tirdea static struct pmc_bit_map cht_d3_sts_1_map[] = {
12080a7581fSIrina Tirdea {"SMB", BIT_SMB},
12180a7581fSIrina Tirdea {"GMM", BIT_STS_GMM},
12280a7581fSIrina Tirdea {"ISH", BIT_STS_ISH},
12327526525SAndy Shevchenko {}
12480a7581fSIrina Tirdea };
12580a7581fSIrina Tirdea
12680a7581fSIrina Tirdea static struct pmc_bit_map cht_func_dis_2_map[] = {
12780a7581fSIrina Tirdea {"SMB", BIT_SMB},
12880a7581fSIrina Tirdea {"GMM", BIT_FD_GMM},
12980a7581fSIrina Tirdea {"ISH", BIT_FD_ISH},
13027526525SAndy Shevchenko {}
13180a7581fSIrina Tirdea };
13280a7581fSIrina Tirdea
13380a7581fSIrina Tirdea static const struct pmc_bit_map byt_pss_map[] = {
13480a7581fSIrina Tirdea {"GBE", PMC_PSS_BIT_GBE},
13580a7581fSIrina Tirdea {"SATA", PMC_PSS_BIT_SATA},
13680a7581fSIrina Tirdea {"HDA", PMC_PSS_BIT_HDA},
13780a7581fSIrina Tirdea {"SEC", PMC_PSS_BIT_SEC},
13880a7581fSIrina Tirdea {"PCIE", PMC_PSS_BIT_PCIE},
13980a7581fSIrina Tirdea {"LPSS", PMC_PSS_BIT_LPSS},
14080a7581fSIrina Tirdea {"LPE", PMC_PSS_BIT_LPE},
14180a7581fSIrina Tirdea {"DFX", PMC_PSS_BIT_DFX},
14280a7581fSIrina Tirdea {"USH_CTRL", PMC_PSS_BIT_USH_CTRL},
14380a7581fSIrina Tirdea {"USH_SUS", PMC_PSS_BIT_USH_SUS},
14480a7581fSIrina Tirdea {"USH_VCCS", PMC_PSS_BIT_USH_VCCS},
14580a7581fSIrina Tirdea {"USH_VCCA", PMC_PSS_BIT_USH_VCCA},
14680a7581fSIrina Tirdea {"OTG_CTRL", PMC_PSS_BIT_OTG_CTRL},
14780a7581fSIrina Tirdea {"OTG_VCCS", PMC_PSS_BIT_OTG_VCCS},
14880a7581fSIrina Tirdea {"OTG_VCCA_CLK", PMC_PSS_BIT_OTG_VCCA_CLK},
14980a7581fSIrina Tirdea {"OTG_VCCA", PMC_PSS_BIT_OTG_VCCA},
15080a7581fSIrina Tirdea {"USB", PMC_PSS_BIT_USB},
15180a7581fSIrina Tirdea {"USB_SUS", PMC_PSS_BIT_USB_SUS},
15227526525SAndy Shevchenko {}
15380a7581fSIrina Tirdea };
15480a7581fSIrina Tirdea
15580a7581fSIrina Tirdea static const struct pmc_bit_map cht_pss_map[] = {
15680a7581fSIrina Tirdea {"SATA", PMC_PSS_BIT_SATA},
15780a7581fSIrina Tirdea {"HDA", PMC_PSS_BIT_HDA},
15880a7581fSIrina Tirdea {"SEC", PMC_PSS_BIT_SEC},
15980a7581fSIrina Tirdea {"PCIE", PMC_PSS_BIT_PCIE},
16080a7581fSIrina Tirdea {"LPSS", PMC_PSS_BIT_LPSS},
16180a7581fSIrina Tirdea {"LPE", PMC_PSS_BIT_LPE},
16280a7581fSIrina Tirdea {"UFS", PMC_PSS_BIT_CHT_UFS},
16380a7581fSIrina Tirdea {"UXD", PMC_PSS_BIT_CHT_UXD},
16480a7581fSIrina Tirdea {"UXD_FD", PMC_PSS_BIT_CHT_UXD_FD},
16580a7581fSIrina Tirdea {"UX_ENG", PMC_PSS_BIT_CHT_UX_ENG},
16680a7581fSIrina Tirdea {"USB_SUS", PMC_PSS_BIT_CHT_USB_SUS},
16780a7581fSIrina Tirdea {"GMM", PMC_PSS_BIT_CHT_GMM},
16880a7581fSIrina Tirdea {"ISH", PMC_PSS_BIT_CHT_ISH},
16980a7581fSIrina Tirdea {"DFX_MASTER", PMC_PSS_BIT_CHT_DFX_MASTER},
17080a7581fSIrina Tirdea {"DFX_CLUSTER1", PMC_PSS_BIT_CHT_DFX_CLUSTER1},
17180a7581fSIrina Tirdea {"DFX_CLUSTER2", PMC_PSS_BIT_CHT_DFX_CLUSTER2},
17280a7581fSIrina Tirdea {"DFX_CLUSTER3", PMC_PSS_BIT_CHT_DFX_CLUSTER3},
17380a7581fSIrina Tirdea {"DFX_CLUSTER4", PMC_PSS_BIT_CHT_DFX_CLUSTER4},
17480a7581fSIrina Tirdea {"DFX_CLUSTER5", PMC_PSS_BIT_CHT_DFX_CLUSTER5},
17527526525SAndy Shevchenko {}
17680a7581fSIrina Tirdea };
17780a7581fSIrina Tirdea
17880a7581fSIrina Tirdea static const struct pmc_reg_map byt_reg_map = {
17980a7581fSIrina Tirdea .d3_sts_0 = d3_sts_0_map,
18080a7581fSIrina Tirdea .d3_sts_1 = byt_d3_sts_1_map,
18180a7581fSIrina Tirdea .func_dis = d3_sts_0_map,
18280a7581fSIrina Tirdea .func_dis_2 = byt_d3_sts_1_map,
18380a7581fSIrina Tirdea .pss = byt_pss_map,
18480a7581fSIrina Tirdea };
18580a7581fSIrina Tirdea
18680a7581fSIrina Tirdea static const struct pmc_reg_map cht_reg_map = {
18780a7581fSIrina Tirdea .d3_sts_0 = d3_sts_0_map,
18880a7581fSIrina Tirdea .d3_sts_1 = cht_d3_sts_1_map,
18980a7581fSIrina Tirdea .func_dis = d3_sts_0_map,
19080a7581fSIrina Tirdea .func_dis_2 = cht_func_dis_2_map,
19180a7581fSIrina Tirdea .pss = cht_pss_map,
19280a7581fSIrina Tirdea };
19380a7581fSIrina Tirdea
194282a4e4cSIrina Tirdea static const struct pmc_data byt_data = {
195282a4e4cSIrina Tirdea .map = &byt_reg_map,
196282a4e4cSIrina Tirdea .clks = byt_clks,
197282a4e4cSIrina Tirdea };
198282a4e4cSIrina Tirdea
199282a4e4cSIrina Tirdea static const struct pmc_data cht_data = {
200282a4e4cSIrina Tirdea .map = &cht_reg_map,
201282a4e4cSIrina Tirdea .clks = cht_clks,
202282a4e4cSIrina Tirdea };
203282a4e4cSIrina Tirdea
pmc_reg_read(struct pmc_dev * pmc,int reg_offset)20480a7581fSIrina Tirdea static inline u32 pmc_reg_read(struct pmc_dev *pmc, int reg_offset)
20580a7581fSIrina Tirdea {
20680a7581fSIrina Tirdea return readl(pmc->regmap + reg_offset);
20780a7581fSIrina Tirdea }
20880a7581fSIrina Tirdea
pmc_reg_write(struct pmc_dev * pmc,int reg_offset,u32 val)20980a7581fSIrina Tirdea static inline void pmc_reg_write(struct pmc_dev *pmc, int reg_offset, u32 val)
21080a7581fSIrina Tirdea {
21180a7581fSIrina Tirdea writel(val, pmc->regmap + reg_offset);
21280a7581fSIrina Tirdea }
21380a7581fSIrina Tirdea
pmc_atom_read(int offset,u32 * value)21480a7581fSIrina Tirdea int pmc_atom_read(int offset, u32 *value)
21580a7581fSIrina Tirdea {
21680a7581fSIrina Tirdea struct pmc_dev *pmc = &pmc_device;
21780a7581fSIrina Tirdea
21880a7581fSIrina Tirdea if (!pmc->init)
21980a7581fSIrina Tirdea return -ENODEV;
22080a7581fSIrina Tirdea
22180a7581fSIrina Tirdea *value = pmc_reg_read(pmc, offset);
22280a7581fSIrina Tirdea return 0;
22380a7581fSIrina Tirdea }
22480a7581fSIrina Tirdea
pmc_power_off(void)22580a7581fSIrina Tirdea static void pmc_power_off(void)
22680a7581fSIrina Tirdea {
22780a7581fSIrina Tirdea u16 pm1_cnt_port;
22880a7581fSIrina Tirdea u32 pm1_cnt_value;
22980a7581fSIrina Tirdea
23080a7581fSIrina Tirdea pr_info("Preparing to enter system sleep state S5\n");
23180a7581fSIrina Tirdea
23280a7581fSIrina Tirdea pm1_cnt_port = acpi_base_addr + PM1_CNT;
23380a7581fSIrina Tirdea
23480a7581fSIrina Tirdea pm1_cnt_value = inl(pm1_cnt_port);
235d8c04e27SAndy Shevchenko pm1_cnt_value &= ~SLEEP_TYPE_MASK;
23680a7581fSIrina Tirdea pm1_cnt_value |= SLEEP_TYPE_S5;
23780a7581fSIrina Tirdea pm1_cnt_value |= SLEEP_ENABLE;
23880a7581fSIrina Tirdea
23980a7581fSIrina Tirdea outl(pm1_cnt_value, pm1_cnt_port);
24080a7581fSIrina Tirdea }
24180a7581fSIrina Tirdea
pmc_hw_reg_setup(struct pmc_dev * pmc)24280a7581fSIrina Tirdea static void pmc_hw_reg_setup(struct pmc_dev *pmc)
24380a7581fSIrina Tirdea {
24480a7581fSIrina Tirdea /*
24580a7581fSIrina Tirdea * Disable PMC S0IX_WAKE_EN events coming from:
24680a7581fSIrina Tirdea * - LPC clock run
24780a7581fSIrina Tirdea * - GPIO_SUS ored dedicated IRQs
24880a7581fSIrina Tirdea * - GPIO_SCORE ored dedicated IRQs
24980a7581fSIrina Tirdea * - GPIO_SUS shared IRQ
25080a7581fSIrina Tirdea * - GPIO_SCORE shared IRQ
25180a7581fSIrina Tirdea */
25280a7581fSIrina Tirdea pmc_reg_write(pmc, PMC_S0IX_WAKE_EN, (u32)PMC_WAKE_EN_SETTING);
25380a7581fSIrina Tirdea }
25480a7581fSIrina Tirdea
25580a7581fSIrina Tirdea #ifdef CONFIG_DEBUG_FS
pmc_dev_state_print(struct seq_file * s,int reg_index,u32 sts,const struct pmc_bit_map * sts_map,u32 fd,const struct pmc_bit_map * fd_map)25680a7581fSIrina Tirdea static void pmc_dev_state_print(struct seq_file *s, int reg_index,
25780a7581fSIrina Tirdea u32 sts, const struct pmc_bit_map *sts_map,
25880a7581fSIrina Tirdea u32 fd, const struct pmc_bit_map *fd_map)
25980a7581fSIrina Tirdea {
26080a7581fSIrina Tirdea int offset = PMC_REG_BIT_WIDTH * reg_index;
26180a7581fSIrina Tirdea int index;
26280a7581fSIrina Tirdea
26380a7581fSIrina Tirdea for (index = 0; sts_map[index].name; index++) {
26480a7581fSIrina Tirdea seq_printf(s, "Dev: %-2d - %-32s\tState: %s [%s]\n",
26580a7581fSIrina Tirdea offset + index, sts_map[index].name,
26680a7581fSIrina Tirdea fd_map[index].bit_mask & fd ? "Disabled" : "Enabled ",
26780a7581fSIrina Tirdea sts_map[index].bit_mask & sts ? "D3" : "D0");
26880a7581fSIrina Tirdea }
26980a7581fSIrina Tirdea }
27080a7581fSIrina Tirdea
pmc_dev_state_show(struct seq_file * s,void * unused)27180a7581fSIrina Tirdea static int pmc_dev_state_show(struct seq_file *s, void *unused)
27280a7581fSIrina Tirdea {
27380a7581fSIrina Tirdea struct pmc_dev *pmc = s->private;
27480a7581fSIrina Tirdea const struct pmc_reg_map *m = pmc->map;
27580a7581fSIrina Tirdea u32 func_dis, func_dis_2;
27680a7581fSIrina Tirdea u32 d3_sts_0, d3_sts_1;
27780a7581fSIrina Tirdea
27880a7581fSIrina Tirdea func_dis = pmc_reg_read(pmc, PMC_FUNC_DIS);
27980a7581fSIrina Tirdea func_dis_2 = pmc_reg_read(pmc, PMC_FUNC_DIS_2);
28080a7581fSIrina Tirdea d3_sts_0 = pmc_reg_read(pmc, PMC_D3_STS_0);
28180a7581fSIrina Tirdea d3_sts_1 = pmc_reg_read(pmc, PMC_D3_STS_1);
28280a7581fSIrina Tirdea
28380a7581fSIrina Tirdea /* Low part */
28480a7581fSIrina Tirdea pmc_dev_state_print(s, 0, d3_sts_0, m->d3_sts_0, func_dis, m->func_dis);
28580a7581fSIrina Tirdea
28680a7581fSIrina Tirdea /* High part */
28780a7581fSIrina Tirdea pmc_dev_state_print(s, 1, d3_sts_1, m->d3_sts_1, func_dis_2, m->func_dis_2);
28880a7581fSIrina Tirdea
28980a7581fSIrina Tirdea return 0;
29080a7581fSIrina Tirdea }
29180a7581fSIrina Tirdea
2921ea74a56SAndy Shevchenko DEFINE_SHOW_ATTRIBUTE(pmc_dev_state);
29380a7581fSIrina Tirdea
pmc_pss_state_show(struct seq_file * s,void * unused)29480a7581fSIrina Tirdea static int pmc_pss_state_show(struct seq_file *s, void *unused)
29580a7581fSIrina Tirdea {
29680a7581fSIrina Tirdea struct pmc_dev *pmc = s->private;
29780a7581fSIrina Tirdea const struct pmc_bit_map *map = pmc->map->pss;
29880a7581fSIrina Tirdea u32 pss = pmc_reg_read(pmc, PMC_PSS);
29980a7581fSIrina Tirdea int index;
30080a7581fSIrina Tirdea
30180a7581fSIrina Tirdea for (index = 0; map[index].name; index++) {
30280a7581fSIrina Tirdea seq_printf(s, "Island: %-2d - %-32s\tState: %s\n",
30380a7581fSIrina Tirdea index, map[index].name,
30480a7581fSIrina Tirdea map[index].bit_mask & pss ? "Off" : "On");
30580a7581fSIrina Tirdea }
30680a7581fSIrina Tirdea return 0;
30780a7581fSIrina Tirdea }
30880a7581fSIrina Tirdea
3091ea74a56SAndy Shevchenko DEFINE_SHOW_ATTRIBUTE(pmc_pss_state);
31080a7581fSIrina Tirdea
pmc_sleep_tmr_show(struct seq_file * s,void * unused)31180a7581fSIrina Tirdea static int pmc_sleep_tmr_show(struct seq_file *s, void *unused)
31280a7581fSIrina Tirdea {
31380a7581fSIrina Tirdea struct pmc_dev *pmc = s->private;
31480a7581fSIrina Tirdea u64 s0ir_tmr, s0i1_tmr, s0i2_tmr, s0i3_tmr, s0_tmr;
31580a7581fSIrina Tirdea
31680a7581fSIrina Tirdea s0ir_tmr = (u64)pmc_reg_read(pmc, PMC_S0IR_TMR) << PMC_TMR_SHIFT;
31780a7581fSIrina Tirdea s0i1_tmr = (u64)pmc_reg_read(pmc, PMC_S0I1_TMR) << PMC_TMR_SHIFT;
31880a7581fSIrina Tirdea s0i2_tmr = (u64)pmc_reg_read(pmc, PMC_S0I2_TMR) << PMC_TMR_SHIFT;
31980a7581fSIrina Tirdea s0i3_tmr = (u64)pmc_reg_read(pmc, PMC_S0I3_TMR) << PMC_TMR_SHIFT;
32080a7581fSIrina Tirdea s0_tmr = (u64)pmc_reg_read(pmc, PMC_S0_TMR) << PMC_TMR_SHIFT;
32180a7581fSIrina Tirdea
32280a7581fSIrina Tirdea seq_printf(s, "S0IR Residency:\t%lldus\n", s0ir_tmr);
32380a7581fSIrina Tirdea seq_printf(s, "S0I1 Residency:\t%lldus\n", s0i1_tmr);
32480a7581fSIrina Tirdea seq_printf(s, "S0I2 Residency:\t%lldus\n", s0i2_tmr);
32580a7581fSIrina Tirdea seq_printf(s, "S0I3 Residency:\t%lldus\n", s0i3_tmr);
32680a7581fSIrina Tirdea seq_printf(s, "S0 Residency:\t%lldus\n", s0_tmr);
32780a7581fSIrina Tirdea return 0;
32880a7581fSIrina Tirdea }
32980a7581fSIrina Tirdea
3301ea74a56SAndy Shevchenko DEFINE_SHOW_ATTRIBUTE(pmc_sleep_tmr);
33180a7581fSIrina Tirdea
pmc_dbgfs_register(struct pmc_dev * pmc)332d42c06c4SGreg Kroah-Hartman static void pmc_dbgfs_register(struct pmc_dev *pmc)
33380a7581fSIrina Tirdea {
334d42c06c4SGreg Kroah-Hartman struct dentry *dir;
33580a7581fSIrina Tirdea
33680a7581fSIrina Tirdea dir = debugfs_create_dir("pmc_atom", NULL);
33780a7581fSIrina Tirdea
33880a7581fSIrina Tirdea pmc->dbgfs_dir = dir;
33980a7581fSIrina Tirdea
340d42c06c4SGreg Kroah-Hartman debugfs_create_file("dev_state", S_IFREG | S_IRUGO, dir, pmc,
341d42c06c4SGreg Kroah-Hartman &pmc_dev_state_fops);
342d42c06c4SGreg Kroah-Hartman debugfs_create_file("pss_state", S_IFREG | S_IRUGO, dir, pmc,
343d42c06c4SGreg Kroah-Hartman &pmc_pss_state_fops);
344d42c06c4SGreg Kroah-Hartman debugfs_create_file("sleep_state", S_IFREG | S_IRUGO, dir, pmc,
345d42c06c4SGreg Kroah-Hartman &pmc_sleep_tmr_fops);
34680a7581fSIrina Tirdea }
34780a7581fSIrina Tirdea #else
pmc_dbgfs_register(struct pmc_dev * pmc)348d42c06c4SGreg Kroah-Hartman static void pmc_dbgfs_register(struct pmc_dev *pmc)
34980a7581fSIrina Tirdea {
35080a7581fSIrina Tirdea }
35180a7581fSIrina Tirdea #endif /* CONFIG_DEBUG_FS */
35280a7581fSIrina Tirdea
3534ba0b818SHenning Schild static bool pmc_clk_is_critical = true;
3544ba0b818SHenning Schild
dmi_callback(const struct dmi_system_id * d)3554ba0b818SHenning Schild static int dmi_callback(const struct dmi_system_id *d)
3564ba0b818SHenning Schild {
35732c9b756SAndy Shevchenko pr_info("%s: PMC critical clocks quirk enabled\n", d->ident);
3584ba0b818SHenning Schild
3594ba0b818SHenning Schild return 1;
3604ba0b818SHenning Schild }
3614ba0b818SHenning Schild
dmi_callback_siemens(const struct dmi_system_id * d)3624ba0b818SHenning Schild static int dmi_callback_siemens(const struct dmi_system_id *d)
3634ba0b818SHenning Schild {
3644ba0b818SHenning Schild u32 st_id;
3654ba0b818SHenning Schild
3664ba0b818SHenning Schild if (dmi_walk(simatic_ipc_find_dmi_entry_helper, &st_id))
3674ba0b818SHenning Schild goto out;
3684ba0b818SHenning Schild
3694ba0b818SHenning Schild if (st_id == SIMATIC_IPC_IPC227E || st_id == SIMATIC_IPC_IPC277E)
3704ba0b818SHenning Schild return dmi_callback(d);
3714ba0b818SHenning Schild
3724ba0b818SHenning Schild out:
3734ba0b818SHenning Schild pmc_clk_is_critical = false;
3744ba0b818SHenning Schild return 1;
3754ba0b818SHenning Schild }
3764ba0b818SHenning Schild
3777c2e0713SDavid Müller /*
3787c2e0713SDavid Müller * Some systems need one or more of their pmc_plt_clks to be
3797c2e0713SDavid Müller * marked as critical.
3807c2e0713SDavid Müller */
381b995dccaSStephen Boyd static const struct dmi_system_id critclk_systems[] = {
3827c2e0713SDavid Müller {
3833d0818f5SHans de Goede /* pmc_plt_clk0 is used for an external HSIC USB HUB */
3847c2e0713SDavid Müller .ident = "MPL CEC1x",
3854ba0b818SHenning Schild .callback = dmi_callback,
3867c2e0713SDavid Müller .matches = {
3877c2e0713SDavid Müller DMI_MATCH(DMI_SYS_VENDOR, "MPL AG"),
3887c2e0713SDavid Müller DMI_MATCH(DMI_PRODUCT_NAME, "CEC10 Family"),
3897c2e0713SDavid Müller },
3907c2e0713SDavid Müller },
3913d0818f5SHans de Goede {
392c9d959fcSHans de Goede /*
393c9d959fcSHans de Goede * Lex System / Lex Computech Co. makes a lot of Bay Trail
394c9d959fcSHans de Goede * based embedded boards which often come with multiple
395c9d959fcSHans de Goede * ethernet controllers using multiple pmc_plt_clks. See:
396c9d959fcSHans de Goede * https://www.lex.com.tw/products/embedded-ipc-board/
397c9d959fcSHans de Goede */
398c9d959fcSHans de Goede .ident = "Lex BayTrail",
3994ba0b818SHenning Schild .callback = dmi_callback,
4003d0818f5SHans de Goede .matches = {
4013d0818f5SHans de Goede DMI_MATCH(DMI_SYS_VENDOR, "Lex BayTrail"),
40295b31e35SGeorg Müller },
40395b31e35SGeorg Müller },
40495b31e35SGeorg Müller {
40595b31e35SGeorg Müller /* pmc_plt_clk* - are used for ethernet controllers */
406d21e5abdSSteffen Dirkwinkel .ident = "Beckhoff Baytrail",
4074ba0b818SHenning Schild .callback = dmi_callback,
408d6423bd0SSteffen Dirkwinkel .matches = {
409d6423bd0SSteffen Dirkwinkel DMI_MATCH(DMI_SYS_VENDOR, "Beckhoff Automation"),
410d21e5abdSSteffen Dirkwinkel DMI_MATCH(DMI_PRODUCT_FAMILY, "CBxx63"),
411d6423bd0SSteffen Dirkwinkel },
412d6423bd0SSteffen Dirkwinkel },
413ad0d315bSJan Kiszka {
4144ba0b818SHenning Schild .ident = "SIEMENS AG",
4154ba0b818SHenning Schild .callback = dmi_callback_siemens,
416ad0d315bSJan Kiszka .matches = {
417ad0d315bSJan Kiszka DMI_MATCH(DMI_SYS_VENDOR, "SIEMENS AG"),
418e8796c6cSMichael Haener },
419e8796c6cSMichael Haener },
42027526525SAndy Shevchenko {}
4217c2e0713SDavid Müller };
4227c2e0713SDavid Müller
pmc_setup_clks(struct pci_dev * pdev,void __iomem * pmc_regmap,const struct pmc_data * pmc_data)423282a4e4cSIrina Tirdea static int pmc_setup_clks(struct pci_dev *pdev, void __iomem *pmc_regmap,
424282a4e4cSIrina Tirdea const struct pmc_data *pmc_data)
425282a4e4cSIrina Tirdea {
426282a4e4cSIrina Tirdea struct platform_device *clkdev;
427282a4e4cSIrina Tirdea struct pmc_clk_data *clk_data;
428282a4e4cSIrina Tirdea
429282a4e4cSIrina Tirdea clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
430282a4e4cSIrina Tirdea if (!clk_data)
431282a4e4cSIrina Tirdea return -ENOMEM;
432282a4e4cSIrina Tirdea
433282a4e4cSIrina Tirdea clk_data->base = pmc_regmap; /* offset is added by client */
434282a4e4cSIrina Tirdea clk_data->clks = pmc_data->clks;
4354ba0b818SHenning Schild if (dmi_check_system(critclk_systems))
4364ba0b818SHenning Schild clk_data->critical = pmc_clk_is_critical;
437282a4e4cSIrina Tirdea
438282a4e4cSIrina Tirdea clkdev = platform_device_register_data(&pdev->dev, "clk-pmc-atom",
439282a4e4cSIrina Tirdea PLATFORM_DEVID_NONE,
440282a4e4cSIrina Tirdea clk_data, sizeof(*clk_data));
441282a4e4cSIrina Tirdea if (IS_ERR(clkdev)) {
442282a4e4cSIrina Tirdea kfree(clk_data);
443282a4e4cSIrina Tirdea return PTR_ERR(clkdev);
444282a4e4cSIrina Tirdea }
445282a4e4cSIrina Tirdea
446282a4e4cSIrina Tirdea kfree(clk_data);
447282a4e4cSIrina Tirdea
448282a4e4cSIrina Tirdea return 0;
449282a4e4cSIrina Tirdea }
450282a4e4cSIrina Tirdea
pmc_setup_dev(struct pci_dev * pdev,const struct pci_device_id * ent)45180a7581fSIrina Tirdea static int pmc_setup_dev(struct pci_dev *pdev, const struct pci_device_id *ent)
45280a7581fSIrina Tirdea {
45380a7581fSIrina Tirdea struct pmc_dev *pmc = &pmc_device;
454282a4e4cSIrina Tirdea const struct pmc_data *data = (struct pmc_data *)ent->driver_data;
455282a4e4cSIrina Tirdea const struct pmc_reg_map *map = data->map;
45680a7581fSIrina Tirdea int ret;
45780a7581fSIrina Tirdea
45880a7581fSIrina Tirdea /* Obtain ACPI base address */
45980a7581fSIrina Tirdea pci_read_config_dword(pdev, ACPI_BASE_ADDR_OFFSET, &acpi_base_addr);
46080a7581fSIrina Tirdea acpi_base_addr &= ACPI_BASE_ADDR_MASK;
46180a7581fSIrina Tirdea
46280a7581fSIrina Tirdea /* Install power off function */
46380a7581fSIrina Tirdea if (acpi_base_addr != 0 && pm_power_off == NULL)
46480a7581fSIrina Tirdea pm_power_off = pmc_power_off;
46580a7581fSIrina Tirdea
46680a7581fSIrina Tirdea pci_read_config_dword(pdev, PMC_BASE_ADDR_OFFSET, &pmc->base_addr);
46780a7581fSIrina Tirdea pmc->base_addr &= PMC_BASE_ADDR_MASK;
46880a7581fSIrina Tirdea
4694bdc0d67SChristoph Hellwig pmc->regmap = ioremap(pmc->base_addr, PMC_MMIO_REG_LEN);
47080a7581fSIrina Tirdea if (!pmc->regmap) {
47180a7581fSIrina Tirdea dev_err(&pdev->dev, "error: ioremap failed\n");
47280a7581fSIrina Tirdea return -ENOMEM;
47380a7581fSIrina Tirdea }
47480a7581fSIrina Tirdea
47580a7581fSIrina Tirdea pmc->map = map;
47680a7581fSIrina Tirdea
47780a7581fSIrina Tirdea /* PMC hardware registers setup */
47880a7581fSIrina Tirdea pmc_hw_reg_setup(pmc);
47980a7581fSIrina Tirdea
480d42c06c4SGreg Kroah-Hartman pmc_dbgfs_register(pmc);
48180a7581fSIrina Tirdea
482282a4e4cSIrina Tirdea /* Register platform clocks - PMC_PLT_CLK [0..5] */
483282a4e4cSIrina Tirdea ret = pmc_setup_clks(pdev, pmc->regmap, data);
484282a4e4cSIrina Tirdea if (ret)
485282a4e4cSIrina Tirdea dev_warn(&pdev->dev, "platform clocks register failed: %d\n",
486282a4e4cSIrina Tirdea ret);
487282a4e4cSIrina Tirdea
48880a7581fSIrina Tirdea pmc->init = true;
48980a7581fSIrina Tirdea return ret;
49080a7581fSIrina Tirdea }
49180a7581fSIrina Tirdea
492*5a88ace4SAndy Shevchenko /* Data for PCI driver interface used by pci_match_id() call below */
49380a7581fSIrina Tirdea static const struct pci_device_id pmc_pci_ids[] = {
494282a4e4cSIrina Tirdea { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_VLV_PMC), (kernel_ulong_t)&byt_data },
495282a4e4cSIrina Tirdea { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_CHT_PMC), (kernel_ulong_t)&cht_data },
49627526525SAndy Shevchenko {}
49780a7581fSIrina Tirdea };
49880a7581fSIrina Tirdea
pmc_atom_init(void)49980a7581fSIrina Tirdea static int __init pmc_atom_init(void)
50080a7581fSIrina Tirdea {
50180a7581fSIrina Tirdea struct pci_dev *pdev = NULL;
50280a7581fSIrina Tirdea const struct pci_device_id *ent;
50380a7581fSIrina Tirdea
504*5a88ace4SAndy Shevchenko /*
505*5a88ace4SAndy Shevchenko * We look for our device - PCU PMC.
506*5a88ace4SAndy Shevchenko * We assume that there is maximum one device.
50780a7581fSIrina Tirdea *
50880a7581fSIrina Tirdea * We can't use plain pci_driver mechanism,
50980a7581fSIrina Tirdea * as the device is really a multiple function device,
51080a7581fSIrina Tirdea * main driver that binds to the pci_device is lpc_ich
51180a7581fSIrina Tirdea * and have to find & bind to the device this way.
51280a7581fSIrina Tirdea */
51380a7581fSIrina Tirdea for_each_pci_dev(pdev) {
51480a7581fSIrina Tirdea ent = pci_match_id(pmc_pci_ids, pdev);
51580a7581fSIrina Tirdea if (ent)
51680a7581fSIrina Tirdea return pmc_setup_dev(pdev, ent);
51780a7581fSIrina Tirdea }
518*5a88ace4SAndy Shevchenko /* Device not found */
51980a7581fSIrina Tirdea return -ENODEV;
52080a7581fSIrina Tirdea }
52180a7581fSIrina Tirdea
52280a7581fSIrina Tirdea device_initcall(pmc_atom_init);
52380a7581fSIrina Tirdea
52480a7581fSIrina Tirdea /*
52580a7581fSIrina Tirdea MODULE_AUTHOR("Aubrey Li <aubrey.li@linux.intel.com>");
526*5a88ace4SAndy Shevchenko MODULE_DESCRIPTION("Intel Atom SoC Power Management Controller Interface");
52780a7581fSIrina Tirdea MODULE_LICENSE("GPL v2");
52880a7581fSIrina Tirdea */
529