1a2f9fbc2SHans de Goede // SPDX-License-Identifier: GPL-2.0 2a2f9fbc2SHans de Goede /* Author: Dan Scally <djrscally@gmail.com> */ 3a2f9fbc2SHans de Goede 4a2f9fbc2SHans de Goede #include <linux/acpi.h> 5a2f9fbc2SHans de Goede #include <linux/clkdev.h> 6a2f9fbc2SHans de Goede #include <linux/clk-provider.h> 7a2f9fbc2SHans de Goede #include <linux/device.h> 8*f1a58250SHans de Goede #include <linux/dmi.h> 9a2f9fbc2SHans de Goede #include <linux/gpio/consumer.h> 10a2f9fbc2SHans de Goede #include <linux/regulator/driver.h> 11a2f9fbc2SHans de Goede #include <linux/slab.h> 12a2f9fbc2SHans de Goede 13a2f9fbc2SHans de Goede #include "common.h" 14a2f9fbc2SHans de Goede 15a2f9fbc2SHans de Goede /* 16e4543de8SBingbu Cao * 82c0d13a-78c5-4244-9bb1-eb8b539a8d11 17e4543de8SBingbu Cao * This _DSM GUID allows controlling the sensor clk when it is not controlled 18e4543de8SBingbu Cao * through a GPIO. 19e4543de8SBingbu Cao */ 20e4543de8SBingbu Cao static const guid_t img_clk_guid = 21e4543de8SBingbu Cao GUID_INIT(0x82c0d13a, 0x78c5, 0x4244, 22e4543de8SBingbu Cao 0x9b, 0xb1, 0xeb, 0x8b, 0x53, 0x9a, 0x8d, 0x11); 23e4543de8SBingbu Cao 24e4543de8SBingbu Cao static void skl_int3472_enable_clk(struct int3472_clock *clk, int enable) 25e4543de8SBingbu Cao { 26e4543de8SBingbu Cao struct int3472_discrete_device *int3472 = to_int3472_device(clk); 27e4543de8SBingbu Cao union acpi_object args[3]; 28e4543de8SBingbu Cao union acpi_object argv4; 29e4543de8SBingbu Cao 30e4543de8SBingbu Cao if (clk->ena_gpio) { 31e4543de8SBingbu Cao gpiod_set_value_cansleep(clk->ena_gpio, enable); 32e4543de8SBingbu Cao return; 33e4543de8SBingbu Cao } 34e4543de8SBingbu Cao 35e4543de8SBingbu Cao args[0].integer.type = ACPI_TYPE_INTEGER; 36e4543de8SBingbu Cao args[0].integer.value = clk->imgclk_index; 37e4543de8SBingbu Cao args[1].integer.type = ACPI_TYPE_INTEGER; 38e4543de8SBingbu Cao args[1].integer.value = enable; 39e4543de8SBingbu Cao args[2].integer.type = ACPI_TYPE_INTEGER; 40e4543de8SBingbu Cao args[2].integer.value = 1; 41e4543de8SBingbu Cao 42e4543de8SBingbu Cao argv4.type = ACPI_TYPE_PACKAGE; 43e4543de8SBingbu Cao argv4.package.count = 3; 44e4543de8SBingbu Cao argv4.package.elements = args; 45e4543de8SBingbu Cao 46e4543de8SBingbu Cao acpi_evaluate_dsm(acpi_device_handle(int3472->adev), &img_clk_guid, 47e4543de8SBingbu Cao 0, 1, &argv4); 48e4543de8SBingbu Cao } 49e4543de8SBingbu Cao 50e4543de8SBingbu Cao /* 51a2f9fbc2SHans de Goede * The regulators have to have .ops to be valid, but the only ops we actually 52a2f9fbc2SHans de Goede * support are .enable and .disable which are handled via .ena_gpiod. Pass an 53a2f9fbc2SHans de Goede * empty struct to clear the check without lying about capabilities. 54a2f9fbc2SHans de Goede */ 55a2f9fbc2SHans de Goede static const struct regulator_ops int3472_gpio_regulator_ops; 56a2f9fbc2SHans de Goede 57a2f9fbc2SHans de Goede static int skl_int3472_clk_prepare(struct clk_hw *hw) 58a2f9fbc2SHans de Goede { 59e4543de8SBingbu Cao skl_int3472_enable_clk(to_int3472_clk(hw), 1); 60a2f9fbc2SHans de Goede return 0; 61a2f9fbc2SHans de Goede } 62a2f9fbc2SHans de Goede 63a2f9fbc2SHans de Goede static void skl_int3472_clk_unprepare(struct clk_hw *hw) 64a2f9fbc2SHans de Goede { 65e4543de8SBingbu Cao skl_int3472_enable_clk(to_int3472_clk(hw), 0); 66a2f9fbc2SHans de Goede } 67a2f9fbc2SHans de Goede 68a2f9fbc2SHans de Goede static int skl_int3472_clk_enable(struct clk_hw *hw) 69a2f9fbc2SHans de Goede { 70a2f9fbc2SHans de Goede /* 71a2f9fbc2SHans de Goede * We're just turning a GPIO on to enable the clock, which operation 72a2f9fbc2SHans de Goede * has the potential to sleep. Given .enable() cannot sleep, but 73a2f9fbc2SHans de Goede * .prepare() can, we toggle the GPIO in .prepare() instead. Thus, 74a2f9fbc2SHans de Goede * nothing to do here. 75a2f9fbc2SHans de Goede */ 76a2f9fbc2SHans de Goede return 0; 77a2f9fbc2SHans de Goede } 78a2f9fbc2SHans de Goede 79a2f9fbc2SHans de Goede static void skl_int3472_clk_disable(struct clk_hw *hw) 80a2f9fbc2SHans de Goede { 81a2f9fbc2SHans de Goede /* Likewise, nothing to do here... */ 82a2f9fbc2SHans de Goede } 83a2f9fbc2SHans de Goede 84a2f9fbc2SHans de Goede static unsigned int skl_int3472_get_clk_frequency(struct int3472_discrete_device *int3472) 85a2f9fbc2SHans de Goede { 86a2f9fbc2SHans de Goede union acpi_object *obj; 87a2f9fbc2SHans de Goede unsigned int freq; 88a2f9fbc2SHans de Goede 89a2f9fbc2SHans de Goede obj = skl_int3472_get_acpi_buffer(int3472->sensor, "SSDB"); 90a2f9fbc2SHans de Goede if (IS_ERR(obj)) 91a2f9fbc2SHans de Goede return 0; /* report rate as 0 on error */ 92a2f9fbc2SHans de Goede 93a2f9fbc2SHans de Goede if (obj->buffer.length < CIO2_SENSOR_SSDB_MCLKSPEED_OFFSET + sizeof(u32)) { 94a2f9fbc2SHans de Goede dev_err(int3472->dev, "The buffer is too small\n"); 95a2f9fbc2SHans de Goede kfree(obj); 96a2f9fbc2SHans de Goede return 0; 97a2f9fbc2SHans de Goede } 98a2f9fbc2SHans de Goede 99a2f9fbc2SHans de Goede freq = *(u32 *)(obj->buffer.pointer + CIO2_SENSOR_SSDB_MCLKSPEED_OFFSET); 100a2f9fbc2SHans de Goede 101a2f9fbc2SHans de Goede kfree(obj); 102a2f9fbc2SHans de Goede return freq; 103a2f9fbc2SHans de Goede } 104a2f9fbc2SHans de Goede 105a2f9fbc2SHans de Goede static unsigned long skl_int3472_clk_recalc_rate(struct clk_hw *hw, 106a2f9fbc2SHans de Goede unsigned long parent_rate) 107a2f9fbc2SHans de Goede { 108e4543de8SBingbu Cao struct int3472_clock *clk = to_int3472_clk(hw); 109a2f9fbc2SHans de Goede 110a2f9fbc2SHans de Goede return clk->frequency; 111a2f9fbc2SHans de Goede } 112a2f9fbc2SHans de Goede 113a2f9fbc2SHans de Goede static const struct clk_ops skl_int3472_clock_ops = { 114a2f9fbc2SHans de Goede .prepare = skl_int3472_clk_prepare, 115a2f9fbc2SHans de Goede .unprepare = skl_int3472_clk_unprepare, 116a2f9fbc2SHans de Goede .enable = skl_int3472_clk_enable, 117a2f9fbc2SHans de Goede .disable = skl_int3472_clk_disable, 118a2f9fbc2SHans de Goede .recalc_rate = skl_int3472_clk_recalc_rate, 119a2f9fbc2SHans de Goede }; 120a2f9fbc2SHans de Goede 121e4543de8SBingbu Cao int skl_int3472_register_dsm_clock(struct int3472_discrete_device *int3472) 122e4543de8SBingbu Cao { 123e4543de8SBingbu Cao struct acpi_device *adev = int3472->adev; 124e4543de8SBingbu Cao struct clk_init_data init = { 125e4543de8SBingbu Cao .ops = &skl_int3472_clock_ops, 126e4543de8SBingbu Cao .flags = CLK_GET_RATE_NOCACHE, 127e4543de8SBingbu Cao }; 128e4543de8SBingbu Cao int ret; 129e4543de8SBingbu Cao 130e4543de8SBingbu Cao if (int3472->clock.cl) 131e4543de8SBingbu Cao return 0; /* A GPIO controlled clk has already been registered */ 132e4543de8SBingbu Cao 133e4543de8SBingbu Cao if (!acpi_check_dsm(adev->handle, &img_clk_guid, 0, BIT(1))) 134e4543de8SBingbu Cao return 0; /* DSM clock control is not available */ 135e4543de8SBingbu Cao 136e4543de8SBingbu Cao init.name = kasprintf(GFP_KERNEL, "%s-clk", acpi_dev_name(adev)); 137e4543de8SBingbu Cao if (!init.name) 138e4543de8SBingbu Cao return -ENOMEM; 139e4543de8SBingbu Cao 140e4543de8SBingbu Cao int3472->clock.frequency = skl_int3472_get_clk_frequency(int3472); 141e4543de8SBingbu Cao int3472->clock.clk_hw.init = &init; 142e4543de8SBingbu Cao int3472->clock.clk = clk_register(&adev->dev, &int3472->clock.clk_hw); 143e4543de8SBingbu Cao if (IS_ERR(int3472->clock.clk)) { 144e4543de8SBingbu Cao ret = PTR_ERR(int3472->clock.clk); 145e4543de8SBingbu Cao goto out_free_init_name; 146e4543de8SBingbu Cao } 147e4543de8SBingbu Cao 148e4543de8SBingbu Cao int3472->clock.cl = clkdev_create(int3472->clock.clk, NULL, int3472->sensor_name); 149e4543de8SBingbu Cao if (!int3472->clock.cl) { 150e4543de8SBingbu Cao ret = -ENOMEM; 151e4543de8SBingbu Cao goto err_unregister_clk; 152e4543de8SBingbu Cao } 153e4543de8SBingbu Cao 154e4543de8SBingbu Cao kfree(init.name); 155e4543de8SBingbu Cao return 0; 156e4543de8SBingbu Cao 157e4543de8SBingbu Cao err_unregister_clk: 158e4543de8SBingbu Cao clk_unregister(int3472->clock.clk); 159e4543de8SBingbu Cao out_free_init_name: 160e4543de8SBingbu Cao kfree(init.name); 161e4543de8SBingbu Cao return ret; 162e4543de8SBingbu Cao } 163e4543de8SBingbu Cao 164e4543de8SBingbu Cao int skl_int3472_register_gpio_clock(struct int3472_discrete_device *int3472, 1657a88de31SHans de Goede struct acpi_resource_gpio *agpio, u32 polarity) 166a2f9fbc2SHans de Goede { 1678cf0e541SHans de Goede char *path = agpio->resource_source.string_ptr; 168a2f9fbc2SHans de Goede struct clk_init_data init = { 169a2f9fbc2SHans de Goede .ops = &skl_int3472_clock_ops, 170a2f9fbc2SHans de Goede .flags = CLK_GET_RATE_NOCACHE, 171a2f9fbc2SHans de Goede }; 172a2f9fbc2SHans de Goede int ret; 173a2f9fbc2SHans de Goede 1748cf0e541SHans de Goede if (int3472->clock.cl) 1758cf0e541SHans de Goede return -EBUSY; 1768cf0e541SHans de Goede 1778cf0e541SHans de Goede int3472->clock.ena_gpio = acpi_get_and_request_gpiod(path, agpio->pin_table[0], 1788cf0e541SHans de Goede "int3472,clk-enable"); 1798cf0e541SHans de Goede if (IS_ERR(int3472->clock.ena_gpio)) 1808cf0e541SHans de Goede return dev_err_probe(int3472->dev, PTR_ERR(int3472->clock.ena_gpio), 1818cf0e541SHans de Goede "getting clk-enable GPIO\n"); 1828cf0e541SHans de Goede 1837a88de31SHans de Goede if (polarity == GPIO_ACTIVE_LOW) 1847a88de31SHans de Goede gpiod_toggle_active_low(int3472->clock.ena_gpio); 1857a88de31SHans de Goede 1868cf0e541SHans de Goede /* Ensure the pin is in output mode and non-active state */ 1878cf0e541SHans de Goede gpiod_direction_output(int3472->clock.ena_gpio, 0); 1888cf0e541SHans de Goede 189a2f9fbc2SHans de Goede init.name = kasprintf(GFP_KERNEL, "%s-clk", 190a2f9fbc2SHans de Goede acpi_dev_name(int3472->adev)); 1918cf0e541SHans de Goede if (!init.name) { 1928cf0e541SHans de Goede ret = -ENOMEM; 1938cf0e541SHans de Goede goto out_put_gpio; 1948cf0e541SHans de Goede } 195a2f9fbc2SHans de Goede 196a2f9fbc2SHans de Goede int3472->clock.frequency = skl_int3472_get_clk_frequency(int3472); 197a2f9fbc2SHans de Goede 198a2f9fbc2SHans de Goede int3472->clock.clk_hw.init = &init; 199a2f9fbc2SHans de Goede int3472->clock.clk = clk_register(&int3472->adev->dev, 200a2f9fbc2SHans de Goede &int3472->clock.clk_hw); 201a2f9fbc2SHans de Goede if (IS_ERR(int3472->clock.clk)) { 202a2f9fbc2SHans de Goede ret = PTR_ERR(int3472->clock.clk); 203a2f9fbc2SHans de Goede goto out_free_init_name; 204a2f9fbc2SHans de Goede } 205a2f9fbc2SHans de Goede 206a2f9fbc2SHans de Goede int3472->clock.cl = clkdev_create(int3472->clock.clk, NULL, 207a2f9fbc2SHans de Goede int3472->sensor_name); 208a2f9fbc2SHans de Goede if (!int3472->clock.cl) { 209a2f9fbc2SHans de Goede ret = -ENOMEM; 210a2f9fbc2SHans de Goede goto err_unregister_clk; 211a2f9fbc2SHans de Goede } 212a2f9fbc2SHans de Goede 213a2f9fbc2SHans de Goede kfree(init.name); 214a2f9fbc2SHans de Goede return 0; 215a2f9fbc2SHans de Goede 216a2f9fbc2SHans de Goede err_unregister_clk: 217a2f9fbc2SHans de Goede clk_unregister(int3472->clock.clk); 218a2f9fbc2SHans de Goede out_free_init_name: 219a2f9fbc2SHans de Goede kfree(init.name); 2208cf0e541SHans de Goede out_put_gpio: 2218cf0e541SHans de Goede gpiod_put(int3472->clock.ena_gpio); 222a2f9fbc2SHans de Goede 223a2f9fbc2SHans de Goede return ret; 224a2f9fbc2SHans de Goede } 225a2f9fbc2SHans de Goede 226a2f9fbc2SHans de Goede void skl_int3472_unregister_clock(struct int3472_discrete_device *int3472) 227a2f9fbc2SHans de Goede { 2288cf0e541SHans de Goede if (!int3472->clock.cl) 2298cf0e541SHans de Goede return; 2308cf0e541SHans de Goede 231a2f9fbc2SHans de Goede clkdev_drop(int3472->clock.cl); 232a2f9fbc2SHans de Goede clk_unregister(int3472->clock.clk); 2338cf0e541SHans de Goede gpiod_put(int3472->clock.ena_gpio); 234a2f9fbc2SHans de Goede } 235a2f9fbc2SHans de Goede 236d4381dcfSHans de Goede /* 237d4381dcfSHans de Goede * The INT3472 device is going to be the only supplier of a regulator for 238d4381dcfSHans de Goede * the sensor device. But unlike the clk framework the regulator framework 239d4381dcfSHans de Goede * does not allow matching by consumer-device-name only. 240d4381dcfSHans de Goede * 241d4381dcfSHans de Goede * Ideally all sensor drivers would use "avdd" as supply-id. But for drivers 242d4381dcfSHans de Goede * where this cannot be changed because another supply-id is already used in 243d4381dcfSHans de Goede * e.g. DeviceTree files an alias for the other supply-id can be added here. 244d4381dcfSHans de Goede * 245d4381dcfSHans de Goede * Do not forget to update GPIO_REGULATOR_SUPPLY_MAP_COUNT when changing this. 246d4381dcfSHans de Goede */ 247d4381dcfSHans de Goede static const char * const skl_int3472_regulator_map_supplies[] = { 248d4381dcfSHans de Goede "avdd", 249d4381dcfSHans de Goede }; 250d4381dcfSHans de Goede 251d4381dcfSHans de Goede static_assert(ARRAY_SIZE(skl_int3472_regulator_map_supplies) == 252d4381dcfSHans de Goede GPIO_REGULATOR_SUPPLY_MAP_COUNT); 253d4381dcfSHans de Goede 254*f1a58250SHans de Goede /* 255*f1a58250SHans de Goede * On some models there is a single GPIO regulator which is shared between 256*f1a58250SHans de Goede * sensors and only listed in the ACPI resources of one sensor. 257*f1a58250SHans de Goede * This DMI table contains the name of the second sensor. This is used to add 258*f1a58250SHans de Goede * entries for the second sensor to the supply_map. 259*f1a58250SHans de Goede */ 260*f1a58250SHans de Goede const struct dmi_system_id skl_int3472_regulator_second_sensor[] = { 261*f1a58250SHans de Goede { 262*f1a58250SHans de Goede /* Lenovo Miix 510-12IKB */ 263*f1a58250SHans de Goede .matches = { 264*f1a58250SHans de Goede DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), 265*f1a58250SHans de Goede DMI_MATCH(DMI_PRODUCT_VERSION, "MIIX 510-12IKB"), 266*f1a58250SHans de Goede }, 267*f1a58250SHans de Goede .driver_data = "i2c-OVTI2680:00", 268*f1a58250SHans de Goede }, 269*f1a58250SHans de Goede { } 270*f1a58250SHans de Goede }; 271*f1a58250SHans de Goede 272a2f9fbc2SHans de Goede int skl_int3472_register_regulator(struct int3472_discrete_device *int3472, 273a2f9fbc2SHans de Goede struct acpi_resource_gpio *agpio) 274a2f9fbc2SHans de Goede { 275a2f9fbc2SHans de Goede char *path = agpio->resource_source.string_ptr; 276a2f9fbc2SHans de Goede struct regulator_init_data init_data = { }; 277a2f9fbc2SHans de Goede struct regulator_config cfg = { }; 278*f1a58250SHans de Goede const char *second_sensor = NULL; 279*f1a58250SHans de Goede const struct dmi_system_id *id; 280*f1a58250SHans de Goede int i, j, ret; 281a2f9fbc2SHans de Goede 282*f1a58250SHans de Goede id = dmi_first_match(skl_int3472_regulator_second_sensor); 283*f1a58250SHans de Goede if (id) 284*f1a58250SHans de Goede second_sensor = id->driver_data; 285*f1a58250SHans de Goede 286*f1a58250SHans de Goede for (i = 0, j = 0; i < ARRAY_SIZE(skl_int3472_regulator_map_supplies); i++) { 287*f1a58250SHans de Goede int3472->regulator.supply_map[j].supply = skl_int3472_regulator_map_supplies[i]; 288*f1a58250SHans de Goede int3472->regulator.supply_map[j].dev_name = int3472->sensor_name; 289*f1a58250SHans de Goede j++; 290*f1a58250SHans de Goede 291*f1a58250SHans de Goede if (second_sensor) { 292*f1a58250SHans de Goede int3472->regulator.supply_map[j].supply = 293*f1a58250SHans de Goede skl_int3472_regulator_map_supplies[i]; 294*f1a58250SHans de Goede int3472->regulator.supply_map[j].dev_name = second_sensor; 295*f1a58250SHans de Goede j++; 296*f1a58250SHans de Goede } 297a2f9fbc2SHans de Goede } 298a2f9fbc2SHans de Goede 299a2f9fbc2SHans de Goede init_data.constraints.valid_ops_mask = REGULATOR_CHANGE_STATUS; 300d4381dcfSHans de Goede init_data.consumer_supplies = int3472->regulator.supply_map; 301*f1a58250SHans de Goede init_data.num_consumer_supplies = j; 302a2f9fbc2SHans de Goede 303a2f9fbc2SHans de Goede snprintf(int3472->regulator.regulator_name, 304a2f9fbc2SHans de Goede sizeof(int3472->regulator.regulator_name), "%s-regulator", 305a2f9fbc2SHans de Goede acpi_dev_name(int3472->adev)); 306a2f9fbc2SHans de Goede snprintf(int3472->regulator.supply_name, 307a2f9fbc2SHans de Goede GPIO_REGULATOR_SUPPLY_NAME_LENGTH, "supply-0"); 308a2f9fbc2SHans de Goede 309a2f9fbc2SHans de Goede int3472->regulator.rdesc = INT3472_REGULATOR( 310a2f9fbc2SHans de Goede int3472->regulator.regulator_name, 311a2f9fbc2SHans de Goede int3472->regulator.supply_name, 312a2f9fbc2SHans de Goede &int3472_gpio_regulator_ops); 313a2f9fbc2SHans de Goede 314a2f9fbc2SHans de Goede int3472->regulator.gpio = acpi_get_and_request_gpiod(path, agpio->pin_table[0], 315a2f9fbc2SHans de Goede "int3472,regulator"); 316a2f9fbc2SHans de Goede if (IS_ERR(int3472->regulator.gpio)) { 317a2f9fbc2SHans de Goede dev_err(int3472->dev, "Failed to get regulator GPIO line\n"); 318a2f9fbc2SHans de Goede return PTR_ERR(int3472->regulator.gpio); 319a2f9fbc2SHans de Goede } 320a2f9fbc2SHans de Goede 321cf5ac2d4SHans de Goede /* Ensure the pin is in output mode and non-active state */ 322cf5ac2d4SHans de Goede gpiod_direction_output(int3472->regulator.gpio, 0); 323cf5ac2d4SHans de Goede 324a2f9fbc2SHans de Goede cfg.dev = &int3472->adev->dev; 325a2f9fbc2SHans de Goede cfg.init_data = &init_data; 326a2f9fbc2SHans de Goede cfg.ena_gpiod = int3472->regulator.gpio; 327a2f9fbc2SHans de Goede 3288f3cbcd6SChiYuan Huang int3472->regulator.rdev = regulator_register(int3472->dev, 3298f3cbcd6SChiYuan Huang &int3472->regulator.rdesc, 330a2f9fbc2SHans de Goede &cfg); 331a2f9fbc2SHans de Goede if (IS_ERR(int3472->regulator.rdev)) { 332a2f9fbc2SHans de Goede ret = PTR_ERR(int3472->regulator.rdev); 333a2f9fbc2SHans de Goede goto err_free_gpio; 334a2f9fbc2SHans de Goede } 335a2f9fbc2SHans de Goede 336a2f9fbc2SHans de Goede return 0; 337a2f9fbc2SHans de Goede 338a2f9fbc2SHans de Goede err_free_gpio: 339a2f9fbc2SHans de Goede gpiod_put(int3472->regulator.gpio); 340a2f9fbc2SHans de Goede 341a2f9fbc2SHans de Goede return ret; 342a2f9fbc2SHans de Goede } 343a2f9fbc2SHans de Goede 344a2f9fbc2SHans de Goede void skl_int3472_unregister_regulator(struct int3472_discrete_device *int3472) 345a2f9fbc2SHans de Goede { 346a2f9fbc2SHans de Goede regulator_unregister(int3472->regulator.rdev); 347a2f9fbc2SHans de Goede gpiod_put(int3472->regulator.gpio); 348a2f9fbc2SHans de Goede } 349