1 // SPDX-License-Identifier: GPL-2.0 2 // LPC variant I/O for Microchip EC 3 // 4 // Copyright (C) 2016 Google, Inc 5 6 #include <linux/delay.h> 7 #include <linux/io.h> 8 #include <linux/mutex.h> 9 #include <linux/types.h> 10 11 #include "cros_ec_lpc_mec.h" 12 13 #define ACPI_LOCK_DELAY_MS 500 14 15 /* 16 * This mutex must be held while accessing the EMI unit. We can't rely on the 17 * EC mutex because memmap data may be accessed without it being held. 18 */ 19 static DEFINE_MUTEX(io_mutex); 20 /* 21 * An alternative mutex to be used when the ACPI AML code may also 22 * access memmap data. When set, this mutex is used in preference to 23 * io_mutex. 24 */ 25 static acpi_handle aml_mutex; 26 27 static u16 mec_emi_base, mec_emi_end; 28 29 /** 30 * cros_ec_lpc_mec_lock() - Acquire mutex for EMI 31 * 32 * @return: Negative error code, or zero for success 33 */ 34 static int cros_ec_lpc_mec_lock(void) 35 { 36 bool success; 37 38 if (!aml_mutex) { 39 mutex_lock(&io_mutex); 40 return 0; 41 } 42 43 success = ACPI_SUCCESS(acpi_acquire_mutex(aml_mutex, 44 NULL, ACPI_LOCK_DELAY_MS)); 45 if (!success) 46 return -EBUSY; 47 48 return 0; 49 } 50 51 /** 52 * cros_ec_lpc_mec_unlock() - Release mutex for EMI 53 * 54 * @return: Negative error code, or zero for success 55 */ 56 static int cros_ec_lpc_mec_unlock(void) 57 { 58 bool success; 59 60 if (!aml_mutex) { 61 mutex_unlock(&io_mutex); 62 return 0; 63 } 64 65 success = ACPI_SUCCESS(acpi_release_mutex(aml_mutex, NULL)); 66 if (!success) 67 return -EBUSY; 68 69 return 0; 70 } 71 72 /** 73 * cros_ec_lpc_mec_emi_write_address() - Initialize EMI at a given address. 74 * 75 * @addr: Starting read / write address 76 * @access_type: Type of access, typically 32-bit auto-increment 77 */ 78 static void cros_ec_lpc_mec_emi_write_address(u16 addr, 79 enum cros_ec_lpc_mec_emi_access_mode access_type) 80 { 81 outb((addr & 0xfc) | access_type, MEC_EMI_EC_ADDRESS_B0(mec_emi_base)); 82 outb((addr >> 8) & 0x7f, MEC_EMI_EC_ADDRESS_B1(mec_emi_base)); 83 } 84 85 /** 86 * cros_ec_lpc_mec_in_range() - Determine if addresses are in MEC EMI range. 87 * 88 * @offset: Address offset 89 * @length: Number of bytes to check 90 * 91 * Return: 1 if in range, 0 if not, and -EINVAL on failure 92 * such as the mec range not being initialized 93 */ 94 int cros_ec_lpc_mec_in_range(unsigned int offset, unsigned int length) 95 { 96 if (length == 0) 97 return -EINVAL; 98 99 if (WARN_ON(mec_emi_base == 0 || mec_emi_end == 0)) 100 return -EINVAL; 101 102 if (offset >= mec_emi_base && offset < mec_emi_end) { 103 if (WARN_ON(offset + length - 1 >= mec_emi_end)) 104 return -EINVAL; 105 return 1; 106 } 107 108 if (WARN_ON(offset + length > mec_emi_base && offset < mec_emi_end)) 109 return -EINVAL; 110 111 return 0; 112 } 113 114 /** 115 * cros_ec_lpc_io_bytes_mec() - Read / write bytes to MEC EMI port. 116 * 117 * @io_type: MEC_IO_READ or MEC_IO_WRITE, depending on request 118 * @offset: Base read / write address 119 * @length: Number of bytes to read / write 120 * @buf: Destination / source buffer 121 * 122 * Return: 8-bit checksum of all bytes read / written 123 */ 124 u8 cros_ec_lpc_io_bytes_mec(enum cros_ec_lpc_mec_io_type io_type, 125 unsigned int offset, unsigned int length, 126 u8 *buf) 127 { 128 int i = 0; 129 int io_addr; 130 u8 sum = 0; 131 enum cros_ec_lpc_mec_emi_access_mode access, new_access; 132 int ret; 133 134 /* Return checksum of 0 if window is not initialized */ 135 WARN_ON(mec_emi_base == 0 || mec_emi_end == 0); 136 if (mec_emi_base == 0 || mec_emi_end == 0) 137 return 0; 138 139 /* 140 * Long access cannot be used on misaligned data since reading B0 loads 141 * the data register and writing B3 flushes. 142 */ 143 if (offset & 0x3 || length < 4) 144 access = ACCESS_TYPE_BYTE; 145 else 146 access = ACCESS_TYPE_LONG_AUTO_INCREMENT; 147 148 ret = cros_ec_lpc_mec_lock(); 149 if (ret) 150 return ret; 151 152 /* Initialize I/O at desired address */ 153 cros_ec_lpc_mec_emi_write_address(offset, access); 154 155 /* Skip bytes in case of misaligned offset */ 156 io_addr = MEC_EMI_EC_DATA_B0(mec_emi_base) + (offset & 0x3); 157 while (i < length) { 158 while (io_addr <= MEC_EMI_EC_DATA_B3(mec_emi_base)) { 159 if (io_type == MEC_IO_READ) 160 buf[i] = inb(io_addr++); 161 else 162 outb(buf[i], io_addr++); 163 164 sum += buf[i++]; 165 offset++; 166 167 /* Extra bounds check in case of misaligned length */ 168 if (i == length) 169 goto done; 170 } 171 172 /* 173 * Use long auto-increment access except for misaligned write, 174 * since writing B3 triggers the flush. 175 */ 176 if (length - i < 4 && io_type == MEC_IO_WRITE) 177 new_access = ACCESS_TYPE_BYTE; 178 else 179 new_access = ACCESS_TYPE_LONG_AUTO_INCREMENT; 180 181 if (new_access != access || 182 access != ACCESS_TYPE_LONG_AUTO_INCREMENT) { 183 access = new_access; 184 cros_ec_lpc_mec_emi_write_address(offset, access); 185 } 186 187 /* Access [B0, B3] on each loop pass */ 188 io_addr = MEC_EMI_EC_DATA_B0(mec_emi_base); 189 } 190 191 done: 192 ret = cros_ec_lpc_mec_unlock(); 193 if (ret) 194 return ret; 195 196 return sum; 197 } 198 EXPORT_SYMBOL(cros_ec_lpc_io_bytes_mec); 199 200 void cros_ec_lpc_mec_init(unsigned int base, unsigned int end) 201 { 202 mec_emi_base = base; 203 mec_emi_end = end; 204 } 205 EXPORT_SYMBOL(cros_ec_lpc_mec_init); 206 207 int cros_ec_lpc_mec_acpi_mutex(struct acpi_device *adev, const char *pathname) 208 { 209 int status; 210 211 if (!adev) 212 return -ENOENT; 213 214 status = acpi_get_handle(adev->handle, pathname, &aml_mutex); 215 if (ACPI_FAILURE(status)) 216 return -ENOENT; 217 218 return 0; 219 } 220 EXPORT_SYMBOL(cros_ec_lpc_mec_acpi_mutex); 221