1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L Pin Control and GPIO driver core 4 * 5 * Copyright (C) 2021 Renesas Electronics Corporation. 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/module.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/seq_file.h> 17 #include <linux/spinlock.h> 18 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/pinctrl/pinconf-generic.h> 21 #include <linux/pinctrl/pinconf.h> 22 #include <linux/pinctrl/pinctrl.h> 23 #include <linux/pinctrl/pinmux.h> 24 25 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 26 27 #include "../core.h" 28 #include "../pinconf.h" 29 #include "../pinmux.h" 30 31 #define DRV_NAME "pinctrl-rzg2l" 32 33 /* 34 * Use 16 lower bits [15:0] for pin identifier 35 * Use 16 higher bits [31:16] for pin mux function 36 */ 37 #define MUX_PIN_ID_MASK GENMASK(15, 0) 38 #define MUX_FUNC_MASK GENMASK(31, 16) 39 #define MUX_FUNC_OFFS 16 40 #define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) 41 42 /* PIN capabilities */ 43 #define PIN_CFG_IOLH_A BIT(0) 44 #define PIN_CFG_IOLH_B BIT(1) 45 #define PIN_CFG_SR BIT(2) 46 #define PIN_CFG_IEN BIT(3) 47 #define PIN_CFG_PUPD BIT(4) 48 #define PIN_CFG_IO_VMC_SD0 BIT(5) 49 #define PIN_CFG_IO_VMC_SD1 BIT(6) 50 #define PIN_CFG_IO_VMC_QSPI BIT(7) 51 #define PIN_CFG_IO_VMC_ETH0 BIT(8) 52 #define PIN_CFG_IO_VMC_ETH1 BIT(9) 53 #define PIN_CFG_FILONOFF BIT(10) 54 #define PIN_CFG_FILNUM BIT(11) 55 #define PIN_CFG_FILCLKSEL BIT(12) 56 57 #define RZG2L_MPXED_PIN_FUNCS (PIN_CFG_IOLH_A | \ 58 PIN_CFG_SR | \ 59 PIN_CFG_PUPD | \ 60 PIN_CFG_FILONOFF | \ 61 PIN_CFG_FILNUM | \ 62 PIN_CFG_FILCLKSEL) 63 64 #define RZG2L_MPXED_ETH_PIN_FUNCS(x) ((x) | \ 65 PIN_CFG_FILONOFF | \ 66 PIN_CFG_FILNUM | \ 67 PIN_CFG_FILCLKSEL) 68 69 /* 70 * n indicates number of pins in the port, a is the register index 71 * and f is pin configuration capabilities supported. 72 */ 73 #define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) 74 #define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) 75 #define RZG2L_GPIO_PORT_GET_INDEX(x) (((x) & GENMASK(26, 20)) >> 20) 76 #define RZG2L_GPIO_PORT_GET_CFGS(x) ((x) & GENMASK(19, 0)) 77 78 /* 79 * BIT(31) indicates dedicated pin, p is the register index while 80 * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits 81 * (b * 8) and f is the pin configuration capabilities supported. 82 */ 83 #define RZG2L_SINGLE_PIN BIT(31) 84 #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ 85 ((p) << 24) | ((b) << 20) | (f)) 86 #define RZG2L_SINGLE_PIN_GET_PORT_OFFSET(x) (((x) & GENMASK(30, 24)) >> 24) 87 #define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) 88 #define RZG2L_SINGLE_PIN_GET_CFGS(x) ((x) & GENMASK(19, 0)) 89 90 #define P(n) (0x0000 + 0x10 + (n)) 91 #define PM(n) (0x0100 + 0x20 + (n) * 2) 92 #define PMC(n) (0x0200 + 0x10 + (n)) 93 #define PFC(n) (0x0400 + 0x40 + (n) * 4) 94 #define PIN(n) (0x0800 + 0x10 + (n)) 95 #define IOLH(n) (0x1000 + (n) * 8) 96 #define IEN(n) (0x1800 + (n) * 8) 97 #define ISEL(n) (0x2c80 + (n) * 8) 98 #define PWPR (0x3014) 99 #define SD_CH(n) (0x3000 + (n) * 4) 100 #define QSPI (0x3008) 101 102 #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */ 103 #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */ 104 105 #define PWPR_B0WI BIT(7) /* Bit Write Disable */ 106 #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */ 107 108 #define PM_MASK 0x03 109 #define PVDD_MASK 0x01 110 #define PFC_MASK 0x07 111 #define IEN_MASK 0x01 112 #define IOLH_MASK 0x03 113 114 #define PM_INPUT 0x1 115 #define PM_OUTPUT 0x2 116 117 #define RZG2L_PIN_ID_TO_PORT(id) ((id) / RZG2L_PINS_PER_PORT) 118 #define RZG2L_PIN_ID_TO_PORT_OFFSET(id) (RZG2L_PIN_ID_TO_PORT(id) + 0x10) 119 #define RZG2L_PIN_ID_TO_PIN(id) ((id) % RZG2L_PINS_PER_PORT) 120 121 #define RZG2L_TINT_MAX_INTERRUPT 32 122 #define RZG2L_TINT_IRQ_START_INDEX 9 123 #define RZG2L_PACK_HWIRQ(t, i) (((t) << 16) | (i)) 124 125 struct rzg2l_dedicated_configs { 126 const char *name; 127 u32 config; 128 }; 129 130 struct rzg2l_pinctrl_data { 131 const char * const *port_pins; 132 const u32 *port_pin_configs; 133 unsigned int n_ports; 134 struct rzg2l_dedicated_configs *dedicated_pins; 135 unsigned int n_port_pins; 136 unsigned int n_dedicated_pins; 137 }; 138 139 struct rzg2l_pinctrl { 140 struct pinctrl_dev *pctl; 141 struct pinctrl_desc desc; 142 struct pinctrl_pin_desc *pins; 143 144 const struct rzg2l_pinctrl_data *data; 145 void __iomem *base; 146 struct device *dev; 147 struct clk *clk; 148 149 struct gpio_chip gpio_chip; 150 struct pinctrl_gpio_range gpio_range; 151 DECLARE_BITMAP(tint_slot, RZG2L_TINT_MAX_INTERRUPT); 152 spinlock_t bitmap_lock; 153 unsigned int hwirq[RZG2L_TINT_MAX_INTERRUPT]; 154 155 spinlock_t lock; 156 }; 157 158 static const unsigned int iolh_groupa_mA[] = { 2, 4, 8, 12 }; 159 static const unsigned int iolh_groupb_oi[] = { 100, 66, 50, 33 }; 160 161 static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, 162 u8 port, u8 pin, u8 func) 163 { 164 unsigned long flags; 165 u32 reg; 166 167 spin_lock_irqsave(&pctrl->lock, flags); 168 169 /* Set pin to 'Non-use (Hi-Z input protection)' */ 170 reg = readw(pctrl->base + PM(port)); 171 reg &= ~(PM_MASK << (pin * 2)); 172 writew(reg, pctrl->base + PM(port)); 173 174 /* Temporarily switch to GPIO mode with PMC register */ 175 reg = readb(pctrl->base + PMC(port)); 176 writeb(reg & ~BIT(pin), pctrl->base + PMC(port)); 177 178 /* Set the PWPR register to allow PFC register to write */ 179 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ 180 writel(PWPR_PFCWE, pctrl->base + PWPR); /* B0WI=0, PFCWE=1 */ 181 182 /* Select Pin function mode with PFC register */ 183 reg = readl(pctrl->base + PFC(port)); 184 reg &= ~(PFC_MASK << (pin * 4)); 185 writel(reg | (func << (pin * 4)), pctrl->base + PFC(port)); 186 187 /* Set the PWPR register to be write-protected */ 188 writel(0x0, pctrl->base + PWPR); /* B0WI=0, PFCWE=0 */ 189 writel(PWPR_B0WI, pctrl->base + PWPR); /* B0WI=1, PFCWE=0 */ 190 191 /* Switch to Peripheral pin function with PMC register */ 192 reg = readb(pctrl->base + PMC(port)); 193 writeb(reg | BIT(pin), pctrl->base + PMC(port)); 194 195 spin_unlock_irqrestore(&pctrl->lock, flags); 196 }; 197 198 static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, 199 unsigned int func_selector, 200 unsigned int group_selector) 201 { 202 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 203 struct function_desc *func; 204 unsigned int i, *psel_val; 205 struct group_desc *group; 206 int *pins; 207 208 func = pinmux_generic_get_function(pctldev, func_selector); 209 if (!func) 210 return -EINVAL; 211 group = pinctrl_generic_get_group(pctldev, group_selector); 212 if (!group) 213 return -EINVAL; 214 215 psel_val = func->data; 216 pins = group->pins; 217 218 for (i = 0; i < group->num_pins; i++) { 219 dev_dbg(pctrl->dev, "port:%u pin: %u PSEL:%u\n", 220 RZG2L_PIN_ID_TO_PORT(pins[i]), RZG2L_PIN_ID_TO_PIN(pins[i]), 221 psel_val[i]); 222 rzg2l_pinctrl_set_pfc_mode(pctrl, RZG2L_PIN_ID_TO_PORT(pins[i]), 223 RZG2L_PIN_ID_TO_PIN(pins[i]), psel_val[i]); 224 } 225 226 return 0; 227 }; 228 229 static int rzg2l_map_add_config(struct pinctrl_map *map, 230 const char *group_or_pin, 231 enum pinctrl_map_type type, 232 unsigned long *configs, 233 unsigned int num_configs) 234 { 235 unsigned long *cfgs; 236 237 cfgs = kmemdup(configs, num_configs * sizeof(*cfgs), 238 GFP_KERNEL); 239 if (!cfgs) 240 return -ENOMEM; 241 242 map->type = type; 243 map->data.configs.group_or_pin = group_or_pin; 244 map->data.configs.configs = cfgs; 245 map->data.configs.num_configs = num_configs; 246 247 return 0; 248 } 249 250 static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, 251 struct device_node *np, 252 struct device_node *parent, 253 struct pinctrl_map **map, 254 unsigned int *num_maps, 255 unsigned int *index) 256 { 257 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 258 struct pinctrl_map *maps = *map; 259 unsigned int nmaps = *num_maps; 260 unsigned long *configs = NULL; 261 unsigned int *pins, *psel_val; 262 unsigned int num_pinmux = 0; 263 unsigned int idx = *index; 264 unsigned int num_pins, i; 265 unsigned int num_configs; 266 struct property *pinmux; 267 struct property *prop; 268 int ret, gsel, fsel; 269 const char **pin_fn; 270 const char *name; 271 const char *pin; 272 273 pinmux = of_find_property(np, "pinmux", NULL); 274 if (pinmux) 275 num_pinmux = pinmux->length / sizeof(u32); 276 277 ret = of_property_count_strings(np, "pins"); 278 if (ret == -EINVAL) { 279 num_pins = 0; 280 } else if (ret < 0) { 281 dev_err(pctrl->dev, "Invalid pins list in DT\n"); 282 return ret; 283 } else { 284 num_pins = ret; 285 } 286 287 if (!num_pinmux && !num_pins) 288 return 0; 289 290 if (num_pinmux && num_pins) { 291 dev_err(pctrl->dev, 292 "DT node must contain either a pinmux or pins and not both\n"); 293 return -EINVAL; 294 } 295 296 ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &num_configs); 297 if (ret < 0) 298 return ret; 299 300 if (num_pins && !num_configs) { 301 dev_err(pctrl->dev, "DT node must contain a config\n"); 302 ret = -ENODEV; 303 goto done; 304 } 305 306 if (num_pinmux) 307 nmaps += 1; 308 309 if (num_pins) 310 nmaps += num_pins; 311 312 maps = krealloc_array(maps, nmaps, sizeof(*maps), GFP_KERNEL); 313 if (!maps) { 314 ret = -ENOMEM; 315 goto done; 316 } 317 318 *map = maps; 319 *num_maps = nmaps; 320 if (num_pins) { 321 of_property_for_each_string(np, "pins", prop, pin) { 322 ret = rzg2l_map_add_config(&maps[idx], pin, 323 PIN_MAP_TYPE_CONFIGS_PIN, 324 configs, num_configs); 325 if (ret < 0) 326 goto done; 327 328 idx++; 329 } 330 ret = 0; 331 goto done; 332 } 333 334 pins = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*pins), GFP_KERNEL); 335 psel_val = devm_kcalloc(pctrl->dev, num_pinmux, sizeof(*psel_val), 336 GFP_KERNEL); 337 pin_fn = devm_kzalloc(pctrl->dev, sizeof(*pin_fn), GFP_KERNEL); 338 if (!pins || !psel_val || !pin_fn) { 339 ret = -ENOMEM; 340 goto done; 341 } 342 343 /* Collect pin locations and mux settings from DT properties */ 344 for (i = 0; i < num_pinmux; ++i) { 345 u32 value; 346 347 ret = of_property_read_u32_index(np, "pinmux", i, &value); 348 if (ret) 349 goto done; 350 pins[i] = value & MUX_PIN_ID_MASK; 351 psel_val[i] = MUX_FUNC(value); 352 } 353 354 if (parent) { 355 name = devm_kasprintf(pctrl->dev, GFP_KERNEL, "%pOFn.%pOFn", 356 parent, np); 357 if (!name) { 358 ret = -ENOMEM; 359 goto done; 360 } 361 } else { 362 name = np->name; 363 } 364 365 /* Register a single pin group listing all the pins we read from DT */ 366 gsel = pinctrl_generic_add_group(pctldev, name, pins, num_pinmux, NULL); 367 if (gsel < 0) { 368 ret = gsel; 369 goto done; 370 } 371 372 /* 373 * Register a single group function where the 'data' is an array PSEL 374 * register values read from DT. 375 */ 376 pin_fn[0] = name; 377 fsel = pinmux_generic_add_function(pctldev, name, pin_fn, 1, psel_val); 378 if (fsel < 0) { 379 ret = fsel; 380 goto remove_group; 381 } 382 383 maps[idx].type = PIN_MAP_TYPE_MUX_GROUP; 384 maps[idx].data.mux.group = name; 385 maps[idx].data.mux.function = name; 386 idx++; 387 388 dev_dbg(pctrl->dev, "Parsed %pOF with %d pins\n", np, num_pinmux); 389 ret = 0; 390 goto done; 391 392 remove_group: 393 pinctrl_generic_remove_group(pctldev, gsel); 394 done: 395 *index = idx; 396 kfree(configs); 397 return ret; 398 } 399 400 static void rzg2l_dt_free_map(struct pinctrl_dev *pctldev, 401 struct pinctrl_map *map, 402 unsigned int num_maps) 403 { 404 unsigned int i; 405 406 if (!map) 407 return; 408 409 for (i = 0; i < num_maps; ++i) { 410 if (map[i].type == PIN_MAP_TYPE_CONFIGS_GROUP || 411 map[i].type == PIN_MAP_TYPE_CONFIGS_PIN) 412 kfree(map[i].data.configs.configs); 413 } 414 kfree(map); 415 } 416 417 static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, 418 struct device_node *np, 419 struct pinctrl_map **map, 420 unsigned int *num_maps) 421 { 422 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 423 struct device_node *child; 424 unsigned int index; 425 int ret; 426 427 *map = NULL; 428 *num_maps = 0; 429 index = 0; 430 431 for_each_child_of_node(np, child) { 432 ret = rzg2l_dt_subnode_to_map(pctldev, child, np, map, 433 num_maps, &index); 434 if (ret < 0) { 435 of_node_put(child); 436 goto done; 437 } 438 } 439 440 if (*num_maps == 0) { 441 ret = rzg2l_dt_subnode_to_map(pctldev, np, NULL, map, 442 num_maps, &index); 443 if (ret < 0) 444 goto done; 445 } 446 447 if (*num_maps) 448 return 0; 449 450 dev_err(pctrl->dev, "no mapping found in node %pOF\n", np); 451 ret = -EINVAL; 452 453 done: 454 rzg2l_dt_free_map(pctldev, *map, *num_maps); 455 456 return ret; 457 } 458 459 static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, 460 u32 cfg, u32 port, u8 bit) 461 { 462 u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); 463 u32 port_index = RZG2L_GPIO_PORT_GET_INDEX(cfg); 464 u32 data; 465 466 if (bit >= pincount || port >= pctrl->data->n_port_pins) 467 return -EINVAL; 468 469 data = pctrl->data->port_pin_configs[port]; 470 if (port_index != RZG2L_GPIO_PORT_GET_INDEX(data)) 471 return -EINVAL; 472 473 return 0; 474 } 475 476 static u32 rzg2l_read_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 477 u8 bit, u32 mask) 478 { 479 void __iomem *addr = pctrl->base + offset; 480 481 /* handle _L/_H for 32-bit register read/write */ 482 if (bit >= 4) { 483 bit -= 4; 484 addr += 4; 485 } 486 487 return (readl(addr) >> (bit * 8)) & mask; 488 } 489 490 static void rzg2l_rmw_pin_config(struct rzg2l_pinctrl *pctrl, u32 offset, 491 u8 bit, u32 mask, u32 val) 492 { 493 void __iomem *addr = pctrl->base + offset; 494 unsigned long flags; 495 u32 reg; 496 497 /* handle _L/_H for 32-bit register read/write */ 498 if (bit >= 4) { 499 bit -= 4; 500 addr += 4; 501 } 502 503 spin_lock_irqsave(&pctrl->lock, flags); 504 reg = readl(addr) & ~(mask << (bit * 8)); 505 writel(reg | (val << (bit * 8)), addr); 506 spin_unlock_irqrestore(&pctrl->lock, flags); 507 } 508 509 static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, 510 unsigned int _pin, 511 unsigned long *config) 512 { 513 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 514 enum pin_config_param param = pinconf_to_config_param(*config); 515 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 516 unsigned int *pin_data = pin->drv_data; 517 unsigned int arg = 0; 518 unsigned long flags; 519 void __iomem *addr; 520 u32 port_offset; 521 u32 cfg = 0; 522 u8 bit = 0; 523 524 if (!pin_data) 525 return -EINVAL; 526 527 if (*pin_data & RZG2L_SINGLE_PIN) { 528 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); 529 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); 530 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); 531 } else { 532 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); 533 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); 534 bit = RZG2L_PIN_ID_TO_PIN(_pin); 535 536 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 537 return -EINVAL; 538 } 539 540 switch (param) { 541 case PIN_CONFIG_INPUT_ENABLE: 542 if (!(cfg & PIN_CFG_IEN)) 543 return -EINVAL; 544 arg = rzg2l_read_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK); 545 if (!arg) 546 return -EINVAL; 547 break; 548 549 case PIN_CONFIG_POWER_SOURCE: { 550 u32 pwr_reg = 0x0; 551 552 if (cfg & PIN_CFG_IO_VMC_SD0) 553 pwr_reg = SD_CH(0); 554 else if (cfg & PIN_CFG_IO_VMC_SD1) 555 pwr_reg = SD_CH(1); 556 else if (cfg & PIN_CFG_IO_VMC_QSPI) 557 pwr_reg = QSPI; 558 else 559 return -EINVAL; 560 561 spin_lock_irqsave(&pctrl->lock, flags); 562 addr = pctrl->base + pwr_reg; 563 arg = (readl(addr) & PVDD_MASK) ? 1800 : 3300; 564 spin_unlock_irqrestore(&pctrl->lock, flags); 565 break; 566 } 567 568 case PIN_CONFIG_DRIVE_STRENGTH: { 569 unsigned int index; 570 571 if (!(cfg & PIN_CFG_IOLH_A)) 572 return -EINVAL; 573 574 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); 575 arg = iolh_groupa_mA[index]; 576 break; 577 } 578 579 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 580 unsigned int index; 581 582 if (!(cfg & PIN_CFG_IOLH_B)) 583 return -EINVAL; 584 585 index = rzg2l_read_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK); 586 arg = iolh_groupb_oi[index]; 587 break; 588 } 589 590 default: 591 return -ENOTSUPP; 592 } 593 594 *config = pinconf_to_config_packed(param, arg); 595 596 return 0; 597 }; 598 599 static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, 600 unsigned int _pin, 601 unsigned long *_configs, 602 unsigned int num_configs) 603 { 604 struct rzg2l_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 605 const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; 606 unsigned int *pin_data = pin->drv_data; 607 enum pin_config_param param; 608 unsigned long flags; 609 void __iomem *addr; 610 u32 port_offset; 611 unsigned int i; 612 u32 cfg = 0; 613 u8 bit = 0; 614 615 if (!pin_data) 616 return -EINVAL; 617 618 if (*pin_data & RZG2L_SINGLE_PIN) { 619 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(*pin_data); 620 cfg = RZG2L_SINGLE_PIN_GET_CFGS(*pin_data); 621 bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); 622 } else { 623 cfg = RZG2L_GPIO_PORT_GET_CFGS(*pin_data); 624 port_offset = RZG2L_PIN_ID_TO_PORT_OFFSET(_pin); 625 bit = RZG2L_PIN_ID_TO_PIN(_pin); 626 627 if (rzg2l_validate_gpio_pin(pctrl, *pin_data, RZG2L_PIN_ID_TO_PORT(_pin), bit)) 628 return -EINVAL; 629 } 630 631 for (i = 0; i < num_configs; i++) { 632 param = pinconf_to_config_param(_configs[i]); 633 switch (param) { 634 case PIN_CONFIG_INPUT_ENABLE: { 635 unsigned int arg = 636 pinconf_to_config_argument(_configs[i]); 637 638 if (!(cfg & PIN_CFG_IEN)) 639 return -EINVAL; 640 641 rzg2l_rmw_pin_config(pctrl, IEN(port_offset), bit, IEN_MASK, !!arg); 642 break; 643 } 644 645 case PIN_CONFIG_POWER_SOURCE: { 646 unsigned int mV = pinconf_to_config_argument(_configs[i]); 647 u32 pwr_reg = 0x0; 648 649 if (mV != 1800 && mV != 3300) 650 return -EINVAL; 651 652 if (cfg & PIN_CFG_IO_VMC_SD0) 653 pwr_reg = SD_CH(0); 654 else if (cfg & PIN_CFG_IO_VMC_SD1) 655 pwr_reg = SD_CH(1); 656 else if (cfg & PIN_CFG_IO_VMC_QSPI) 657 pwr_reg = QSPI; 658 else 659 return -EINVAL; 660 661 addr = pctrl->base + pwr_reg; 662 spin_lock_irqsave(&pctrl->lock, flags); 663 writel((mV == 1800) ? PVDD_1800 : PVDD_3300, addr); 664 spin_unlock_irqrestore(&pctrl->lock, flags); 665 break; 666 } 667 668 case PIN_CONFIG_DRIVE_STRENGTH: { 669 unsigned int arg = pinconf_to_config_argument(_configs[i]); 670 unsigned int index; 671 672 if (!(cfg & PIN_CFG_IOLH_A)) 673 return -EINVAL; 674 675 for (index = 0; index < ARRAY_SIZE(iolh_groupa_mA); index++) { 676 if (arg == iolh_groupa_mA[index]) 677 break; 678 } 679 if (index >= ARRAY_SIZE(iolh_groupa_mA)) 680 return -EINVAL; 681 682 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); 683 break; 684 } 685 686 case PIN_CONFIG_OUTPUT_IMPEDANCE_OHMS: { 687 unsigned int arg = pinconf_to_config_argument(_configs[i]); 688 unsigned int index; 689 690 if (!(cfg & PIN_CFG_IOLH_B)) 691 return -EINVAL; 692 693 for (index = 0; index < ARRAY_SIZE(iolh_groupb_oi); index++) { 694 if (arg == iolh_groupb_oi[index]) 695 break; 696 } 697 if (index >= ARRAY_SIZE(iolh_groupb_oi)) 698 return -EINVAL; 699 700 rzg2l_rmw_pin_config(pctrl, IOLH(port_offset), bit, IOLH_MASK, index); 701 break; 702 } 703 704 default: 705 return -EOPNOTSUPP; 706 } 707 } 708 709 return 0; 710 } 711 712 static int rzg2l_pinctrl_pinconf_group_set(struct pinctrl_dev *pctldev, 713 unsigned int group, 714 unsigned long *configs, 715 unsigned int num_configs) 716 { 717 const unsigned int *pins; 718 unsigned int i, npins; 719 int ret; 720 721 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 722 if (ret) 723 return ret; 724 725 for (i = 0; i < npins; i++) { 726 ret = rzg2l_pinctrl_pinconf_set(pctldev, pins[i], configs, 727 num_configs); 728 if (ret) 729 return ret; 730 } 731 732 return 0; 733 }; 734 735 static int rzg2l_pinctrl_pinconf_group_get(struct pinctrl_dev *pctldev, 736 unsigned int group, 737 unsigned long *config) 738 { 739 const unsigned int *pins; 740 unsigned int i, npins, prev_config = 0; 741 int ret; 742 743 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins); 744 if (ret) 745 return ret; 746 747 for (i = 0; i < npins; i++) { 748 ret = rzg2l_pinctrl_pinconf_get(pctldev, pins[i], config); 749 if (ret) 750 return ret; 751 752 /* Check config matching between to pin */ 753 if (i && prev_config != *config) 754 return -EOPNOTSUPP; 755 756 prev_config = *config; 757 } 758 759 return 0; 760 }; 761 762 static const struct pinctrl_ops rzg2l_pinctrl_pctlops = { 763 .get_groups_count = pinctrl_generic_get_group_count, 764 .get_group_name = pinctrl_generic_get_group_name, 765 .get_group_pins = pinctrl_generic_get_group_pins, 766 .dt_node_to_map = rzg2l_dt_node_to_map, 767 .dt_free_map = rzg2l_dt_free_map, 768 }; 769 770 static const struct pinmux_ops rzg2l_pinctrl_pmxops = { 771 .get_functions_count = pinmux_generic_get_function_count, 772 .get_function_name = pinmux_generic_get_function_name, 773 .get_function_groups = pinmux_generic_get_function_groups, 774 .set_mux = rzg2l_pinctrl_set_mux, 775 .strict = true, 776 }; 777 778 static const struct pinconf_ops rzg2l_pinctrl_confops = { 779 .is_generic = true, 780 .pin_config_get = rzg2l_pinctrl_pinconf_get, 781 .pin_config_set = rzg2l_pinctrl_pinconf_set, 782 .pin_config_group_set = rzg2l_pinctrl_pinconf_group_set, 783 .pin_config_group_get = rzg2l_pinctrl_pinconf_group_get, 784 .pin_config_config_dbg_show = pinconf_generic_dump_config, 785 }; 786 787 static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) 788 { 789 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 790 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 791 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 792 unsigned long flags; 793 u8 reg8; 794 int ret; 795 796 ret = pinctrl_gpio_request(chip->base + offset); 797 if (ret) 798 return ret; 799 800 spin_lock_irqsave(&pctrl->lock, flags); 801 802 /* Select GPIO mode in PMC Register */ 803 reg8 = readb(pctrl->base + PMC(port)); 804 reg8 &= ~BIT(bit); 805 writeb(reg8, pctrl->base + PMC(port)); 806 807 spin_unlock_irqrestore(&pctrl->lock, flags); 808 809 return 0; 810 } 811 812 static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 port, 813 u8 bit, bool output) 814 { 815 unsigned long flags; 816 u16 reg16; 817 818 spin_lock_irqsave(&pctrl->lock, flags); 819 820 reg16 = readw(pctrl->base + PM(port)); 821 reg16 &= ~(PM_MASK << (bit * 2)); 822 823 reg16 |= (output ? PM_OUTPUT : PM_INPUT) << (bit * 2); 824 writew(reg16, pctrl->base + PM(port)); 825 826 spin_unlock_irqrestore(&pctrl->lock, flags); 827 } 828 829 static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 830 { 831 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 832 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 833 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 834 835 if (!(readb(pctrl->base + PMC(port)) & BIT(bit))) { 836 u16 reg16; 837 838 reg16 = readw(pctrl->base + PM(port)); 839 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 840 if (reg16 == PM_OUTPUT) 841 return GPIO_LINE_DIRECTION_OUT; 842 } 843 844 return GPIO_LINE_DIRECTION_IN; 845 } 846 847 static int rzg2l_gpio_direction_input(struct gpio_chip *chip, 848 unsigned int offset) 849 { 850 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 851 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 852 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 853 854 rzg2l_gpio_set_direction(pctrl, port, bit, false); 855 856 return 0; 857 } 858 859 static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, 860 int value) 861 { 862 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 863 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 864 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 865 unsigned long flags; 866 u8 reg8; 867 868 spin_lock_irqsave(&pctrl->lock, flags); 869 870 reg8 = readb(pctrl->base + P(port)); 871 872 if (value) 873 writeb(reg8 | BIT(bit), pctrl->base + P(port)); 874 else 875 writeb(reg8 & ~BIT(bit), pctrl->base + P(port)); 876 877 spin_unlock_irqrestore(&pctrl->lock, flags); 878 } 879 880 static int rzg2l_gpio_direction_output(struct gpio_chip *chip, 881 unsigned int offset, int value) 882 { 883 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 884 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 885 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 886 887 rzg2l_gpio_set(chip, offset, value); 888 rzg2l_gpio_set_direction(pctrl, port, bit, true); 889 890 return 0; 891 } 892 893 static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) 894 { 895 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); 896 u32 port = RZG2L_PIN_ID_TO_PORT(offset); 897 u8 bit = RZG2L_PIN_ID_TO_PIN(offset); 898 u16 reg16; 899 900 reg16 = readw(pctrl->base + PM(port)); 901 reg16 = (reg16 >> (bit * 2)) & PM_MASK; 902 903 if (reg16 == PM_INPUT) 904 return !!(readb(pctrl->base + PIN(port)) & BIT(bit)); 905 else if (reg16 == PM_OUTPUT) 906 return !!(readb(pctrl->base + P(port)) & BIT(bit)); 907 else 908 return -EINVAL; 909 } 910 911 static void rzg2l_gpio_free(struct gpio_chip *chip, unsigned int offset) 912 { 913 unsigned int virq; 914 915 pinctrl_gpio_free(chip->base + offset); 916 917 virq = irq_find_mapping(chip->irq.domain, offset); 918 if (virq) 919 irq_dispose_mapping(virq); 920 921 /* 922 * Set the GPIO as an input to ensure that the next GPIO request won't 923 * drive the GPIO pin as an output. 924 */ 925 rzg2l_gpio_direction_input(chip, offset); 926 } 927 928 static const char * const rzg2l_gpio_names[] = { 929 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 930 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 931 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 932 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 933 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 934 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 935 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 936 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 937 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 938 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 939 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 940 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 941 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 942 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 943 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 944 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 945 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 946 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 947 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 948 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 949 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 950 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 951 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 952 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 953 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 954 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 955 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 956 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 957 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 958 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 959 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 960 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 961 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 962 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 963 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 964 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 965 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 966 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 967 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 968 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 969 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 970 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 971 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 972 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 973 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 974 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 975 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 976 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 977 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 978 }; 979 980 static const u32 rzg2l_gpio_configs[] = { 981 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 982 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 983 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 984 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 985 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 986 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 987 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 988 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 989 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 990 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 991 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 992 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 993 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 994 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 995 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 996 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 997 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 998 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 999 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 1000 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 1001 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1002 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1003 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1004 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1005 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1006 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1007 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1008 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1009 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1010 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1011 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1012 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1013 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1014 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1015 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1016 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1017 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1018 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1019 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 1020 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 1021 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 1022 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 1023 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 1024 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 1025 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 1026 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 1027 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 1028 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 1029 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 1030 }; 1031 1032 static const u32 r9a07g043_gpio_configs[] = { 1033 RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), 1034 RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1035 RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1036 RZG2L_GPIO_PORT_PACK(4, 0x13, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1037 RZG2L_GPIO_PORT_PACK(6, 0x14, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 1038 RZG2L_GPIO_PORT_PACK(5, 0x15, RZG2L_MPXED_PIN_FUNCS), 1039 RZG2L_GPIO_PORT_PACK(5, 0x16, RZG2L_MPXED_PIN_FUNCS), 1040 RZG2L_GPIO_PORT_PACK(5, 0x17, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1041 RZG2L_GPIO_PORT_PACK(5, 0x18, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1042 RZG2L_GPIO_PORT_PACK(4, 0x19, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1043 RZG2L_GPIO_PORT_PACK(5, 0x1a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 1044 RZG2L_GPIO_PORT_PACK(4, 0x1b, RZG2L_MPXED_PIN_FUNCS), 1045 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 1046 RZG2L_GPIO_PORT_PACK(5, 0x1d, RZG2L_MPXED_PIN_FUNCS), 1047 RZG2L_GPIO_PORT_PACK(3, 0x1e, RZG2L_MPXED_PIN_FUNCS), 1048 RZG2L_GPIO_PORT_PACK(4, 0x1f, RZG2L_MPXED_PIN_FUNCS), 1049 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 1050 RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), 1051 RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), 1052 }; 1053 1054 static struct { 1055 struct rzg2l_dedicated_configs common[35]; 1056 struct rzg2l_dedicated_configs rzg2l_pins[7]; 1057 } rzg2l_dedicated_pins = { 1058 .common = { 1059 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, 1060 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, 1061 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 1062 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1063 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 1064 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 1065 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 1066 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 1067 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 1068 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1069 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 1070 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1071 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 1072 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 1073 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 1074 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1075 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 1076 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1077 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 1078 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1079 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 1080 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1081 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 1082 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1083 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 1084 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1085 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 1086 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1087 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 1088 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 1089 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 1090 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 1091 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 1092 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1093 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 1094 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1095 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 1096 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1097 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 1098 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1099 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 1100 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 1101 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 1102 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1103 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 1104 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1105 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 1106 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1107 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 1108 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1109 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 1110 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1111 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 1112 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1113 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 1114 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1115 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 1116 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1117 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 1118 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 1119 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 1120 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 1121 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 1122 }, 1123 .rzg2l_pins = { 1124 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1125 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 1126 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1127 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 1128 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1129 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 1130 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1131 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 1132 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1133 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 1134 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1135 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 1136 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 1137 } 1138 }; 1139 1140 static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) 1141 { 1142 unsigned int gpioint; 1143 unsigned int i; 1144 u32 port, bit; 1145 1146 port = virq / 8; 1147 bit = virq % 8; 1148 1149 if (port >= data->n_ports || 1150 bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port])) 1151 return -EINVAL; 1152 1153 gpioint = bit; 1154 for (i = 0; i < port; i++) 1155 gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]); 1156 1157 return gpioint; 1158 } 1159 1160 static void rzg2l_gpio_irq_disable(struct irq_data *d) 1161 { 1162 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1163 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1164 unsigned int hwirq = irqd_to_hwirq(d); 1165 unsigned long flags; 1166 void __iomem *addr; 1167 u32 port; 1168 u8 bit; 1169 1170 port = RZG2L_PIN_ID_TO_PORT(hwirq); 1171 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1172 1173 addr = pctrl->base + ISEL(port); 1174 if (bit >= 4) { 1175 bit -= 4; 1176 addr += 4; 1177 } 1178 1179 spin_lock_irqsave(&pctrl->lock, flags); 1180 writel(readl(addr) & ~BIT(bit * 8), addr); 1181 spin_unlock_irqrestore(&pctrl->lock, flags); 1182 1183 gpiochip_disable_irq(gc, hwirq); 1184 irq_chip_disable_parent(d); 1185 } 1186 1187 static void rzg2l_gpio_irq_enable(struct irq_data *d) 1188 { 1189 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1190 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1191 unsigned int hwirq = irqd_to_hwirq(d); 1192 unsigned long flags; 1193 void __iomem *addr; 1194 u32 port; 1195 u8 bit; 1196 1197 gpiochip_enable_irq(gc, hwirq); 1198 1199 port = RZG2L_PIN_ID_TO_PORT(hwirq); 1200 bit = RZG2L_PIN_ID_TO_PIN(hwirq); 1201 1202 addr = pctrl->base + ISEL(port); 1203 if (bit >= 4) { 1204 bit -= 4; 1205 addr += 4; 1206 } 1207 1208 spin_lock_irqsave(&pctrl->lock, flags); 1209 writel(readl(addr) | BIT(bit * 8), addr); 1210 spin_unlock_irqrestore(&pctrl->lock, flags); 1211 1212 irq_chip_enable_parent(d); 1213 } 1214 1215 static int rzg2l_gpio_irq_set_type(struct irq_data *d, unsigned int type) 1216 { 1217 return irq_chip_set_type_parent(d, type); 1218 } 1219 1220 static void rzg2l_gpio_irqc_eoi(struct irq_data *d) 1221 { 1222 irq_chip_eoi_parent(d); 1223 } 1224 1225 static void rzg2l_gpio_irq_print_chip(struct irq_data *data, struct seq_file *p) 1226 { 1227 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 1228 1229 seq_printf(p, dev_name(gc->parent)); 1230 } 1231 1232 static const struct irq_chip rzg2l_gpio_irqchip = { 1233 .name = "rzg2l-gpio", 1234 .irq_disable = rzg2l_gpio_irq_disable, 1235 .irq_enable = rzg2l_gpio_irq_enable, 1236 .irq_mask = irq_chip_mask_parent, 1237 .irq_unmask = irq_chip_unmask_parent, 1238 .irq_set_type = rzg2l_gpio_irq_set_type, 1239 .irq_eoi = rzg2l_gpio_irqc_eoi, 1240 .irq_print_chip = rzg2l_gpio_irq_print_chip, 1241 .flags = IRQCHIP_IMMUTABLE, 1242 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1243 }; 1244 1245 static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 1246 unsigned int child, 1247 unsigned int child_type, 1248 unsigned int *parent, 1249 unsigned int *parent_type) 1250 { 1251 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1252 unsigned long flags; 1253 int gpioint, irq; 1254 1255 gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); 1256 if (gpioint < 0) 1257 return gpioint; 1258 1259 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 1260 irq = bitmap_find_free_region(pctrl->tint_slot, RZG2L_TINT_MAX_INTERRUPT, get_order(1)); 1261 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 1262 if (irq < 0) 1263 return -ENOSPC; 1264 pctrl->hwirq[irq] = child; 1265 irq += RZG2L_TINT_IRQ_START_INDEX; 1266 1267 /* All these interrupts are level high in the CPU */ 1268 *parent_type = IRQ_TYPE_LEVEL_HIGH; 1269 *parent = RZG2L_PACK_HWIRQ(gpioint, irq); 1270 return 0; 1271 } 1272 1273 static int rzg2l_gpio_populate_parent_fwspec(struct gpio_chip *chip, 1274 union gpio_irq_fwspec *gfwspec, 1275 unsigned int parent_hwirq, 1276 unsigned int parent_type) 1277 { 1278 struct irq_fwspec *fwspec = &gfwspec->fwspec; 1279 1280 fwspec->fwnode = chip->irq.parent_domain->fwnode; 1281 fwspec->param_count = 2; 1282 fwspec->param[0] = parent_hwirq; 1283 fwspec->param[1] = parent_type; 1284 1285 return 0; 1286 } 1287 1288 static void rzg2l_gpio_irq_domain_free(struct irq_domain *domain, unsigned int virq, 1289 unsigned int nr_irqs) 1290 { 1291 struct irq_data *d; 1292 1293 d = irq_domain_get_irq_data(domain, virq); 1294 if (d) { 1295 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1296 struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); 1297 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1298 unsigned long flags; 1299 unsigned int i; 1300 1301 for (i = 0; i < RZG2L_TINT_MAX_INTERRUPT; i++) { 1302 if (pctrl->hwirq[i] == hwirq) { 1303 spin_lock_irqsave(&pctrl->bitmap_lock, flags); 1304 bitmap_release_region(pctrl->tint_slot, i, get_order(1)); 1305 spin_unlock_irqrestore(&pctrl->bitmap_lock, flags); 1306 pctrl->hwirq[i] = 0; 1307 break; 1308 } 1309 } 1310 } 1311 irq_domain_free_irqs_common(domain, virq, nr_irqs); 1312 } 1313 1314 static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, 1315 unsigned long *valid_mask, 1316 unsigned int ngpios) 1317 { 1318 struct rzg2l_pinctrl *pctrl = gpiochip_get_data(gc); 1319 struct gpio_chip *chip = &pctrl->gpio_chip; 1320 unsigned int offset; 1321 1322 /* Forbid unused lines to be mapped as IRQs */ 1323 for (offset = 0; offset < chip->ngpio; offset++) { 1324 u32 port, bit; 1325 1326 port = offset / 8; 1327 bit = offset % 8; 1328 1329 if (port >= pctrl->data->n_ports || 1330 bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port])) 1331 clear_bit(offset, valid_mask); 1332 } 1333 } 1334 1335 static int rzg2l_gpio_register(struct rzg2l_pinctrl *pctrl) 1336 { 1337 struct device_node *np = pctrl->dev->of_node; 1338 struct gpio_chip *chip = &pctrl->gpio_chip; 1339 const char *name = dev_name(pctrl->dev); 1340 struct irq_domain *parent_domain; 1341 struct of_phandle_args of_args; 1342 struct device_node *parent_np; 1343 struct gpio_irq_chip *girq; 1344 int ret; 1345 1346 parent_np = of_irq_find_parent(np); 1347 if (!parent_np) 1348 return -ENXIO; 1349 1350 parent_domain = irq_find_host(parent_np); 1351 of_node_put(parent_np); 1352 if (!parent_domain) 1353 return -EPROBE_DEFER; 1354 1355 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 0, &of_args); 1356 if (ret) { 1357 dev_err(pctrl->dev, "Unable to parse gpio-ranges\n"); 1358 return ret; 1359 } 1360 1361 if (of_args.args[0] != 0 || of_args.args[1] != 0 || 1362 of_args.args[2] != pctrl->data->n_port_pins) { 1363 dev_err(pctrl->dev, "gpio-ranges does not match selected SOC\n"); 1364 return -EINVAL; 1365 } 1366 1367 chip->names = pctrl->data->port_pins; 1368 chip->request = rzg2l_gpio_request; 1369 chip->free = rzg2l_gpio_free; 1370 chip->get_direction = rzg2l_gpio_get_direction; 1371 chip->direction_input = rzg2l_gpio_direction_input; 1372 chip->direction_output = rzg2l_gpio_direction_output; 1373 chip->get = rzg2l_gpio_get; 1374 chip->set = rzg2l_gpio_set; 1375 chip->label = name; 1376 chip->parent = pctrl->dev; 1377 chip->owner = THIS_MODULE; 1378 chip->base = -1; 1379 chip->ngpio = of_args.args[2]; 1380 1381 girq = &chip->irq; 1382 gpio_irq_chip_set_chip(girq, &rzg2l_gpio_irqchip); 1383 girq->fwnode = of_node_to_fwnode(np); 1384 girq->parent_domain = parent_domain; 1385 girq->child_to_parent_hwirq = rzg2l_gpio_child_to_parent_hwirq; 1386 girq->populate_parent_alloc_arg = rzg2l_gpio_populate_parent_fwspec; 1387 girq->child_irq_domain_ops.free = rzg2l_gpio_irq_domain_free; 1388 girq->init_valid_mask = rzg2l_init_irq_valid_mask; 1389 1390 pctrl->gpio_range.id = 0; 1391 pctrl->gpio_range.pin_base = 0; 1392 pctrl->gpio_range.base = 0; 1393 pctrl->gpio_range.npins = chip->ngpio; 1394 pctrl->gpio_range.name = chip->label; 1395 pctrl->gpio_range.gc = chip; 1396 ret = devm_gpiochip_add_data(pctrl->dev, chip, pctrl); 1397 if (ret) { 1398 dev_err(pctrl->dev, "failed to add GPIO controller\n"); 1399 return ret; 1400 } 1401 1402 dev_dbg(pctrl->dev, "Registered gpio controller\n"); 1403 1404 return 0; 1405 } 1406 1407 static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) 1408 { 1409 struct pinctrl_pin_desc *pins; 1410 unsigned int i, j; 1411 u32 *pin_data; 1412 int ret; 1413 1414 pctrl->desc.name = DRV_NAME; 1415 pctrl->desc.npins = pctrl->data->n_port_pins + pctrl->data->n_dedicated_pins; 1416 pctrl->desc.pctlops = &rzg2l_pinctrl_pctlops; 1417 pctrl->desc.pmxops = &rzg2l_pinctrl_pmxops; 1418 pctrl->desc.confops = &rzg2l_pinctrl_confops; 1419 pctrl->desc.owner = THIS_MODULE; 1420 1421 pins = devm_kcalloc(pctrl->dev, pctrl->desc.npins, sizeof(*pins), GFP_KERNEL); 1422 if (!pins) 1423 return -ENOMEM; 1424 1425 pin_data = devm_kcalloc(pctrl->dev, pctrl->desc.npins, 1426 sizeof(*pin_data), GFP_KERNEL); 1427 if (!pin_data) 1428 return -ENOMEM; 1429 1430 pctrl->pins = pins; 1431 pctrl->desc.pins = pins; 1432 1433 for (i = 0, j = 0; i < pctrl->data->n_port_pins; i++) { 1434 pins[i].number = i; 1435 pins[i].name = pctrl->data->port_pins[i]; 1436 if (i && !(i % RZG2L_PINS_PER_PORT)) 1437 j++; 1438 pin_data[i] = pctrl->data->port_pin_configs[j]; 1439 pins[i].drv_data = &pin_data[i]; 1440 } 1441 1442 for (i = 0; i < pctrl->data->n_dedicated_pins; i++) { 1443 unsigned int index = pctrl->data->n_port_pins + i; 1444 1445 pins[index].number = index; 1446 pins[index].name = pctrl->data->dedicated_pins[i].name; 1447 pin_data[index] = pctrl->data->dedicated_pins[i].config; 1448 pins[index].drv_data = &pin_data[index]; 1449 } 1450 1451 ret = devm_pinctrl_register_and_init(pctrl->dev, &pctrl->desc, pctrl, 1452 &pctrl->pctl); 1453 if (ret) { 1454 dev_err(pctrl->dev, "pinctrl registration failed\n"); 1455 return ret; 1456 } 1457 1458 ret = pinctrl_enable(pctrl->pctl); 1459 if (ret) { 1460 dev_err(pctrl->dev, "pinctrl enable failed\n"); 1461 return ret; 1462 } 1463 1464 ret = rzg2l_gpio_register(pctrl); 1465 if (ret) { 1466 dev_err(pctrl->dev, "failed to add GPIO chip: %i\n", ret); 1467 return ret; 1468 } 1469 1470 return 0; 1471 } 1472 1473 static void rzg2l_pinctrl_clk_disable(void *data) 1474 { 1475 clk_disable_unprepare(data); 1476 } 1477 1478 static int rzg2l_pinctrl_probe(struct platform_device *pdev) 1479 { 1480 struct rzg2l_pinctrl *pctrl; 1481 int ret; 1482 1483 BUILD_BUG_ON(ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT > 1484 ARRAY_SIZE(rzg2l_gpio_names)); 1485 1486 BUILD_BUG_ON(ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT > 1487 ARRAY_SIZE(rzg2l_gpio_names)); 1488 1489 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1490 if (!pctrl) 1491 return -ENOMEM; 1492 1493 pctrl->dev = &pdev->dev; 1494 1495 pctrl->data = of_device_get_match_data(&pdev->dev); 1496 if (!pctrl->data) 1497 return -EINVAL; 1498 1499 pctrl->base = devm_platform_ioremap_resource(pdev, 0); 1500 if (IS_ERR(pctrl->base)) 1501 return PTR_ERR(pctrl->base); 1502 1503 pctrl->clk = devm_clk_get(pctrl->dev, NULL); 1504 if (IS_ERR(pctrl->clk)) { 1505 ret = PTR_ERR(pctrl->clk); 1506 dev_err(pctrl->dev, "failed to get GPIO clk : %i\n", ret); 1507 return ret; 1508 } 1509 1510 spin_lock_init(&pctrl->lock); 1511 spin_lock_init(&pctrl->bitmap_lock); 1512 1513 platform_set_drvdata(pdev, pctrl); 1514 1515 ret = clk_prepare_enable(pctrl->clk); 1516 if (ret) { 1517 dev_err(pctrl->dev, "failed to enable GPIO clk: %i\n", ret); 1518 return ret; 1519 } 1520 1521 ret = devm_add_action_or_reset(&pdev->dev, rzg2l_pinctrl_clk_disable, 1522 pctrl->clk); 1523 if (ret) { 1524 dev_err(pctrl->dev, 1525 "failed to register GPIO clk disable action, %i\n", 1526 ret); 1527 return ret; 1528 } 1529 1530 ret = rzg2l_pinctrl_register(pctrl); 1531 if (ret) 1532 return ret; 1533 1534 dev_info(pctrl->dev, "%s support registered\n", DRV_NAME); 1535 return 0; 1536 } 1537 1538 static struct rzg2l_pinctrl_data r9a07g043_data = { 1539 .port_pins = rzg2l_gpio_names, 1540 .port_pin_configs = r9a07g043_gpio_configs, 1541 .n_ports = ARRAY_SIZE(r9a07g043_gpio_configs), 1542 .dedicated_pins = rzg2l_dedicated_pins.common, 1543 .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, 1544 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), 1545 }; 1546 1547 static struct rzg2l_pinctrl_data r9a07g044_data = { 1548 .port_pins = rzg2l_gpio_names, 1549 .port_pin_configs = rzg2l_gpio_configs, 1550 .n_ports = ARRAY_SIZE(rzg2l_gpio_configs), 1551 .dedicated_pins = rzg2l_dedicated_pins.common, 1552 .n_port_pins = ARRAY_SIZE(rzg2l_gpio_configs) * RZG2L_PINS_PER_PORT, 1553 .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 1554 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 1555 }; 1556 1557 static const struct of_device_id rzg2l_pinctrl_of_table[] = { 1558 { 1559 .compatible = "renesas,r9a07g043-pinctrl", 1560 .data = &r9a07g043_data, 1561 }, 1562 { 1563 .compatible = "renesas,r9a07g044-pinctrl", 1564 .data = &r9a07g044_data, 1565 }, 1566 { /* sentinel */ } 1567 }; 1568 1569 static struct platform_driver rzg2l_pinctrl_driver = { 1570 .driver = { 1571 .name = DRV_NAME, 1572 .of_match_table = of_match_ptr(rzg2l_pinctrl_of_table), 1573 }, 1574 .probe = rzg2l_pinctrl_probe, 1575 }; 1576 1577 static int __init rzg2l_pinctrl_init(void) 1578 { 1579 return platform_driver_register(&rzg2l_pinctrl_driver); 1580 } 1581 core_initcall(rzg2l_pinctrl_init); 1582 1583 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 1584 MODULE_DESCRIPTION("Pin and gpio controller driver for RZ/G2L family"); 1585