1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/gpio/driver.h>
7 #include <linux/interrupt.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_irq.h>
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinconf.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <linux/spmi.h>
18 #include <linux/types.h>
19 
20 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
21 
22 #include "../core.h"
23 #include "../pinctrl-utils.h"
24 
25 #define PMIC_GPIO_ADDRESS_RANGE			0x100
26 
27 /* type and subtype registers base address offsets */
28 #define PMIC_GPIO_REG_TYPE			0x4
29 #define PMIC_GPIO_REG_SUBTYPE			0x5
30 
31 /* GPIO peripheral type and subtype out_values */
32 #define PMIC_GPIO_TYPE				0x10
33 #define PMIC_GPIO_SUBTYPE_GPIO_4CH		0x1
34 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH		0x5
35 #define PMIC_GPIO_SUBTYPE_GPIO_8CH		0x9
36 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH		0xd
37 #define PMIC_GPIO_SUBTYPE_GPIO_LV		0x10
38 #define PMIC_GPIO_SUBTYPE_GPIO_MV		0x11
39 
40 #define PMIC_MPP_REG_RT_STS			0x10
41 #define PMIC_MPP_REG_RT_STS_VAL_MASK		0x1
42 
43 /* control register base address offsets */
44 #define PMIC_GPIO_REG_MODE_CTL			0x40
45 #define PMIC_GPIO_REG_DIG_VIN_CTL		0x41
46 #define PMIC_GPIO_REG_DIG_PULL_CTL		0x42
47 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL	0x44
48 #define PMIC_GPIO_REG_DIG_IN_CTL		0x43
49 #define PMIC_GPIO_REG_DIG_OUT_CTL		0x45
50 #define PMIC_GPIO_REG_EN_CTL			0x46
51 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL	0x4A
52 
53 /* PMIC_GPIO_REG_MODE_CTL */
54 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT		0x1
55 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT	1
56 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK	0x7
57 #define PMIC_GPIO_REG_MODE_DIR_SHIFT		4
58 #define PMIC_GPIO_REG_MODE_DIR_MASK		0x7
59 
60 #define PMIC_GPIO_MODE_DIGITAL_INPUT		0
61 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT		1
62 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT	2
63 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU		3
64 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK	0x3
65 
66 /* PMIC_GPIO_REG_DIG_VIN_CTL */
67 #define PMIC_GPIO_REG_VIN_SHIFT			0
68 #define PMIC_GPIO_REG_VIN_MASK			0x7
69 
70 /* PMIC_GPIO_REG_DIG_PULL_CTL */
71 #define PMIC_GPIO_REG_PULL_SHIFT		0
72 #define PMIC_GPIO_REG_PULL_MASK			0x7
73 
74 #define PMIC_GPIO_PULL_DOWN			4
75 #define PMIC_GPIO_PULL_DISABLE			5
76 
77 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
78 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT		0x80
79 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT	7
80 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK	0xF
81 
82 /* PMIC_GPIO_REG_DIG_IN_CTL */
83 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN		0x80
84 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK	0x7
85 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK		0xf
86 
87 /* PMIC_GPIO_REG_DIG_OUT_CTL */
88 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT	0
89 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK		0x3
90 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT		4
91 #define PMIC_GPIO_REG_OUT_TYPE_MASK		0x3
92 
93 /*
94  * Output type - indicates pin should be configured as push-pull,
95  * open drain or open source.
96  */
97 #define PMIC_GPIO_OUT_BUF_CMOS			0
98 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS	1
99 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS	2
100 
101 /* PMIC_GPIO_REG_EN_CTL */
102 #define PMIC_GPIO_REG_MASTER_EN_SHIFT		7
103 
104 #define PMIC_GPIO_PHYSICAL_OFFSET		1
105 
106 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
107 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK		0x3
108 
109 /* Qualcomm specific pin configurations */
110 #define PMIC_GPIO_CONF_PULL_UP			(PIN_CONFIG_END + 1)
111 #define PMIC_GPIO_CONF_STRENGTH			(PIN_CONFIG_END + 2)
112 #define PMIC_GPIO_CONF_ATEST			(PIN_CONFIG_END + 3)
113 #define PMIC_GPIO_CONF_ANALOG_PASS		(PIN_CONFIG_END + 4)
114 #define PMIC_GPIO_CONF_DTEST_BUFFER		(PIN_CONFIG_END + 5)
115 
116 /* The index of each function in pmic_gpio_functions[] array */
117 enum pmic_gpio_func_index {
118 	PMIC_GPIO_FUNC_INDEX_NORMAL,
119 	PMIC_GPIO_FUNC_INDEX_PAIRED,
120 	PMIC_GPIO_FUNC_INDEX_FUNC1,
121 	PMIC_GPIO_FUNC_INDEX_FUNC2,
122 	PMIC_GPIO_FUNC_INDEX_FUNC3,
123 	PMIC_GPIO_FUNC_INDEX_FUNC4,
124 	PMIC_GPIO_FUNC_INDEX_DTEST1,
125 	PMIC_GPIO_FUNC_INDEX_DTEST2,
126 	PMIC_GPIO_FUNC_INDEX_DTEST3,
127 	PMIC_GPIO_FUNC_INDEX_DTEST4,
128 };
129 
130 /**
131  * struct pmic_gpio_pad - keep current GPIO settings
132  * @base: Address base in SPMI device.
133  * @is_enabled: Set to false when GPIO should be put in high Z state.
134  * @out_value: Cached pin output value
135  * @have_buffer: Set to true if GPIO output could be configured in push-pull,
136  *	open-drain or open-source mode.
137  * @output_enabled: Set to true if GPIO output logic is enabled.
138  * @input_enabled: Set to true if GPIO input buffer logic is enabled.
139  * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
140  * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
141  * @num_sources: Number of power-sources supported by this GPIO.
142  * @power_source: Current power-source used.
143  * @buffer_type: Push-pull, open-drain or open-source.
144  * @pullup: Constant current which flow trough GPIO output buffer.
145  * @strength: No, Low, Medium, High
146  * @function: See pmic_gpio_functions[]
147  * @atest: the ATEST selection for GPIO analog-pass-through mode
148  * @dtest_buffer: the DTEST buffer selection for digital input mode.
149  */
150 struct pmic_gpio_pad {
151 	u16		base;
152 	bool		is_enabled;
153 	bool		out_value;
154 	bool		have_buffer;
155 	bool		output_enabled;
156 	bool		input_enabled;
157 	bool		analog_pass;
158 	bool		lv_mv_type;
159 	unsigned int	num_sources;
160 	unsigned int	power_source;
161 	unsigned int	buffer_type;
162 	unsigned int	pullup;
163 	unsigned int	strength;
164 	unsigned int	function;
165 	unsigned int	atest;
166 	unsigned int	dtest_buffer;
167 };
168 
169 struct pmic_gpio_state {
170 	struct device	*dev;
171 	struct regmap	*map;
172 	struct pinctrl_dev *ctrl;
173 	struct gpio_chip chip;
174 	struct irq_chip irq;
175 	u8 usid;
176 	u8 pid_base;
177 };
178 
179 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
180 	{"qcom,pull-up-strength",	PMIC_GPIO_CONF_PULL_UP,		0},
181 	{"qcom,drive-strength",		PMIC_GPIO_CONF_STRENGTH,	0},
182 	{"qcom,atest",			PMIC_GPIO_CONF_ATEST,		0},
183 	{"qcom,analog-pass",		PMIC_GPIO_CONF_ANALOG_PASS,	0},
184 	{"qcom,dtest-buffer",           PMIC_GPIO_CONF_DTEST_BUFFER,    0},
185 };
186 
187 #ifdef CONFIG_DEBUG_FS
188 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
189 	PCONFDUMP(PMIC_GPIO_CONF_PULL_UP,  "pull up strength", NULL, true),
190 	PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
191 	PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
192 	PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
193 	PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
194 };
195 #endif
196 
197 static const char *const pmic_gpio_groups[] = {
198 	"gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
199 	"gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
200 	"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
201 	"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
202 	"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
203 };
204 
205 static const char *const pmic_gpio_functions[] = {
206 	[PMIC_GPIO_FUNC_INDEX_NORMAL]	= PMIC_GPIO_FUNC_NORMAL,
207 	[PMIC_GPIO_FUNC_INDEX_PAIRED]	= PMIC_GPIO_FUNC_PAIRED,
208 	[PMIC_GPIO_FUNC_INDEX_FUNC1]	= PMIC_GPIO_FUNC_FUNC1,
209 	[PMIC_GPIO_FUNC_INDEX_FUNC2]	= PMIC_GPIO_FUNC_FUNC2,
210 	[PMIC_GPIO_FUNC_INDEX_FUNC3]	= PMIC_GPIO_FUNC_FUNC3,
211 	[PMIC_GPIO_FUNC_INDEX_FUNC4]	= PMIC_GPIO_FUNC_FUNC4,
212 	[PMIC_GPIO_FUNC_INDEX_DTEST1]	= PMIC_GPIO_FUNC_DTEST1,
213 	[PMIC_GPIO_FUNC_INDEX_DTEST2]	= PMIC_GPIO_FUNC_DTEST2,
214 	[PMIC_GPIO_FUNC_INDEX_DTEST3]	= PMIC_GPIO_FUNC_DTEST3,
215 	[PMIC_GPIO_FUNC_INDEX_DTEST4]	= PMIC_GPIO_FUNC_DTEST4,
216 };
217 
218 static int pmic_gpio_read(struct pmic_gpio_state *state,
219 			  struct pmic_gpio_pad *pad, unsigned int addr)
220 {
221 	unsigned int val;
222 	int ret;
223 
224 	ret = regmap_read(state->map, pad->base + addr, &val);
225 	if (ret < 0)
226 		dev_err(state->dev, "read 0x%x failed\n", addr);
227 	else
228 		ret = val;
229 
230 	return ret;
231 }
232 
233 static int pmic_gpio_write(struct pmic_gpio_state *state,
234 			   struct pmic_gpio_pad *pad, unsigned int addr,
235 			   unsigned int val)
236 {
237 	int ret;
238 
239 	ret = regmap_write(state->map, pad->base + addr, val);
240 	if (ret < 0)
241 		dev_err(state->dev, "write 0x%x failed\n", addr);
242 
243 	return ret;
244 }
245 
246 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
247 {
248 	/* Every PIN is a group */
249 	return pctldev->desc->npins;
250 }
251 
252 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
253 					    unsigned pin)
254 {
255 	return pctldev->desc->pins[pin].name;
256 }
257 
258 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
259 				    const unsigned **pins, unsigned *num_pins)
260 {
261 	*pins = &pctldev->desc->pins[pin].number;
262 	*num_pins = 1;
263 	return 0;
264 }
265 
266 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
267 	.get_groups_count	= pmic_gpio_get_groups_count,
268 	.get_group_name		= pmic_gpio_get_group_name,
269 	.get_group_pins		= pmic_gpio_get_group_pins,
270 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
271 	.dt_free_map		= pinctrl_utils_free_map,
272 };
273 
274 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
275 {
276 	return ARRAY_SIZE(pmic_gpio_functions);
277 }
278 
279 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
280 					       unsigned function)
281 {
282 	return pmic_gpio_functions[function];
283 }
284 
285 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
286 					 unsigned function,
287 					 const char *const **groups,
288 					 unsigned *const num_qgroups)
289 {
290 	*groups = pmic_gpio_groups;
291 	*num_qgroups = pctldev->desc->npins;
292 	return 0;
293 }
294 
295 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
296 				unsigned pin)
297 {
298 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
299 	struct pmic_gpio_pad *pad;
300 	unsigned int val;
301 	int ret;
302 
303 	if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
304 		pr_err("function: %d is not defined\n", function);
305 		return -EINVAL;
306 	}
307 
308 	pad = pctldev->desc->pins[pin].drv_data;
309 	/*
310 	 * Non-LV/MV subtypes only support 2 special functions,
311 	 * offsetting the dtestx function values by 2
312 	 */
313 	if (!pad->lv_mv_type) {
314 		if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
315 				function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
316 			pr_err("LV/MV subtype doesn't have func3/func4\n");
317 			return -EINVAL;
318 		}
319 		if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
320 			function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
321 					PMIC_GPIO_FUNC_INDEX_FUNC3);
322 	}
323 
324 	pad->function = function;
325 
326 	if (pad->analog_pass)
327 		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
328 	else if (pad->output_enabled && pad->input_enabled)
329 		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
330 	else if (pad->output_enabled)
331 		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
332 	else
333 		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
334 
335 	if (pad->lv_mv_type) {
336 		ret = pmic_gpio_write(state, pad,
337 				PMIC_GPIO_REG_MODE_CTL, val);
338 		if (ret < 0)
339 			return ret;
340 
341 		val = pad->atest - 1;
342 		ret = pmic_gpio_write(state, pad,
343 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
344 		if (ret < 0)
345 			return ret;
346 
347 		val = pad->out_value
348 			<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
349 		val |= pad->function
350 			& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
351 		ret = pmic_gpio_write(state, pad,
352 			PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
353 		if (ret < 0)
354 			return ret;
355 	} else {
356 		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
357 		val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
358 		val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
359 
360 		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
361 		if (ret < 0)
362 			return ret;
363 	}
364 
365 	val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
366 
367 	return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
368 }
369 
370 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
371 	.get_functions_count	= pmic_gpio_get_functions_count,
372 	.get_function_name	= pmic_gpio_get_function_name,
373 	.get_function_groups	= pmic_gpio_get_function_groups,
374 	.set_mux		= pmic_gpio_set_mux,
375 };
376 
377 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
378 				unsigned int pin, unsigned long *config)
379 {
380 	unsigned param = pinconf_to_config_param(*config);
381 	struct pmic_gpio_pad *pad;
382 	unsigned arg;
383 
384 	pad = pctldev->desc->pins[pin].drv_data;
385 
386 	switch (param) {
387 	case PIN_CONFIG_DRIVE_PUSH_PULL:
388 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
389 			return -EINVAL;
390 		arg = 1;
391 		break;
392 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
393 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
394 			return -EINVAL;
395 		arg = 1;
396 		break;
397 	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
398 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
399 			return -EINVAL;
400 		arg = 1;
401 		break;
402 	case PIN_CONFIG_BIAS_PULL_DOWN:
403 		if (pad->pullup != PMIC_GPIO_PULL_DOWN)
404 			return -EINVAL;
405 		arg = 1;
406 		break;
407 	case PIN_CONFIG_BIAS_DISABLE:
408 		if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
409 			return -EINVAL;
410 		arg = 1;
411 		break;
412 	case PIN_CONFIG_BIAS_PULL_UP:
413 		if (pad->pullup != PMIC_GPIO_PULL_UP_30)
414 			return -EINVAL;
415 		arg = 1;
416 		break;
417 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
418 		if (pad->is_enabled)
419 			return -EINVAL;
420 		arg = 1;
421 		break;
422 	case PIN_CONFIG_POWER_SOURCE:
423 		arg = pad->power_source;
424 		break;
425 	case PIN_CONFIG_INPUT_ENABLE:
426 		if (!pad->input_enabled)
427 			return -EINVAL;
428 		arg = 1;
429 		break;
430 	case PIN_CONFIG_OUTPUT:
431 		arg = pad->out_value;
432 		break;
433 	case PMIC_GPIO_CONF_PULL_UP:
434 		arg = pad->pullup;
435 		break;
436 	case PMIC_GPIO_CONF_STRENGTH:
437 		arg = pad->strength;
438 		break;
439 	case PMIC_GPIO_CONF_ATEST:
440 		arg = pad->atest;
441 		break;
442 	case PMIC_GPIO_CONF_ANALOG_PASS:
443 		arg = pad->analog_pass;
444 		break;
445 	case PMIC_GPIO_CONF_DTEST_BUFFER:
446 		arg = pad->dtest_buffer;
447 		break;
448 	default:
449 		return -EINVAL;
450 	}
451 
452 	*config = pinconf_to_config_packed(param, arg);
453 	return 0;
454 }
455 
456 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
457 				unsigned long *configs, unsigned nconfs)
458 {
459 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
460 	struct pmic_gpio_pad *pad;
461 	unsigned param, arg;
462 	unsigned int val;
463 	int i, ret;
464 
465 	pad = pctldev->desc->pins[pin].drv_data;
466 
467 	pad->is_enabled = true;
468 	for (i = 0; i < nconfs; i++) {
469 		param = pinconf_to_config_param(configs[i]);
470 		arg = pinconf_to_config_argument(configs[i]);
471 
472 		switch (param) {
473 		case PIN_CONFIG_DRIVE_PUSH_PULL:
474 			pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
475 			break;
476 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
477 			if (!pad->have_buffer)
478 				return -EINVAL;
479 			pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
480 			break;
481 		case PIN_CONFIG_DRIVE_OPEN_SOURCE:
482 			if (!pad->have_buffer)
483 				return -EINVAL;
484 			pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
485 			break;
486 		case PIN_CONFIG_BIAS_DISABLE:
487 			pad->pullup = PMIC_GPIO_PULL_DISABLE;
488 			break;
489 		case PIN_CONFIG_BIAS_PULL_UP:
490 			pad->pullup = PMIC_GPIO_PULL_UP_30;
491 			break;
492 		case PIN_CONFIG_BIAS_PULL_DOWN:
493 			if (arg)
494 				pad->pullup = PMIC_GPIO_PULL_DOWN;
495 			else
496 				pad->pullup = PMIC_GPIO_PULL_DISABLE;
497 			break;
498 		case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
499 			pad->is_enabled = false;
500 			break;
501 		case PIN_CONFIG_POWER_SOURCE:
502 			if (arg >= pad->num_sources)
503 				return -EINVAL;
504 			pad->power_source = arg;
505 			break;
506 		case PIN_CONFIG_INPUT_ENABLE:
507 			pad->input_enabled = arg ? true : false;
508 			break;
509 		case PIN_CONFIG_OUTPUT:
510 			pad->output_enabled = true;
511 			pad->out_value = arg;
512 			break;
513 		case PMIC_GPIO_CONF_PULL_UP:
514 			if (arg > PMIC_GPIO_PULL_UP_1P5_30)
515 				return -EINVAL;
516 			pad->pullup = arg;
517 			break;
518 		case PMIC_GPIO_CONF_STRENGTH:
519 			if (arg > PMIC_GPIO_STRENGTH_LOW)
520 				return -EINVAL;
521 			pad->strength = arg;
522 			break;
523 		case PMIC_GPIO_CONF_ATEST:
524 			if (!pad->lv_mv_type || arg > 4)
525 				return -EINVAL;
526 			pad->atest = arg;
527 			break;
528 		case PMIC_GPIO_CONF_ANALOG_PASS:
529 			if (!pad->lv_mv_type)
530 				return -EINVAL;
531 			pad->analog_pass = true;
532 			break;
533 		case PMIC_GPIO_CONF_DTEST_BUFFER:
534 			if (arg > 4)
535 				return -EINVAL;
536 			pad->dtest_buffer = arg;
537 			break;
538 		default:
539 			return -EINVAL;
540 		}
541 	}
542 
543 	val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
544 
545 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
546 	if (ret < 0)
547 		return ret;
548 
549 	val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
550 
551 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
552 	if (ret < 0)
553 		return ret;
554 
555 	val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
556 	val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
557 
558 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
559 	if (ret < 0)
560 		return ret;
561 
562 	if (pad->dtest_buffer == 0) {
563 		val = 0;
564 	} else {
565 		if (pad->lv_mv_type) {
566 			val = pad->dtest_buffer - 1;
567 			val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
568 		} else {
569 			val = BIT(pad->dtest_buffer - 1);
570 		}
571 	}
572 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
573 	if (ret < 0)
574 		return ret;
575 
576 	if (pad->analog_pass)
577 		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
578 	else if (pad->output_enabled && pad->input_enabled)
579 		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
580 	else if (pad->output_enabled)
581 		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
582 	else
583 		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
584 
585 	if (pad->lv_mv_type) {
586 		ret = pmic_gpio_write(state, pad,
587 				PMIC_GPIO_REG_MODE_CTL, val);
588 		if (ret < 0)
589 			return ret;
590 
591 		val = pad->atest - 1;
592 		ret = pmic_gpio_write(state, pad,
593 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
594 		if (ret < 0)
595 			return ret;
596 
597 		val = pad->out_value
598 			<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
599 		val |= pad->function
600 			& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
601 		ret = pmic_gpio_write(state, pad,
602 			PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
603 		if (ret < 0)
604 			return ret;
605 	} else {
606 		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
607 		val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
608 		val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
609 
610 		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
611 		if (ret < 0)
612 			return ret;
613 	}
614 
615 	val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
616 
617 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
618 
619 	return ret;
620 }
621 
622 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
623 				      struct seq_file *s, unsigned pin)
624 {
625 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
626 	struct pmic_gpio_pad *pad;
627 	int ret, val, function;
628 
629 	static const char *const biases[] = {
630 		"pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
631 		"pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
632 	};
633 	static const char *const buffer_types[] = {
634 		"push-pull", "open-drain", "open-source"
635 	};
636 	static const char *const strengths[] = {
637 		"no", "high", "medium", "low"
638 	};
639 
640 	pad = pctldev->desc->pins[pin].drv_data;
641 
642 	seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
643 
644 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
645 
646 	if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
647 		seq_puts(s, " ---");
648 	} else {
649 		if (pad->input_enabled) {
650 			ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
651 			if (ret < 0)
652 				return;
653 
654 			ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
655 			pad->out_value = ret;
656 		}
657 		/*
658 		 * For the non-LV/MV subtypes only 2 special functions are
659 		 * available, offsetting the dtest function values by 2.
660 		 */
661 		function = pad->function;
662 		if (!pad->lv_mv_type &&
663 				pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
664 			function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
665 				PMIC_GPIO_FUNC_INDEX_FUNC3;
666 
667 		if (pad->analog_pass)
668 			seq_puts(s, " analog-pass");
669 		else
670 			seq_printf(s, " %-4s",
671 					pad->output_enabled ? "out" : "in");
672 		seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
673 		seq_printf(s, " %-7s", pmic_gpio_functions[function]);
674 		seq_printf(s, " vin-%d", pad->power_source);
675 		seq_printf(s, " %-27s", biases[pad->pullup]);
676 		seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
677 		seq_printf(s, " %-7s", strengths[pad->strength]);
678 		seq_printf(s, " atest-%d", pad->atest);
679 		seq_printf(s, " dtest-%d", pad->dtest_buffer);
680 	}
681 }
682 
683 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
684 	.is_generic			= true,
685 	.pin_config_group_get		= pmic_gpio_config_get,
686 	.pin_config_group_set		= pmic_gpio_config_set,
687 	.pin_config_group_dbg_show	= pmic_gpio_config_dbg_show,
688 };
689 
690 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
691 {
692 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
693 	unsigned long config;
694 
695 	config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
696 
697 	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
698 }
699 
700 static int pmic_gpio_direction_output(struct gpio_chip *chip,
701 				      unsigned pin, int val)
702 {
703 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
704 	unsigned long config;
705 
706 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
707 
708 	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
709 }
710 
711 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
712 {
713 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
714 	struct pmic_gpio_pad *pad;
715 	int ret;
716 
717 	pad = state->ctrl->desc->pins[pin].drv_data;
718 
719 	if (!pad->is_enabled)
720 		return -EINVAL;
721 
722 	if (pad->input_enabled) {
723 		ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
724 		if (ret < 0)
725 			return ret;
726 
727 		pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
728 	}
729 
730 	return !!pad->out_value;
731 }
732 
733 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
734 {
735 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
736 	unsigned long config;
737 
738 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
739 
740 	pmic_gpio_config_set(state->ctrl, pin, &config, 1);
741 }
742 
743 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
744 			      const struct of_phandle_args *gpio_desc,
745 			      u32 *flags)
746 {
747 	if (chip->of_gpio_n_cells < 2)
748 		return -EINVAL;
749 
750 	if (flags)
751 		*flags = gpio_desc->args[1];
752 
753 	return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
754 }
755 
756 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
757 {
758 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
759 	unsigned i;
760 
761 	for (i = 0; i < chip->ngpio; i++) {
762 		pmic_gpio_config_dbg_show(state->ctrl, s, i);
763 		seq_puts(s, "\n");
764 	}
765 }
766 
767 static const struct gpio_chip pmic_gpio_gpio_template = {
768 	.direction_input	= pmic_gpio_direction_input,
769 	.direction_output	= pmic_gpio_direction_output,
770 	.get			= pmic_gpio_get,
771 	.set			= pmic_gpio_set,
772 	.request		= gpiochip_generic_request,
773 	.free			= gpiochip_generic_free,
774 	.of_xlate		= pmic_gpio_of_xlate,
775 	.dbg_show		= pmic_gpio_dbg_show,
776 };
777 
778 static int pmic_gpio_populate(struct pmic_gpio_state *state,
779 			      struct pmic_gpio_pad *pad)
780 {
781 	int type, subtype, val, dir;
782 
783 	type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
784 	if (type < 0)
785 		return type;
786 
787 	if (type != PMIC_GPIO_TYPE) {
788 		dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
789 			type, pad->base);
790 		return -ENODEV;
791 	}
792 
793 	subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
794 	if (subtype < 0)
795 		return subtype;
796 
797 	switch (subtype) {
798 	case PMIC_GPIO_SUBTYPE_GPIO_4CH:
799 		pad->have_buffer = true;
800 		fallthrough;
801 	case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
802 		pad->num_sources = 4;
803 		break;
804 	case PMIC_GPIO_SUBTYPE_GPIO_8CH:
805 		pad->have_buffer = true;
806 		fallthrough;
807 	case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
808 		pad->num_sources = 8;
809 		break;
810 	case PMIC_GPIO_SUBTYPE_GPIO_LV:
811 		pad->num_sources = 1;
812 		pad->have_buffer = true;
813 		pad->lv_mv_type = true;
814 		break;
815 	case PMIC_GPIO_SUBTYPE_GPIO_MV:
816 		pad->num_sources = 2;
817 		pad->have_buffer = true;
818 		pad->lv_mv_type = true;
819 		break;
820 	default:
821 		dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
822 		return -ENODEV;
823 	}
824 
825 	if (pad->lv_mv_type) {
826 		val = pmic_gpio_read(state, pad,
827 				PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
828 		if (val < 0)
829 			return val;
830 
831 		pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
832 		pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
833 
834 		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
835 		if (val < 0)
836 			return val;
837 
838 		dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
839 	} else {
840 		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
841 		if (val < 0)
842 			return val;
843 
844 		pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
845 
846 		dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
847 		dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
848 		pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
849 		pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
850 	}
851 
852 	switch (dir) {
853 	case PMIC_GPIO_MODE_DIGITAL_INPUT:
854 		pad->input_enabled = true;
855 		pad->output_enabled = false;
856 		break;
857 	case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
858 		pad->input_enabled = false;
859 		pad->output_enabled = true;
860 		break;
861 	case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
862 		pad->input_enabled = true;
863 		pad->output_enabled = true;
864 		break;
865 	case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
866 		if (!pad->lv_mv_type)
867 			return -ENODEV;
868 		pad->analog_pass = true;
869 		break;
870 	default:
871 		dev_err(state->dev, "unknown GPIO direction\n");
872 		return -ENODEV;
873 	}
874 
875 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
876 	if (val < 0)
877 		return val;
878 
879 	pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
880 	pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
881 
882 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
883 	if (val < 0)
884 		return val;
885 
886 	pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
887 	pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
888 
889 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
890 	if (val < 0)
891 		return val;
892 
893 	if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
894 		pad->dtest_buffer =
895 			(val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
896 	else if (!pad->lv_mv_type)
897 		pad->dtest_buffer = ffs(val);
898 	else
899 		pad->dtest_buffer = 0;
900 
901 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
902 	if (val < 0)
903 		return val;
904 
905 	pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
906 	pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
907 
908 	pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
909 	pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
910 
911 	if (pad->lv_mv_type) {
912 		val = pmic_gpio_read(state, pad,
913 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
914 		if (val < 0)
915 			return val;
916 		pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
917 	}
918 
919 	/* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
920 	pad->is_enabled = true;
921 	return 0;
922 }
923 
924 static int pmic_gpio_domain_translate(struct irq_domain *domain,
925 				      struct irq_fwspec *fwspec,
926 				      unsigned long *hwirq,
927 				      unsigned int *type)
928 {
929 	struct pmic_gpio_state *state = container_of(domain->host_data,
930 						     struct pmic_gpio_state,
931 						     chip);
932 
933 	if (fwspec->param_count != 2 ||
934 	    fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
935 		return -EINVAL;
936 
937 	*hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
938 	*type = fwspec->param[1];
939 
940 	return 0;
941 }
942 
943 static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
944 						  unsigned int offset)
945 {
946 	return offset + PMIC_GPIO_PHYSICAL_OFFSET;
947 }
948 
949 static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
950 					   unsigned int child_hwirq,
951 					   unsigned int child_type,
952 					   unsigned int *parent_hwirq,
953 					   unsigned int *parent_type)
954 {
955 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
956 
957 	*parent_hwirq = child_hwirq + state->pid_base;
958 	*parent_type = child_type;
959 
960 	return 0;
961 }
962 
963 static void *pmic_gpio_populate_parent_fwspec(struct gpio_chip *chip,
964 					     unsigned int parent_hwirq,
965 					     unsigned int parent_type)
966 {
967 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
968 	struct irq_fwspec *fwspec;
969 
970 	fwspec = kzalloc(sizeof(*fwspec), GFP_KERNEL);
971 	if (!fwspec)
972 		return NULL;
973 
974 	fwspec->fwnode = chip->irq.parent_domain->fwnode;
975 
976 	fwspec->param_count = 4;
977 	fwspec->param[0] = state->usid;
978 	fwspec->param[1] = parent_hwirq;
979 	/* param[2] must be left as 0 */
980 	fwspec->param[3] = parent_type;
981 
982 	return fwspec;
983 }
984 
985 static int pmic_gpio_probe(struct platform_device *pdev)
986 {
987 	struct irq_domain *parent_domain;
988 	struct device_node *parent_node;
989 	struct device *dev = &pdev->dev;
990 	struct pinctrl_pin_desc *pindesc;
991 	struct pinctrl_desc *pctrldesc;
992 	struct pmic_gpio_pad *pad, *pads;
993 	struct pmic_gpio_state *state;
994 	struct gpio_irq_chip *girq;
995 	const struct spmi_device *parent_spmi_dev;
996 	int ret, npins, i;
997 	u32 reg;
998 
999 	ret = of_property_read_u32(dev->of_node, "reg", &reg);
1000 	if (ret < 0) {
1001 		dev_err(dev, "missing base address");
1002 		return ret;
1003 	}
1004 
1005 	npins = (uintptr_t) device_get_match_data(&pdev->dev);
1006 
1007 	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1008 	if (!state)
1009 		return -ENOMEM;
1010 
1011 	platform_set_drvdata(pdev, state);
1012 
1013 	state->dev = &pdev->dev;
1014 	state->map = dev_get_regmap(dev->parent, NULL);
1015 	parent_spmi_dev = to_spmi_device(dev->parent);
1016 	state->usid = parent_spmi_dev->usid;
1017 	state->pid_base = reg >> 8;
1018 
1019 	pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
1020 	if (!pindesc)
1021 		return -ENOMEM;
1022 
1023 	pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
1024 	if (!pads)
1025 		return -ENOMEM;
1026 
1027 	pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
1028 	if (!pctrldesc)
1029 		return -ENOMEM;
1030 
1031 	pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1032 	pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1033 	pctrldesc->confops = &pmic_gpio_pinconf_ops;
1034 	pctrldesc->owner = THIS_MODULE;
1035 	pctrldesc->name = dev_name(dev);
1036 	pctrldesc->pins = pindesc;
1037 	pctrldesc->npins = npins;
1038 	pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1039 	pctrldesc->custom_params = pmic_gpio_bindings;
1040 #ifdef CONFIG_DEBUG_FS
1041 	pctrldesc->custom_conf_items = pmic_conf_items;
1042 #endif
1043 
1044 	for (i = 0; i < npins; i++, pindesc++) {
1045 		pad = &pads[i];
1046 		pindesc->drv_data = pad;
1047 		pindesc->number = i;
1048 		pindesc->name = pmic_gpio_groups[i];
1049 
1050 		pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1051 
1052 		ret = pmic_gpio_populate(state, pad);
1053 		if (ret < 0)
1054 			return ret;
1055 	}
1056 
1057 	state->chip = pmic_gpio_gpio_template;
1058 	state->chip.parent = dev;
1059 	state->chip.base = -1;
1060 	state->chip.ngpio = npins;
1061 	state->chip.label = dev_name(dev);
1062 	state->chip.of_gpio_n_cells = 2;
1063 	state->chip.can_sleep = false;
1064 
1065 	state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1066 	if (IS_ERR(state->ctrl))
1067 		return PTR_ERR(state->ctrl);
1068 
1069 	parent_node = of_irq_find_parent(state->dev->of_node);
1070 	if (!parent_node)
1071 		return -ENXIO;
1072 
1073 	parent_domain = irq_find_host(parent_node);
1074 	of_node_put(parent_node);
1075 	if (!parent_domain)
1076 		return -ENXIO;
1077 
1078 	state->irq.name = "spmi-gpio",
1079 	state->irq.irq_ack = irq_chip_ack_parent,
1080 	state->irq.irq_mask = irq_chip_mask_parent,
1081 	state->irq.irq_unmask = irq_chip_unmask_parent,
1082 	state->irq.irq_set_type = irq_chip_set_type_parent,
1083 	state->irq.irq_set_wake = irq_chip_set_wake_parent,
1084 	state->irq.flags = IRQCHIP_MASK_ON_SUSPEND,
1085 
1086 	girq = &state->chip.irq;
1087 	girq->chip = &state->irq;
1088 	girq->default_type = IRQ_TYPE_NONE;
1089 	girq->handler = handle_level_irq;
1090 	girq->fwnode = of_node_to_fwnode(state->dev->of_node);
1091 	girq->parent_domain = parent_domain;
1092 	girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
1093 	girq->populate_parent_alloc_arg = pmic_gpio_populate_parent_fwspec;
1094 	girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
1095 	girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
1096 
1097 	ret = gpiochip_add_data(&state->chip, state);
1098 	if (ret) {
1099 		dev_err(state->dev, "can't add gpio chip\n");
1100 		return ret;
1101 	}
1102 
1103 	/*
1104 	 * For DeviceTree-supported systems, the gpio core checks the
1105 	 * pinctrl's device node for the "gpio-ranges" property.
1106 	 * If it is present, it takes care of adding the pin ranges
1107 	 * for the driver. In this case the driver can skip ahead.
1108 	 *
1109 	 * In order to remain compatible with older, existing DeviceTree
1110 	 * files which don't set the "gpio-ranges" property or systems that
1111 	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1112 	 */
1113 	if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
1114 		ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1115 					     npins);
1116 		if (ret) {
1117 			dev_err(dev, "failed to add pin range\n");
1118 			goto err_range;
1119 		}
1120 	}
1121 
1122 	return 0;
1123 
1124 err_range:
1125 	gpiochip_remove(&state->chip);
1126 	return ret;
1127 }
1128 
1129 static int pmic_gpio_remove(struct platform_device *pdev)
1130 {
1131 	struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1132 
1133 	gpiochip_remove(&state->chip);
1134 	return 0;
1135 }
1136 
1137 static const struct of_device_id pmic_gpio_of_match[] = {
1138 	/* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
1139 	{ .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
1140 	/* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
1141 	{ .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
1142 	{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
1143 	{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
1144 	{ .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
1145 	{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1146 	{ .compatible = "qcom,pm8008-gpio", .data = (void *) 2 },
1147 	/* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
1148 	{ .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
1149 	{ .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 },
1150 	/* pm8150b has 12 GPIOs with holes on 3, r and 7 */
1151 	{ .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
1152 	/* pm8150l has 12 GPIOs with holes on 7 */
1153 	{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
1154 	{ .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 },
1155 	{ .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
1156 	{ .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
1157 	{ .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
1158 	{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1159 	{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1160 	/* pm8950 has 8 GPIOs with holes on 3 */
1161 	{ .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
1162 	{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1163 	{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1164 	{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1165 	{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
1166 	{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1167 	{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1168 	{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
1169 	{ .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
1170 	{ .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
1171 	{ .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
1172 	/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1173 	{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1174 	/* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
1175 	{ .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
1176 	{ },
1177 };
1178 
1179 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1180 
1181 static struct platform_driver pmic_gpio_driver = {
1182 	.driver = {
1183 		   .name = "qcom-spmi-gpio",
1184 		   .of_match_table = pmic_gpio_of_match,
1185 	},
1186 	.probe	= pmic_gpio_probe,
1187 	.remove = pmic_gpio_remove,
1188 };
1189 
1190 module_platform_driver(pmic_gpio_driver);
1191 
1192 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1193 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1194 MODULE_ALIAS("platform:qcom-spmi-gpio");
1195 MODULE_LICENSE("GPL v2");
1196