1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/gpio/driver.h>
7 #include <linux/interrupt.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_irq.h>
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinconf.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <linux/spmi.h>
18 #include <linux/types.h>
19 
20 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
21 
22 #include "../core.h"
23 #include "../pinctrl-utils.h"
24 
25 #define PMIC_GPIO_ADDRESS_RANGE			0x100
26 
27 /* type and subtype registers base address offsets */
28 #define PMIC_GPIO_REG_TYPE			0x4
29 #define PMIC_GPIO_REG_SUBTYPE			0x5
30 
31 /* GPIO peripheral type and subtype out_values */
32 #define PMIC_GPIO_TYPE				0x10
33 #define PMIC_GPIO_SUBTYPE_GPIO_4CH		0x1
34 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH		0x5
35 #define PMIC_GPIO_SUBTYPE_GPIO_8CH		0x9
36 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH		0xd
37 #define PMIC_GPIO_SUBTYPE_GPIO_LV		0x10
38 #define PMIC_GPIO_SUBTYPE_GPIO_MV		0x11
39 
40 #define PMIC_MPP_REG_RT_STS			0x10
41 #define PMIC_MPP_REG_RT_STS_VAL_MASK		0x1
42 
43 /* control register base address offsets */
44 #define PMIC_GPIO_REG_MODE_CTL			0x40
45 #define PMIC_GPIO_REG_DIG_VIN_CTL		0x41
46 #define PMIC_GPIO_REG_DIG_PULL_CTL		0x42
47 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL	0x44
48 #define PMIC_GPIO_REG_DIG_IN_CTL		0x43
49 #define PMIC_GPIO_REG_DIG_OUT_CTL		0x45
50 #define PMIC_GPIO_REG_EN_CTL			0x46
51 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL	0x4A
52 
53 /* PMIC_GPIO_REG_MODE_CTL */
54 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT		0x1
55 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT	1
56 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK	0x7
57 #define PMIC_GPIO_REG_MODE_DIR_SHIFT		4
58 #define PMIC_GPIO_REG_MODE_DIR_MASK		0x7
59 
60 #define PMIC_GPIO_MODE_DIGITAL_INPUT		0
61 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT		1
62 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT	2
63 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU		3
64 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK	0x3
65 
66 /* PMIC_GPIO_REG_DIG_VIN_CTL */
67 #define PMIC_GPIO_REG_VIN_SHIFT			0
68 #define PMIC_GPIO_REG_VIN_MASK			0x7
69 
70 /* PMIC_GPIO_REG_DIG_PULL_CTL */
71 #define PMIC_GPIO_REG_PULL_SHIFT		0
72 #define PMIC_GPIO_REG_PULL_MASK			0x7
73 
74 #define PMIC_GPIO_PULL_DOWN			4
75 #define PMIC_GPIO_PULL_DISABLE			5
76 
77 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
78 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT		0x80
79 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT	7
80 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK	0xF
81 
82 /* PMIC_GPIO_REG_DIG_IN_CTL */
83 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN		0x80
84 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK	0x7
85 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK		0xf
86 
87 /* PMIC_GPIO_REG_DIG_OUT_CTL */
88 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT	0
89 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK		0x3
90 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT		4
91 #define PMIC_GPIO_REG_OUT_TYPE_MASK		0x3
92 
93 /*
94  * Output type - indicates pin should be configured as push-pull,
95  * open drain or open source.
96  */
97 #define PMIC_GPIO_OUT_BUF_CMOS			0
98 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS	1
99 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS	2
100 
101 /* PMIC_GPIO_REG_EN_CTL */
102 #define PMIC_GPIO_REG_MASTER_EN_SHIFT		7
103 
104 #define PMIC_GPIO_PHYSICAL_OFFSET		1
105 
106 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
107 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK		0x3
108 
109 /* Qualcomm specific pin configurations */
110 #define PMIC_GPIO_CONF_PULL_UP			(PIN_CONFIG_END + 1)
111 #define PMIC_GPIO_CONF_STRENGTH			(PIN_CONFIG_END + 2)
112 #define PMIC_GPIO_CONF_ATEST			(PIN_CONFIG_END + 3)
113 #define PMIC_GPIO_CONF_ANALOG_PASS		(PIN_CONFIG_END + 4)
114 #define PMIC_GPIO_CONF_DTEST_BUFFER		(PIN_CONFIG_END + 5)
115 
116 /* The index of each function in pmic_gpio_functions[] array */
117 enum pmic_gpio_func_index {
118 	PMIC_GPIO_FUNC_INDEX_NORMAL,
119 	PMIC_GPIO_FUNC_INDEX_PAIRED,
120 	PMIC_GPIO_FUNC_INDEX_FUNC1,
121 	PMIC_GPIO_FUNC_INDEX_FUNC2,
122 	PMIC_GPIO_FUNC_INDEX_FUNC3,
123 	PMIC_GPIO_FUNC_INDEX_FUNC4,
124 	PMIC_GPIO_FUNC_INDEX_DTEST1,
125 	PMIC_GPIO_FUNC_INDEX_DTEST2,
126 	PMIC_GPIO_FUNC_INDEX_DTEST3,
127 	PMIC_GPIO_FUNC_INDEX_DTEST4,
128 };
129 
130 /**
131  * struct pmic_gpio_pad - keep current GPIO settings
132  * @base: Address base in SPMI device.
133  * @is_enabled: Set to false when GPIO should be put in high Z state.
134  * @out_value: Cached pin output value
135  * @have_buffer: Set to true if GPIO output could be configured in push-pull,
136  *	open-drain or open-source mode.
137  * @output_enabled: Set to true if GPIO output logic is enabled.
138  * @input_enabled: Set to true if GPIO input buffer logic is enabled.
139  * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
140  * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
141  * @num_sources: Number of power-sources supported by this GPIO.
142  * @power_source: Current power-source used.
143  * @buffer_type: Push-pull, open-drain or open-source.
144  * @pullup: Constant current which flow trough GPIO output buffer.
145  * @strength: No, Low, Medium, High
146  * @function: See pmic_gpio_functions[]
147  * @atest: the ATEST selection for GPIO analog-pass-through mode
148  * @dtest_buffer: the DTEST buffer selection for digital input mode.
149  */
150 struct pmic_gpio_pad {
151 	u16		base;
152 	bool		is_enabled;
153 	bool		out_value;
154 	bool		have_buffer;
155 	bool		output_enabled;
156 	bool		input_enabled;
157 	bool		analog_pass;
158 	bool		lv_mv_type;
159 	unsigned int	num_sources;
160 	unsigned int	power_source;
161 	unsigned int	buffer_type;
162 	unsigned int	pullup;
163 	unsigned int	strength;
164 	unsigned int	function;
165 	unsigned int	atest;
166 	unsigned int	dtest_buffer;
167 };
168 
169 struct pmic_gpio_state {
170 	struct device	*dev;
171 	struct regmap	*map;
172 	struct pinctrl_dev *ctrl;
173 	struct gpio_chip chip;
174 	struct irq_chip irq;
175 	u8 usid;
176 	u8 pid_base;
177 };
178 
179 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
180 	{"qcom,pull-up-strength",	PMIC_GPIO_CONF_PULL_UP,		0},
181 	{"qcom,drive-strength",		PMIC_GPIO_CONF_STRENGTH,	0},
182 	{"qcom,atest",			PMIC_GPIO_CONF_ATEST,		0},
183 	{"qcom,analog-pass",		PMIC_GPIO_CONF_ANALOG_PASS,	0},
184 	{"qcom,dtest-buffer",           PMIC_GPIO_CONF_DTEST_BUFFER,    0},
185 };
186 
187 #ifdef CONFIG_DEBUG_FS
188 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
189 	PCONFDUMP(PMIC_GPIO_CONF_PULL_UP,  "pull up strength", NULL, true),
190 	PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
191 	PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
192 	PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
193 	PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
194 };
195 #endif
196 
197 static const char *const pmic_gpio_groups[] = {
198 	"gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
199 	"gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
200 	"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
201 	"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
202 	"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
203 };
204 
205 static const char *const pmic_gpio_functions[] = {
206 	[PMIC_GPIO_FUNC_INDEX_NORMAL]	= PMIC_GPIO_FUNC_NORMAL,
207 	[PMIC_GPIO_FUNC_INDEX_PAIRED]	= PMIC_GPIO_FUNC_PAIRED,
208 	[PMIC_GPIO_FUNC_INDEX_FUNC1]	= PMIC_GPIO_FUNC_FUNC1,
209 	[PMIC_GPIO_FUNC_INDEX_FUNC2]	= PMIC_GPIO_FUNC_FUNC2,
210 	[PMIC_GPIO_FUNC_INDEX_FUNC3]	= PMIC_GPIO_FUNC_FUNC3,
211 	[PMIC_GPIO_FUNC_INDEX_FUNC4]	= PMIC_GPIO_FUNC_FUNC4,
212 	[PMIC_GPIO_FUNC_INDEX_DTEST1]	= PMIC_GPIO_FUNC_DTEST1,
213 	[PMIC_GPIO_FUNC_INDEX_DTEST2]	= PMIC_GPIO_FUNC_DTEST2,
214 	[PMIC_GPIO_FUNC_INDEX_DTEST3]	= PMIC_GPIO_FUNC_DTEST3,
215 	[PMIC_GPIO_FUNC_INDEX_DTEST4]	= PMIC_GPIO_FUNC_DTEST4,
216 };
217 
218 static int pmic_gpio_read(struct pmic_gpio_state *state,
219 			  struct pmic_gpio_pad *pad, unsigned int addr)
220 {
221 	unsigned int val;
222 	int ret;
223 
224 	ret = regmap_read(state->map, pad->base + addr, &val);
225 	if (ret < 0)
226 		dev_err(state->dev, "read 0x%x failed\n", addr);
227 	else
228 		ret = val;
229 
230 	return ret;
231 }
232 
233 static int pmic_gpio_write(struct pmic_gpio_state *state,
234 			   struct pmic_gpio_pad *pad, unsigned int addr,
235 			   unsigned int val)
236 {
237 	int ret;
238 
239 	ret = regmap_write(state->map, pad->base + addr, val);
240 	if (ret < 0)
241 		dev_err(state->dev, "write 0x%x failed\n", addr);
242 
243 	return ret;
244 }
245 
246 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
247 {
248 	/* Every PIN is a group */
249 	return pctldev->desc->npins;
250 }
251 
252 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
253 					    unsigned pin)
254 {
255 	return pctldev->desc->pins[pin].name;
256 }
257 
258 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
259 				    const unsigned **pins, unsigned *num_pins)
260 {
261 	*pins = &pctldev->desc->pins[pin].number;
262 	*num_pins = 1;
263 	return 0;
264 }
265 
266 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
267 	.get_groups_count	= pmic_gpio_get_groups_count,
268 	.get_group_name		= pmic_gpio_get_group_name,
269 	.get_group_pins		= pmic_gpio_get_group_pins,
270 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
271 	.dt_free_map		= pinctrl_utils_free_map,
272 };
273 
274 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
275 {
276 	return ARRAY_SIZE(pmic_gpio_functions);
277 }
278 
279 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
280 					       unsigned function)
281 {
282 	return pmic_gpio_functions[function];
283 }
284 
285 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
286 					 unsigned function,
287 					 const char *const **groups,
288 					 unsigned *const num_qgroups)
289 {
290 	*groups = pmic_gpio_groups;
291 	*num_qgroups = pctldev->desc->npins;
292 	return 0;
293 }
294 
295 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
296 				unsigned pin)
297 {
298 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
299 	struct pmic_gpio_pad *pad;
300 	unsigned int val;
301 	int ret;
302 
303 	if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
304 		pr_err("function: %d is not defined\n", function);
305 		return -EINVAL;
306 	}
307 
308 	pad = pctldev->desc->pins[pin].drv_data;
309 	/*
310 	 * Non-LV/MV subtypes only support 2 special functions,
311 	 * offsetting the dtestx function values by 2
312 	 */
313 	if (!pad->lv_mv_type) {
314 		if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
315 				function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
316 			pr_err("LV/MV subtype doesn't have func3/func4\n");
317 			return -EINVAL;
318 		}
319 		if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
320 			function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
321 					PMIC_GPIO_FUNC_INDEX_FUNC3);
322 	}
323 
324 	pad->function = function;
325 
326 	if (pad->analog_pass)
327 		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
328 	else if (pad->output_enabled && pad->input_enabled)
329 		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
330 	else if (pad->output_enabled)
331 		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
332 	else
333 		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
334 
335 	if (pad->lv_mv_type) {
336 		ret = pmic_gpio_write(state, pad,
337 				PMIC_GPIO_REG_MODE_CTL, val);
338 		if (ret < 0)
339 			return ret;
340 
341 		val = pad->atest - 1;
342 		ret = pmic_gpio_write(state, pad,
343 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
344 		if (ret < 0)
345 			return ret;
346 
347 		val = pad->out_value
348 			<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
349 		val |= pad->function
350 			& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
351 		ret = pmic_gpio_write(state, pad,
352 			PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
353 		if (ret < 0)
354 			return ret;
355 	} else {
356 		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
357 		val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
358 		val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
359 
360 		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
361 		if (ret < 0)
362 			return ret;
363 	}
364 
365 	val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
366 
367 	return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
368 }
369 
370 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
371 	.get_functions_count	= pmic_gpio_get_functions_count,
372 	.get_function_name	= pmic_gpio_get_function_name,
373 	.get_function_groups	= pmic_gpio_get_function_groups,
374 	.set_mux		= pmic_gpio_set_mux,
375 };
376 
377 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
378 				unsigned int pin, unsigned long *config)
379 {
380 	unsigned param = pinconf_to_config_param(*config);
381 	struct pmic_gpio_pad *pad;
382 	unsigned arg;
383 
384 	pad = pctldev->desc->pins[pin].drv_data;
385 
386 	switch (param) {
387 	case PIN_CONFIG_DRIVE_PUSH_PULL:
388 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
389 			return -EINVAL;
390 		arg = 1;
391 		break;
392 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
393 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
394 			return -EINVAL;
395 		arg = 1;
396 		break;
397 	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
398 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
399 			return -EINVAL;
400 		arg = 1;
401 		break;
402 	case PIN_CONFIG_BIAS_PULL_DOWN:
403 		if (pad->pullup != PMIC_GPIO_PULL_DOWN)
404 			return -EINVAL;
405 		arg = 1;
406 		break;
407 	case PIN_CONFIG_BIAS_DISABLE:
408 		if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
409 			return -EINVAL;
410 		arg = 1;
411 		break;
412 	case PIN_CONFIG_BIAS_PULL_UP:
413 		if (pad->pullup != PMIC_GPIO_PULL_UP_30)
414 			return -EINVAL;
415 		arg = 1;
416 		break;
417 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
418 		if (pad->is_enabled)
419 			return -EINVAL;
420 		arg = 1;
421 		break;
422 	case PIN_CONFIG_POWER_SOURCE:
423 		arg = pad->power_source;
424 		break;
425 	case PIN_CONFIG_INPUT_ENABLE:
426 		if (!pad->input_enabled)
427 			return -EINVAL;
428 		arg = 1;
429 		break;
430 	case PIN_CONFIG_OUTPUT_ENABLE:
431 		arg = pad->output_enabled;
432 		break;
433 	case PIN_CONFIG_OUTPUT:
434 		arg = pad->out_value;
435 		break;
436 	case PMIC_GPIO_CONF_PULL_UP:
437 		arg = pad->pullup;
438 		break;
439 	case PMIC_GPIO_CONF_STRENGTH:
440 		arg = pad->strength;
441 		break;
442 	case PMIC_GPIO_CONF_ATEST:
443 		arg = pad->atest;
444 		break;
445 	case PMIC_GPIO_CONF_ANALOG_PASS:
446 		arg = pad->analog_pass;
447 		break;
448 	case PMIC_GPIO_CONF_DTEST_BUFFER:
449 		arg = pad->dtest_buffer;
450 		break;
451 	default:
452 		return -EINVAL;
453 	}
454 
455 	*config = pinconf_to_config_packed(param, arg);
456 	return 0;
457 }
458 
459 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
460 				unsigned long *configs, unsigned nconfs)
461 {
462 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
463 	struct pmic_gpio_pad *pad;
464 	unsigned param, arg;
465 	unsigned int val;
466 	int i, ret;
467 
468 	pad = pctldev->desc->pins[pin].drv_data;
469 
470 	pad->is_enabled = true;
471 	for (i = 0; i < nconfs; i++) {
472 		param = pinconf_to_config_param(configs[i]);
473 		arg = pinconf_to_config_argument(configs[i]);
474 
475 		switch (param) {
476 		case PIN_CONFIG_DRIVE_PUSH_PULL:
477 			pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
478 			break;
479 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
480 			if (!pad->have_buffer)
481 				return -EINVAL;
482 			pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
483 			break;
484 		case PIN_CONFIG_DRIVE_OPEN_SOURCE:
485 			if (!pad->have_buffer)
486 				return -EINVAL;
487 			pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
488 			break;
489 		case PIN_CONFIG_BIAS_DISABLE:
490 			pad->pullup = PMIC_GPIO_PULL_DISABLE;
491 			break;
492 		case PIN_CONFIG_BIAS_PULL_UP:
493 			pad->pullup = PMIC_GPIO_PULL_UP_30;
494 			break;
495 		case PIN_CONFIG_BIAS_PULL_DOWN:
496 			if (arg)
497 				pad->pullup = PMIC_GPIO_PULL_DOWN;
498 			else
499 				pad->pullup = PMIC_GPIO_PULL_DISABLE;
500 			break;
501 		case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
502 			pad->is_enabled = false;
503 			break;
504 		case PIN_CONFIG_POWER_SOURCE:
505 			if (arg >= pad->num_sources)
506 				return -EINVAL;
507 			pad->power_source = arg;
508 			break;
509 		case PIN_CONFIG_INPUT_ENABLE:
510 			pad->input_enabled = arg ? true : false;
511 			break;
512 		case PIN_CONFIG_OUTPUT_ENABLE:
513 			pad->output_enabled = arg ? true : false;
514 			break;
515 		case PIN_CONFIG_OUTPUT:
516 			pad->output_enabled = true;
517 			pad->out_value = arg;
518 			break;
519 		case PMIC_GPIO_CONF_PULL_UP:
520 			if (arg > PMIC_GPIO_PULL_UP_1P5_30)
521 				return -EINVAL;
522 			pad->pullup = arg;
523 			break;
524 		case PMIC_GPIO_CONF_STRENGTH:
525 			if (arg > PMIC_GPIO_STRENGTH_LOW)
526 				return -EINVAL;
527 			pad->strength = arg;
528 			break;
529 		case PMIC_GPIO_CONF_ATEST:
530 			if (!pad->lv_mv_type || arg > 4)
531 				return -EINVAL;
532 			pad->atest = arg;
533 			break;
534 		case PMIC_GPIO_CONF_ANALOG_PASS:
535 			if (!pad->lv_mv_type)
536 				return -EINVAL;
537 			pad->analog_pass = true;
538 			break;
539 		case PMIC_GPIO_CONF_DTEST_BUFFER:
540 			if (arg > 4)
541 				return -EINVAL;
542 			pad->dtest_buffer = arg;
543 			break;
544 		default:
545 			return -EINVAL;
546 		}
547 	}
548 
549 	val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
550 
551 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
552 	if (ret < 0)
553 		return ret;
554 
555 	val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
556 
557 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
558 	if (ret < 0)
559 		return ret;
560 
561 	val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
562 	val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
563 
564 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
565 	if (ret < 0)
566 		return ret;
567 
568 	if (pad->dtest_buffer == 0) {
569 		val = 0;
570 	} else {
571 		if (pad->lv_mv_type) {
572 			val = pad->dtest_buffer - 1;
573 			val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
574 		} else {
575 			val = BIT(pad->dtest_buffer - 1);
576 		}
577 	}
578 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
579 	if (ret < 0)
580 		return ret;
581 
582 	if (pad->analog_pass)
583 		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
584 	else if (pad->output_enabled && pad->input_enabled)
585 		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
586 	else if (pad->output_enabled)
587 		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
588 	else
589 		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
590 
591 	if (pad->lv_mv_type) {
592 		ret = pmic_gpio_write(state, pad,
593 				PMIC_GPIO_REG_MODE_CTL, val);
594 		if (ret < 0)
595 			return ret;
596 
597 		val = pad->atest - 1;
598 		ret = pmic_gpio_write(state, pad,
599 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
600 		if (ret < 0)
601 			return ret;
602 
603 		val = pad->out_value
604 			<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
605 		val |= pad->function
606 			& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
607 		ret = pmic_gpio_write(state, pad,
608 			PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
609 		if (ret < 0)
610 			return ret;
611 	} else {
612 		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
613 		val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
614 		val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
615 
616 		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
617 		if (ret < 0)
618 			return ret;
619 	}
620 
621 	val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
622 
623 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
624 
625 	return ret;
626 }
627 
628 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
629 				      struct seq_file *s, unsigned pin)
630 {
631 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
632 	struct pmic_gpio_pad *pad;
633 	int ret, val, function;
634 
635 	static const char *const biases[] = {
636 		"pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
637 		"pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
638 	};
639 	static const char *const buffer_types[] = {
640 		"push-pull", "open-drain", "open-source"
641 	};
642 	static const char *const strengths[] = {
643 		"no", "high", "medium", "low"
644 	};
645 
646 	pad = pctldev->desc->pins[pin].drv_data;
647 
648 	seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
649 
650 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
651 
652 	if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
653 		seq_puts(s, " ---");
654 	} else {
655 		if (pad->input_enabled) {
656 			ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
657 			if (ret < 0)
658 				return;
659 
660 			ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
661 			pad->out_value = ret;
662 		}
663 		/*
664 		 * For the non-LV/MV subtypes only 2 special functions are
665 		 * available, offsetting the dtest function values by 2.
666 		 */
667 		function = pad->function;
668 		if (!pad->lv_mv_type &&
669 				pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
670 			function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
671 				PMIC_GPIO_FUNC_INDEX_FUNC3;
672 
673 		if (pad->analog_pass)
674 			seq_puts(s, " analog-pass");
675 		else
676 			seq_printf(s, " %-4s",
677 					pad->output_enabled ? "out" : "in");
678 		seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
679 		seq_printf(s, " %-7s", pmic_gpio_functions[function]);
680 		seq_printf(s, " vin-%d", pad->power_source);
681 		seq_printf(s, " %-27s", biases[pad->pullup]);
682 		seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
683 		seq_printf(s, " %-7s", strengths[pad->strength]);
684 		seq_printf(s, " atest-%d", pad->atest);
685 		seq_printf(s, " dtest-%d", pad->dtest_buffer);
686 	}
687 }
688 
689 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
690 	.is_generic			= true,
691 	.pin_config_group_get		= pmic_gpio_config_get,
692 	.pin_config_group_set		= pmic_gpio_config_set,
693 	.pin_config_group_dbg_show	= pmic_gpio_config_dbg_show,
694 };
695 
696 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
697 {
698 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
699 	unsigned long config;
700 
701 	config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
702 
703 	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
704 }
705 
706 static int pmic_gpio_direction_output(struct gpio_chip *chip,
707 				      unsigned pin, int val)
708 {
709 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
710 	unsigned long config;
711 
712 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
713 
714 	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
715 }
716 
717 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
718 {
719 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
720 	struct pmic_gpio_pad *pad;
721 	int ret;
722 
723 	pad = state->ctrl->desc->pins[pin].drv_data;
724 
725 	if (!pad->is_enabled)
726 		return -EINVAL;
727 
728 	if (pad->input_enabled) {
729 		ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
730 		if (ret < 0)
731 			return ret;
732 
733 		pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
734 	}
735 
736 	return !!pad->out_value;
737 }
738 
739 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
740 {
741 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
742 	unsigned long config;
743 
744 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
745 
746 	pmic_gpio_config_set(state->ctrl, pin, &config, 1);
747 }
748 
749 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
750 			      const struct of_phandle_args *gpio_desc,
751 			      u32 *flags)
752 {
753 	if (chip->of_gpio_n_cells < 2)
754 		return -EINVAL;
755 
756 	if (flags)
757 		*flags = gpio_desc->args[1];
758 
759 	return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
760 }
761 
762 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
763 {
764 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
765 	unsigned i;
766 
767 	for (i = 0; i < chip->ngpio; i++) {
768 		pmic_gpio_config_dbg_show(state->ctrl, s, i);
769 		seq_puts(s, "\n");
770 	}
771 }
772 
773 static const struct gpio_chip pmic_gpio_gpio_template = {
774 	.direction_input	= pmic_gpio_direction_input,
775 	.direction_output	= pmic_gpio_direction_output,
776 	.get			= pmic_gpio_get,
777 	.set			= pmic_gpio_set,
778 	.request		= gpiochip_generic_request,
779 	.free			= gpiochip_generic_free,
780 	.of_xlate		= pmic_gpio_of_xlate,
781 	.dbg_show		= pmic_gpio_dbg_show,
782 };
783 
784 static int pmic_gpio_populate(struct pmic_gpio_state *state,
785 			      struct pmic_gpio_pad *pad)
786 {
787 	int type, subtype, val, dir;
788 
789 	type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
790 	if (type < 0)
791 		return type;
792 
793 	if (type != PMIC_GPIO_TYPE) {
794 		dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
795 			type, pad->base);
796 		return -ENODEV;
797 	}
798 
799 	subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
800 	if (subtype < 0)
801 		return subtype;
802 
803 	switch (subtype) {
804 	case PMIC_GPIO_SUBTYPE_GPIO_4CH:
805 		pad->have_buffer = true;
806 		fallthrough;
807 	case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
808 		pad->num_sources = 4;
809 		break;
810 	case PMIC_GPIO_SUBTYPE_GPIO_8CH:
811 		pad->have_buffer = true;
812 		fallthrough;
813 	case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
814 		pad->num_sources = 8;
815 		break;
816 	case PMIC_GPIO_SUBTYPE_GPIO_LV:
817 		pad->num_sources = 1;
818 		pad->have_buffer = true;
819 		pad->lv_mv_type = true;
820 		break;
821 	case PMIC_GPIO_SUBTYPE_GPIO_MV:
822 		pad->num_sources = 2;
823 		pad->have_buffer = true;
824 		pad->lv_mv_type = true;
825 		break;
826 	default:
827 		dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
828 		return -ENODEV;
829 	}
830 
831 	if (pad->lv_mv_type) {
832 		val = pmic_gpio_read(state, pad,
833 				PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
834 		if (val < 0)
835 			return val;
836 
837 		pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
838 		pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
839 
840 		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
841 		if (val < 0)
842 			return val;
843 
844 		dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
845 	} else {
846 		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
847 		if (val < 0)
848 			return val;
849 
850 		pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
851 
852 		dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
853 		dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
854 		pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
855 		pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
856 	}
857 
858 	switch (dir) {
859 	case PMIC_GPIO_MODE_DIGITAL_INPUT:
860 		pad->input_enabled = true;
861 		pad->output_enabled = false;
862 		break;
863 	case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
864 		pad->input_enabled = false;
865 		pad->output_enabled = true;
866 		break;
867 	case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
868 		pad->input_enabled = true;
869 		pad->output_enabled = true;
870 		break;
871 	case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
872 		if (!pad->lv_mv_type)
873 			return -ENODEV;
874 		pad->analog_pass = true;
875 		break;
876 	default:
877 		dev_err(state->dev, "unknown GPIO direction\n");
878 		return -ENODEV;
879 	}
880 
881 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
882 	if (val < 0)
883 		return val;
884 
885 	pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
886 	pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
887 
888 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
889 	if (val < 0)
890 		return val;
891 
892 	pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
893 	pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
894 
895 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
896 	if (val < 0)
897 		return val;
898 
899 	if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
900 		pad->dtest_buffer =
901 			(val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
902 	else if (!pad->lv_mv_type)
903 		pad->dtest_buffer = ffs(val);
904 	else
905 		pad->dtest_buffer = 0;
906 
907 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
908 	if (val < 0)
909 		return val;
910 
911 	pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
912 	pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
913 
914 	pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
915 	pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
916 
917 	if (pad->lv_mv_type) {
918 		val = pmic_gpio_read(state, pad,
919 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
920 		if (val < 0)
921 			return val;
922 		pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
923 	}
924 
925 	/* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
926 	pad->is_enabled = true;
927 	return 0;
928 }
929 
930 static int pmic_gpio_domain_translate(struct irq_domain *domain,
931 				      struct irq_fwspec *fwspec,
932 				      unsigned long *hwirq,
933 				      unsigned int *type)
934 {
935 	struct pmic_gpio_state *state = container_of(domain->host_data,
936 						     struct pmic_gpio_state,
937 						     chip);
938 
939 	if (fwspec->param_count != 2 ||
940 	    fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
941 		return -EINVAL;
942 
943 	*hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
944 	*type = fwspec->param[1];
945 
946 	return 0;
947 }
948 
949 static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
950 						  unsigned int offset)
951 {
952 	return offset + PMIC_GPIO_PHYSICAL_OFFSET;
953 }
954 
955 static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
956 					   unsigned int child_hwirq,
957 					   unsigned int child_type,
958 					   unsigned int *parent_hwirq,
959 					   unsigned int *parent_type)
960 {
961 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
962 
963 	*parent_hwirq = child_hwirq + state->pid_base;
964 	*parent_type = child_type;
965 
966 	return 0;
967 }
968 
969 static void *pmic_gpio_populate_parent_fwspec(struct gpio_chip *chip,
970 					     unsigned int parent_hwirq,
971 					     unsigned int parent_type)
972 {
973 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
974 	struct irq_fwspec *fwspec;
975 
976 	fwspec = kzalloc(sizeof(*fwspec), GFP_KERNEL);
977 	if (!fwspec)
978 		return NULL;
979 
980 	fwspec->fwnode = chip->irq.parent_domain->fwnode;
981 
982 	fwspec->param_count = 4;
983 	fwspec->param[0] = state->usid;
984 	fwspec->param[1] = parent_hwirq;
985 	/* param[2] must be left as 0 */
986 	fwspec->param[3] = parent_type;
987 
988 	return fwspec;
989 }
990 
991 static int pmic_gpio_probe(struct platform_device *pdev)
992 {
993 	struct irq_domain *parent_domain;
994 	struct device_node *parent_node;
995 	struct device *dev = &pdev->dev;
996 	struct pinctrl_pin_desc *pindesc;
997 	struct pinctrl_desc *pctrldesc;
998 	struct pmic_gpio_pad *pad, *pads;
999 	struct pmic_gpio_state *state;
1000 	struct gpio_irq_chip *girq;
1001 	const struct spmi_device *parent_spmi_dev;
1002 	int ret, npins, i;
1003 	u32 reg;
1004 
1005 	ret = of_property_read_u32(dev->of_node, "reg", &reg);
1006 	if (ret < 0) {
1007 		dev_err(dev, "missing base address");
1008 		return ret;
1009 	}
1010 
1011 	npins = (uintptr_t) device_get_match_data(&pdev->dev);
1012 
1013 	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1014 	if (!state)
1015 		return -ENOMEM;
1016 
1017 	platform_set_drvdata(pdev, state);
1018 
1019 	state->dev = &pdev->dev;
1020 	state->map = dev_get_regmap(dev->parent, NULL);
1021 	parent_spmi_dev = to_spmi_device(dev->parent);
1022 	state->usid = parent_spmi_dev->usid;
1023 	state->pid_base = reg >> 8;
1024 
1025 	pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
1026 	if (!pindesc)
1027 		return -ENOMEM;
1028 
1029 	pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
1030 	if (!pads)
1031 		return -ENOMEM;
1032 
1033 	pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
1034 	if (!pctrldesc)
1035 		return -ENOMEM;
1036 
1037 	pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1038 	pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1039 	pctrldesc->confops = &pmic_gpio_pinconf_ops;
1040 	pctrldesc->owner = THIS_MODULE;
1041 	pctrldesc->name = dev_name(dev);
1042 	pctrldesc->pins = pindesc;
1043 	pctrldesc->npins = npins;
1044 	pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1045 	pctrldesc->custom_params = pmic_gpio_bindings;
1046 #ifdef CONFIG_DEBUG_FS
1047 	pctrldesc->custom_conf_items = pmic_conf_items;
1048 #endif
1049 
1050 	for (i = 0; i < npins; i++, pindesc++) {
1051 		pad = &pads[i];
1052 		pindesc->drv_data = pad;
1053 		pindesc->number = i;
1054 		pindesc->name = pmic_gpio_groups[i];
1055 
1056 		pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1057 
1058 		ret = pmic_gpio_populate(state, pad);
1059 		if (ret < 0)
1060 			return ret;
1061 	}
1062 
1063 	state->chip = pmic_gpio_gpio_template;
1064 	state->chip.parent = dev;
1065 	state->chip.base = -1;
1066 	state->chip.ngpio = npins;
1067 	state->chip.label = dev_name(dev);
1068 	state->chip.of_gpio_n_cells = 2;
1069 	state->chip.can_sleep = false;
1070 
1071 	state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1072 	if (IS_ERR(state->ctrl))
1073 		return PTR_ERR(state->ctrl);
1074 
1075 	parent_node = of_irq_find_parent(state->dev->of_node);
1076 	if (!parent_node)
1077 		return -ENXIO;
1078 
1079 	parent_domain = irq_find_host(parent_node);
1080 	of_node_put(parent_node);
1081 	if (!parent_domain)
1082 		return -ENXIO;
1083 
1084 	state->irq.name = "spmi-gpio",
1085 	state->irq.irq_ack = irq_chip_ack_parent,
1086 	state->irq.irq_mask = irq_chip_mask_parent,
1087 	state->irq.irq_unmask = irq_chip_unmask_parent,
1088 	state->irq.irq_set_type = irq_chip_set_type_parent,
1089 	state->irq.irq_set_wake = irq_chip_set_wake_parent,
1090 	state->irq.flags = IRQCHIP_MASK_ON_SUSPEND,
1091 
1092 	girq = &state->chip.irq;
1093 	girq->chip = &state->irq;
1094 	girq->default_type = IRQ_TYPE_NONE;
1095 	girq->handler = handle_level_irq;
1096 	girq->fwnode = of_node_to_fwnode(state->dev->of_node);
1097 	girq->parent_domain = parent_domain;
1098 	girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
1099 	girq->populate_parent_alloc_arg = pmic_gpio_populate_parent_fwspec;
1100 	girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
1101 	girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
1102 
1103 	ret = gpiochip_add_data(&state->chip, state);
1104 	if (ret) {
1105 		dev_err(state->dev, "can't add gpio chip\n");
1106 		return ret;
1107 	}
1108 
1109 	/*
1110 	 * For DeviceTree-supported systems, the gpio core checks the
1111 	 * pinctrl's device node for the "gpio-ranges" property.
1112 	 * If it is present, it takes care of adding the pin ranges
1113 	 * for the driver. In this case the driver can skip ahead.
1114 	 *
1115 	 * In order to remain compatible with older, existing DeviceTree
1116 	 * files which don't set the "gpio-ranges" property or systems that
1117 	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1118 	 */
1119 	if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
1120 		ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1121 					     npins);
1122 		if (ret) {
1123 			dev_err(dev, "failed to add pin range\n");
1124 			goto err_range;
1125 		}
1126 	}
1127 
1128 	return 0;
1129 
1130 err_range:
1131 	gpiochip_remove(&state->chip);
1132 	return ret;
1133 }
1134 
1135 static int pmic_gpio_remove(struct platform_device *pdev)
1136 {
1137 	struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1138 
1139 	gpiochip_remove(&state->chip);
1140 	return 0;
1141 }
1142 
1143 static const struct of_device_id pmic_gpio_of_match[] = {
1144 	{ .compatible = "qcom,pm2250-gpio", .data = (void *) 10 },
1145 	/* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
1146 	{ .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
1147 	/* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
1148 	{ .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
1149 	{ .compatible = "qcom,pm6125-gpio", .data = (void *) 9 },
1150 	{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
1151 	{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
1152 	{ .compatible = "qcom,pm6350-gpio", .data = (void *) 9 },
1153 	{ .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
1154 	{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1155 	{ .compatible = "qcom,pm8008-gpio", .data = (void *) 2 },
1156 	{ .compatible = "qcom,pm8019-gpio", .data = (void *) 6 },
1157 	/* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
1158 	{ .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
1159 	{ .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 },
1160 	/* pm8150b has 12 GPIOs with holes on 3, r and 7 */
1161 	{ .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
1162 	/* pm8150l has 12 GPIOs with holes on 7 */
1163 	{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
1164 	{ .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 },
1165 	{ .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
1166 	{ .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
1167 	{ .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
1168 	{ .compatible = "qcom,pm8450-gpio", .data = (void *) 4 },
1169 	{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1170 	{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1171 	/* pm8950 has 8 GPIOs with holes on 3 */
1172 	{ .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
1173 	{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1174 	{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1175 	{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1176 	{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
1177 	{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1178 	{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1179 	{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
1180 	{ .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
1181 	{ .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
1182 	{ .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
1183 	/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1184 	{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1185 	/* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
1186 	{ .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
1187 	{ .compatible = "qcom,pmx65-gpio", .data = (void *) 16 },
1188 	{ },
1189 };
1190 
1191 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1192 
1193 static struct platform_driver pmic_gpio_driver = {
1194 	.driver = {
1195 		   .name = "qcom-spmi-gpio",
1196 		   .of_match_table = pmic_gpio_of_match,
1197 	},
1198 	.probe	= pmic_gpio_probe,
1199 	.remove = pmic_gpio_remove,
1200 };
1201 
1202 module_platform_driver(pmic_gpio_driver);
1203 
1204 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1205 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1206 MODULE_ALIAS("platform:qcom-spmi-gpio");
1207 MODULE_LICENSE("GPL v2");
1208