1 /* 2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/gpio.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/pinctrl/pinconf-generic.h> 18 #include <linux/pinctrl/pinconf.h> 19 #include <linux/pinctrl/pinmux.h> 20 #include <linux/platform_device.h> 21 #include <linux/regmap.h> 22 #include <linux/slab.h> 23 #include <linux/types.h> 24 25 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 26 27 #include "../core.h" 28 #include "../pinctrl-utils.h" 29 30 #define PMIC_GPIO_ADDRESS_RANGE 0x100 31 32 /* type and subtype registers base address offsets */ 33 #define PMIC_GPIO_REG_TYPE 0x4 34 #define PMIC_GPIO_REG_SUBTYPE 0x5 35 36 /* GPIO peripheral type and subtype out_values */ 37 #define PMIC_GPIO_TYPE 0x10 38 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1 39 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5 40 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9 41 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd 42 43 #define PMIC_MPP_REG_RT_STS 0x10 44 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 45 46 /* control register base address offsets */ 47 #define PMIC_GPIO_REG_MODE_CTL 0x40 48 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41 49 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42 50 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45 51 #define PMIC_GPIO_REG_EN_CTL 0x46 52 53 /* PMIC_GPIO_REG_MODE_CTL */ 54 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1 55 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1 56 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7 57 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4 58 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7 59 60 /* PMIC_GPIO_REG_DIG_VIN_CTL */ 61 #define PMIC_GPIO_REG_VIN_SHIFT 0 62 #define PMIC_GPIO_REG_VIN_MASK 0x7 63 64 /* PMIC_GPIO_REG_DIG_PULL_CTL */ 65 #define PMIC_GPIO_REG_PULL_SHIFT 0 66 #define PMIC_GPIO_REG_PULL_MASK 0x7 67 68 #define PMIC_GPIO_PULL_DOWN 4 69 #define PMIC_GPIO_PULL_DISABLE 5 70 71 /* PMIC_GPIO_REG_DIG_OUT_CTL */ 72 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0 73 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3 74 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4 75 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3 76 77 /* 78 * Output type - indicates pin should be configured as push-pull, 79 * open drain or open source. 80 */ 81 #define PMIC_GPIO_OUT_BUF_CMOS 0 82 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1 83 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2 84 85 /* PMIC_GPIO_REG_EN_CTL */ 86 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7 87 88 #define PMIC_GPIO_PHYSICAL_OFFSET 1 89 90 /* Qualcomm specific pin configurations */ 91 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1) 92 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2) 93 94 /** 95 * struct pmic_gpio_pad - keep current GPIO settings 96 * @base: Address base in SPMI device. 97 * @irq: IRQ number which this GPIO generate. 98 * @is_enabled: Set to false when GPIO should be put in high Z state. 99 * @out_value: Cached pin output value 100 * @have_buffer: Set to true if GPIO output could be configured in push-pull, 101 * open-drain or open-source mode. 102 * @output_enabled: Set to true if GPIO output logic is enabled. 103 * @input_enabled: Set to true if GPIO input buffer logic is enabled. 104 * @num_sources: Number of power-sources supported by this GPIO. 105 * @power_source: Current power-source used. 106 * @buffer_type: Push-pull, open-drain or open-source. 107 * @pullup: Constant current which flow trough GPIO output buffer. 108 * @strength: No, Low, Medium, High 109 * @function: See pmic_gpio_functions[] 110 */ 111 struct pmic_gpio_pad { 112 u16 base; 113 int irq; 114 bool is_enabled; 115 bool out_value; 116 bool have_buffer; 117 bool output_enabled; 118 bool input_enabled; 119 unsigned int num_sources; 120 unsigned int power_source; 121 unsigned int buffer_type; 122 unsigned int pullup; 123 unsigned int strength; 124 unsigned int function; 125 }; 126 127 struct pmic_gpio_state { 128 struct device *dev; 129 struct regmap *map; 130 struct pinctrl_dev *ctrl; 131 struct gpio_chip chip; 132 }; 133 134 static const struct pinconf_generic_params pmic_gpio_bindings[] = { 135 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0}, 136 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0}, 137 }; 138 139 #ifdef CONFIG_DEBUG_FS 140 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { 141 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true), 142 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true), 143 }; 144 #endif 145 146 static const char *const pmic_gpio_groups[] = { 147 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", 148 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", 149 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 150 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 151 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", 152 }; 153 154 static const char *const pmic_gpio_functions[] = { 155 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED, 156 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2, 157 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2, 158 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4, 159 }; 160 161 static inline struct pmic_gpio_state *to_gpio_state(struct gpio_chip *chip) 162 { 163 return container_of(chip, struct pmic_gpio_state, chip); 164 }; 165 166 static int pmic_gpio_read(struct pmic_gpio_state *state, 167 struct pmic_gpio_pad *pad, unsigned int addr) 168 { 169 unsigned int val; 170 int ret; 171 172 ret = regmap_read(state->map, pad->base + addr, &val); 173 if (ret < 0) 174 dev_err(state->dev, "read 0x%x failed\n", addr); 175 else 176 ret = val; 177 178 return ret; 179 } 180 181 static int pmic_gpio_write(struct pmic_gpio_state *state, 182 struct pmic_gpio_pad *pad, unsigned int addr, 183 unsigned int val) 184 { 185 int ret; 186 187 ret = regmap_write(state->map, pad->base + addr, val); 188 if (ret < 0) 189 dev_err(state->dev, "write 0x%x failed\n", addr); 190 191 return ret; 192 } 193 194 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev) 195 { 196 /* Every PIN is a group */ 197 return pctldev->desc->npins; 198 } 199 200 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev, 201 unsigned pin) 202 { 203 return pctldev->desc->pins[pin].name; 204 } 205 206 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin, 207 const unsigned **pins, unsigned *num_pins) 208 { 209 *pins = &pctldev->desc->pins[pin].number; 210 *num_pins = 1; 211 return 0; 212 } 213 214 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = { 215 .get_groups_count = pmic_gpio_get_groups_count, 216 .get_group_name = pmic_gpio_get_group_name, 217 .get_group_pins = pmic_gpio_get_group_pins, 218 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 219 .dt_free_map = pinctrl_utils_dt_free_map, 220 }; 221 222 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev) 223 { 224 return ARRAY_SIZE(pmic_gpio_functions); 225 } 226 227 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev, 228 unsigned function) 229 { 230 return pmic_gpio_functions[function]; 231 } 232 233 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev, 234 unsigned function, 235 const char *const **groups, 236 unsigned *const num_qgroups) 237 { 238 *groups = pmic_gpio_groups; 239 *num_qgroups = pctldev->desc->npins; 240 return 0; 241 } 242 243 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function, 244 unsigned pin) 245 { 246 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 247 struct pmic_gpio_pad *pad; 248 unsigned int val; 249 int ret; 250 251 pad = pctldev->desc->pins[pin].drv_data; 252 253 pad->function = function; 254 255 val = 0; 256 if (pad->output_enabled) { 257 if (pad->input_enabled) 258 val = 2; 259 else 260 val = 1; 261 } 262 263 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 264 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 265 266 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); 267 if (ret < 0) 268 return ret; 269 270 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; 271 272 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); 273 } 274 275 static const struct pinmux_ops pmic_gpio_pinmux_ops = { 276 .get_functions_count = pmic_gpio_get_functions_count, 277 .get_function_name = pmic_gpio_get_function_name, 278 .get_function_groups = pmic_gpio_get_function_groups, 279 .set_mux = pmic_gpio_set_mux, 280 }; 281 282 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev, 283 unsigned int pin, unsigned long *config) 284 { 285 unsigned param = pinconf_to_config_param(*config); 286 struct pmic_gpio_pad *pad; 287 unsigned arg; 288 289 pad = pctldev->desc->pins[pin].drv_data; 290 291 switch (param) { 292 case PIN_CONFIG_DRIVE_PUSH_PULL: 293 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_CMOS; 294 break; 295 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 296 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; 297 break; 298 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 299 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; 300 break; 301 case PIN_CONFIG_BIAS_PULL_DOWN: 302 arg = pad->pullup == PMIC_GPIO_PULL_DOWN; 303 break; 304 case PIN_CONFIG_BIAS_DISABLE: 305 arg = pad->pullup = PMIC_GPIO_PULL_DISABLE; 306 break; 307 case PIN_CONFIG_BIAS_PULL_UP: 308 arg = pad->pullup == PMIC_GPIO_PULL_UP_30; 309 break; 310 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 311 arg = !pad->is_enabled; 312 break; 313 case PIN_CONFIG_POWER_SOURCE: 314 arg = pad->power_source; 315 break; 316 case PIN_CONFIG_INPUT_ENABLE: 317 arg = pad->input_enabled; 318 break; 319 case PIN_CONFIG_OUTPUT: 320 arg = pad->out_value; 321 break; 322 case PMIC_GPIO_CONF_PULL_UP: 323 arg = pad->pullup; 324 break; 325 case PMIC_GPIO_CONF_STRENGTH: 326 arg = pad->strength; 327 break; 328 default: 329 return -EINVAL; 330 } 331 332 *config = pinconf_to_config_packed(param, arg); 333 return 0; 334 } 335 336 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 337 unsigned long *configs, unsigned nconfs) 338 { 339 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 340 struct pmic_gpio_pad *pad; 341 unsigned param, arg; 342 unsigned int val; 343 int i, ret; 344 345 pad = pctldev->desc->pins[pin].drv_data; 346 347 for (i = 0; i < nconfs; i++) { 348 param = pinconf_to_config_param(configs[i]); 349 arg = pinconf_to_config_argument(configs[i]); 350 351 switch (param) { 352 case PIN_CONFIG_DRIVE_PUSH_PULL: 353 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS; 354 break; 355 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 356 if (!pad->have_buffer) 357 return -EINVAL; 358 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; 359 break; 360 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 361 if (!pad->have_buffer) 362 return -EINVAL; 363 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; 364 break; 365 case PIN_CONFIG_BIAS_DISABLE: 366 pad->pullup = PMIC_GPIO_PULL_DISABLE; 367 break; 368 case PIN_CONFIG_BIAS_PULL_UP: 369 pad->pullup = PMIC_GPIO_PULL_UP_30; 370 break; 371 case PIN_CONFIG_BIAS_PULL_DOWN: 372 if (arg) 373 pad->pullup = PMIC_GPIO_PULL_DOWN; 374 else 375 pad->pullup = PMIC_GPIO_PULL_DISABLE; 376 break; 377 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 378 pad->is_enabled = false; 379 break; 380 case PIN_CONFIG_POWER_SOURCE: 381 if (arg > pad->num_sources) 382 return -EINVAL; 383 pad->power_source = arg; 384 break; 385 case PIN_CONFIG_INPUT_ENABLE: 386 pad->input_enabled = arg ? true : false; 387 break; 388 case PIN_CONFIG_OUTPUT: 389 pad->output_enabled = true; 390 pad->out_value = arg; 391 break; 392 case PMIC_GPIO_CONF_PULL_UP: 393 if (arg > PMIC_GPIO_PULL_UP_1P5_30) 394 return -EINVAL; 395 pad->pullup = arg; 396 break; 397 case PMIC_GPIO_CONF_STRENGTH: 398 if (arg > PMIC_GPIO_STRENGTH_LOW) 399 return -EINVAL; 400 pad->strength = arg; 401 break; 402 default: 403 return -EINVAL; 404 } 405 } 406 407 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT; 408 409 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val); 410 if (ret < 0) 411 return ret; 412 413 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT; 414 415 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val); 416 if (ret < 0) 417 return ret; 418 419 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT; 420 val = pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; 421 422 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val); 423 if (ret < 0) 424 return ret; 425 426 val = 0; 427 if (pad->output_enabled) { 428 if (pad->input_enabled) 429 val = 2; 430 else 431 val = 1; 432 } 433 434 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; 435 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 436 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 437 438 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); 439 } 440 441 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, 442 struct seq_file *s, unsigned pin) 443 { 444 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 445 struct pmic_gpio_pad *pad; 446 int ret, val; 447 448 static const char *const biases[] = { 449 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", 450 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" 451 }; 452 static const char *const buffer_types[] = { 453 "push-pull", "open-drain", "open-source" 454 }; 455 static const char *const strengths[] = { 456 "no", "high", "medium", "low" 457 }; 458 459 pad = pctldev->desc->pins[pin].drv_data; 460 461 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET); 462 463 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL); 464 465 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) { 466 seq_puts(s, " ---"); 467 } else { 468 469 if (!pad->input_enabled) { 470 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); 471 if (!ret) { 472 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; 473 pad->out_value = ret; 474 } 475 } 476 477 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); 478 seq_printf(s, " %-7s", pmic_gpio_functions[pad->function]); 479 seq_printf(s, " vin-%d", pad->power_source); 480 seq_printf(s, " %-27s", biases[pad->pullup]); 481 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]); 482 seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); 483 seq_printf(s, " %-7s", strengths[pad->strength]); 484 } 485 } 486 487 static const struct pinconf_ops pmic_gpio_pinconf_ops = { 488 .is_generic = true, 489 .pin_config_group_get = pmic_gpio_config_get, 490 .pin_config_group_set = pmic_gpio_config_set, 491 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show, 492 }; 493 494 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 495 { 496 struct pmic_gpio_state *state = to_gpio_state(chip); 497 unsigned long config; 498 499 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); 500 501 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); 502 } 503 504 static int pmic_gpio_direction_output(struct gpio_chip *chip, 505 unsigned pin, int val) 506 { 507 struct pmic_gpio_state *state = to_gpio_state(chip); 508 unsigned long config; 509 510 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); 511 512 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); 513 } 514 515 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin) 516 { 517 struct pmic_gpio_state *state = to_gpio_state(chip); 518 struct pmic_gpio_pad *pad; 519 int ret; 520 521 pad = state->ctrl->desc->pins[pin].drv_data; 522 523 if (!pad->is_enabled) 524 return -EINVAL; 525 526 if (pad->input_enabled) { 527 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); 528 if (ret < 0) 529 return ret; 530 531 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; 532 } 533 534 return pad->out_value; 535 } 536 537 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 538 { 539 struct pmic_gpio_state *state = to_gpio_state(chip); 540 unsigned long config; 541 542 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); 543 544 pmic_gpio_config_set(state->ctrl, pin, &config, 1); 545 } 546 547 static int pmic_gpio_request(struct gpio_chip *chip, unsigned base) 548 { 549 return pinctrl_request_gpio(chip->base + base); 550 } 551 552 static void pmic_gpio_free(struct gpio_chip *chip, unsigned base) 553 { 554 pinctrl_free_gpio(chip->base + base); 555 } 556 557 static int pmic_gpio_of_xlate(struct gpio_chip *chip, 558 const struct of_phandle_args *gpio_desc, 559 u32 *flags) 560 { 561 if (chip->of_gpio_n_cells < 2) 562 return -EINVAL; 563 564 if (flags) 565 *flags = gpio_desc->args[1]; 566 567 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET; 568 } 569 570 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 571 { 572 struct pmic_gpio_state *state = to_gpio_state(chip); 573 struct pmic_gpio_pad *pad; 574 575 pad = state->ctrl->desc->pins[pin].drv_data; 576 577 return pad->irq; 578 } 579 580 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 581 { 582 struct pmic_gpio_state *state = to_gpio_state(chip); 583 unsigned i; 584 585 for (i = 0; i < chip->ngpio; i++) { 586 pmic_gpio_config_dbg_show(state->ctrl, s, i); 587 seq_puts(s, "\n"); 588 } 589 } 590 591 static const struct gpio_chip pmic_gpio_gpio_template = { 592 .direction_input = pmic_gpio_direction_input, 593 .direction_output = pmic_gpio_direction_output, 594 .get = pmic_gpio_get, 595 .set = pmic_gpio_set, 596 .request = pmic_gpio_request, 597 .free = pmic_gpio_free, 598 .of_xlate = pmic_gpio_of_xlate, 599 .to_irq = pmic_gpio_to_irq, 600 .dbg_show = pmic_gpio_dbg_show, 601 }; 602 603 static int pmic_gpio_populate(struct pmic_gpio_state *state, 604 struct pmic_gpio_pad *pad) 605 { 606 int type, subtype, val, dir; 607 608 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE); 609 if (type < 0) 610 return type; 611 612 if (type != PMIC_GPIO_TYPE) { 613 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", 614 type, pad->base); 615 return -ENODEV; 616 } 617 618 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE); 619 if (subtype < 0) 620 return subtype; 621 622 switch (subtype) { 623 case PMIC_GPIO_SUBTYPE_GPIO_4CH: 624 pad->have_buffer = true; 625 case PMIC_GPIO_SUBTYPE_GPIOC_4CH: 626 pad->num_sources = 4; 627 break; 628 case PMIC_GPIO_SUBTYPE_GPIO_8CH: 629 pad->have_buffer = true; 630 case PMIC_GPIO_SUBTYPE_GPIOC_8CH: 631 pad->num_sources = 8; 632 break; 633 default: 634 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype); 635 return -ENODEV; 636 } 637 638 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); 639 if (val < 0) 640 return val; 641 642 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 643 644 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; 645 dir &= PMIC_GPIO_REG_MODE_DIR_MASK; 646 switch (dir) { 647 case 0: 648 pad->input_enabled = true; 649 pad->output_enabled = false; 650 break; 651 case 1: 652 pad->input_enabled = false; 653 pad->output_enabled = true; 654 break; 655 case 2: 656 pad->input_enabled = true; 657 pad->output_enabled = true; 658 break; 659 default: 660 dev_err(state->dev, "unknown GPIO direction\n"); 661 return -ENODEV; 662 } 663 664 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 665 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK; 666 667 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL); 668 if (val < 0) 669 return val; 670 671 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT; 672 pad->power_source &= PMIC_GPIO_REG_VIN_MASK; 673 674 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL); 675 if (val < 0) 676 return val; 677 678 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT; 679 pad->pullup &= PMIC_GPIO_REG_PULL_MASK; 680 681 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL); 682 if (val < 0) 683 return val; 684 685 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; 686 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK; 687 688 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT; 689 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK; 690 691 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ 692 pad->is_enabled = true; 693 return 0; 694 } 695 696 static int pmic_gpio_probe(struct platform_device *pdev) 697 { 698 struct device *dev = &pdev->dev; 699 struct pinctrl_pin_desc *pindesc; 700 struct pinctrl_desc *pctrldesc; 701 struct pmic_gpio_pad *pad, *pads; 702 struct pmic_gpio_state *state; 703 int ret, npins, i; 704 u32 res[2]; 705 706 ret = of_property_read_u32_array(dev->of_node, "reg", res, 2); 707 if (ret < 0) { 708 dev_err(dev, "missing base address and/or range"); 709 return ret; 710 } 711 712 npins = res[1] / PMIC_GPIO_ADDRESS_RANGE; 713 714 if (!npins) 715 return -EINVAL; 716 717 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups)); 718 719 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); 720 if (!state) 721 return -ENOMEM; 722 723 platform_set_drvdata(pdev, state); 724 725 state->dev = &pdev->dev; 726 state->map = dev_get_regmap(dev->parent, NULL); 727 728 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); 729 if (!pindesc) 730 return -ENOMEM; 731 732 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); 733 if (!pads) 734 return -ENOMEM; 735 736 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); 737 if (!pctrldesc) 738 return -ENOMEM; 739 740 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops; 741 pctrldesc->pmxops = &pmic_gpio_pinmux_ops; 742 pctrldesc->confops = &pmic_gpio_pinconf_ops; 743 pctrldesc->owner = THIS_MODULE; 744 pctrldesc->name = dev_name(dev); 745 pctrldesc->pins = pindesc; 746 pctrldesc->npins = npins; 747 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings); 748 pctrldesc->custom_params = pmic_gpio_bindings; 749 #ifdef CONFIG_DEBUG_FS 750 pctrldesc->custom_conf_items = pmic_conf_items; 751 #endif 752 753 for (i = 0; i < npins; i++, pindesc++) { 754 pad = &pads[i]; 755 pindesc->drv_data = pad; 756 pindesc->number = i; 757 pindesc->name = pmic_gpio_groups[i]; 758 759 pad->irq = platform_get_irq(pdev, i); 760 if (pad->irq < 0) 761 return pad->irq; 762 763 pad->base = res[0] + i * PMIC_GPIO_ADDRESS_RANGE; 764 765 ret = pmic_gpio_populate(state, pad); 766 if (ret < 0) 767 return ret; 768 } 769 770 state->chip = pmic_gpio_gpio_template; 771 state->chip.dev = dev; 772 state->chip.base = -1; 773 state->chip.ngpio = npins; 774 state->chip.label = dev_name(dev); 775 state->chip.of_gpio_n_cells = 2; 776 state->chip.can_sleep = false; 777 778 state->ctrl = pinctrl_register(pctrldesc, dev, state); 779 if (!state->ctrl) 780 return -ENODEV; 781 782 ret = gpiochip_add(&state->chip); 783 if (ret) { 784 dev_err(state->dev, "can't add gpio chip\n"); 785 goto err_chip; 786 } 787 788 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); 789 if (ret) { 790 dev_err(dev, "failed to add pin range\n"); 791 goto err_range; 792 } 793 794 return 0; 795 796 err_range: 797 gpiochip_remove(&state->chip); 798 err_chip: 799 pinctrl_unregister(state->ctrl); 800 return ret; 801 } 802 803 static int pmic_gpio_remove(struct platform_device *pdev) 804 { 805 struct pmic_gpio_state *state = platform_get_drvdata(pdev); 806 807 gpiochip_remove(&state->chip); 808 pinctrl_unregister(state->ctrl); 809 return 0; 810 } 811 812 static const struct of_device_id pmic_gpio_of_match[] = { 813 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */ 814 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */ 815 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ 816 { }, 817 }; 818 819 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match); 820 821 static struct platform_driver pmic_gpio_driver = { 822 .driver = { 823 .name = "qcom-spmi-gpio", 824 .of_match_table = pmic_gpio_of_match, 825 }, 826 .probe = pmic_gpio_probe, 827 .remove = pmic_gpio_remove, 828 }; 829 830 module_platform_driver(pmic_gpio_driver); 831 832 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); 833 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver"); 834 MODULE_ALIAS("platform:qcom-spmi-gpio"); 835 MODULE_LICENSE("GPL v2"); 836