1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2012-2014, 2016-2021 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #include <linux/gpio/driver.h>
8 #include <linux/interrupt.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_irq.h>
12 #include <linux/pinctrl/pinconf-generic.h>
13 #include <linux/pinctrl/pinconf.h>
14 #include <linux/pinctrl/pinmux.h>
15 #include <linux/platform_device.h>
16 #include <linux/regmap.h>
17 #include <linux/slab.h>
18 #include <linux/spmi.h>
19 #include <linux/types.h>
20 
21 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
22 
23 #include "../core.h"
24 #include "../pinctrl-utils.h"
25 
26 #define PMIC_GPIO_ADDRESS_RANGE			0x100
27 
28 /* type and subtype registers base address offsets */
29 #define PMIC_GPIO_REG_TYPE			0x4
30 #define PMIC_GPIO_REG_SUBTYPE			0x5
31 
32 /* GPIO peripheral type and subtype out_values */
33 #define PMIC_GPIO_TYPE				0x10
34 #define PMIC_GPIO_SUBTYPE_GPIO_4CH		0x1
35 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH		0x5
36 #define PMIC_GPIO_SUBTYPE_GPIO_8CH		0x9
37 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH		0xd
38 #define PMIC_GPIO_SUBTYPE_GPIO_LV		0x10
39 #define PMIC_GPIO_SUBTYPE_GPIO_MV		0x11
40 #define PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2		0x12
41 #define PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3		0x13
42 
43 #define PMIC_MPP_REG_RT_STS			0x10
44 #define PMIC_MPP_REG_RT_STS_VAL_MASK		0x1
45 
46 /* control register base address offsets */
47 #define PMIC_GPIO_REG_MODE_CTL			0x40
48 #define PMIC_GPIO_REG_DIG_VIN_CTL		0x41
49 #define PMIC_GPIO_REG_DIG_PULL_CTL		0x42
50 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL	0x44
51 #define PMIC_GPIO_REG_DIG_IN_CTL		0x43
52 #define PMIC_GPIO_REG_DIG_OUT_CTL		0x45
53 #define PMIC_GPIO_REG_EN_CTL			0x46
54 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL	0x4A
55 
56 /* PMIC_GPIO_REG_MODE_CTL */
57 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT		0x1
58 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT	1
59 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK	0x7
60 #define PMIC_GPIO_REG_MODE_DIR_SHIFT		4
61 #define PMIC_GPIO_REG_MODE_DIR_MASK		0x7
62 
63 #define PMIC_GPIO_MODE_DIGITAL_INPUT		0
64 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT		1
65 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT	2
66 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU		3
67 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK	0x3
68 
69 /* PMIC_GPIO_REG_DIG_VIN_CTL */
70 #define PMIC_GPIO_REG_VIN_SHIFT			0
71 #define PMIC_GPIO_REG_VIN_MASK			0x7
72 
73 /* PMIC_GPIO_REG_DIG_PULL_CTL */
74 #define PMIC_GPIO_REG_PULL_SHIFT		0
75 #define PMIC_GPIO_REG_PULL_MASK			0x7
76 
77 #define PMIC_GPIO_PULL_DOWN			4
78 #define PMIC_GPIO_PULL_DISABLE			5
79 
80 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
81 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT		0x80
82 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT	7
83 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK	0xF
84 
85 /* PMIC_GPIO_REG_DIG_IN_CTL */
86 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN		0x80
87 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK	0x7
88 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK		0xf
89 
90 /* PMIC_GPIO_REG_DIG_OUT_CTL */
91 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT	0
92 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK		0x3
93 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT		4
94 #define PMIC_GPIO_REG_OUT_TYPE_MASK		0x3
95 
96 /*
97  * Output type - indicates pin should be configured as push-pull,
98  * open drain or open source.
99  */
100 #define PMIC_GPIO_OUT_BUF_CMOS			0
101 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS	1
102 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS	2
103 
104 #define PMIC_GPIO_OUT_STRENGTH_LOW		1
105 #define PMIC_GPIO_OUT_STRENGTH_HIGH		3
106 
107 /* PMIC_GPIO_REG_EN_CTL */
108 #define PMIC_GPIO_REG_MASTER_EN_SHIFT		7
109 
110 #define PMIC_GPIO_PHYSICAL_OFFSET		1
111 
112 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
113 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK		0x3
114 
115 /* Qualcomm specific pin configurations */
116 #define PMIC_GPIO_CONF_PULL_UP			(PIN_CONFIG_END + 1)
117 #define PMIC_GPIO_CONF_STRENGTH			(PIN_CONFIG_END + 2)
118 #define PMIC_GPIO_CONF_ATEST			(PIN_CONFIG_END + 3)
119 #define PMIC_GPIO_CONF_ANALOG_PASS		(PIN_CONFIG_END + 4)
120 #define PMIC_GPIO_CONF_DTEST_BUFFER		(PIN_CONFIG_END + 5)
121 
122 /* The index of each function in pmic_gpio_functions[] array */
123 enum pmic_gpio_func_index {
124 	PMIC_GPIO_FUNC_INDEX_NORMAL,
125 	PMIC_GPIO_FUNC_INDEX_PAIRED,
126 	PMIC_GPIO_FUNC_INDEX_FUNC1,
127 	PMIC_GPIO_FUNC_INDEX_FUNC2,
128 	PMIC_GPIO_FUNC_INDEX_FUNC3,
129 	PMIC_GPIO_FUNC_INDEX_FUNC4,
130 	PMIC_GPIO_FUNC_INDEX_DTEST1,
131 	PMIC_GPIO_FUNC_INDEX_DTEST2,
132 	PMIC_GPIO_FUNC_INDEX_DTEST3,
133 	PMIC_GPIO_FUNC_INDEX_DTEST4,
134 };
135 
136 /**
137  * struct pmic_gpio_pad - keep current GPIO settings
138  * @base: Address base in SPMI device.
139  * @is_enabled: Set to false when GPIO should be put in high Z state.
140  * @out_value: Cached pin output value
141  * @have_buffer: Set to true if GPIO output could be configured in push-pull,
142  *	open-drain or open-source mode.
143  * @output_enabled: Set to true if GPIO output logic is enabled.
144  * @input_enabled: Set to true if GPIO input buffer logic is enabled.
145  * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
146  * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
147  * @num_sources: Number of power-sources supported by this GPIO.
148  * @power_source: Current power-source used.
149  * @buffer_type: Push-pull, open-drain or open-source.
150  * @pullup: Constant current which flow trough GPIO output buffer.
151  * @strength: No, Low, Medium, High
152  * @function: See pmic_gpio_functions[]
153  * @atest: the ATEST selection for GPIO analog-pass-through mode
154  * @dtest_buffer: the DTEST buffer selection for digital input mode.
155  */
156 struct pmic_gpio_pad {
157 	u16		base;
158 	bool		is_enabled;
159 	bool		out_value;
160 	bool		have_buffer;
161 	bool		output_enabled;
162 	bool		input_enabled;
163 	bool		analog_pass;
164 	bool		lv_mv_type;
165 	unsigned int	num_sources;
166 	unsigned int	power_source;
167 	unsigned int	buffer_type;
168 	unsigned int	pullup;
169 	unsigned int	strength;
170 	unsigned int	function;
171 	unsigned int	atest;
172 	unsigned int	dtest_buffer;
173 };
174 
175 struct pmic_gpio_state {
176 	struct device	*dev;
177 	struct regmap	*map;
178 	struct pinctrl_dev *ctrl;
179 	struct gpio_chip chip;
180 	u8 usid;
181 	u8 pid_base;
182 };
183 
184 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
185 	{"qcom,pull-up-strength",	PMIC_GPIO_CONF_PULL_UP,		0},
186 	{"qcom,drive-strength",		PMIC_GPIO_CONF_STRENGTH,	0},
187 	{"qcom,atest",			PMIC_GPIO_CONF_ATEST,		0},
188 	{"qcom,analog-pass",		PMIC_GPIO_CONF_ANALOG_PASS,	0},
189 	{"qcom,dtest-buffer",           PMIC_GPIO_CONF_DTEST_BUFFER,    0},
190 };
191 
192 #ifdef CONFIG_DEBUG_FS
193 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
194 	PCONFDUMP(PMIC_GPIO_CONF_PULL_UP,  "pull up strength", NULL, true),
195 	PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
196 	PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
197 	PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
198 	PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
199 };
200 #endif
201 
202 static const char *const pmic_gpio_groups[] = {
203 	"gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
204 	"gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
205 	"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
206 	"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
207 	"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
208 };
209 
210 static const char *const pmic_gpio_functions[] = {
211 	[PMIC_GPIO_FUNC_INDEX_NORMAL]	= PMIC_GPIO_FUNC_NORMAL,
212 	[PMIC_GPIO_FUNC_INDEX_PAIRED]	= PMIC_GPIO_FUNC_PAIRED,
213 	[PMIC_GPIO_FUNC_INDEX_FUNC1]	= PMIC_GPIO_FUNC_FUNC1,
214 	[PMIC_GPIO_FUNC_INDEX_FUNC2]	= PMIC_GPIO_FUNC_FUNC2,
215 	[PMIC_GPIO_FUNC_INDEX_FUNC3]	= PMIC_GPIO_FUNC_FUNC3,
216 	[PMIC_GPIO_FUNC_INDEX_FUNC4]	= PMIC_GPIO_FUNC_FUNC4,
217 	[PMIC_GPIO_FUNC_INDEX_DTEST1]	= PMIC_GPIO_FUNC_DTEST1,
218 	[PMIC_GPIO_FUNC_INDEX_DTEST2]	= PMIC_GPIO_FUNC_DTEST2,
219 	[PMIC_GPIO_FUNC_INDEX_DTEST3]	= PMIC_GPIO_FUNC_DTEST3,
220 	[PMIC_GPIO_FUNC_INDEX_DTEST4]	= PMIC_GPIO_FUNC_DTEST4,
221 };
222 
223 static int pmic_gpio_read(struct pmic_gpio_state *state,
224 			  struct pmic_gpio_pad *pad, unsigned int addr)
225 {
226 	unsigned int val;
227 	int ret;
228 
229 	ret = regmap_read(state->map, pad->base + addr, &val);
230 	if (ret < 0)
231 		dev_err(state->dev, "read 0x%x failed\n", addr);
232 	else
233 		ret = val;
234 
235 	return ret;
236 }
237 
238 static int pmic_gpio_write(struct pmic_gpio_state *state,
239 			   struct pmic_gpio_pad *pad, unsigned int addr,
240 			   unsigned int val)
241 {
242 	int ret;
243 
244 	ret = regmap_write(state->map, pad->base + addr, val);
245 	if (ret < 0)
246 		dev_err(state->dev, "write 0x%x failed\n", addr);
247 
248 	return ret;
249 }
250 
251 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
252 {
253 	/* Every PIN is a group */
254 	return pctldev->desc->npins;
255 }
256 
257 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
258 					    unsigned pin)
259 {
260 	return pctldev->desc->pins[pin].name;
261 }
262 
263 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
264 				    const unsigned **pins, unsigned *num_pins)
265 {
266 	*pins = &pctldev->desc->pins[pin].number;
267 	*num_pins = 1;
268 	return 0;
269 }
270 
271 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
272 	.get_groups_count	= pmic_gpio_get_groups_count,
273 	.get_group_name		= pmic_gpio_get_group_name,
274 	.get_group_pins		= pmic_gpio_get_group_pins,
275 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
276 	.dt_free_map		= pinctrl_utils_free_map,
277 };
278 
279 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
280 {
281 	return ARRAY_SIZE(pmic_gpio_functions);
282 }
283 
284 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
285 					       unsigned function)
286 {
287 	return pmic_gpio_functions[function];
288 }
289 
290 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
291 					 unsigned function,
292 					 const char *const **groups,
293 					 unsigned *const num_qgroups)
294 {
295 	*groups = pmic_gpio_groups;
296 	*num_qgroups = pctldev->desc->npins;
297 	return 0;
298 }
299 
300 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
301 				unsigned pin)
302 {
303 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
304 	struct pmic_gpio_pad *pad;
305 	unsigned int val;
306 	int ret;
307 
308 	if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
309 		pr_err("function: %d is not defined\n", function);
310 		return -EINVAL;
311 	}
312 
313 	pad = pctldev->desc->pins[pin].drv_data;
314 	/*
315 	 * Non-LV/MV subtypes only support 2 special functions,
316 	 * offsetting the dtestx function values by 2
317 	 */
318 	if (!pad->lv_mv_type) {
319 		if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
320 				function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
321 			pr_err("LV/MV subtype doesn't have func3/func4\n");
322 			return -EINVAL;
323 		}
324 		if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
325 			function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
326 					PMIC_GPIO_FUNC_INDEX_FUNC3);
327 	}
328 
329 	pad->function = function;
330 
331 	if (pad->analog_pass)
332 		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
333 	else if (pad->output_enabled && pad->input_enabled)
334 		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
335 	else if (pad->output_enabled)
336 		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
337 	else
338 		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
339 
340 	if (pad->lv_mv_type) {
341 		ret = pmic_gpio_write(state, pad,
342 				PMIC_GPIO_REG_MODE_CTL, val);
343 		if (ret < 0)
344 			return ret;
345 
346 		val = pad->atest - 1;
347 		ret = pmic_gpio_write(state, pad,
348 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
349 		if (ret < 0)
350 			return ret;
351 
352 		val = pad->out_value
353 			<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
354 		val |= pad->function
355 			& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
356 		ret = pmic_gpio_write(state, pad,
357 			PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
358 		if (ret < 0)
359 			return ret;
360 	} else {
361 		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
362 		val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
363 		val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
364 
365 		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
366 		if (ret < 0)
367 			return ret;
368 	}
369 
370 	val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
371 
372 	return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
373 }
374 
375 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
376 	.get_functions_count	= pmic_gpio_get_functions_count,
377 	.get_function_name	= pmic_gpio_get_function_name,
378 	.get_function_groups	= pmic_gpio_get_function_groups,
379 	.set_mux		= pmic_gpio_set_mux,
380 };
381 
382 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
383 				unsigned int pin, unsigned long *config)
384 {
385 	unsigned param = pinconf_to_config_param(*config);
386 	struct pmic_gpio_pad *pad;
387 	unsigned arg;
388 
389 	pad = pctldev->desc->pins[pin].drv_data;
390 
391 	switch (param) {
392 	case PIN_CONFIG_DRIVE_PUSH_PULL:
393 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
394 			return -EINVAL;
395 		arg = 1;
396 		break;
397 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
398 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
399 			return -EINVAL;
400 		arg = 1;
401 		break;
402 	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
403 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
404 			return -EINVAL;
405 		arg = 1;
406 		break;
407 	case PIN_CONFIG_BIAS_PULL_DOWN:
408 		if (pad->pullup != PMIC_GPIO_PULL_DOWN)
409 			return -EINVAL;
410 		arg = 1;
411 		break;
412 	case PIN_CONFIG_BIAS_DISABLE:
413 		if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
414 			return -EINVAL;
415 		arg = 1;
416 		break;
417 	case PIN_CONFIG_BIAS_PULL_UP:
418 		if (pad->pullup != PMIC_GPIO_PULL_UP_30)
419 			return -EINVAL;
420 		arg = 1;
421 		break;
422 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
423 		if (pad->is_enabled)
424 			return -EINVAL;
425 		arg = 1;
426 		break;
427 	case PIN_CONFIG_POWER_SOURCE:
428 		arg = pad->power_source;
429 		break;
430 	case PIN_CONFIG_INPUT_ENABLE:
431 		if (!pad->input_enabled)
432 			return -EINVAL;
433 		arg = 1;
434 		break;
435 	case PIN_CONFIG_OUTPUT_ENABLE:
436 		arg = pad->output_enabled;
437 		break;
438 	case PIN_CONFIG_OUTPUT:
439 		arg = pad->out_value;
440 		break;
441 	case PMIC_GPIO_CONF_PULL_UP:
442 		arg = pad->pullup;
443 		break;
444 	case PMIC_GPIO_CONF_STRENGTH:
445 		switch (pad->strength) {
446 		case PMIC_GPIO_OUT_STRENGTH_HIGH:
447 			arg = PMIC_GPIO_STRENGTH_HIGH;
448 			break;
449 		case PMIC_GPIO_OUT_STRENGTH_LOW:
450 			arg = PMIC_GPIO_STRENGTH_LOW;
451 			break;
452 		default:
453 			arg = pad->strength;
454 			break;
455 		}
456 		break;
457 	case PMIC_GPIO_CONF_ATEST:
458 		arg = pad->atest;
459 		break;
460 	case PMIC_GPIO_CONF_ANALOG_PASS:
461 		arg = pad->analog_pass;
462 		break;
463 	case PMIC_GPIO_CONF_DTEST_BUFFER:
464 		arg = pad->dtest_buffer;
465 		break;
466 	default:
467 		return -EINVAL;
468 	}
469 
470 	*config = pinconf_to_config_packed(param, arg);
471 	return 0;
472 }
473 
474 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
475 				unsigned long *configs, unsigned nconfs)
476 {
477 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
478 	struct pmic_gpio_pad *pad;
479 	unsigned param, arg;
480 	unsigned int val;
481 	int i, ret;
482 
483 	pad = pctldev->desc->pins[pin].drv_data;
484 
485 	pad->is_enabled = true;
486 	for (i = 0; i < nconfs; i++) {
487 		param = pinconf_to_config_param(configs[i]);
488 		arg = pinconf_to_config_argument(configs[i]);
489 
490 		switch (param) {
491 		case PIN_CONFIG_DRIVE_PUSH_PULL:
492 			pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
493 			break;
494 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
495 			if (!pad->have_buffer)
496 				return -EINVAL;
497 			pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
498 			break;
499 		case PIN_CONFIG_DRIVE_OPEN_SOURCE:
500 			if (!pad->have_buffer)
501 				return -EINVAL;
502 			pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
503 			break;
504 		case PIN_CONFIG_BIAS_DISABLE:
505 			pad->pullup = PMIC_GPIO_PULL_DISABLE;
506 			break;
507 		case PIN_CONFIG_BIAS_PULL_UP:
508 			pad->pullup = PMIC_GPIO_PULL_UP_30;
509 			break;
510 		case PIN_CONFIG_BIAS_PULL_DOWN:
511 			if (arg)
512 				pad->pullup = PMIC_GPIO_PULL_DOWN;
513 			else
514 				pad->pullup = PMIC_GPIO_PULL_DISABLE;
515 			break;
516 		case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
517 			pad->is_enabled = false;
518 			break;
519 		case PIN_CONFIG_POWER_SOURCE:
520 			if (arg >= pad->num_sources)
521 				return -EINVAL;
522 			pad->power_source = arg;
523 			break;
524 		case PIN_CONFIG_INPUT_ENABLE:
525 			pad->input_enabled = arg ? true : false;
526 			break;
527 		case PIN_CONFIG_OUTPUT_ENABLE:
528 			pad->output_enabled = arg ? true : false;
529 			break;
530 		case PIN_CONFIG_OUTPUT:
531 			pad->output_enabled = true;
532 			pad->out_value = arg;
533 			break;
534 		case PMIC_GPIO_CONF_PULL_UP:
535 			if (arg > PMIC_GPIO_PULL_UP_1P5_30)
536 				return -EINVAL;
537 			pad->pullup = arg;
538 			break;
539 		case PMIC_GPIO_CONF_STRENGTH:
540 			if (arg > PMIC_GPIO_STRENGTH_LOW)
541 				return -EINVAL;
542 			switch (arg) {
543 			case PMIC_GPIO_STRENGTH_HIGH:
544 				pad->strength = PMIC_GPIO_OUT_STRENGTH_HIGH;
545 				break;
546 			case PMIC_GPIO_STRENGTH_LOW:
547 				pad->strength = PMIC_GPIO_OUT_STRENGTH_LOW;
548 				break;
549 			default:
550 				pad->strength = arg;
551 				break;
552 			}
553 			break;
554 		case PMIC_GPIO_CONF_ATEST:
555 			if (!pad->lv_mv_type || arg > 4)
556 				return -EINVAL;
557 			pad->atest = arg;
558 			break;
559 		case PMIC_GPIO_CONF_ANALOG_PASS:
560 			if (!pad->lv_mv_type)
561 				return -EINVAL;
562 			pad->analog_pass = true;
563 			break;
564 		case PMIC_GPIO_CONF_DTEST_BUFFER:
565 			if (arg > 4)
566 				return -EINVAL;
567 			pad->dtest_buffer = arg;
568 			break;
569 		default:
570 			return -EINVAL;
571 		}
572 	}
573 
574 	val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
575 
576 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
577 	if (ret < 0)
578 		return ret;
579 
580 	val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
581 
582 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
583 	if (ret < 0)
584 		return ret;
585 
586 	val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
587 	val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
588 
589 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
590 	if (ret < 0)
591 		return ret;
592 
593 	if (pad->dtest_buffer == 0) {
594 		val = 0;
595 	} else {
596 		if (pad->lv_mv_type) {
597 			val = pad->dtest_buffer - 1;
598 			val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
599 		} else {
600 			val = BIT(pad->dtest_buffer - 1);
601 		}
602 	}
603 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
604 	if (ret < 0)
605 		return ret;
606 
607 	if (pad->analog_pass)
608 		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
609 	else if (pad->output_enabled && pad->input_enabled)
610 		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
611 	else if (pad->output_enabled)
612 		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
613 	else
614 		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
615 
616 	if (pad->lv_mv_type) {
617 		ret = pmic_gpio_write(state, pad,
618 				PMIC_GPIO_REG_MODE_CTL, val);
619 		if (ret < 0)
620 			return ret;
621 
622 		val = pad->atest - 1;
623 		ret = pmic_gpio_write(state, pad,
624 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
625 		if (ret < 0)
626 			return ret;
627 
628 		val = pad->out_value
629 			<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
630 		val |= pad->function
631 			& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
632 		ret = pmic_gpio_write(state, pad,
633 			PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
634 		if (ret < 0)
635 			return ret;
636 	} else {
637 		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
638 		val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
639 		val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
640 
641 		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
642 		if (ret < 0)
643 			return ret;
644 	}
645 
646 	val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
647 
648 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
649 
650 	return ret;
651 }
652 
653 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
654 				      struct seq_file *s, unsigned pin)
655 {
656 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
657 	struct pmic_gpio_pad *pad;
658 	int ret, val, function;
659 
660 	static const char *const biases[] = {
661 		"pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
662 		"pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
663 	};
664 	static const char *const buffer_types[] = {
665 		"push-pull", "open-drain", "open-source"
666 	};
667 	static const char *const strengths[] = {
668 		"no", "high", "medium", "low"
669 	};
670 
671 	pad = pctldev->desc->pins[pin].drv_data;
672 
673 	seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
674 
675 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
676 
677 	if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
678 		seq_puts(s, " ---");
679 	} else {
680 		if (pad->input_enabled) {
681 			ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
682 			if (ret < 0)
683 				return;
684 
685 			ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
686 			pad->out_value = ret;
687 		}
688 		/*
689 		 * For the non-LV/MV subtypes only 2 special functions are
690 		 * available, offsetting the dtest function values by 2.
691 		 */
692 		function = pad->function;
693 		if (!pad->lv_mv_type &&
694 				pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
695 			function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
696 				PMIC_GPIO_FUNC_INDEX_FUNC3;
697 
698 		if (pad->analog_pass)
699 			seq_puts(s, " analog-pass");
700 		else
701 			seq_printf(s, " %-4s",
702 					pad->output_enabled ? "out" : "in");
703 		seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
704 		seq_printf(s, " %-7s", pmic_gpio_functions[function]);
705 		seq_printf(s, " vin-%d", pad->power_source);
706 		seq_printf(s, " %-27s", biases[pad->pullup]);
707 		seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
708 		seq_printf(s, " %-7s", strengths[pad->strength]);
709 		seq_printf(s, " atest-%d", pad->atest);
710 		seq_printf(s, " dtest-%d", pad->dtest_buffer);
711 	}
712 }
713 
714 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
715 	.is_generic			= true,
716 	.pin_config_group_get		= pmic_gpio_config_get,
717 	.pin_config_group_set		= pmic_gpio_config_set,
718 	.pin_config_group_dbg_show	= pmic_gpio_config_dbg_show,
719 };
720 
721 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
722 {
723 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
724 	unsigned long config;
725 
726 	config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
727 
728 	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
729 }
730 
731 static int pmic_gpio_direction_output(struct gpio_chip *chip,
732 				      unsigned pin, int val)
733 {
734 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
735 	unsigned long config;
736 
737 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
738 
739 	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
740 }
741 
742 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
743 {
744 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
745 	struct pmic_gpio_pad *pad;
746 	int ret;
747 
748 	pad = state->ctrl->desc->pins[pin].drv_data;
749 
750 	if (!pad->is_enabled)
751 		return -EINVAL;
752 
753 	if (pad->input_enabled) {
754 		ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
755 		if (ret < 0)
756 			return ret;
757 
758 		pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
759 	}
760 
761 	return !!pad->out_value;
762 }
763 
764 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
765 {
766 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
767 	unsigned long config;
768 
769 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
770 
771 	pmic_gpio_config_set(state->ctrl, pin, &config, 1);
772 }
773 
774 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
775 			      const struct of_phandle_args *gpio_desc,
776 			      u32 *flags)
777 {
778 	if (chip->of_gpio_n_cells < 2)
779 		return -EINVAL;
780 
781 	if (flags)
782 		*flags = gpio_desc->args[1];
783 
784 	return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
785 }
786 
787 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
788 {
789 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
790 	unsigned i;
791 
792 	for (i = 0; i < chip->ngpio; i++) {
793 		pmic_gpio_config_dbg_show(state->ctrl, s, i);
794 		seq_puts(s, "\n");
795 	}
796 }
797 
798 static const struct gpio_chip pmic_gpio_gpio_template = {
799 	.direction_input	= pmic_gpio_direction_input,
800 	.direction_output	= pmic_gpio_direction_output,
801 	.get			= pmic_gpio_get,
802 	.set			= pmic_gpio_set,
803 	.request		= gpiochip_generic_request,
804 	.free			= gpiochip_generic_free,
805 	.of_xlate		= pmic_gpio_of_xlate,
806 	.dbg_show		= pmic_gpio_dbg_show,
807 };
808 
809 static int pmic_gpio_populate(struct pmic_gpio_state *state,
810 			      struct pmic_gpio_pad *pad)
811 {
812 	int type, subtype, val, dir;
813 
814 	type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
815 	if (type < 0)
816 		return type;
817 
818 	if (type != PMIC_GPIO_TYPE) {
819 		dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
820 			type, pad->base);
821 		return -ENODEV;
822 	}
823 
824 	subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
825 	if (subtype < 0)
826 		return subtype;
827 
828 	switch (subtype) {
829 	case PMIC_GPIO_SUBTYPE_GPIO_4CH:
830 		pad->have_buffer = true;
831 		fallthrough;
832 	case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
833 		pad->num_sources = 4;
834 		break;
835 	case PMIC_GPIO_SUBTYPE_GPIO_8CH:
836 		pad->have_buffer = true;
837 		fallthrough;
838 	case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
839 		pad->num_sources = 8;
840 		break;
841 	case PMIC_GPIO_SUBTYPE_GPIO_LV:
842 		pad->num_sources = 1;
843 		pad->have_buffer = true;
844 		pad->lv_mv_type = true;
845 		break;
846 	case PMIC_GPIO_SUBTYPE_GPIO_MV:
847 		pad->num_sources = 2;
848 		pad->have_buffer = true;
849 		pad->lv_mv_type = true;
850 		break;
851 	case PMIC_GPIO_SUBTYPE_GPIO_LV_VIN2:
852 		pad->num_sources = 2;
853 		pad->have_buffer = true;
854 		pad->lv_mv_type = true;
855 		break;
856 	case PMIC_GPIO_SUBTYPE_GPIO_MV_VIN3:
857 		pad->num_sources = 3;
858 		pad->have_buffer = true;
859 		pad->lv_mv_type = true;
860 		break;
861 	default:
862 		dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
863 		return -ENODEV;
864 	}
865 
866 	if (pad->lv_mv_type) {
867 		val = pmic_gpio_read(state, pad,
868 				PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
869 		if (val < 0)
870 			return val;
871 
872 		pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
873 		pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
874 
875 		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
876 		if (val < 0)
877 			return val;
878 
879 		dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
880 	} else {
881 		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
882 		if (val < 0)
883 			return val;
884 
885 		pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
886 
887 		dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
888 		dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
889 		pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
890 		pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
891 	}
892 
893 	switch (dir) {
894 	case PMIC_GPIO_MODE_DIGITAL_INPUT:
895 		pad->input_enabled = true;
896 		pad->output_enabled = false;
897 		break;
898 	case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
899 		pad->input_enabled = false;
900 		pad->output_enabled = true;
901 		break;
902 	case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
903 		pad->input_enabled = true;
904 		pad->output_enabled = true;
905 		break;
906 	case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
907 		if (!pad->lv_mv_type)
908 			return -ENODEV;
909 		pad->analog_pass = true;
910 		break;
911 	default:
912 		dev_err(state->dev, "unknown GPIO direction\n");
913 		return -ENODEV;
914 	}
915 
916 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
917 	if (val < 0)
918 		return val;
919 
920 	pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
921 	pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
922 
923 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
924 	if (val < 0)
925 		return val;
926 
927 	pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
928 	pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
929 
930 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
931 	if (val < 0)
932 		return val;
933 
934 	if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
935 		pad->dtest_buffer =
936 			(val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
937 	else if (!pad->lv_mv_type)
938 		pad->dtest_buffer = ffs(val);
939 	else
940 		pad->dtest_buffer = 0;
941 
942 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
943 	if (val < 0)
944 		return val;
945 
946 	pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
947 	pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
948 
949 	pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
950 	pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
951 
952 	if (pad->lv_mv_type) {
953 		val = pmic_gpio_read(state, pad,
954 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
955 		if (val < 0)
956 			return val;
957 		pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
958 	}
959 
960 	/* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
961 	pad->is_enabled = true;
962 	return 0;
963 }
964 
965 static int pmic_gpio_domain_translate(struct irq_domain *domain,
966 				      struct irq_fwspec *fwspec,
967 				      unsigned long *hwirq,
968 				      unsigned int *type)
969 {
970 	struct pmic_gpio_state *state = container_of(domain->host_data,
971 						     struct pmic_gpio_state,
972 						     chip);
973 
974 	if (fwspec->param_count != 2 ||
975 	    fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
976 		return -EINVAL;
977 
978 	*hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
979 	*type = fwspec->param[1];
980 
981 	return 0;
982 }
983 
984 static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
985 						  unsigned int offset)
986 {
987 	return offset + PMIC_GPIO_PHYSICAL_OFFSET;
988 }
989 
990 static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
991 					   unsigned int child_hwirq,
992 					   unsigned int child_type,
993 					   unsigned int *parent_hwirq,
994 					   unsigned int *parent_type)
995 {
996 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
997 
998 	*parent_hwirq = child_hwirq + state->pid_base;
999 	*parent_type = child_type;
1000 
1001 	return 0;
1002 }
1003 
1004 static int pmic_gpio_populate_parent_fwspec(struct gpio_chip *chip,
1005 					    union gpio_irq_fwspec *gfwspec,
1006 					    unsigned int parent_hwirq,
1007 					    unsigned int parent_type)
1008 {
1009 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
1010 	struct irq_fwspec *fwspec = &gfwspec->fwspec;
1011 
1012 	fwspec->fwnode = chip->irq.parent_domain->fwnode;
1013 
1014 	fwspec->param_count = 4;
1015 	fwspec->param[0] = state->usid;
1016 	fwspec->param[1] = parent_hwirq;
1017 	/* param[2] must be left as 0 */
1018 	fwspec->param[3] = parent_type;
1019 
1020 	return 0;
1021 }
1022 
1023 static void pmic_gpio_irq_mask(struct irq_data *data)
1024 {
1025 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1026 
1027 	irq_chip_mask_parent(data);
1028 	gpiochip_disable_irq(gc, data->hwirq);
1029 }
1030 
1031 static void pmic_gpio_irq_unmask(struct irq_data *data)
1032 {
1033 	struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
1034 
1035 	gpiochip_enable_irq(gc, data->hwirq);
1036 	irq_chip_unmask_parent(data);
1037 }
1038 
1039 static const struct irq_chip spmi_gpio_irq_chip = {
1040 	.name		= "spmi-gpio",
1041 	.irq_ack	= irq_chip_ack_parent,
1042 	.irq_mask	= pmic_gpio_irq_mask,
1043 	.irq_unmask	= pmic_gpio_irq_unmask,
1044 	.irq_set_type	= irq_chip_set_type_parent,
1045 	.irq_set_wake	= irq_chip_set_wake_parent,
1046 	.flags		= IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND,
1047 	GPIOCHIP_IRQ_RESOURCE_HELPERS,
1048 };
1049 
1050 static int pmic_gpio_probe(struct platform_device *pdev)
1051 {
1052 	struct irq_domain *parent_domain;
1053 	struct device_node *parent_node;
1054 	struct device *dev = &pdev->dev;
1055 	struct pinctrl_pin_desc *pindesc;
1056 	struct pinctrl_desc *pctrldesc;
1057 	struct pmic_gpio_pad *pad, *pads;
1058 	struct pmic_gpio_state *state;
1059 	struct gpio_irq_chip *girq;
1060 	const struct spmi_device *parent_spmi_dev;
1061 	int ret, npins, i;
1062 	u32 reg;
1063 
1064 	ret = of_property_read_u32(dev->of_node, "reg", &reg);
1065 	if (ret < 0) {
1066 		dev_err(dev, "missing base address");
1067 		return ret;
1068 	}
1069 
1070 	npins = (uintptr_t) device_get_match_data(&pdev->dev);
1071 
1072 	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1073 	if (!state)
1074 		return -ENOMEM;
1075 
1076 	platform_set_drvdata(pdev, state);
1077 
1078 	state->dev = &pdev->dev;
1079 	state->map = dev_get_regmap(dev->parent, NULL);
1080 	parent_spmi_dev = to_spmi_device(dev->parent);
1081 	state->usid = parent_spmi_dev->usid;
1082 	state->pid_base = reg >> 8;
1083 
1084 	pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
1085 	if (!pindesc)
1086 		return -ENOMEM;
1087 
1088 	pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
1089 	if (!pads)
1090 		return -ENOMEM;
1091 
1092 	pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
1093 	if (!pctrldesc)
1094 		return -ENOMEM;
1095 
1096 	pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1097 	pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1098 	pctrldesc->confops = &pmic_gpio_pinconf_ops;
1099 	pctrldesc->owner = THIS_MODULE;
1100 	pctrldesc->name = dev_name(dev);
1101 	pctrldesc->pins = pindesc;
1102 	pctrldesc->npins = npins;
1103 	pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1104 	pctrldesc->custom_params = pmic_gpio_bindings;
1105 #ifdef CONFIG_DEBUG_FS
1106 	pctrldesc->custom_conf_items = pmic_conf_items;
1107 #endif
1108 
1109 	for (i = 0; i < npins; i++, pindesc++) {
1110 		pad = &pads[i];
1111 		pindesc->drv_data = pad;
1112 		pindesc->number = i;
1113 		pindesc->name = pmic_gpio_groups[i];
1114 
1115 		pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1116 
1117 		ret = pmic_gpio_populate(state, pad);
1118 		if (ret < 0)
1119 			return ret;
1120 	}
1121 
1122 	state->chip = pmic_gpio_gpio_template;
1123 	state->chip.parent = dev;
1124 	state->chip.base = -1;
1125 	state->chip.ngpio = npins;
1126 	state->chip.label = dev_name(dev);
1127 	state->chip.of_gpio_n_cells = 2;
1128 	state->chip.can_sleep = false;
1129 
1130 	state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1131 	if (IS_ERR(state->ctrl))
1132 		return PTR_ERR(state->ctrl);
1133 
1134 	parent_node = of_irq_find_parent(state->dev->of_node);
1135 	if (!parent_node)
1136 		return -ENXIO;
1137 
1138 	parent_domain = irq_find_host(parent_node);
1139 	of_node_put(parent_node);
1140 	if (!parent_domain)
1141 		return -ENXIO;
1142 
1143 	girq = &state->chip.irq;
1144 	gpio_irq_chip_set_chip(girq, &spmi_gpio_irq_chip);
1145 	girq->default_type = IRQ_TYPE_NONE;
1146 	girq->handler = handle_level_irq;
1147 	girq->fwnode = of_node_to_fwnode(state->dev->of_node);
1148 	girq->parent_domain = parent_domain;
1149 	girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
1150 	girq->populate_parent_alloc_arg = pmic_gpio_populate_parent_fwspec;
1151 	girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
1152 	girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
1153 
1154 	ret = gpiochip_add_data(&state->chip, state);
1155 	if (ret) {
1156 		dev_err(state->dev, "can't add gpio chip\n");
1157 		return ret;
1158 	}
1159 
1160 	/*
1161 	 * For DeviceTree-supported systems, the gpio core checks the
1162 	 * pinctrl's device node for the "gpio-ranges" property.
1163 	 * If it is present, it takes care of adding the pin ranges
1164 	 * for the driver. In this case the driver can skip ahead.
1165 	 *
1166 	 * In order to remain compatible with older, existing DeviceTree
1167 	 * files which don't set the "gpio-ranges" property or systems that
1168 	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1169 	 */
1170 	if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
1171 		ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1172 					     npins);
1173 		if (ret) {
1174 			dev_err(dev, "failed to add pin range\n");
1175 			goto err_range;
1176 		}
1177 	}
1178 
1179 	return 0;
1180 
1181 err_range:
1182 	gpiochip_remove(&state->chip);
1183 	return ret;
1184 }
1185 
1186 static int pmic_gpio_remove(struct platform_device *pdev)
1187 {
1188 	struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1189 
1190 	gpiochip_remove(&state->chip);
1191 	return 0;
1192 }
1193 
1194 static const struct of_device_id pmic_gpio_of_match[] = {
1195 	{ .compatible = "qcom,pm2250-gpio", .data = (void *) 10 },
1196 	/* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
1197 	{ .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
1198 	/* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
1199 	{ .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
1200 	{ .compatible = "qcom,pm6125-gpio", .data = (void *) 9 },
1201 	{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
1202 	{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
1203 	{ .compatible = "qcom,pm6350-gpio", .data = (void *) 9 },
1204 	{ .compatible = "qcom,pm7250b-gpio", .data = (void *) 12 },
1205 	{ .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
1206 	{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1207 	{ .compatible = "qcom,pm8008-gpio", .data = (void *) 2 },
1208 	{ .compatible = "qcom,pm8019-gpio", .data = (void *) 6 },
1209 	/* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
1210 	{ .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
1211 	{ .compatible = "qcom,pmc8180-gpio", .data = (void *) 10 },
1212 	/* pm8150b has 12 GPIOs with holes on 3, r and 7 */
1213 	{ .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
1214 	/* pm8150l has 12 GPIOs with holes on 7 */
1215 	{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
1216 	{ .compatible = "qcom,pmc8180c-gpio", .data = (void *) 12 },
1217 	{ .compatible = "qcom,pm8226-gpio", .data = (void *) 8 },
1218 	{ .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
1219 	{ .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
1220 	{ .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
1221 	{ .compatible = "qcom,pm8450-gpio", .data = (void *) 4 },
1222 	{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1223 	{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1224 	/* pm8950 has 8 GPIOs with holes on 3 */
1225 	{ .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
1226 	{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1227 	{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1228 	{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1229 	{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
1230 	{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1231 	{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1232 	{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
1233 	{ .compatible = "qcom,pmm8155au-gpio", .data = (void *) 10 },
1234 	/* pmp8074 has 12 GPIOs with holes on 1 and 12 */
1235 	{ .compatible = "qcom,pmp8074-gpio", .data = (void *) 12 },
1236 	{ .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
1237 	{ .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
1238 	/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1239 	{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1240 	/* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
1241 	{ .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
1242 	{ .compatible = "qcom,pmx65-gpio", .data = (void *) 16 },
1243 	{ },
1244 };
1245 
1246 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1247 
1248 static struct platform_driver pmic_gpio_driver = {
1249 	.driver = {
1250 		   .name = "qcom-spmi-gpio",
1251 		   .of_match_table = pmic_gpio_of_match,
1252 	},
1253 	.probe	= pmic_gpio_probe,
1254 	.remove = pmic_gpio_remove,
1255 };
1256 
1257 module_platform_driver(pmic_gpio_driver);
1258 
1259 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1260 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1261 MODULE_ALIAS("platform:qcom-spmi-gpio");
1262 MODULE_LICENSE("GPL v2");
1263