1 /* 2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/gpio.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/pinctrl/pinconf-generic.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 #include <linux/types.h> 25 26 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 27 28 #include "../core.h" 29 #include "../pinctrl-utils.h" 30 31 #define PMIC_GPIO_ADDRESS_RANGE 0x100 32 33 /* type and subtype registers base address offsets */ 34 #define PMIC_GPIO_REG_TYPE 0x4 35 #define PMIC_GPIO_REG_SUBTYPE 0x5 36 37 /* GPIO peripheral type and subtype out_values */ 38 #define PMIC_GPIO_TYPE 0x10 39 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1 40 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5 41 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9 42 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd 43 44 #define PMIC_MPP_REG_RT_STS 0x10 45 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 46 47 /* control register base address offsets */ 48 #define PMIC_GPIO_REG_MODE_CTL 0x40 49 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41 50 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42 51 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45 52 #define PMIC_GPIO_REG_EN_CTL 0x46 53 54 /* PMIC_GPIO_REG_MODE_CTL */ 55 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1 56 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1 57 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7 58 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4 59 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7 60 61 /* PMIC_GPIO_REG_DIG_VIN_CTL */ 62 #define PMIC_GPIO_REG_VIN_SHIFT 0 63 #define PMIC_GPIO_REG_VIN_MASK 0x7 64 65 /* PMIC_GPIO_REG_DIG_PULL_CTL */ 66 #define PMIC_GPIO_REG_PULL_SHIFT 0 67 #define PMIC_GPIO_REG_PULL_MASK 0x7 68 69 #define PMIC_GPIO_PULL_DOWN 4 70 #define PMIC_GPIO_PULL_DISABLE 5 71 72 /* PMIC_GPIO_REG_DIG_OUT_CTL */ 73 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0 74 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3 75 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4 76 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3 77 78 /* 79 * Output type - indicates pin should be configured as push-pull, 80 * open drain or open source. 81 */ 82 #define PMIC_GPIO_OUT_BUF_CMOS 0 83 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1 84 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2 85 86 /* PMIC_GPIO_REG_EN_CTL */ 87 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7 88 89 #define PMIC_GPIO_PHYSICAL_OFFSET 1 90 91 /* Qualcomm specific pin configurations */ 92 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1) 93 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2) 94 95 /** 96 * struct pmic_gpio_pad - keep current GPIO settings 97 * @base: Address base in SPMI device. 98 * @irq: IRQ number which this GPIO generate. 99 * @is_enabled: Set to false when GPIO should be put in high Z state. 100 * @out_value: Cached pin output value 101 * @have_buffer: Set to true if GPIO output could be configured in push-pull, 102 * open-drain or open-source mode. 103 * @output_enabled: Set to true if GPIO output logic is enabled. 104 * @input_enabled: Set to true if GPIO input buffer logic is enabled. 105 * @num_sources: Number of power-sources supported by this GPIO. 106 * @power_source: Current power-source used. 107 * @buffer_type: Push-pull, open-drain or open-source. 108 * @pullup: Constant current which flow trough GPIO output buffer. 109 * @strength: No, Low, Medium, High 110 * @function: See pmic_gpio_functions[] 111 */ 112 struct pmic_gpio_pad { 113 u16 base; 114 int irq; 115 bool is_enabled; 116 bool out_value; 117 bool have_buffer; 118 bool output_enabled; 119 bool input_enabled; 120 unsigned int num_sources; 121 unsigned int power_source; 122 unsigned int buffer_type; 123 unsigned int pullup; 124 unsigned int strength; 125 unsigned int function; 126 }; 127 128 struct pmic_gpio_state { 129 struct device *dev; 130 struct regmap *map; 131 struct pinctrl_dev *ctrl; 132 struct gpio_chip chip; 133 }; 134 135 static const struct pinconf_generic_params pmic_gpio_bindings[] = { 136 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0}, 137 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0}, 138 }; 139 140 #ifdef CONFIG_DEBUG_FS 141 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { 142 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true), 143 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true), 144 }; 145 #endif 146 147 static const char *const pmic_gpio_groups[] = { 148 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", 149 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", 150 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 151 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 152 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", 153 }; 154 155 static const char *const pmic_gpio_functions[] = { 156 PMIC_GPIO_FUNC_NORMAL, PMIC_GPIO_FUNC_PAIRED, 157 PMIC_GPIO_FUNC_FUNC1, PMIC_GPIO_FUNC_FUNC2, 158 PMIC_GPIO_FUNC_DTEST1, PMIC_GPIO_FUNC_DTEST2, 159 PMIC_GPIO_FUNC_DTEST3, PMIC_GPIO_FUNC_DTEST4, 160 }; 161 162 static int pmic_gpio_read(struct pmic_gpio_state *state, 163 struct pmic_gpio_pad *pad, unsigned int addr) 164 { 165 unsigned int val; 166 int ret; 167 168 ret = regmap_read(state->map, pad->base + addr, &val); 169 if (ret < 0) 170 dev_err(state->dev, "read 0x%x failed\n", addr); 171 else 172 ret = val; 173 174 return ret; 175 } 176 177 static int pmic_gpio_write(struct pmic_gpio_state *state, 178 struct pmic_gpio_pad *pad, unsigned int addr, 179 unsigned int val) 180 { 181 int ret; 182 183 ret = regmap_write(state->map, pad->base + addr, val); 184 if (ret < 0) 185 dev_err(state->dev, "write 0x%x failed\n", addr); 186 187 return ret; 188 } 189 190 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev) 191 { 192 /* Every PIN is a group */ 193 return pctldev->desc->npins; 194 } 195 196 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev, 197 unsigned pin) 198 { 199 return pctldev->desc->pins[pin].name; 200 } 201 202 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin, 203 const unsigned **pins, unsigned *num_pins) 204 { 205 *pins = &pctldev->desc->pins[pin].number; 206 *num_pins = 1; 207 return 0; 208 } 209 210 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = { 211 .get_groups_count = pmic_gpio_get_groups_count, 212 .get_group_name = pmic_gpio_get_group_name, 213 .get_group_pins = pmic_gpio_get_group_pins, 214 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 215 .dt_free_map = pinctrl_utils_dt_free_map, 216 }; 217 218 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev) 219 { 220 return ARRAY_SIZE(pmic_gpio_functions); 221 } 222 223 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev, 224 unsigned function) 225 { 226 return pmic_gpio_functions[function]; 227 } 228 229 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev, 230 unsigned function, 231 const char *const **groups, 232 unsigned *const num_qgroups) 233 { 234 *groups = pmic_gpio_groups; 235 *num_qgroups = pctldev->desc->npins; 236 return 0; 237 } 238 239 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function, 240 unsigned pin) 241 { 242 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 243 struct pmic_gpio_pad *pad; 244 unsigned int val; 245 int ret; 246 247 pad = pctldev->desc->pins[pin].drv_data; 248 249 pad->function = function; 250 251 val = 0; 252 if (pad->output_enabled) { 253 if (pad->input_enabled) 254 val = 2; 255 else 256 val = 1; 257 } 258 259 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; 260 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 261 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 262 263 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); 264 if (ret < 0) 265 return ret; 266 267 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; 268 269 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); 270 } 271 272 static const struct pinmux_ops pmic_gpio_pinmux_ops = { 273 .get_functions_count = pmic_gpio_get_functions_count, 274 .get_function_name = pmic_gpio_get_function_name, 275 .get_function_groups = pmic_gpio_get_function_groups, 276 .set_mux = pmic_gpio_set_mux, 277 }; 278 279 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev, 280 unsigned int pin, unsigned long *config) 281 { 282 unsigned param = pinconf_to_config_param(*config); 283 struct pmic_gpio_pad *pad; 284 unsigned arg; 285 286 pad = pctldev->desc->pins[pin].drv_data; 287 288 switch (param) { 289 case PIN_CONFIG_DRIVE_PUSH_PULL: 290 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_CMOS; 291 break; 292 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 293 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; 294 break; 295 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 296 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; 297 break; 298 case PIN_CONFIG_BIAS_PULL_DOWN: 299 arg = pad->pullup == PMIC_GPIO_PULL_DOWN; 300 break; 301 case PIN_CONFIG_BIAS_DISABLE: 302 arg = pad->pullup = PMIC_GPIO_PULL_DISABLE; 303 break; 304 case PIN_CONFIG_BIAS_PULL_UP: 305 arg = pad->pullup == PMIC_GPIO_PULL_UP_30; 306 break; 307 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 308 arg = !pad->is_enabled; 309 break; 310 case PIN_CONFIG_POWER_SOURCE: 311 arg = pad->power_source; 312 break; 313 case PIN_CONFIG_INPUT_ENABLE: 314 arg = pad->input_enabled; 315 break; 316 case PIN_CONFIG_OUTPUT: 317 arg = pad->out_value; 318 break; 319 case PMIC_GPIO_CONF_PULL_UP: 320 arg = pad->pullup; 321 break; 322 case PMIC_GPIO_CONF_STRENGTH: 323 arg = pad->strength; 324 break; 325 default: 326 return -EINVAL; 327 } 328 329 *config = pinconf_to_config_packed(param, arg); 330 return 0; 331 } 332 333 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 334 unsigned long *configs, unsigned nconfs) 335 { 336 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 337 struct pmic_gpio_pad *pad; 338 unsigned param, arg; 339 unsigned int val; 340 int i, ret; 341 342 pad = pctldev->desc->pins[pin].drv_data; 343 344 for (i = 0; i < nconfs; i++) { 345 param = pinconf_to_config_param(configs[i]); 346 arg = pinconf_to_config_argument(configs[i]); 347 348 switch (param) { 349 case PIN_CONFIG_DRIVE_PUSH_PULL: 350 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS; 351 break; 352 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 353 if (!pad->have_buffer) 354 return -EINVAL; 355 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; 356 break; 357 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 358 if (!pad->have_buffer) 359 return -EINVAL; 360 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; 361 break; 362 case PIN_CONFIG_BIAS_DISABLE: 363 pad->pullup = PMIC_GPIO_PULL_DISABLE; 364 break; 365 case PIN_CONFIG_BIAS_PULL_UP: 366 pad->pullup = PMIC_GPIO_PULL_UP_30; 367 break; 368 case PIN_CONFIG_BIAS_PULL_DOWN: 369 if (arg) 370 pad->pullup = PMIC_GPIO_PULL_DOWN; 371 else 372 pad->pullup = PMIC_GPIO_PULL_DISABLE; 373 break; 374 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 375 pad->is_enabled = false; 376 break; 377 case PIN_CONFIG_POWER_SOURCE: 378 if (arg > pad->num_sources) 379 return -EINVAL; 380 pad->power_source = arg; 381 break; 382 case PIN_CONFIG_INPUT_ENABLE: 383 pad->input_enabled = arg ? true : false; 384 break; 385 case PIN_CONFIG_OUTPUT: 386 pad->output_enabled = true; 387 pad->out_value = arg; 388 break; 389 case PMIC_GPIO_CONF_PULL_UP: 390 if (arg > PMIC_GPIO_PULL_UP_1P5_30) 391 return -EINVAL; 392 pad->pullup = arg; 393 break; 394 case PMIC_GPIO_CONF_STRENGTH: 395 if (arg > PMIC_GPIO_STRENGTH_LOW) 396 return -EINVAL; 397 pad->strength = arg; 398 break; 399 default: 400 return -EINVAL; 401 } 402 } 403 404 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT; 405 406 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val); 407 if (ret < 0) 408 return ret; 409 410 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT; 411 412 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val); 413 if (ret < 0) 414 return ret; 415 416 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT; 417 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; 418 419 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val); 420 if (ret < 0) 421 return ret; 422 423 val = 0; 424 if (pad->output_enabled) { 425 if (pad->input_enabled) 426 val = 2; 427 else 428 val = 1; 429 } 430 431 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; 432 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 433 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 434 435 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); 436 } 437 438 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, 439 struct seq_file *s, unsigned pin) 440 { 441 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 442 struct pmic_gpio_pad *pad; 443 int ret, val; 444 445 static const char *const biases[] = { 446 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", 447 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" 448 }; 449 static const char *const buffer_types[] = { 450 "push-pull", "open-drain", "open-source" 451 }; 452 static const char *const strengths[] = { 453 "no", "high", "medium", "low" 454 }; 455 456 pad = pctldev->desc->pins[pin].drv_data; 457 458 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET); 459 460 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL); 461 462 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) { 463 seq_puts(s, " ---"); 464 } else { 465 466 if (pad->input_enabled) { 467 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); 468 if (ret < 0) 469 return; 470 471 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; 472 pad->out_value = ret; 473 } 474 475 seq_printf(s, " %-4s", pad->output_enabled ? "out" : "in"); 476 seq_printf(s, " %-7s", pmic_gpio_functions[pad->function]); 477 seq_printf(s, " vin-%d", pad->power_source); 478 seq_printf(s, " %-27s", biases[pad->pullup]); 479 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]); 480 seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); 481 seq_printf(s, " %-7s", strengths[pad->strength]); 482 } 483 } 484 485 static const struct pinconf_ops pmic_gpio_pinconf_ops = { 486 .is_generic = true, 487 .pin_config_group_get = pmic_gpio_config_get, 488 .pin_config_group_set = pmic_gpio_config_set, 489 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show, 490 }; 491 492 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 493 { 494 struct pmic_gpio_state *state = gpiochip_get_data(chip); 495 unsigned long config; 496 497 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); 498 499 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); 500 } 501 502 static int pmic_gpio_direction_output(struct gpio_chip *chip, 503 unsigned pin, int val) 504 { 505 struct pmic_gpio_state *state = gpiochip_get_data(chip); 506 unsigned long config; 507 508 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); 509 510 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); 511 } 512 513 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin) 514 { 515 struct pmic_gpio_state *state = gpiochip_get_data(chip); 516 struct pmic_gpio_pad *pad; 517 int ret; 518 519 pad = state->ctrl->desc->pins[pin].drv_data; 520 521 if (!pad->is_enabled) 522 return -EINVAL; 523 524 if (pad->input_enabled) { 525 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); 526 if (ret < 0) 527 return ret; 528 529 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; 530 } 531 532 return !!pad->out_value; 533 } 534 535 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 536 { 537 struct pmic_gpio_state *state = gpiochip_get_data(chip); 538 unsigned long config; 539 540 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); 541 542 pmic_gpio_config_set(state->ctrl, pin, &config, 1); 543 } 544 545 static int pmic_gpio_of_xlate(struct gpio_chip *chip, 546 const struct of_phandle_args *gpio_desc, 547 u32 *flags) 548 { 549 if (chip->of_gpio_n_cells < 2) 550 return -EINVAL; 551 552 if (flags) 553 *flags = gpio_desc->args[1]; 554 555 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET; 556 } 557 558 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 559 { 560 struct pmic_gpio_state *state = gpiochip_get_data(chip); 561 struct pmic_gpio_pad *pad; 562 563 pad = state->ctrl->desc->pins[pin].drv_data; 564 565 return pad->irq; 566 } 567 568 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 569 { 570 struct pmic_gpio_state *state = gpiochip_get_data(chip); 571 unsigned i; 572 573 for (i = 0; i < chip->ngpio; i++) { 574 pmic_gpio_config_dbg_show(state->ctrl, s, i); 575 seq_puts(s, "\n"); 576 } 577 } 578 579 static const struct gpio_chip pmic_gpio_gpio_template = { 580 .direction_input = pmic_gpio_direction_input, 581 .direction_output = pmic_gpio_direction_output, 582 .get = pmic_gpio_get, 583 .set = pmic_gpio_set, 584 .request = gpiochip_generic_request, 585 .free = gpiochip_generic_free, 586 .of_xlate = pmic_gpio_of_xlate, 587 .to_irq = pmic_gpio_to_irq, 588 .dbg_show = pmic_gpio_dbg_show, 589 }; 590 591 static int pmic_gpio_populate(struct pmic_gpio_state *state, 592 struct pmic_gpio_pad *pad) 593 { 594 int type, subtype, val, dir; 595 596 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE); 597 if (type < 0) 598 return type; 599 600 if (type != PMIC_GPIO_TYPE) { 601 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", 602 type, pad->base); 603 return -ENODEV; 604 } 605 606 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE); 607 if (subtype < 0) 608 return subtype; 609 610 switch (subtype) { 611 case PMIC_GPIO_SUBTYPE_GPIO_4CH: 612 pad->have_buffer = true; 613 case PMIC_GPIO_SUBTYPE_GPIOC_4CH: 614 pad->num_sources = 4; 615 break; 616 case PMIC_GPIO_SUBTYPE_GPIO_8CH: 617 pad->have_buffer = true; 618 case PMIC_GPIO_SUBTYPE_GPIOC_8CH: 619 pad->num_sources = 8; 620 break; 621 default: 622 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype); 623 return -ENODEV; 624 } 625 626 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); 627 if (val < 0) 628 return val; 629 630 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 631 632 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; 633 dir &= PMIC_GPIO_REG_MODE_DIR_MASK; 634 switch (dir) { 635 case 0: 636 pad->input_enabled = true; 637 pad->output_enabled = false; 638 break; 639 case 1: 640 pad->input_enabled = false; 641 pad->output_enabled = true; 642 break; 643 case 2: 644 pad->input_enabled = true; 645 pad->output_enabled = true; 646 break; 647 default: 648 dev_err(state->dev, "unknown GPIO direction\n"); 649 return -ENODEV; 650 } 651 652 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 653 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK; 654 655 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL); 656 if (val < 0) 657 return val; 658 659 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT; 660 pad->power_source &= PMIC_GPIO_REG_VIN_MASK; 661 662 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL); 663 if (val < 0) 664 return val; 665 666 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT; 667 pad->pullup &= PMIC_GPIO_REG_PULL_MASK; 668 669 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL); 670 if (val < 0) 671 return val; 672 673 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; 674 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK; 675 676 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT; 677 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK; 678 679 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ 680 pad->is_enabled = true; 681 return 0; 682 } 683 684 static int pmic_gpio_probe(struct platform_device *pdev) 685 { 686 struct device *dev = &pdev->dev; 687 struct pinctrl_pin_desc *pindesc; 688 struct pinctrl_desc *pctrldesc; 689 struct pmic_gpio_pad *pad, *pads; 690 struct pmic_gpio_state *state; 691 int ret, npins, i; 692 u32 reg; 693 694 ret = of_property_read_u32(dev->of_node, "reg", ®); 695 if (ret < 0) { 696 dev_err(dev, "missing base address"); 697 return ret; 698 } 699 700 npins = platform_irq_count(pdev); 701 if (!npins) 702 return -EINVAL; 703 if (npins < 0) 704 return npins; 705 706 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups)); 707 708 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); 709 if (!state) 710 return -ENOMEM; 711 712 platform_set_drvdata(pdev, state); 713 714 state->dev = &pdev->dev; 715 state->map = dev_get_regmap(dev->parent, NULL); 716 717 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); 718 if (!pindesc) 719 return -ENOMEM; 720 721 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); 722 if (!pads) 723 return -ENOMEM; 724 725 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); 726 if (!pctrldesc) 727 return -ENOMEM; 728 729 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops; 730 pctrldesc->pmxops = &pmic_gpio_pinmux_ops; 731 pctrldesc->confops = &pmic_gpio_pinconf_ops; 732 pctrldesc->owner = THIS_MODULE; 733 pctrldesc->name = dev_name(dev); 734 pctrldesc->pins = pindesc; 735 pctrldesc->npins = npins; 736 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings); 737 pctrldesc->custom_params = pmic_gpio_bindings; 738 #ifdef CONFIG_DEBUG_FS 739 pctrldesc->custom_conf_items = pmic_conf_items; 740 #endif 741 742 for (i = 0; i < npins; i++, pindesc++) { 743 pad = &pads[i]; 744 pindesc->drv_data = pad; 745 pindesc->number = i; 746 pindesc->name = pmic_gpio_groups[i]; 747 748 pad->irq = platform_get_irq(pdev, i); 749 if (pad->irq < 0) 750 return pad->irq; 751 752 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE; 753 754 ret = pmic_gpio_populate(state, pad); 755 if (ret < 0) 756 return ret; 757 } 758 759 state->chip = pmic_gpio_gpio_template; 760 state->chip.parent = dev; 761 state->chip.base = -1; 762 state->chip.ngpio = npins; 763 state->chip.label = dev_name(dev); 764 state->chip.of_gpio_n_cells = 2; 765 state->chip.can_sleep = false; 766 767 state->ctrl = pinctrl_register(pctrldesc, dev, state); 768 if (IS_ERR(state->ctrl)) 769 return PTR_ERR(state->ctrl); 770 771 ret = gpiochip_add_data(&state->chip, state); 772 if (ret) { 773 dev_err(state->dev, "can't add gpio chip\n"); 774 goto err_chip; 775 } 776 777 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); 778 if (ret) { 779 dev_err(dev, "failed to add pin range\n"); 780 goto err_range; 781 } 782 783 return 0; 784 785 err_range: 786 gpiochip_remove(&state->chip); 787 err_chip: 788 pinctrl_unregister(state->ctrl); 789 return ret; 790 } 791 792 static int pmic_gpio_remove(struct platform_device *pdev) 793 { 794 struct pmic_gpio_state *state = platform_get_drvdata(pdev); 795 796 gpiochip_remove(&state->chip); 797 pinctrl_unregister(state->ctrl); 798 return 0; 799 } 800 801 static const struct of_device_id pmic_gpio_of_match[] = { 802 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */ 803 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */ 804 { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ 805 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ 806 { }, 807 }; 808 809 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match); 810 811 static struct platform_driver pmic_gpio_driver = { 812 .driver = { 813 .name = "qcom-spmi-gpio", 814 .of_match_table = pmic_gpio_of_match, 815 }, 816 .probe = pmic_gpio_probe, 817 .remove = pmic_gpio_remove, 818 }; 819 820 module_platform_driver(pmic_gpio_driver); 821 822 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); 823 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver"); 824 MODULE_ALIAS("platform:qcom-spmi-gpio"); 825 MODULE_LICENSE("GPL v2"); 826