1 /* 2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/gpio/driver.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/pinctrl/pinconf-generic.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 #include <linux/types.h> 25 26 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 27 28 #include "../core.h" 29 #include "../pinctrl-utils.h" 30 31 #define PMIC_GPIO_ADDRESS_RANGE 0x100 32 33 /* type and subtype registers base address offsets */ 34 #define PMIC_GPIO_REG_TYPE 0x4 35 #define PMIC_GPIO_REG_SUBTYPE 0x5 36 37 /* GPIO peripheral type and subtype out_values */ 38 #define PMIC_GPIO_TYPE 0x10 39 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1 40 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5 41 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9 42 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd 43 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10 44 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11 45 46 #define PMIC_MPP_REG_RT_STS 0x10 47 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 48 49 /* control register base address offsets */ 50 #define PMIC_GPIO_REG_MODE_CTL 0x40 51 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41 52 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42 53 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44 54 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43 55 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45 56 #define PMIC_GPIO_REG_EN_CTL 0x46 57 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A 58 59 /* PMIC_GPIO_REG_MODE_CTL */ 60 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1 61 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1 62 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7 63 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4 64 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7 65 66 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0 67 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1 68 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2 69 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3 70 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3 71 72 /* PMIC_GPIO_REG_DIG_VIN_CTL */ 73 #define PMIC_GPIO_REG_VIN_SHIFT 0 74 #define PMIC_GPIO_REG_VIN_MASK 0x7 75 76 /* PMIC_GPIO_REG_DIG_PULL_CTL */ 77 #define PMIC_GPIO_REG_PULL_SHIFT 0 78 #define PMIC_GPIO_REG_PULL_MASK 0x7 79 80 #define PMIC_GPIO_PULL_DOWN 4 81 #define PMIC_GPIO_PULL_DISABLE 5 82 83 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */ 84 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80 85 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7 86 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF 87 88 /* PMIC_GPIO_REG_DIG_IN_CTL */ 89 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80 90 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7 91 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf 92 93 /* PMIC_GPIO_REG_DIG_OUT_CTL */ 94 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0 95 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3 96 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4 97 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3 98 99 /* 100 * Output type - indicates pin should be configured as push-pull, 101 * open drain or open source. 102 */ 103 #define PMIC_GPIO_OUT_BUF_CMOS 0 104 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1 105 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2 106 107 /* PMIC_GPIO_REG_EN_CTL */ 108 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7 109 110 #define PMIC_GPIO_PHYSICAL_OFFSET 1 111 112 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */ 113 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3 114 115 /* Qualcomm specific pin configurations */ 116 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1) 117 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2) 118 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3) 119 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4) 120 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5) 121 122 /* The index of each function in pmic_gpio_functions[] array */ 123 enum pmic_gpio_func_index { 124 PMIC_GPIO_FUNC_INDEX_NORMAL, 125 PMIC_GPIO_FUNC_INDEX_PAIRED, 126 PMIC_GPIO_FUNC_INDEX_FUNC1, 127 PMIC_GPIO_FUNC_INDEX_FUNC2, 128 PMIC_GPIO_FUNC_INDEX_FUNC3, 129 PMIC_GPIO_FUNC_INDEX_FUNC4, 130 PMIC_GPIO_FUNC_INDEX_DTEST1, 131 PMIC_GPIO_FUNC_INDEX_DTEST2, 132 PMIC_GPIO_FUNC_INDEX_DTEST3, 133 PMIC_GPIO_FUNC_INDEX_DTEST4, 134 }; 135 136 /** 137 * struct pmic_gpio_pad - keep current GPIO settings 138 * @base: Address base in SPMI device. 139 * @irq: IRQ number which this GPIO generate. 140 * @is_enabled: Set to false when GPIO should be put in high Z state. 141 * @out_value: Cached pin output value 142 * @have_buffer: Set to true if GPIO output could be configured in push-pull, 143 * open-drain or open-source mode. 144 * @output_enabled: Set to true if GPIO output logic is enabled. 145 * @input_enabled: Set to true if GPIO input buffer logic is enabled. 146 * @analog_pass: Set to true if GPIO is in analog-pass-through mode. 147 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11). 148 * @num_sources: Number of power-sources supported by this GPIO. 149 * @power_source: Current power-source used. 150 * @buffer_type: Push-pull, open-drain or open-source. 151 * @pullup: Constant current which flow trough GPIO output buffer. 152 * @strength: No, Low, Medium, High 153 * @function: See pmic_gpio_functions[] 154 * @atest: the ATEST selection for GPIO analog-pass-through mode 155 * @dtest_buffer: the DTEST buffer selection for digital input mode. 156 */ 157 struct pmic_gpio_pad { 158 u16 base; 159 int irq; 160 bool is_enabled; 161 bool out_value; 162 bool have_buffer; 163 bool output_enabled; 164 bool input_enabled; 165 bool analog_pass; 166 bool lv_mv_type; 167 unsigned int num_sources; 168 unsigned int power_source; 169 unsigned int buffer_type; 170 unsigned int pullup; 171 unsigned int strength; 172 unsigned int function; 173 unsigned int atest; 174 unsigned int dtest_buffer; 175 }; 176 177 struct pmic_gpio_state { 178 struct device *dev; 179 struct regmap *map; 180 struct pinctrl_dev *ctrl; 181 struct gpio_chip chip; 182 }; 183 184 static const struct pinconf_generic_params pmic_gpio_bindings[] = { 185 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0}, 186 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0}, 187 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0}, 188 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0}, 189 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0}, 190 }; 191 192 #ifdef CONFIG_DEBUG_FS 193 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { 194 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true), 195 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true), 196 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true), 197 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true), 198 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true), 199 }; 200 #endif 201 202 static const char *const pmic_gpio_groups[] = { 203 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", 204 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", 205 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 206 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 207 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", 208 }; 209 210 static const char *const pmic_gpio_functions[] = { 211 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL, 212 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED, 213 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1, 214 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2, 215 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3, 216 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4, 217 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1, 218 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2, 219 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3, 220 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4, 221 }; 222 223 static int pmic_gpio_read(struct pmic_gpio_state *state, 224 struct pmic_gpio_pad *pad, unsigned int addr) 225 { 226 unsigned int val; 227 int ret; 228 229 ret = regmap_read(state->map, pad->base + addr, &val); 230 if (ret < 0) 231 dev_err(state->dev, "read 0x%x failed\n", addr); 232 else 233 ret = val; 234 235 return ret; 236 } 237 238 static int pmic_gpio_write(struct pmic_gpio_state *state, 239 struct pmic_gpio_pad *pad, unsigned int addr, 240 unsigned int val) 241 { 242 int ret; 243 244 ret = regmap_write(state->map, pad->base + addr, val); 245 if (ret < 0) 246 dev_err(state->dev, "write 0x%x failed\n", addr); 247 248 return ret; 249 } 250 251 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev) 252 { 253 /* Every PIN is a group */ 254 return pctldev->desc->npins; 255 } 256 257 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev, 258 unsigned pin) 259 { 260 return pctldev->desc->pins[pin].name; 261 } 262 263 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin, 264 const unsigned **pins, unsigned *num_pins) 265 { 266 *pins = &pctldev->desc->pins[pin].number; 267 *num_pins = 1; 268 return 0; 269 } 270 271 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = { 272 .get_groups_count = pmic_gpio_get_groups_count, 273 .get_group_name = pmic_gpio_get_group_name, 274 .get_group_pins = pmic_gpio_get_group_pins, 275 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 276 .dt_free_map = pinctrl_utils_free_map, 277 }; 278 279 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev) 280 { 281 return ARRAY_SIZE(pmic_gpio_functions); 282 } 283 284 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev, 285 unsigned function) 286 { 287 return pmic_gpio_functions[function]; 288 } 289 290 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev, 291 unsigned function, 292 const char *const **groups, 293 unsigned *const num_qgroups) 294 { 295 *groups = pmic_gpio_groups; 296 *num_qgroups = pctldev->desc->npins; 297 return 0; 298 } 299 300 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function, 301 unsigned pin) 302 { 303 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 304 struct pmic_gpio_pad *pad; 305 unsigned int val; 306 int ret; 307 308 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) { 309 pr_err("function: %d is not defined\n", function); 310 return -EINVAL; 311 } 312 313 pad = pctldev->desc->pins[pin].drv_data; 314 /* 315 * Non-LV/MV subtypes only support 2 special functions, 316 * offsetting the dtestx function values by 2 317 */ 318 if (!pad->lv_mv_type) { 319 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 || 320 function == PMIC_GPIO_FUNC_INDEX_FUNC4) { 321 pr_err("LV/MV subtype doesn't have func3/func4\n"); 322 return -EINVAL; 323 } 324 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1) 325 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 - 326 PMIC_GPIO_FUNC_INDEX_FUNC3); 327 } 328 329 pad->function = function; 330 331 if (pad->analog_pass) 332 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; 333 else if (pad->output_enabled && pad->input_enabled) 334 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; 335 else if (pad->output_enabled) 336 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; 337 else 338 val = PMIC_GPIO_MODE_DIGITAL_INPUT; 339 340 if (pad->lv_mv_type) { 341 ret = pmic_gpio_write(state, pad, 342 PMIC_GPIO_REG_MODE_CTL, val); 343 if (ret < 0) 344 return ret; 345 346 val = pad->atest - 1; 347 ret = pmic_gpio_write(state, pad, 348 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); 349 if (ret < 0) 350 return ret; 351 352 val = pad->out_value 353 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; 354 val |= pad->function 355 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; 356 ret = pmic_gpio_write(state, pad, 357 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); 358 if (ret < 0) 359 return ret; 360 } else { 361 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; 362 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 363 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 364 365 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); 366 if (ret < 0) 367 return ret; 368 } 369 370 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; 371 372 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); 373 } 374 375 static const struct pinmux_ops pmic_gpio_pinmux_ops = { 376 .get_functions_count = pmic_gpio_get_functions_count, 377 .get_function_name = pmic_gpio_get_function_name, 378 .get_function_groups = pmic_gpio_get_function_groups, 379 .set_mux = pmic_gpio_set_mux, 380 }; 381 382 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev, 383 unsigned int pin, unsigned long *config) 384 { 385 unsigned param = pinconf_to_config_param(*config); 386 struct pmic_gpio_pad *pad; 387 unsigned arg; 388 389 pad = pctldev->desc->pins[pin].drv_data; 390 391 switch (param) { 392 case PIN_CONFIG_DRIVE_PUSH_PULL: 393 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS) 394 return -EINVAL; 395 arg = 1; 396 break; 397 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 398 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS) 399 return -EINVAL; 400 arg = 1; 401 break; 402 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 403 if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS) 404 return -EINVAL; 405 arg = 1; 406 break; 407 case PIN_CONFIG_BIAS_PULL_DOWN: 408 if (pad->pullup != PMIC_GPIO_PULL_DOWN) 409 return -EINVAL; 410 arg = 1; 411 break; 412 case PIN_CONFIG_BIAS_DISABLE: 413 if (pad->pullup != PMIC_GPIO_PULL_DISABLE) 414 return -EINVAL; 415 arg = 1; 416 break; 417 case PIN_CONFIG_BIAS_PULL_UP: 418 if (pad->pullup != PMIC_GPIO_PULL_UP_30) 419 return -EINVAL; 420 arg = 1; 421 break; 422 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 423 if (pad->is_enabled) 424 return -EINVAL; 425 arg = 1; 426 break; 427 case PIN_CONFIG_POWER_SOURCE: 428 arg = pad->power_source; 429 break; 430 case PIN_CONFIG_INPUT_ENABLE: 431 if (!pad->input_enabled) 432 return -EINVAL; 433 arg = 1; 434 break; 435 case PIN_CONFIG_OUTPUT: 436 arg = pad->out_value; 437 break; 438 case PMIC_GPIO_CONF_PULL_UP: 439 arg = pad->pullup; 440 break; 441 case PMIC_GPIO_CONF_STRENGTH: 442 arg = pad->strength; 443 break; 444 case PMIC_GPIO_CONF_ATEST: 445 arg = pad->atest; 446 break; 447 case PMIC_GPIO_CONF_ANALOG_PASS: 448 arg = pad->analog_pass; 449 break; 450 case PMIC_GPIO_CONF_DTEST_BUFFER: 451 arg = pad->dtest_buffer; 452 break; 453 default: 454 return -EINVAL; 455 } 456 457 *config = pinconf_to_config_packed(param, arg); 458 return 0; 459 } 460 461 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 462 unsigned long *configs, unsigned nconfs) 463 { 464 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 465 struct pmic_gpio_pad *pad; 466 unsigned param, arg; 467 unsigned int val; 468 int i, ret; 469 470 pad = pctldev->desc->pins[pin].drv_data; 471 472 pad->is_enabled = true; 473 for (i = 0; i < nconfs; i++) { 474 param = pinconf_to_config_param(configs[i]); 475 arg = pinconf_to_config_argument(configs[i]); 476 477 switch (param) { 478 case PIN_CONFIG_DRIVE_PUSH_PULL: 479 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS; 480 break; 481 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 482 if (!pad->have_buffer) 483 return -EINVAL; 484 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; 485 break; 486 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 487 if (!pad->have_buffer) 488 return -EINVAL; 489 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; 490 break; 491 case PIN_CONFIG_BIAS_DISABLE: 492 pad->pullup = PMIC_GPIO_PULL_DISABLE; 493 break; 494 case PIN_CONFIG_BIAS_PULL_UP: 495 pad->pullup = PMIC_GPIO_PULL_UP_30; 496 break; 497 case PIN_CONFIG_BIAS_PULL_DOWN: 498 if (arg) 499 pad->pullup = PMIC_GPIO_PULL_DOWN; 500 else 501 pad->pullup = PMIC_GPIO_PULL_DISABLE; 502 break; 503 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 504 pad->is_enabled = false; 505 break; 506 case PIN_CONFIG_POWER_SOURCE: 507 if (arg >= pad->num_sources) 508 return -EINVAL; 509 pad->power_source = arg; 510 break; 511 case PIN_CONFIG_INPUT_ENABLE: 512 pad->input_enabled = arg ? true : false; 513 break; 514 case PIN_CONFIG_OUTPUT: 515 pad->output_enabled = true; 516 pad->out_value = arg; 517 break; 518 case PMIC_GPIO_CONF_PULL_UP: 519 if (arg > PMIC_GPIO_PULL_UP_1P5_30) 520 return -EINVAL; 521 pad->pullup = arg; 522 break; 523 case PMIC_GPIO_CONF_STRENGTH: 524 if (arg > PMIC_GPIO_STRENGTH_LOW) 525 return -EINVAL; 526 pad->strength = arg; 527 break; 528 case PMIC_GPIO_CONF_ATEST: 529 if (!pad->lv_mv_type || arg > 4) 530 return -EINVAL; 531 pad->atest = arg; 532 break; 533 case PMIC_GPIO_CONF_ANALOG_PASS: 534 if (!pad->lv_mv_type) 535 return -EINVAL; 536 pad->analog_pass = true; 537 break; 538 case PMIC_GPIO_CONF_DTEST_BUFFER: 539 if (arg > 4) 540 return -EINVAL; 541 pad->dtest_buffer = arg; 542 break; 543 default: 544 return -EINVAL; 545 } 546 } 547 548 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT; 549 550 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val); 551 if (ret < 0) 552 return ret; 553 554 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT; 555 556 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val); 557 if (ret < 0) 558 return ret; 559 560 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT; 561 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; 562 563 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val); 564 if (ret < 0) 565 return ret; 566 567 if (pad->dtest_buffer == 0) { 568 val = 0; 569 } else { 570 if (pad->lv_mv_type) { 571 val = pad->dtest_buffer - 1; 572 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN; 573 } else { 574 val = BIT(pad->dtest_buffer - 1); 575 } 576 } 577 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val); 578 if (ret < 0) 579 return ret; 580 581 if (pad->analog_pass) 582 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; 583 else if (pad->output_enabled && pad->input_enabled) 584 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; 585 else if (pad->output_enabled) 586 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; 587 else 588 val = PMIC_GPIO_MODE_DIGITAL_INPUT; 589 590 if (pad->lv_mv_type) { 591 ret = pmic_gpio_write(state, pad, 592 PMIC_GPIO_REG_MODE_CTL, val); 593 if (ret < 0) 594 return ret; 595 596 val = pad->atest - 1; 597 ret = pmic_gpio_write(state, pad, 598 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); 599 if (ret < 0) 600 return ret; 601 602 val = pad->out_value 603 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; 604 val |= pad->function 605 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; 606 ret = pmic_gpio_write(state, pad, 607 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); 608 if (ret < 0) 609 return ret; 610 } else { 611 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; 612 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 613 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 614 615 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); 616 if (ret < 0) 617 return ret; 618 } 619 620 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; 621 622 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); 623 624 return ret; 625 } 626 627 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, 628 struct seq_file *s, unsigned pin) 629 { 630 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 631 struct pmic_gpio_pad *pad; 632 int ret, val, function; 633 634 static const char *const biases[] = { 635 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", 636 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" 637 }; 638 static const char *const buffer_types[] = { 639 "push-pull", "open-drain", "open-source" 640 }; 641 static const char *const strengths[] = { 642 "no", "high", "medium", "low" 643 }; 644 645 pad = pctldev->desc->pins[pin].drv_data; 646 647 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET); 648 649 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL); 650 651 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) { 652 seq_puts(s, " ---"); 653 } else { 654 if (pad->input_enabled) { 655 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); 656 if (ret < 0) 657 return; 658 659 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; 660 pad->out_value = ret; 661 } 662 /* 663 * For the non-LV/MV subtypes only 2 special functions are 664 * available, offsetting the dtest function values by 2. 665 */ 666 function = pad->function; 667 if (!pad->lv_mv_type && 668 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3) 669 function += PMIC_GPIO_FUNC_INDEX_DTEST1 - 670 PMIC_GPIO_FUNC_INDEX_FUNC3; 671 672 if (pad->analog_pass) 673 seq_puts(s, " analog-pass"); 674 else 675 seq_printf(s, " %-4s", 676 pad->output_enabled ? "out" : "in"); 677 seq_printf(s, " %-7s", pmic_gpio_functions[function]); 678 seq_printf(s, " vin-%d", pad->power_source); 679 seq_printf(s, " %-27s", biases[pad->pullup]); 680 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]); 681 seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); 682 seq_printf(s, " %-7s", strengths[pad->strength]); 683 seq_printf(s, " atest-%d", pad->atest); 684 seq_printf(s, " dtest-%d", pad->dtest_buffer); 685 } 686 } 687 688 static const struct pinconf_ops pmic_gpio_pinconf_ops = { 689 .is_generic = true, 690 .pin_config_group_get = pmic_gpio_config_get, 691 .pin_config_group_set = pmic_gpio_config_set, 692 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show, 693 }; 694 695 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 696 { 697 struct pmic_gpio_state *state = gpiochip_get_data(chip); 698 unsigned long config; 699 700 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); 701 702 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); 703 } 704 705 static int pmic_gpio_direction_output(struct gpio_chip *chip, 706 unsigned pin, int val) 707 { 708 struct pmic_gpio_state *state = gpiochip_get_data(chip); 709 unsigned long config; 710 711 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); 712 713 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); 714 } 715 716 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin) 717 { 718 struct pmic_gpio_state *state = gpiochip_get_data(chip); 719 struct pmic_gpio_pad *pad; 720 int ret; 721 722 pad = state->ctrl->desc->pins[pin].drv_data; 723 724 if (!pad->is_enabled) 725 return -EINVAL; 726 727 if (pad->input_enabled) { 728 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); 729 if (ret < 0) 730 return ret; 731 732 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; 733 } 734 735 return !!pad->out_value; 736 } 737 738 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 739 { 740 struct pmic_gpio_state *state = gpiochip_get_data(chip); 741 unsigned long config; 742 743 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); 744 745 pmic_gpio_config_set(state->ctrl, pin, &config, 1); 746 } 747 748 static int pmic_gpio_of_xlate(struct gpio_chip *chip, 749 const struct of_phandle_args *gpio_desc, 750 u32 *flags) 751 { 752 if (chip->of_gpio_n_cells < 2) 753 return -EINVAL; 754 755 if (flags) 756 *flags = gpio_desc->args[1]; 757 758 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET; 759 } 760 761 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 762 { 763 struct pmic_gpio_state *state = gpiochip_get_data(chip); 764 struct pmic_gpio_pad *pad; 765 766 pad = state->ctrl->desc->pins[pin].drv_data; 767 768 return pad->irq; 769 } 770 771 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 772 { 773 struct pmic_gpio_state *state = gpiochip_get_data(chip); 774 unsigned i; 775 776 for (i = 0; i < chip->ngpio; i++) { 777 pmic_gpio_config_dbg_show(state->ctrl, s, i); 778 seq_puts(s, "\n"); 779 } 780 } 781 782 static const struct gpio_chip pmic_gpio_gpio_template = { 783 .direction_input = pmic_gpio_direction_input, 784 .direction_output = pmic_gpio_direction_output, 785 .get = pmic_gpio_get, 786 .set = pmic_gpio_set, 787 .request = gpiochip_generic_request, 788 .free = gpiochip_generic_free, 789 .of_xlate = pmic_gpio_of_xlate, 790 .to_irq = pmic_gpio_to_irq, 791 .dbg_show = pmic_gpio_dbg_show, 792 }; 793 794 static int pmic_gpio_populate(struct pmic_gpio_state *state, 795 struct pmic_gpio_pad *pad) 796 { 797 int type, subtype, val, dir; 798 799 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE); 800 if (type < 0) 801 return type; 802 803 if (type != PMIC_GPIO_TYPE) { 804 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", 805 type, pad->base); 806 return -ENODEV; 807 } 808 809 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE); 810 if (subtype < 0) 811 return subtype; 812 813 switch (subtype) { 814 case PMIC_GPIO_SUBTYPE_GPIO_4CH: 815 pad->have_buffer = true; 816 case PMIC_GPIO_SUBTYPE_GPIOC_4CH: 817 pad->num_sources = 4; 818 break; 819 case PMIC_GPIO_SUBTYPE_GPIO_8CH: 820 pad->have_buffer = true; 821 case PMIC_GPIO_SUBTYPE_GPIOC_8CH: 822 pad->num_sources = 8; 823 break; 824 case PMIC_GPIO_SUBTYPE_GPIO_LV: 825 pad->num_sources = 1; 826 pad->have_buffer = true; 827 pad->lv_mv_type = true; 828 break; 829 case PMIC_GPIO_SUBTYPE_GPIO_MV: 830 pad->num_sources = 2; 831 pad->have_buffer = true; 832 pad->lv_mv_type = true; 833 break; 834 default: 835 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype); 836 return -ENODEV; 837 } 838 839 if (pad->lv_mv_type) { 840 val = pmic_gpio_read(state, pad, 841 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL); 842 if (val < 0) 843 return val; 844 845 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT); 846 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; 847 848 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); 849 if (val < 0) 850 return val; 851 852 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK; 853 } else { 854 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); 855 if (val < 0) 856 return val; 857 858 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 859 860 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; 861 dir &= PMIC_GPIO_REG_MODE_DIR_MASK; 862 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 863 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK; 864 } 865 866 switch (dir) { 867 case PMIC_GPIO_MODE_DIGITAL_INPUT: 868 pad->input_enabled = true; 869 pad->output_enabled = false; 870 break; 871 case PMIC_GPIO_MODE_DIGITAL_OUTPUT: 872 pad->input_enabled = false; 873 pad->output_enabled = true; 874 break; 875 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT: 876 pad->input_enabled = true; 877 pad->output_enabled = true; 878 break; 879 case PMIC_GPIO_MODE_ANALOG_PASS_THRU: 880 if (!pad->lv_mv_type) 881 return -ENODEV; 882 pad->analog_pass = true; 883 break; 884 default: 885 dev_err(state->dev, "unknown GPIO direction\n"); 886 return -ENODEV; 887 } 888 889 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL); 890 if (val < 0) 891 return val; 892 893 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT; 894 pad->power_source &= PMIC_GPIO_REG_VIN_MASK; 895 896 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL); 897 if (val < 0) 898 return val; 899 900 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT; 901 pad->pullup &= PMIC_GPIO_REG_PULL_MASK; 902 903 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL); 904 if (val < 0) 905 return val; 906 907 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN)) 908 pad->dtest_buffer = 909 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1; 910 else if (!pad->lv_mv_type) 911 pad->dtest_buffer = ffs(val); 912 else 913 pad->dtest_buffer = 0; 914 915 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL); 916 if (val < 0) 917 return val; 918 919 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; 920 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK; 921 922 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT; 923 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK; 924 925 if (pad->lv_mv_type) { 926 val = pmic_gpio_read(state, pad, 927 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL); 928 if (val < 0) 929 return val; 930 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1; 931 } 932 933 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ 934 pad->is_enabled = true; 935 return 0; 936 } 937 938 static int pmic_gpio_probe(struct platform_device *pdev) 939 { 940 struct device *dev = &pdev->dev; 941 struct pinctrl_pin_desc *pindesc; 942 struct pinctrl_desc *pctrldesc; 943 struct pmic_gpio_pad *pad, *pads; 944 struct pmic_gpio_state *state; 945 int ret, npins, i; 946 u32 reg; 947 948 ret = of_property_read_u32(dev->of_node, "reg", ®); 949 if (ret < 0) { 950 dev_err(dev, "missing base address"); 951 return ret; 952 } 953 954 npins = platform_irq_count(pdev); 955 if (!npins) 956 return -EINVAL; 957 if (npins < 0) 958 return npins; 959 960 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups)); 961 962 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); 963 if (!state) 964 return -ENOMEM; 965 966 platform_set_drvdata(pdev, state); 967 968 state->dev = &pdev->dev; 969 state->map = dev_get_regmap(dev->parent, NULL); 970 971 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); 972 if (!pindesc) 973 return -ENOMEM; 974 975 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); 976 if (!pads) 977 return -ENOMEM; 978 979 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); 980 if (!pctrldesc) 981 return -ENOMEM; 982 983 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops; 984 pctrldesc->pmxops = &pmic_gpio_pinmux_ops; 985 pctrldesc->confops = &pmic_gpio_pinconf_ops; 986 pctrldesc->owner = THIS_MODULE; 987 pctrldesc->name = dev_name(dev); 988 pctrldesc->pins = pindesc; 989 pctrldesc->npins = npins; 990 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings); 991 pctrldesc->custom_params = pmic_gpio_bindings; 992 #ifdef CONFIG_DEBUG_FS 993 pctrldesc->custom_conf_items = pmic_conf_items; 994 #endif 995 996 for (i = 0; i < npins; i++, pindesc++) { 997 pad = &pads[i]; 998 pindesc->drv_data = pad; 999 pindesc->number = i; 1000 pindesc->name = pmic_gpio_groups[i]; 1001 1002 pad->irq = platform_get_irq(pdev, i); 1003 if (pad->irq < 0) 1004 return pad->irq; 1005 1006 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE; 1007 1008 ret = pmic_gpio_populate(state, pad); 1009 if (ret < 0) 1010 return ret; 1011 } 1012 1013 state->chip = pmic_gpio_gpio_template; 1014 state->chip.parent = dev; 1015 state->chip.base = -1; 1016 state->chip.ngpio = npins; 1017 state->chip.label = dev_name(dev); 1018 state->chip.of_gpio_n_cells = 2; 1019 state->chip.can_sleep = false; 1020 1021 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state); 1022 if (IS_ERR(state->ctrl)) 1023 return PTR_ERR(state->ctrl); 1024 1025 ret = gpiochip_add_data(&state->chip, state); 1026 if (ret) { 1027 dev_err(state->dev, "can't add gpio chip\n"); 1028 return ret; 1029 } 1030 1031 /* 1032 * For DeviceTree-supported systems, the gpio core checks the 1033 * pinctrl's device node for the "gpio-ranges" property. 1034 * If it is present, it takes care of adding the pin ranges 1035 * for the driver. In this case the driver can skip ahead. 1036 * 1037 * In order to remain compatible with older, existing DeviceTree 1038 * files which don't set the "gpio-ranges" property or systems that 1039 * utilize ACPI the driver has to call gpiochip_add_pin_range(). 1040 */ 1041 if (!of_property_read_bool(dev->of_node, "gpio-ranges")) { 1042 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, 1043 npins); 1044 if (ret) { 1045 dev_err(dev, "failed to add pin range\n"); 1046 goto err_range; 1047 } 1048 } 1049 1050 return 0; 1051 1052 err_range: 1053 gpiochip_remove(&state->chip); 1054 return ret; 1055 } 1056 1057 static int pmic_gpio_remove(struct platform_device *pdev) 1058 { 1059 struct pmic_gpio_state *state = platform_get_drvdata(pdev); 1060 1061 gpiochip_remove(&state->chip); 1062 return 0; 1063 } 1064 1065 static const struct of_device_id pmic_gpio_of_match[] = { 1066 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */ 1067 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */ 1068 { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ 1069 { .compatible = "qcom,pmi8994-gpio" }, /* 10 GPIO's */ 1070 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ 1071 { .compatible = "qcom,pms405-gpio" }, /* 12 GPIO's, holes on 1 9 10 */ 1072 { .compatible = "qcom,spmi-gpio" }, /* Generic */ 1073 { }, 1074 }; 1075 1076 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match); 1077 1078 static struct platform_driver pmic_gpio_driver = { 1079 .driver = { 1080 .name = "qcom-spmi-gpio", 1081 .of_match_table = pmic_gpio_of_match, 1082 }, 1083 .probe = pmic_gpio_probe, 1084 .remove = pmic_gpio_remove, 1085 }; 1086 1087 module_platform_driver(pmic_gpio_driver); 1088 1089 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); 1090 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver"); 1091 MODULE_ALIAS("platform:qcom-spmi-gpio"); 1092 MODULE_LICENSE("GPL v2"); 1093