1 /* 2 * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 and 6 * only version 2 as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #include <linux/gpio.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_irq.h> 18 #include <linux/pinctrl/pinconf-generic.h> 19 #include <linux/pinctrl/pinconf.h> 20 #include <linux/pinctrl/pinmux.h> 21 #include <linux/platform_device.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 #include <linux/types.h> 25 26 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h> 27 28 #include "../core.h" 29 #include "../pinctrl-utils.h" 30 31 #define PMIC_GPIO_ADDRESS_RANGE 0x100 32 33 /* type and subtype registers base address offsets */ 34 #define PMIC_GPIO_REG_TYPE 0x4 35 #define PMIC_GPIO_REG_SUBTYPE 0x5 36 37 /* GPIO peripheral type and subtype out_values */ 38 #define PMIC_GPIO_TYPE 0x10 39 #define PMIC_GPIO_SUBTYPE_GPIO_4CH 0x1 40 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH 0x5 41 #define PMIC_GPIO_SUBTYPE_GPIO_8CH 0x9 42 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH 0xd 43 #define PMIC_GPIO_SUBTYPE_GPIO_LV 0x10 44 #define PMIC_GPIO_SUBTYPE_GPIO_MV 0x11 45 46 #define PMIC_MPP_REG_RT_STS 0x10 47 #define PMIC_MPP_REG_RT_STS_VAL_MASK 0x1 48 49 /* control register base address offsets */ 50 #define PMIC_GPIO_REG_MODE_CTL 0x40 51 #define PMIC_GPIO_REG_DIG_VIN_CTL 0x41 52 #define PMIC_GPIO_REG_DIG_PULL_CTL 0x42 53 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL 0x44 54 #define PMIC_GPIO_REG_DIG_IN_CTL 0x43 55 #define PMIC_GPIO_REG_DIG_OUT_CTL 0x45 56 #define PMIC_GPIO_REG_EN_CTL 0x46 57 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL 0x4A 58 59 /* PMIC_GPIO_REG_MODE_CTL */ 60 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT 0x1 61 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT 1 62 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK 0x7 63 #define PMIC_GPIO_REG_MODE_DIR_SHIFT 4 64 #define PMIC_GPIO_REG_MODE_DIR_MASK 0x7 65 66 #define PMIC_GPIO_MODE_DIGITAL_INPUT 0 67 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT 1 68 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT 2 69 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU 3 70 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK 0x3 71 72 /* PMIC_GPIO_REG_DIG_VIN_CTL */ 73 #define PMIC_GPIO_REG_VIN_SHIFT 0 74 #define PMIC_GPIO_REG_VIN_MASK 0x7 75 76 /* PMIC_GPIO_REG_DIG_PULL_CTL */ 77 #define PMIC_GPIO_REG_PULL_SHIFT 0 78 #define PMIC_GPIO_REG_PULL_MASK 0x7 79 80 #define PMIC_GPIO_PULL_DOWN 4 81 #define PMIC_GPIO_PULL_DISABLE 5 82 83 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */ 84 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT 0x80 85 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT 7 86 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK 0xF 87 88 /* PMIC_GPIO_REG_DIG_IN_CTL */ 89 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN 0x80 90 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK 0x7 91 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK 0xf 92 93 /* PMIC_GPIO_REG_DIG_OUT_CTL */ 94 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT 0 95 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK 0x3 96 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT 4 97 #define PMIC_GPIO_REG_OUT_TYPE_MASK 0x3 98 99 /* 100 * Output type - indicates pin should be configured as push-pull, 101 * open drain or open source. 102 */ 103 #define PMIC_GPIO_OUT_BUF_CMOS 0 104 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS 1 105 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS 2 106 107 /* PMIC_GPIO_REG_EN_CTL */ 108 #define PMIC_GPIO_REG_MASTER_EN_SHIFT 7 109 110 #define PMIC_GPIO_PHYSICAL_OFFSET 1 111 112 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */ 113 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK 0x3 114 115 /* Qualcomm specific pin configurations */ 116 #define PMIC_GPIO_CONF_PULL_UP (PIN_CONFIG_END + 1) 117 #define PMIC_GPIO_CONF_STRENGTH (PIN_CONFIG_END + 2) 118 #define PMIC_GPIO_CONF_ATEST (PIN_CONFIG_END + 3) 119 #define PMIC_GPIO_CONF_ANALOG_PASS (PIN_CONFIG_END + 4) 120 #define PMIC_GPIO_CONF_DTEST_BUFFER (PIN_CONFIG_END + 5) 121 122 /* The index of each function in pmic_gpio_functions[] array */ 123 enum pmic_gpio_func_index { 124 PMIC_GPIO_FUNC_INDEX_NORMAL, 125 PMIC_GPIO_FUNC_INDEX_PAIRED, 126 PMIC_GPIO_FUNC_INDEX_FUNC1, 127 PMIC_GPIO_FUNC_INDEX_FUNC2, 128 PMIC_GPIO_FUNC_INDEX_FUNC3, 129 PMIC_GPIO_FUNC_INDEX_FUNC4, 130 PMIC_GPIO_FUNC_INDEX_DTEST1, 131 PMIC_GPIO_FUNC_INDEX_DTEST2, 132 PMIC_GPIO_FUNC_INDEX_DTEST3, 133 PMIC_GPIO_FUNC_INDEX_DTEST4, 134 }; 135 136 /** 137 * struct pmic_gpio_pad - keep current GPIO settings 138 * @base: Address base in SPMI device. 139 * @irq: IRQ number which this GPIO generate. 140 * @is_enabled: Set to false when GPIO should be put in high Z state. 141 * @out_value: Cached pin output value 142 * @have_buffer: Set to true if GPIO output could be configured in push-pull, 143 * open-drain or open-source mode. 144 * @output_enabled: Set to true if GPIO output logic is enabled. 145 * @input_enabled: Set to true if GPIO input buffer logic is enabled. 146 * @analog_pass: Set to true if GPIO is in analog-pass-through mode. 147 * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11). 148 * @num_sources: Number of power-sources supported by this GPIO. 149 * @power_source: Current power-source used. 150 * @buffer_type: Push-pull, open-drain or open-source. 151 * @pullup: Constant current which flow trough GPIO output buffer. 152 * @strength: No, Low, Medium, High 153 * @function: See pmic_gpio_functions[] 154 * @atest: the ATEST selection for GPIO analog-pass-through mode 155 * @dtest_buffer: the DTEST buffer selection for digital input mode. 156 */ 157 struct pmic_gpio_pad { 158 u16 base; 159 int irq; 160 bool is_enabled; 161 bool out_value; 162 bool have_buffer; 163 bool output_enabled; 164 bool input_enabled; 165 bool analog_pass; 166 bool lv_mv_type; 167 unsigned int num_sources; 168 unsigned int power_source; 169 unsigned int buffer_type; 170 unsigned int pullup; 171 unsigned int strength; 172 unsigned int function; 173 unsigned int atest; 174 unsigned int dtest_buffer; 175 }; 176 177 struct pmic_gpio_state { 178 struct device *dev; 179 struct regmap *map; 180 struct pinctrl_dev *ctrl; 181 struct gpio_chip chip; 182 }; 183 184 static const struct pinconf_generic_params pmic_gpio_bindings[] = { 185 {"qcom,pull-up-strength", PMIC_GPIO_CONF_PULL_UP, 0}, 186 {"qcom,drive-strength", PMIC_GPIO_CONF_STRENGTH, 0}, 187 {"qcom,atest", PMIC_GPIO_CONF_ATEST, 0}, 188 {"qcom,analog-pass", PMIC_GPIO_CONF_ANALOG_PASS, 0}, 189 {"qcom,dtest-buffer", PMIC_GPIO_CONF_DTEST_BUFFER, 0}, 190 }; 191 192 #ifdef CONFIG_DEBUG_FS 193 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = { 194 PCONFDUMP(PMIC_GPIO_CONF_PULL_UP, "pull up strength", NULL, true), 195 PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true), 196 PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true), 197 PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true), 198 PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true), 199 }; 200 #endif 201 202 static const char *const pmic_gpio_groups[] = { 203 "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", 204 "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15", 205 "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22", 206 "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29", 207 "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36", 208 }; 209 210 static const char *const pmic_gpio_functions[] = { 211 [PMIC_GPIO_FUNC_INDEX_NORMAL] = PMIC_GPIO_FUNC_NORMAL, 212 [PMIC_GPIO_FUNC_INDEX_PAIRED] = PMIC_GPIO_FUNC_PAIRED, 213 [PMIC_GPIO_FUNC_INDEX_FUNC1] = PMIC_GPIO_FUNC_FUNC1, 214 [PMIC_GPIO_FUNC_INDEX_FUNC2] = PMIC_GPIO_FUNC_FUNC2, 215 [PMIC_GPIO_FUNC_INDEX_FUNC3] = PMIC_GPIO_FUNC_FUNC3, 216 [PMIC_GPIO_FUNC_INDEX_FUNC4] = PMIC_GPIO_FUNC_FUNC4, 217 [PMIC_GPIO_FUNC_INDEX_DTEST1] = PMIC_GPIO_FUNC_DTEST1, 218 [PMIC_GPIO_FUNC_INDEX_DTEST2] = PMIC_GPIO_FUNC_DTEST2, 219 [PMIC_GPIO_FUNC_INDEX_DTEST3] = PMIC_GPIO_FUNC_DTEST3, 220 [PMIC_GPIO_FUNC_INDEX_DTEST4] = PMIC_GPIO_FUNC_DTEST4, 221 }; 222 223 static int pmic_gpio_read(struct pmic_gpio_state *state, 224 struct pmic_gpio_pad *pad, unsigned int addr) 225 { 226 unsigned int val; 227 int ret; 228 229 ret = regmap_read(state->map, pad->base + addr, &val); 230 if (ret < 0) 231 dev_err(state->dev, "read 0x%x failed\n", addr); 232 else 233 ret = val; 234 235 return ret; 236 } 237 238 static int pmic_gpio_write(struct pmic_gpio_state *state, 239 struct pmic_gpio_pad *pad, unsigned int addr, 240 unsigned int val) 241 { 242 int ret; 243 244 ret = regmap_write(state->map, pad->base + addr, val); 245 if (ret < 0) 246 dev_err(state->dev, "write 0x%x failed\n", addr); 247 248 return ret; 249 } 250 251 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev) 252 { 253 /* Every PIN is a group */ 254 return pctldev->desc->npins; 255 } 256 257 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev, 258 unsigned pin) 259 { 260 return pctldev->desc->pins[pin].name; 261 } 262 263 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin, 264 const unsigned **pins, unsigned *num_pins) 265 { 266 *pins = &pctldev->desc->pins[pin].number; 267 *num_pins = 1; 268 return 0; 269 } 270 271 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = { 272 .get_groups_count = pmic_gpio_get_groups_count, 273 .get_group_name = pmic_gpio_get_group_name, 274 .get_group_pins = pmic_gpio_get_group_pins, 275 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 276 .dt_free_map = pinctrl_utils_free_map, 277 }; 278 279 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev) 280 { 281 return ARRAY_SIZE(pmic_gpio_functions); 282 } 283 284 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev, 285 unsigned function) 286 { 287 return pmic_gpio_functions[function]; 288 } 289 290 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev, 291 unsigned function, 292 const char *const **groups, 293 unsigned *const num_qgroups) 294 { 295 *groups = pmic_gpio_groups; 296 *num_qgroups = pctldev->desc->npins; 297 return 0; 298 } 299 300 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function, 301 unsigned pin) 302 { 303 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 304 struct pmic_gpio_pad *pad; 305 unsigned int val; 306 int ret; 307 308 if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) { 309 pr_err("function: %d is not defined\n", function); 310 return -EINVAL; 311 } 312 313 pad = pctldev->desc->pins[pin].drv_data; 314 /* 315 * Non-LV/MV subtypes only support 2 special functions, 316 * offsetting the dtestx function values by 2 317 */ 318 if (!pad->lv_mv_type) { 319 if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 || 320 function == PMIC_GPIO_FUNC_INDEX_FUNC4) { 321 pr_err("LV/MV subtype doesn't have func3/func4\n"); 322 return -EINVAL; 323 } 324 if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1) 325 function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 - 326 PMIC_GPIO_FUNC_INDEX_FUNC3); 327 } 328 329 pad->function = function; 330 331 if (pad->analog_pass) 332 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; 333 else if (pad->output_enabled && pad->input_enabled) 334 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; 335 else if (pad->output_enabled) 336 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; 337 else 338 val = PMIC_GPIO_MODE_DIGITAL_INPUT; 339 340 if (pad->lv_mv_type) { 341 ret = pmic_gpio_write(state, pad, 342 PMIC_GPIO_REG_MODE_CTL, val); 343 if (ret < 0) 344 return ret; 345 346 val = pad->atest - 1; 347 ret = pmic_gpio_write(state, pad, 348 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); 349 if (ret < 0) 350 return ret; 351 352 val = pad->out_value 353 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; 354 val |= pad->function 355 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; 356 ret = pmic_gpio_write(state, pad, 357 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); 358 if (ret < 0) 359 return ret; 360 } else { 361 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; 362 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 363 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 364 365 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); 366 if (ret < 0) 367 return ret; 368 } 369 370 val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT; 371 372 return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val); 373 } 374 375 static const struct pinmux_ops pmic_gpio_pinmux_ops = { 376 .get_functions_count = pmic_gpio_get_functions_count, 377 .get_function_name = pmic_gpio_get_function_name, 378 .get_function_groups = pmic_gpio_get_function_groups, 379 .set_mux = pmic_gpio_set_mux, 380 }; 381 382 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev, 383 unsigned int pin, unsigned long *config) 384 { 385 unsigned param = pinconf_to_config_param(*config); 386 struct pmic_gpio_pad *pad; 387 unsigned arg; 388 389 pad = pctldev->desc->pins[pin].drv_data; 390 391 switch (param) { 392 case PIN_CONFIG_DRIVE_PUSH_PULL: 393 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_CMOS; 394 break; 395 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 396 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; 397 break; 398 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 399 arg = pad->buffer_type == PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; 400 break; 401 case PIN_CONFIG_BIAS_PULL_DOWN: 402 arg = pad->pullup == PMIC_GPIO_PULL_DOWN; 403 break; 404 case PIN_CONFIG_BIAS_DISABLE: 405 arg = pad->pullup = PMIC_GPIO_PULL_DISABLE; 406 break; 407 case PIN_CONFIG_BIAS_PULL_UP: 408 arg = pad->pullup == PMIC_GPIO_PULL_UP_30; 409 break; 410 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 411 arg = !pad->is_enabled; 412 break; 413 case PIN_CONFIG_POWER_SOURCE: 414 arg = pad->power_source; 415 break; 416 case PIN_CONFIG_INPUT_ENABLE: 417 arg = pad->input_enabled; 418 break; 419 case PIN_CONFIG_OUTPUT: 420 arg = pad->out_value; 421 break; 422 case PMIC_GPIO_CONF_PULL_UP: 423 arg = pad->pullup; 424 break; 425 case PMIC_GPIO_CONF_STRENGTH: 426 arg = pad->strength; 427 break; 428 case PMIC_GPIO_CONF_ATEST: 429 arg = pad->atest; 430 break; 431 case PMIC_GPIO_CONF_ANALOG_PASS: 432 arg = pad->analog_pass; 433 break; 434 case PMIC_GPIO_CONF_DTEST_BUFFER: 435 arg = pad->dtest_buffer; 436 break; 437 default: 438 return -EINVAL; 439 } 440 441 *config = pinconf_to_config_packed(param, arg); 442 return 0; 443 } 444 445 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 446 unsigned long *configs, unsigned nconfs) 447 { 448 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 449 struct pmic_gpio_pad *pad; 450 unsigned param, arg; 451 unsigned int val; 452 int i, ret; 453 454 pad = pctldev->desc->pins[pin].drv_data; 455 456 for (i = 0; i < nconfs; i++) { 457 param = pinconf_to_config_param(configs[i]); 458 arg = pinconf_to_config_argument(configs[i]); 459 460 switch (param) { 461 case PIN_CONFIG_DRIVE_PUSH_PULL: 462 pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS; 463 break; 464 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 465 if (!pad->have_buffer) 466 return -EINVAL; 467 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS; 468 break; 469 case PIN_CONFIG_DRIVE_OPEN_SOURCE: 470 if (!pad->have_buffer) 471 return -EINVAL; 472 pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS; 473 break; 474 case PIN_CONFIG_BIAS_DISABLE: 475 pad->pullup = PMIC_GPIO_PULL_DISABLE; 476 break; 477 case PIN_CONFIG_BIAS_PULL_UP: 478 pad->pullup = PMIC_GPIO_PULL_UP_30; 479 break; 480 case PIN_CONFIG_BIAS_PULL_DOWN: 481 if (arg) 482 pad->pullup = PMIC_GPIO_PULL_DOWN; 483 else 484 pad->pullup = PMIC_GPIO_PULL_DISABLE; 485 break; 486 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: 487 pad->is_enabled = false; 488 break; 489 case PIN_CONFIG_POWER_SOURCE: 490 if (arg >= pad->num_sources) 491 return -EINVAL; 492 pad->power_source = arg; 493 break; 494 case PIN_CONFIG_INPUT_ENABLE: 495 pad->input_enabled = arg ? true : false; 496 break; 497 case PIN_CONFIG_OUTPUT: 498 pad->output_enabled = true; 499 pad->out_value = arg; 500 break; 501 case PMIC_GPIO_CONF_PULL_UP: 502 if (arg > PMIC_GPIO_PULL_UP_1P5_30) 503 return -EINVAL; 504 pad->pullup = arg; 505 break; 506 case PMIC_GPIO_CONF_STRENGTH: 507 if (arg > PMIC_GPIO_STRENGTH_LOW) 508 return -EINVAL; 509 pad->strength = arg; 510 break; 511 case PMIC_GPIO_CONF_ATEST: 512 if (!pad->lv_mv_type || arg > 4) 513 return -EINVAL; 514 pad->atest = arg; 515 break; 516 case PMIC_GPIO_CONF_ANALOG_PASS: 517 if (!pad->lv_mv_type) 518 return -EINVAL; 519 pad->analog_pass = true; 520 break; 521 case PMIC_GPIO_CONF_DTEST_BUFFER: 522 if (arg > 4) 523 return -EINVAL; 524 pad->dtest_buffer = arg; 525 break; 526 default: 527 return -EINVAL; 528 } 529 } 530 531 val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT; 532 533 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val); 534 if (ret < 0) 535 return ret; 536 537 val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT; 538 539 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val); 540 if (ret < 0) 541 return ret; 542 543 val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT; 544 val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; 545 546 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val); 547 if (ret < 0) 548 return ret; 549 550 if (pad->dtest_buffer == 0) { 551 val = 0; 552 } else { 553 if (pad->lv_mv_type) { 554 val = pad->dtest_buffer - 1; 555 val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN; 556 } else { 557 val = BIT(pad->dtest_buffer - 1); 558 } 559 } 560 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val); 561 if (ret < 0) 562 return ret; 563 564 if (pad->analog_pass) 565 val = PMIC_GPIO_MODE_ANALOG_PASS_THRU; 566 else if (pad->output_enabled && pad->input_enabled) 567 val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT; 568 else if (pad->output_enabled) 569 val = PMIC_GPIO_MODE_DIGITAL_OUTPUT; 570 else 571 val = PMIC_GPIO_MODE_DIGITAL_INPUT; 572 573 if (pad->lv_mv_type) { 574 ret = pmic_gpio_write(state, pad, 575 PMIC_GPIO_REG_MODE_CTL, val); 576 if (ret < 0) 577 return ret; 578 579 val = pad->atest - 1; 580 ret = pmic_gpio_write(state, pad, 581 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val); 582 if (ret < 0) 583 return ret; 584 585 val = pad->out_value 586 << PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT; 587 val |= pad->function 588 & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; 589 ret = pmic_gpio_write(state, pad, 590 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val); 591 if (ret < 0) 592 return ret; 593 } else { 594 val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT; 595 val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 596 val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 597 598 ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val); 599 if (ret < 0) 600 return ret; 601 } 602 603 return ret; 604 } 605 606 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev, 607 struct seq_file *s, unsigned pin) 608 { 609 struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev); 610 struct pmic_gpio_pad *pad; 611 int ret, val, function; 612 613 static const char *const biases[] = { 614 "pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA", 615 "pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull" 616 }; 617 static const char *const buffer_types[] = { 618 "push-pull", "open-drain", "open-source" 619 }; 620 static const char *const strengths[] = { 621 "no", "high", "medium", "low" 622 }; 623 624 pad = pctldev->desc->pins[pin].drv_data; 625 626 seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET); 627 628 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL); 629 630 if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) { 631 seq_puts(s, " ---"); 632 } else { 633 if (pad->input_enabled) { 634 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); 635 if (ret < 0) 636 return; 637 638 ret &= PMIC_MPP_REG_RT_STS_VAL_MASK; 639 pad->out_value = ret; 640 } 641 /* 642 * For the non-LV/MV subtypes only 2 special functions are 643 * available, offsetting the dtest function values by 2. 644 */ 645 function = pad->function; 646 if (!pad->lv_mv_type && 647 pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3) 648 function += PMIC_GPIO_FUNC_INDEX_DTEST1 - 649 PMIC_GPIO_FUNC_INDEX_FUNC3; 650 651 if (pad->analog_pass) 652 seq_puts(s, " analog-pass"); 653 else 654 seq_printf(s, " %-4s", 655 pad->output_enabled ? "out" : "in"); 656 seq_printf(s, " %-7s", pmic_gpio_functions[function]); 657 seq_printf(s, " vin-%d", pad->power_source); 658 seq_printf(s, " %-27s", biases[pad->pullup]); 659 seq_printf(s, " %-10s", buffer_types[pad->buffer_type]); 660 seq_printf(s, " %-4s", pad->out_value ? "high" : "low"); 661 seq_printf(s, " %-7s", strengths[pad->strength]); 662 seq_printf(s, " atest-%d", pad->atest); 663 seq_printf(s, " dtest-%d", pad->dtest_buffer); 664 } 665 } 666 667 static const struct pinconf_ops pmic_gpio_pinconf_ops = { 668 .is_generic = true, 669 .pin_config_group_get = pmic_gpio_config_get, 670 .pin_config_group_set = pmic_gpio_config_set, 671 .pin_config_group_dbg_show = pmic_gpio_config_dbg_show, 672 }; 673 674 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 675 { 676 struct pmic_gpio_state *state = gpiochip_get_data(chip); 677 unsigned long config; 678 679 config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1); 680 681 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); 682 } 683 684 static int pmic_gpio_direction_output(struct gpio_chip *chip, 685 unsigned pin, int val) 686 { 687 struct pmic_gpio_state *state = gpiochip_get_data(chip); 688 unsigned long config; 689 690 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val); 691 692 return pmic_gpio_config_set(state->ctrl, pin, &config, 1); 693 } 694 695 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin) 696 { 697 struct pmic_gpio_state *state = gpiochip_get_data(chip); 698 struct pmic_gpio_pad *pad; 699 int ret; 700 701 pad = state->ctrl->desc->pins[pin].drv_data; 702 703 if (!pad->is_enabled) 704 return -EINVAL; 705 706 if (pad->input_enabled) { 707 ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS); 708 if (ret < 0) 709 return ret; 710 711 pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK; 712 } 713 714 return !!pad->out_value; 715 } 716 717 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 718 { 719 struct pmic_gpio_state *state = gpiochip_get_data(chip); 720 unsigned long config; 721 722 config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value); 723 724 pmic_gpio_config_set(state->ctrl, pin, &config, 1); 725 } 726 727 static int pmic_gpio_of_xlate(struct gpio_chip *chip, 728 const struct of_phandle_args *gpio_desc, 729 u32 *flags) 730 { 731 if (chip->of_gpio_n_cells < 2) 732 return -EINVAL; 733 734 if (flags) 735 *flags = gpio_desc->args[1]; 736 737 return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET; 738 } 739 740 static int pmic_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 741 { 742 struct pmic_gpio_state *state = gpiochip_get_data(chip); 743 struct pmic_gpio_pad *pad; 744 745 pad = state->ctrl->desc->pins[pin].drv_data; 746 747 return pad->irq; 748 } 749 750 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 751 { 752 struct pmic_gpio_state *state = gpiochip_get_data(chip); 753 unsigned i; 754 755 for (i = 0; i < chip->ngpio; i++) { 756 pmic_gpio_config_dbg_show(state->ctrl, s, i); 757 seq_puts(s, "\n"); 758 } 759 } 760 761 static const struct gpio_chip pmic_gpio_gpio_template = { 762 .direction_input = pmic_gpio_direction_input, 763 .direction_output = pmic_gpio_direction_output, 764 .get = pmic_gpio_get, 765 .set = pmic_gpio_set, 766 .request = gpiochip_generic_request, 767 .free = gpiochip_generic_free, 768 .of_xlate = pmic_gpio_of_xlate, 769 .to_irq = pmic_gpio_to_irq, 770 .dbg_show = pmic_gpio_dbg_show, 771 }; 772 773 static int pmic_gpio_populate(struct pmic_gpio_state *state, 774 struct pmic_gpio_pad *pad) 775 { 776 int type, subtype, val, dir; 777 778 type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE); 779 if (type < 0) 780 return type; 781 782 if (type != PMIC_GPIO_TYPE) { 783 dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n", 784 type, pad->base); 785 return -ENODEV; 786 } 787 788 subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE); 789 if (subtype < 0) 790 return subtype; 791 792 switch (subtype) { 793 case PMIC_GPIO_SUBTYPE_GPIO_4CH: 794 pad->have_buffer = true; 795 case PMIC_GPIO_SUBTYPE_GPIOC_4CH: 796 pad->num_sources = 4; 797 break; 798 case PMIC_GPIO_SUBTYPE_GPIO_8CH: 799 pad->have_buffer = true; 800 case PMIC_GPIO_SUBTYPE_GPIOC_8CH: 801 pad->num_sources = 8; 802 break; 803 case PMIC_GPIO_SUBTYPE_GPIO_LV: 804 pad->num_sources = 1; 805 pad->have_buffer = true; 806 pad->lv_mv_type = true; 807 break; 808 case PMIC_GPIO_SUBTYPE_GPIO_MV: 809 pad->num_sources = 2; 810 pad->have_buffer = true; 811 pad->lv_mv_type = true; 812 break; 813 default: 814 dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype); 815 return -ENODEV; 816 } 817 818 if (pad->lv_mv_type) { 819 val = pmic_gpio_read(state, pad, 820 PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL); 821 if (val < 0) 822 return val; 823 824 pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT); 825 pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK; 826 827 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); 828 if (val < 0) 829 return val; 830 831 dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK; 832 } else { 833 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL); 834 if (val < 0) 835 return val; 836 837 pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT; 838 839 dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT; 840 dir &= PMIC_GPIO_REG_MODE_DIR_MASK; 841 pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT; 842 pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK; 843 } 844 845 switch (dir) { 846 case PMIC_GPIO_MODE_DIGITAL_INPUT: 847 pad->input_enabled = true; 848 pad->output_enabled = false; 849 break; 850 case PMIC_GPIO_MODE_DIGITAL_OUTPUT: 851 pad->input_enabled = false; 852 pad->output_enabled = true; 853 break; 854 case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT: 855 pad->input_enabled = true; 856 pad->output_enabled = true; 857 break; 858 case PMIC_GPIO_MODE_ANALOG_PASS_THRU: 859 if (!pad->lv_mv_type) 860 return -ENODEV; 861 pad->analog_pass = true; 862 break; 863 default: 864 dev_err(state->dev, "unknown GPIO direction\n"); 865 return -ENODEV; 866 } 867 868 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL); 869 if (val < 0) 870 return val; 871 872 pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT; 873 pad->power_source &= PMIC_GPIO_REG_VIN_MASK; 874 875 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL); 876 if (val < 0) 877 return val; 878 879 pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT; 880 pad->pullup &= PMIC_GPIO_REG_PULL_MASK; 881 882 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL); 883 if (val < 0) 884 return val; 885 886 if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN)) 887 pad->dtest_buffer = 888 (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1; 889 else if (!pad->lv_mv_type) 890 pad->dtest_buffer = ffs(val); 891 else 892 pad->dtest_buffer = 0; 893 894 val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL); 895 if (val < 0) 896 return val; 897 898 pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT; 899 pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK; 900 901 pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT; 902 pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK; 903 904 if (pad->lv_mv_type) { 905 val = pmic_gpio_read(state, pad, 906 PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL); 907 if (val < 0) 908 return val; 909 pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1; 910 } 911 912 /* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */ 913 pad->is_enabled = true; 914 return 0; 915 } 916 917 static int pmic_gpio_probe(struct platform_device *pdev) 918 { 919 struct device *dev = &pdev->dev; 920 struct pinctrl_pin_desc *pindesc; 921 struct pinctrl_desc *pctrldesc; 922 struct pmic_gpio_pad *pad, *pads; 923 struct pmic_gpio_state *state; 924 int ret, npins, i; 925 u32 reg; 926 927 ret = of_property_read_u32(dev->of_node, "reg", ®); 928 if (ret < 0) { 929 dev_err(dev, "missing base address"); 930 return ret; 931 } 932 933 npins = platform_irq_count(pdev); 934 if (!npins) 935 return -EINVAL; 936 if (npins < 0) 937 return npins; 938 939 BUG_ON(npins > ARRAY_SIZE(pmic_gpio_groups)); 940 941 state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL); 942 if (!state) 943 return -ENOMEM; 944 945 platform_set_drvdata(pdev, state); 946 947 state->dev = &pdev->dev; 948 state->map = dev_get_regmap(dev->parent, NULL); 949 950 pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL); 951 if (!pindesc) 952 return -ENOMEM; 953 954 pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL); 955 if (!pads) 956 return -ENOMEM; 957 958 pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL); 959 if (!pctrldesc) 960 return -ENOMEM; 961 962 pctrldesc->pctlops = &pmic_gpio_pinctrl_ops; 963 pctrldesc->pmxops = &pmic_gpio_pinmux_ops; 964 pctrldesc->confops = &pmic_gpio_pinconf_ops; 965 pctrldesc->owner = THIS_MODULE; 966 pctrldesc->name = dev_name(dev); 967 pctrldesc->pins = pindesc; 968 pctrldesc->npins = npins; 969 pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings); 970 pctrldesc->custom_params = pmic_gpio_bindings; 971 #ifdef CONFIG_DEBUG_FS 972 pctrldesc->custom_conf_items = pmic_conf_items; 973 #endif 974 975 for (i = 0; i < npins; i++, pindesc++) { 976 pad = &pads[i]; 977 pindesc->drv_data = pad; 978 pindesc->number = i; 979 pindesc->name = pmic_gpio_groups[i]; 980 981 pad->irq = platform_get_irq(pdev, i); 982 if (pad->irq < 0) 983 return pad->irq; 984 985 pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE; 986 987 ret = pmic_gpio_populate(state, pad); 988 if (ret < 0) 989 return ret; 990 } 991 992 state->chip = pmic_gpio_gpio_template; 993 state->chip.parent = dev; 994 state->chip.base = -1; 995 state->chip.ngpio = npins; 996 state->chip.label = dev_name(dev); 997 state->chip.of_gpio_n_cells = 2; 998 state->chip.can_sleep = false; 999 1000 state->ctrl = devm_pinctrl_register(dev, pctrldesc, state); 1001 if (IS_ERR(state->ctrl)) 1002 return PTR_ERR(state->ctrl); 1003 1004 ret = gpiochip_add_data(&state->chip, state); 1005 if (ret) { 1006 dev_err(state->dev, "can't add gpio chip\n"); 1007 return ret; 1008 } 1009 1010 ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0, npins); 1011 if (ret) { 1012 dev_err(dev, "failed to add pin range\n"); 1013 goto err_range; 1014 } 1015 1016 return 0; 1017 1018 err_range: 1019 gpiochip_remove(&state->chip); 1020 return ret; 1021 } 1022 1023 static int pmic_gpio_remove(struct platform_device *pdev) 1024 { 1025 struct pmic_gpio_state *state = platform_get_drvdata(pdev); 1026 1027 gpiochip_remove(&state->chip); 1028 return 0; 1029 } 1030 1031 static const struct of_device_id pmic_gpio_of_match[] = { 1032 { .compatible = "qcom,pm8916-gpio" }, /* 4 GPIO's */ 1033 { .compatible = "qcom,pm8941-gpio" }, /* 36 GPIO's */ 1034 { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */ 1035 { .compatible = "qcom,pma8084-gpio" }, /* 22 GPIO's */ 1036 { .compatible = "qcom,spmi-gpio" }, /* Generic */ 1037 { }, 1038 }; 1039 1040 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match); 1041 1042 static struct platform_driver pmic_gpio_driver = { 1043 .driver = { 1044 .name = "qcom-spmi-gpio", 1045 .of_match_table = pmic_gpio_of_match, 1046 }, 1047 .probe = pmic_gpio_probe, 1048 .remove = pmic_gpio_remove, 1049 }; 1050 1051 module_platform_driver(pmic_gpio_driver); 1052 1053 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>"); 1054 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver"); 1055 MODULE_ALIAS("platform:qcom-spmi-gpio"); 1056 MODULE_LICENSE("GPL v2"); 1057