1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/gpio/driver.h>
7 #include <linux/interrupt.h>
8 #include <linux/module.h>
9 #include <linux/of.h>
10 #include <linux/of_irq.h>
11 #include <linux/pinctrl/pinconf-generic.h>
12 #include <linux/pinctrl/pinconf.h>
13 #include <linux/pinctrl/pinmux.h>
14 #include <linux/platform_device.h>
15 #include <linux/regmap.h>
16 #include <linux/slab.h>
17 #include <linux/types.h>
18 
19 #include <dt-bindings/pinctrl/qcom,pmic-gpio.h>
20 
21 #include "../core.h"
22 #include "../pinctrl-utils.h"
23 
24 #define PMIC_GPIO_ADDRESS_RANGE			0x100
25 
26 /* type and subtype registers base address offsets */
27 #define PMIC_GPIO_REG_TYPE			0x4
28 #define PMIC_GPIO_REG_SUBTYPE			0x5
29 
30 /* GPIO peripheral type and subtype out_values */
31 #define PMIC_GPIO_TYPE				0x10
32 #define PMIC_GPIO_SUBTYPE_GPIO_4CH		0x1
33 #define PMIC_GPIO_SUBTYPE_GPIOC_4CH		0x5
34 #define PMIC_GPIO_SUBTYPE_GPIO_8CH		0x9
35 #define PMIC_GPIO_SUBTYPE_GPIOC_8CH		0xd
36 #define PMIC_GPIO_SUBTYPE_GPIO_LV		0x10
37 #define PMIC_GPIO_SUBTYPE_GPIO_MV		0x11
38 
39 #define PMIC_MPP_REG_RT_STS			0x10
40 #define PMIC_MPP_REG_RT_STS_VAL_MASK		0x1
41 
42 /* control register base address offsets */
43 #define PMIC_GPIO_REG_MODE_CTL			0x40
44 #define PMIC_GPIO_REG_DIG_VIN_CTL		0x41
45 #define PMIC_GPIO_REG_DIG_PULL_CTL		0x42
46 #define PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL	0x44
47 #define PMIC_GPIO_REG_DIG_IN_CTL		0x43
48 #define PMIC_GPIO_REG_DIG_OUT_CTL		0x45
49 #define PMIC_GPIO_REG_EN_CTL			0x46
50 #define PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL	0x4A
51 
52 /* PMIC_GPIO_REG_MODE_CTL */
53 #define PMIC_GPIO_REG_MODE_VALUE_SHIFT		0x1
54 #define PMIC_GPIO_REG_MODE_FUNCTION_SHIFT	1
55 #define PMIC_GPIO_REG_MODE_FUNCTION_MASK	0x7
56 #define PMIC_GPIO_REG_MODE_DIR_SHIFT		4
57 #define PMIC_GPIO_REG_MODE_DIR_MASK		0x7
58 
59 #define PMIC_GPIO_MODE_DIGITAL_INPUT		0
60 #define PMIC_GPIO_MODE_DIGITAL_OUTPUT		1
61 #define PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT	2
62 #define PMIC_GPIO_MODE_ANALOG_PASS_THRU		3
63 #define PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK	0x3
64 
65 /* PMIC_GPIO_REG_DIG_VIN_CTL */
66 #define PMIC_GPIO_REG_VIN_SHIFT			0
67 #define PMIC_GPIO_REG_VIN_MASK			0x7
68 
69 /* PMIC_GPIO_REG_DIG_PULL_CTL */
70 #define PMIC_GPIO_REG_PULL_SHIFT		0
71 #define PMIC_GPIO_REG_PULL_MASK			0x7
72 
73 #define PMIC_GPIO_PULL_DOWN			4
74 #define PMIC_GPIO_PULL_DISABLE			5
75 
76 /* PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL for LV/MV */
77 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT		0x80
78 #define PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT	7
79 #define PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK	0xF
80 
81 /* PMIC_GPIO_REG_DIG_IN_CTL */
82 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN		0x80
83 #define PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK	0x7
84 #define PMIC_GPIO_DIG_IN_DTEST_SEL_MASK		0xf
85 
86 /* PMIC_GPIO_REG_DIG_OUT_CTL */
87 #define PMIC_GPIO_REG_OUT_STRENGTH_SHIFT	0
88 #define PMIC_GPIO_REG_OUT_STRENGTH_MASK		0x3
89 #define PMIC_GPIO_REG_OUT_TYPE_SHIFT		4
90 #define PMIC_GPIO_REG_OUT_TYPE_MASK		0x3
91 
92 /*
93  * Output type - indicates pin should be configured as push-pull,
94  * open drain or open source.
95  */
96 #define PMIC_GPIO_OUT_BUF_CMOS			0
97 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS	1
98 #define PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS	2
99 
100 /* PMIC_GPIO_REG_EN_CTL */
101 #define PMIC_GPIO_REG_MASTER_EN_SHIFT		7
102 
103 #define PMIC_GPIO_PHYSICAL_OFFSET		1
104 
105 /* PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL */
106 #define PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK		0x3
107 
108 /* Qualcomm specific pin configurations */
109 #define PMIC_GPIO_CONF_PULL_UP			(PIN_CONFIG_END + 1)
110 #define PMIC_GPIO_CONF_STRENGTH			(PIN_CONFIG_END + 2)
111 #define PMIC_GPIO_CONF_ATEST			(PIN_CONFIG_END + 3)
112 #define PMIC_GPIO_CONF_ANALOG_PASS		(PIN_CONFIG_END + 4)
113 #define PMIC_GPIO_CONF_DTEST_BUFFER		(PIN_CONFIG_END + 5)
114 
115 /* The index of each function in pmic_gpio_functions[] array */
116 enum pmic_gpio_func_index {
117 	PMIC_GPIO_FUNC_INDEX_NORMAL,
118 	PMIC_GPIO_FUNC_INDEX_PAIRED,
119 	PMIC_GPIO_FUNC_INDEX_FUNC1,
120 	PMIC_GPIO_FUNC_INDEX_FUNC2,
121 	PMIC_GPIO_FUNC_INDEX_FUNC3,
122 	PMIC_GPIO_FUNC_INDEX_FUNC4,
123 	PMIC_GPIO_FUNC_INDEX_DTEST1,
124 	PMIC_GPIO_FUNC_INDEX_DTEST2,
125 	PMIC_GPIO_FUNC_INDEX_DTEST3,
126 	PMIC_GPIO_FUNC_INDEX_DTEST4,
127 };
128 
129 /**
130  * struct pmic_gpio_pad - keep current GPIO settings
131  * @base: Address base in SPMI device.
132  * @is_enabled: Set to false when GPIO should be put in high Z state.
133  * @out_value: Cached pin output value
134  * @have_buffer: Set to true if GPIO output could be configured in push-pull,
135  *	open-drain or open-source mode.
136  * @output_enabled: Set to true if GPIO output logic is enabled.
137  * @input_enabled: Set to true if GPIO input buffer logic is enabled.
138  * @analog_pass: Set to true if GPIO is in analog-pass-through mode.
139  * @lv_mv_type: Set to true if GPIO subtype is GPIO_LV(0x10) or GPIO_MV(0x11).
140  * @num_sources: Number of power-sources supported by this GPIO.
141  * @power_source: Current power-source used.
142  * @buffer_type: Push-pull, open-drain or open-source.
143  * @pullup: Constant current which flow trough GPIO output buffer.
144  * @strength: No, Low, Medium, High
145  * @function: See pmic_gpio_functions[]
146  * @atest: the ATEST selection for GPIO analog-pass-through mode
147  * @dtest_buffer: the DTEST buffer selection for digital input mode.
148  */
149 struct pmic_gpio_pad {
150 	u16		base;
151 	bool		is_enabled;
152 	bool		out_value;
153 	bool		have_buffer;
154 	bool		output_enabled;
155 	bool		input_enabled;
156 	bool		analog_pass;
157 	bool		lv_mv_type;
158 	unsigned int	num_sources;
159 	unsigned int	power_source;
160 	unsigned int	buffer_type;
161 	unsigned int	pullup;
162 	unsigned int	strength;
163 	unsigned int	function;
164 	unsigned int	atest;
165 	unsigned int	dtest_buffer;
166 };
167 
168 struct pmic_gpio_state {
169 	struct device	*dev;
170 	struct regmap	*map;
171 	struct pinctrl_dev *ctrl;
172 	struct gpio_chip chip;
173 	struct irq_chip irq;
174 };
175 
176 static const struct pinconf_generic_params pmic_gpio_bindings[] = {
177 	{"qcom,pull-up-strength",	PMIC_GPIO_CONF_PULL_UP,		0},
178 	{"qcom,drive-strength",		PMIC_GPIO_CONF_STRENGTH,	0},
179 	{"qcom,atest",			PMIC_GPIO_CONF_ATEST,		0},
180 	{"qcom,analog-pass",		PMIC_GPIO_CONF_ANALOG_PASS,	0},
181 	{"qcom,dtest-buffer",           PMIC_GPIO_CONF_DTEST_BUFFER,    0},
182 };
183 
184 #ifdef CONFIG_DEBUG_FS
185 static const struct pin_config_item pmic_conf_items[ARRAY_SIZE(pmic_gpio_bindings)] = {
186 	PCONFDUMP(PMIC_GPIO_CONF_PULL_UP,  "pull up strength", NULL, true),
187 	PCONFDUMP(PMIC_GPIO_CONF_STRENGTH, "drive-strength", NULL, true),
188 	PCONFDUMP(PMIC_GPIO_CONF_ATEST, "atest", NULL, true),
189 	PCONFDUMP(PMIC_GPIO_CONF_ANALOG_PASS, "analog-pass", NULL, true),
190 	PCONFDUMP(PMIC_GPIO_CONF_DTEST_BUFFER, "dtest-buffer", NULL, true),
191 };
192 #endif
193 
194 static const char *const pmic_gpio_groups[] = {
195 	"gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8",
196 	"gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14", "gpio15",
197 	"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
198 	"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
199 	"gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35", "gpio36",
200 };
201 
202 static const char *const pmic_gpio_functions[] = {
203 	[PMIC_GPIO_FUNC_INDEX_NORMAL]	= PMIC_GPIO_FUNC_NORMAL,
204 	[PMIC_GPIO_FUNC_INDEX_PAIRED]	= PMIC_GPIO_FUNC_PAIRED,
205 	[PMIC_GPIO_FUNC_INDEX_FUNC1]	= PMIC_GPIO_FUNC_FUNC1,
206 	[PMIC_GPIO_FUNC_INDEX_FUNC2]	= PMIC_GPIO_FUNC_FUNC2,
207 	[PMIC_GPIO_FUNC_INDEX_FUNC3]	= PMIC_GPIO_FUNC_FUNC3,
208 	[PMIC_GPIO_FUNC_INDEX_FUNC4]	= PMIC_GPIO_FUNC_FUNC4,
209 	[PMIC_GPIO_FUNC_INDEX_DTEST1]	= PMIC_GPIO_FUNC_DTEST1,
210 	[PMIC_GPIO_FUNC_INDEX_DTEST2]	= PMIC_GPIO_FUNC_DTEST2,
211 	[PMIC_GPIO_FUNC_INDEX_DTEST3]	= PMIC_GPIO_FUNC_DTEST3,
212 	[PMIC_GPIO_FUNC_INDEX_DTEST4]	= PMIC_GPIO_FUNC_DTEST4,
213 };
214 
215 static int pmic_gpio_read(struct pmic_gpio_state *state,
216 			  struct pmic_gpio_pad *pad, unsigned int addr)
217 {
218 	unsigned int val;
219 	int ret;
220 
221 	ret = regmap_read(state->map, pad->base + addr, &val);
222 	if (ret < 0)
223 		dev_err(state->dev, "read 0x%x failed\n", addr);
224 	else
225 		ret = val;
226 
227 	return ret;
228 }
229 
230 static int pmic_gpio_write(struct pmic_gpio_state *state,
231 			   struct pmic_gpio_pad *pad, unsigned int addr,
232 			   unsigned int val)
233 {
234 	int ret;
235 
236 	ret = regmap_write(state->map, pad->base + addr, val);
237 	if (ret < 0)
238 		dev_err(state->dev, "write 0x%x failed\n", addr);
239 
240 	return ret;
241 }
242 
243 static int pmic_gpio_get_groups_count(struct pinctrl_dev *pctldev)
244 {
245 	/* Every PIN is a group */
246 	return pctldev->desc->npins;
247 }
248 
249 static const char *pmic_gpio_get_group_name(struct pinctrl_dev *pctldev,
250 					    unsigned pin)
251 {
252 	return pctldev->desc->pins[pin].name;
253 }
254 
255 static int pmic_gpio_get_group_pins(struct pinctrl_dev *pctldev, unsigned pin,
256 				    const unsigned **pins, unsigned *num_pins)
257 {
258 	*pins = &pctldev->desc->pins[pin].number;
259 	*num_pins = 1;
260 	return 0;
261 }
262 
263 static const struct pinctrl_ops pmic_gpio_pinctrl_ops = {
264 	.get_groups_count	= pmic_gpio_get_groups_count,
265 	.get_group_name		= pmic_gpio_get_group_name,
266 	.get_group_pins		= pmic_gpio_get_group_pins,
267 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
268 	.dt_free_map		= pinctrl_utils_free_map,
269 };
270 
271 static int pmic_gpio_get_functions_count(struct pinctrl_dev *pctldev)
272 {
273 	return ARRAY_SIZE(pmic_gpio_functions);
274 }
275 
276 static const char *pmic_gpio_get_function_name(struct pinctrl_dev *pctldev,
277 					       unsigned function)
278 {
279 	return pmic_gpio_functions[function];
280 }
281 
282 static int pmic_gpio_get_function_groups(struct pinctrl_dev *pctldev,
283 					 unsigned function,
284 					 const char *const **groups,
285 					 unsigned *const num_qgroups)
286 {
287 	*groups = pmic_gpio_groups;
288 	*num_qgroups = pctldev->desc->npins;
289 	return 0;
290 }
291 
292 static int pmic_gpio_set_mux(struct pinctrl_dev *pctldev, unsigned function,
293 				unsigned pin)
294 {
295 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
296 	struct pmic_gpio_pad *pad;
297 	unsigned int val;
298 	int ret;
299 
300 	if (function > PMIC_GPIO_FUNC_INDEX_DTEST4) {
301 		pr_err("function: %d is not defined\n", function);
302 		return -EINVAL;
303 	}
304 
305 	pad = pctldev->desc->pins[pin].drv_data;
306 	/*
307 	 * Non-LV/MV subtypes only support 2 special functions,
308 	 * offsetting the dtestx function values by 2
309 	 */
310 	if (!pad->lv_mv_type) {
311 		if (function == PMIC_GPIO_FUNC_INDEX_FUNC3 ||
312 				function == PMIC_GPIO_FUNC_INDEX_FUNC4) {
313 			pr_err("LV/MV subtype doesn't have func3/func4\n");
314 			return -EINVAL;
315 		}
316 		if (function >= PMIC_GPIO_FUNC_INDEX_DTEST1)
317 			function -= (PMIC_GPIO_FUNC_INDEX_DTEST1 -
318 					PMIC_GPIO_FUNC_INDEX_FUNC3);
319 	}
320 
321 	pad->function = function;
322 
323 	if (pad->analog_pass)
324 		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
325 	else if (pad->output_enabled && pad->input_enabled)
326 		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
327 	else if (pad->output_enabled)
328 		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
329 	else
330 		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
331 
332 	if (pad->lv_mv_type) {
333 		ret = pmic_gpio_write(state, pad,
334 				PMIC_GPIO_REG_MODE_CTL, val);
335 		if (ret < 0)
336 			return ret;
337 
338 		val = pad->atest - 1;
339 		ret = pmic_gpio_write(state, pad,
340 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
341 		if (ret < 0)
342 			return ret;
343 
344 		val = pad->out_value
345 			<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
346 		val |= pad->function
347 			& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
348 		ret = pmic_gpio_write(state, pad,
349 			PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
350 		if (ret < 0)
351 			return ret;
352 	} else {
353 		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
354 		val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
355 		val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
356 
357 		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
358 		if (ret < 0)
359 			return ret;
360 	}
361 
362 	val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
363 
364 	return pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
365 }
366 
367 static const struct pinmux_ops pmic_gpio_pinmux_ops = {
368 	.get_functions_count	= pmic_gpio_get_functions_count,
369 	.get_function_name	= pmic_gpio_get_function_name,
370 	.get_function_groups	= pmic_gpio_get_function_groups,
371 	.set_mux		= pmic_gpio_set_mux,
372 };
373 
374 static int pmic_gpio_config_get(struct pinctrl_dev *pctldev,
375 				unsigned int pin, unsigned long *config)
376 {
377 	unsigned param = pinconf_to_config_param(*config);
378 	struct pmic_gpio_pad *pad;
379 	unsigned arg;
380 
381 	pad = pctldev->desc->pins[pin].drv_data;
382 
383 	switch (param) {
384 	case PIN_CONFIG_DRIVE_PUSH_PULL:
385 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_CMOS)
386 			return -EINVAL;
387 		arg = 1;
388 		break;
389 	case PIN_CONFIG_DRIVE_OPEN_DRAIN:
390 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS)
391 			return -EINVAL;
392 		arg = 1;
393 		break;
394 	case PIN_CONFIG_DRIVE_OPEN_SOURCE:
395 		if (pad->buffer_type != PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS)
396 			return -EINVAL;
397 		arg = 1;
398 		break;
399 	case PIN_CONFIG_BIAS_PULL_DOWN:
400 		if (pad->pullup != PMIC_GPIO_PULL_DOWN)
401 			return -EINVAL;
402 		arg = 1;
403 		break;
404 	case PIN_CONFIG_BIAS_DISABLE:
405 		if (pad->pullup != PMIC_GPIO_PULL_DISABLE)
406 			return -EINVAL;
407 		arg = 1;
408 		break;
409 	case PIN_CONFIG_BIAS_PULL_UP:
410 		if (pad->pullup != PMIC_GPIO_PULL_UP_30)
411 			return -EINVAL;
412 		arg = 1;
413 		break;
414 	case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
415 		if (pad->is_enabled)
416 			return -EINVAL;
417 		arg = 1;
418 		break;
419 	case PIN_CONFIG_POWER_SOURCE:
420 		arg = pad->power_source;
421 		break;
422 	case PIN_CONFIG_INPUT_ENABLE:
423 		if (!pad->input_enabled)
424 			return -EINVAL;
425 		arg = 1;
426 		break;
427 	case PIN_CONFIG_OUTPUT:
428 		arg = pad->out_value;
429 		break;
430 	case PMIC_GPIO_CONF_PULL_UP:
431 		arg = pad->pullup;
432 		break;
433 	case PMIC_GPIO_CONF_STRENGTH:
434 		arg = pad->strength;
435 		break;
436 	case PMIC_GPIO_CONF_ATEST:
437 		arg = pad->atest;
438 		break;
439 	case PMIC_GPIO_CONF_ANALOG_PASS:
440 		arg = pad->analog_pass;
441 		break;
442 	case PMIC_GPIO_CONF_DTEST_BUFFER:
443 		arg = pad->dtest_buffer;
444 		break;
445 	default:
446 		return -EINVAL;
447 	}
448 
449 	*config = pinconf_to_config_packed(param, arg);
450 	return 0;
451 }
452 
453 static int pmic_gpio_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
454 				unsigned long *configs, unsigned nconfs)
455 {
456 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
457 	struct pmic_gpio_pad *pad;
458 	unsigned param, arg;
459 	unsigned int val;
460 	int i, ret;
461 
462 	pad = pctldev->desc->pins[pin].drv_data;
463 
464 	pad->is_enabled = true;
465 	for (i = 0; i < nconfs; i++) {
466 		param = pinconf_to_config_param(configs[i]);
467 		arg = pinconf_to_config_argument(configs[i]);
468 
469 		switch (param) {
470 		case PIN_CONFIG_DRIVE_PUSH_PULL:
471 			pad->buffer_type = PMIC_GPIO_OUT_BUF_CMOS;
472 			break;
473 		case PIN_CONFIG_DRIVE_OPEN_DRAIN:
474 			if (!pad->have_buffer)
475 				return -EINVAL;
476 			pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_NMOS;
477 			break;
478 		case PIN_CONFIG_DRIVE_OPEN_SOURCE:
479 			if (!pad->have_buffer)
480 				return -EINVAL;
481 			pad->buffer_type = PMIC_GPIO_OUT_BUF_OPEN_DRAIN_PMOS;
482 			break;
483 		case PIN_CONFIG_BIAS_DISABLE:
484 			pad->pullup = PMIC_GPIO_PULL_DISABLE;
485 			break;
486 		case PIN_CONFIG_BIAS_PULL_UP:
487 			pad->pullup = PMIC_GPIO_PULL_UP_30;
488 			break;
489 		case PIN_CONFIG_BIAS_PULL_DOWN:
490 			if (arg)
491 				pad->pullup = PMIC_GPIO_PULL_DOWN;
492 			else
493 				pad->pullup = PMIC_GPIO_PULL_DISABLE;
494 			break;
495 		case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
496 			pad->is_enabled = false;
497 			break;
498 		case PIN_CONFIG_POWER_SOURCE:
499 			if (arg >= pad->num_sources)
500 				return -EINVAL;
501 			pad->power_source = arg;
502 			break;
503 		case PIN_CONFIG_INPUT_ENABLE:
504 			pad->input_enabled = arg ? true : false;
505 			break;
506 		case PIN_CONFIG_OUTPUT:
507 			pad->output_enabled = true;
508 			pad->out_value = arg;
509 			break;
510 		case PMIC_GPIO_CONF_PULL_UP:
511 			if (arg > PMIC_GPIO_PULL_UP_1P5_30)
512 				return -EINVAL;
513 			pad->pullup = arg;
514 			break;
515 		case PMIC_GPIO_CONF_STRENGTH:
516 			if (arg > PMIC_GPIO_STRENGTH_LOW)
517 				return -EINVAL;
518 			pad->strength = arg;
519 			break;
520 		case PMIC_GPIO_CONF_ATEST:
521 			if (!pad->lv_mv_type || arg > 4)
522 				return -EINVAL;
523 			pad->atest = arg;
524 			break;
525 		case PMIC_GPIO_CONF_ANALOG_PASS:
526 			if (!pad->lv_mv_type)
527 				return -EINVAL;
528 			pad->analog_pass = true;
529 			break;
530 		case PMIC_GPIO_CONF_DTEST_BUFFER:
531 			if (arg > 4)
532 				return -EINVAL;
533 			pad->dtest_buffer = arg;
534 			break;
535 		default:
536 			return -EINVAL;
537 		}
538 	}
539 
540 	val = pad->power_source << PMIC_GPIO_REG_VIN_SHIFT;
541 
542 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL, val);
543 	if (ret < 0)
544 		return ret;
545 
546 	val = pad->pullup << PMIC_GPIO_REG_PULL_SHIFT;
547 
548 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL, val);
549 	if (ret < 0)
550 		return ret;
551 
552 	val = pad->buffer_type << PMIC_GPIO_REG_OUT_TYPE_SHIFT;
553 	val |= pad->strength << PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
554 
555 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL, val);
556 	if (ret < 0)
557 		return ret;
558 
559 	if (pad->dtest_buffer == 0) {
560 		val = 0;
561 	} else {
562 		if (pad->lv_mv_type) {
563 			val = pad->dtest_buffer - 1;
564 			val |= PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN;
565 		} else {
566 			val = BIT(pad->dtest_buffer - 1);
567 		}
568 	}
569 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_DIG_IN_CTL, val);
570 	if (ret < 0)
571 		return ret;
572 
573 	if (pad->analog_pass)
574 		val = PMIC_GPIO_MODE_ANALOG_PASS_THRU;
575 	else if (pad->output_enabled && pad->input_enabled)
576 		val = PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT;
577 	else if (pad->output_enabled)
578 		val = PMIC_GPIO_MODE_DIGITAL_OUTPUT;
579 	else
580 		val = PMIC_GPIO_MODE_DIGITAL_INPUT;
581 
582 	if (pad->lv_mv_type) {
583 		ret = pmic_gpio_write(state, pad,
584 				PMIC_GPIO_REG_MODE_CTL, val);
585 		if (ret < 0)
586 			return ret;
587 
588 		val = pad->atest - 1;
589 		ret = pmic_gpio_write(state, pad,
590 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL, val);
591 		if (ret < 0)
592 			return ret;
593 
594 		val = pad->out_value
595 			<< PMIC_GPIO_LV_MV_OUTPUT_INVERT_SHIFT;
596 		val |= pad->function
597 			& PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
598 		ret = pmic_gpio_write(state, pad,
599 			PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL, val);
600 		if (ret < 0)
601 			return ret;
602 	} else {
603 		val = val << PMIC_GPIO_REG_MODE_DIR_SHIFT;
604 		val |= pad->function << PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
605 		val |= pad->out_value & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
606 
607 		ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_MODE_CTL, val);
608 		if (ret < 0)
609 			return ret;
610 	}
611 
612 	val = pad->is_enabled << PMIC_GPIO_REG_MASTER_EN_SHIFT;
613 
614 	ret = pmic_gpio_write(state, pad, PMIC_GPIO_REG_EN_CTL, val);
615 
616 	return ret;
617 }
618 
619 static void pmic_gpio_config_dbg_show(struct pinctrl_dev *pctldev,
620 				      struct seq_file *s, unsigned pin)
621 {
622 	struct pmic_gpio_state *state = pinctrl_dev_get_drvdata(pctldev);
623 	struct pmic_gpio_pad *pad;
624 	int ret, val, function;
625 
626 	static const char *const biases[] = {
627 		"pull-up 30uA", "pull-up 1.5uA", "pull-up 31.5uA",
628 		"pull-up 1.5uA + 30uA boost", "pull-down 10uA", "no pull"
629 	};
630 	static const char *const buffer_types[] = {
631 		"push-pull", "open-drain", "open-source"
632 	};
633 	static const char *const strengths[] = {
634 		"no", "high", "medium", "low"
635 	};
636 
637 	pad = pctldev->desc->pins[pin].drv_data;
638 
639 	seq_printf(s, " gpio%-2d:", pin + PMIC_GPIO_PHYSICAL_OFFSET);
640 
641 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_EN_CTL);
642 
643 	if (val < 0 || !(val >> PMIC_GPIO_REG_MASTER_EN_SHIFT)) {
644 		seq_puts(s, " ---");
645 	} else {
646 		if (pad->input_enabled) {
647 			ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
648 			if (ret < 0)
649 				return;
650 
651 			ret &= PMIC_MPP_REG_RT_STS_VAL_MASK;
652 			pad->out_value = ret;
653 		}
654 		/*
655 		 * For the non-LV/MV subtypes only 2 special functions are
656 		 * available, offsetting the dtest function values by 2.
657 		 */
658 		function = pad->function;
659 		if (!pad->lv_mv_type &&
660 				pad->function >= PMIC_GPIO_FUNC_INDEX_FUNC3)
661 			function += PMIC_GPIO_FUNC_INDEX_DTEST1 -
662 				PMIC_GPIO_FUNC_INDEX_FUNC3;
663 
664 		if (pad->analog_pass)
665 			seq_puts(s, " analog-pass");
666 		else
667 			seq_printf(s, " %-4s",
668 					pad->output_enabled ? "out" : "in");
669 		seq_printf(s, " %-4s", pad->out_value ? "high" : "low");
670 		seq_printf(s, " %-7s", pmic_gpio_functions[function]);
671 		seq_printf(s, " vin-%d", pad->power_source);
672 		seq_printf(s, " %-27s", biases[pad->pullup]);
673 		seq_printf(s, " %-10s", buffer_types[pad->buffer_type]);
674 		seq_printf(s, " %-7s", strengths[pad->strength]);
675 		seq_printf(s, " atest-%d", pad->atest);
676 		seq_printf(s, " dtest-%d", pad->dtest_buffer);
677 	}
678 }
679 
680 static const struct pinconf_ops pmic_gpio_pinconf_ops = {
681 	.is_generic			= true,
682 	.pin_config_group_get		= pmic_gpio_config_get,
683 	.pin_config_group_set		= pmic_gpio_config_set,
684 	.pin_config_group_dbg_show	= pmic_gpio_config_dbg_show,
685 };
686 
687 static int pmic_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
688 {
689 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
690 	unsigned long config;
691 
692 	config = pinconf_to_config_packed(PIN_CONFIG_INPUT_ENABLE, 1);
693 
694 	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
695 }
696 
697 static int pmic_gpio_direction_output(struct gpio_chip *chip,
698 				      unsigned pin, int val)
699 {
700 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
701 	unsigned long config;
702 
703 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, val);
704 
705 	return pmic_gpio_config_set(state->ctrl, pin, &config, 1);
706 }
707 
708 static int pmic_gpio_get(struct gpio_chip *chip, unsigned pin)
709 {
710 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
711 	struct pmic_gpio_pad *pad;
712 	int ret;
713 
714 	pad = state->ctrl->desc->pins[pin].drv_data;
715 
716 	if (!pad->is_enabled)
717 		return -EINVAL;
718 
719 	if (pad->input_enabled) {
720 		ret = pmic_gpio_read(state, pad, PMIC_MPP_REG_RT_STS);
721 		if (ret < 0)
722 			return ret;
723 
724 		pad->out_value = ret & PMIC_MPP_REG_RT_STS_VAL_MASK;
725 	}
726 
727 	return !!pad->out_value;
728 }
729 
730 static void pmic_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
731 {
732 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
733 	unsigned long config;
734 
735 	config = pinconf_to_config_packed(PIN_CONFIG_OUTPUT, value);
736 
737 	pmic_gpio_config_set(state->ctrl, pin, &config, 1);
738 }
739 
740 static int pmic_gpio_of_xlate(struct gpio_chip *chip,
741 			      const struct of_phandle_args *gpio_desc,
742 			      u32 *flags)
743 {
744 	if (chip->of_gpio_n_cells < 2)
745 		return -EINVAL;
746 
747 	if (flags)
748 		*flags = gpio_desc->args[1];
749 
750 	return gpio_desc->args[0] - PMIC_GPIO_PHYSICAL_OFFSET;
751 }
752 
753 static void pmic_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
754 {
755 	struct pmic_gpio_state *state = gpiochip_get_data(chip);
756 	unsigned i;
757 
758 	for (i = 0; i < chip->ngpio; i++) {
759 		pmic_gpio_config_dbg_show(state->ctrl, s, i);
760 		seq_puts(s, "\n");
761 	}
762 }
763 
764 static const struct gpio_chip pmic_gpio_gpio_template = {
765 	.direction_input	= pmic_gpio_direction_input,
766 	.direction_output	= pmic_gpio_direction_output,
767 	.get			= pmic_gpio_get,
768 	.set			= pmic_gpio_set,
769 	.request		= gpiochip_generic_request,
770 	.free			= gpiochip_generic_free,
771 	.of_xlate		= pmic_gpio_of_xlate,
772 	.dbg_show		= pmic_gpio_dbg_show,
773 };
774 
775 static int pmic_gpio_populate(struct pmic_gpio_state *state,
776 			      struct pmic_gpio_pad *pad)
777 {
778 	int type, subtype, val, dir;
779 
780 	type = pmic_gpio_read(state, pad, PMIC_GPIO_REG_TYPE);
781 	if (type < 0)
782 		return type;
783 
784 	if (type != PMIC_GPIO_TYPE) {
785 		dev_err(state->dev, "incorrect block type 0x%x at 0x%x\n",
786 			type, pad->base);
787 		return -ENODEV;
788 	}
789 
790 	subtype = pmic_gpio_read(state, pad, PMIC_GPIO_REG_SUBTYPE);
791 	if (subtype < 0)
792 		return subtype;
793 
794 	switch (subtype) {
795 	case PMIC_GPIO_SUBTYPE_GPIO_4CH:
796 		pad->have_buffer = true;
797 		fallthrough;
798 	case PMIC_GPIO_SUBTYPE_GPIOC_4CH:
799 		pad->num_sources = 4;
800 		break;
801 	case PMIC_GPIO_SUBTYPE_GPIO_8CH:
802 		pad->have_buffer = true;
803 		fallthrough;
804 	case PMIC_GPIO_SUBTYPE_GPIOC_8CH:
805 		pad->num_sources = 8;
806 		break;
807 	case PMIC_GPIO_SUBTYPE_GPIO_LV:
808 		pad->num_sources = 1;
809 		pad->have_buffer = true;
810 		pad->lv_mv_type = true;
811 		break;
812 	case PMIC_GPIO_SUBTYPE_GPIO_MV:
813 		pad->num_sources = 2;
814 		pad->have_buffer = true;
815 		pad->lv_mv_type = true;
816 		break;
817 	default:
818 		dev_err(state->dev, "unknown GPIO type 0x%x\n", subtype);
819 		return -ENODEV;
820 	}
821 
822 	if (pad->lv_mv_type) {
823 		val = pmic_gpio_read(state, pad,
824 				PMIC_GPIO_REG_LV_MV_DIG_OUT_SOURCE_CTL);
825 		if (val < 0)
826 			return val;
827 
828 		pad->out_value = !!(val & PMIC_GPIO_LV_MV_OUTPUT_INVERT);
829 		pad->function = val & PMIC_GPIO_LV_MV_OUTPUT_SOURCE_SEL_MASK;
830 
831 		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
832 		if (val < 0)
833 			return val;
834 
835 		dir = val & PMIC_GPIO_REG_LV_MV_MODE_DIR_MASK;
836 	} else {
837 		val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_MODE_CTL);
838 		if (val < 0)
839 			return val;
840 
841 		pad->out_value = val & PMIC_GPIO_REG_MODE_VALUE_SHIFT;
842 
843 		dir = val >> PMIC_GPIO_REG_MODE_DIR_SHIFT;
844 		dir &= PMIC_GPIO_REG_MODE_DIR_MASK;
845 		pad->function = val >> PMIC_GPIO_REG_MODE_FUNCTION_SHIFT;
846 		pad->function &= PMIC_GPIO_REG_MODE_FUNCTION_MASK;
847 	}
848 
849 	switch (dir) {
850 	case PMIC_GPIO_MODE_DIGITAL_INPUT:
851 		pad->input_enabled = true;
852 		pad->output_enabled = false;
853 		break;
854 	case PMIC_GPIO_MODE_DIGITAL_OUTPUT:
855 		pad->input_enabled = false;
856 		pad->output_enabled = true;
857 		break;
858 	case PMIC_GPIO_MODE_DIGITAL_INPUT_OUTPUT:
859 		pad->input_enabled = true;
860 		pad->output_enabled = true;
861 		break;
862 	case PMIC_GPIO_MODE_ANALOG_PASS_THRU:
863 		if (!pad->lv_mv_type)
864 			return -ENODEV;
865 		pad->analog_pass = true;
866 		break;
867 	default:
868 		dev_err(state->dev, "unknown GPIO direction\n");
869 		return -ENODEV;
870 	}
871 
872 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_VIN_CTL);
873 	if (val < 0)
874 		return val;
875 
876 	pad->power_source = val >> PMIC_GPIO_REG_VIN_SHIFT;
877 	pad->power_source &= PMIC_GPIO_REG_VIN_MASK;
878 
879 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_PULL_CTL);
880 	if (val < 0)
881 		return val;
882 
883 	pad->pullup = val >> PMIC_GPIO_REG_PULL_SHIFT;
884 	pad->pullup &= PMIC_GPIO_REG_PULL_MASK;
885 
886 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_IN_CTL);
887 	if (val < 0)
888 		return val;
889 
890 	if (pad->lv_mv_type && (val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_EN))
891 		pad->dtest_buffer =
892 			(val & PMIC_GPIO_LV_MV_DIG_IN_DTEST_SEL_MASK) + 1;
893 	else if (!pad->lv_mv_type)
894 		pad->dtest_buffer = ffs(val);
895 	else
896 		pad->dtest_buffer = 0;
897 
898 	val = pmic_gpio_read(state, pad, PMIC_GPIO_REG_DIG_OUT_CTL);
899 	if (val < 0)
900 		return val;
901 
902 	pad->strength = val >> PMIC_GPIO_REG_OUT_STRENGTH_SHIFT;
903 	pad->strength &= PMIC_GPIO_REG_OUT_STRENGTH_MASK;
904 
905 	pad->buffer_type = val >> PMIC_GPIO_REG_OUT_TYPE_SHIFT;
906 	pad->buffer_type &= PMIC_GPIO_REG_OUT_TYPE_MASK;
907 
908 	if (pad->lv_mv_type) {
909 		val = pmic_gpio_read(state, pad,
910 				PMIC_GPIO_REG_LV_MV_ANA_PASS_THRU_SEL);
911 		if (val < 0)
912 			return val;
913 		pad->atest = (val & PMIC_GPIO_LV_MV_ANA_MUX_SEL_MASK) + 1;
914 	}
915 
916 	/* Pin could be disabled with PIN_CONFIG_BIAS_HIGH_IMPEDANCE */
917 	pad->is_enabled = true;
918 	return 0;
919 }
920 
921 static int pmic_gpio_domain_translate(struct irq_domain *domain,
922 				      struct irq_fwspec *fwspec,
923 				      unsigned long *hwirq,
924 				      unsigned int *type)
925 {
926 	struct pmic_gpio_state *state = container_of(domain->host_data,
927 						     struct pmic_gpio_state,
928 						     chip);
929 
930 	if (fwspec->param_count != 2 ||
931 	    fwspec->param[0] < 1 || fwspec->param[0] > state->chip.ngpio)
932 		return -EINVAL;
933 
934 	*hwirq = fwspec->param[0] - PMIC_GPIO_PHYSICAL_OFFSET;
935 	*type = fwspec->param[1];
936 
937 	return 0;
938 }
939 
940 static unsigned int pmic_gpio_child_offset_to_irq(struct gpio_chip *chip,
941 						  unsigned int offset)
942 {
943 	return offset + PMIC_GPIO_PHYSICAL_OFFSET;
944 }
945 
946 static int pmic_gpio_child_to_parent_hwirq(struct gpio_chip *chip,
947 					   unsigned int child_hwirq,
948 					   unsigned int child_type,
949 					   unsigned int *parent_hwirq,
950 					   unsigned int *parent_type)
951 {
952 	*parent_hwirq = child_hwirq + 0xc0;
953 	*parent_type = child_type;
954 
955 	return 0;
956 }
957 
958 static int pmic_gpio_probe(struct platform_device *pdev)
959 {
960 	struct irq_domain *parent_domain;
961 	struct device_node *parent_node;
962 	struct device *dev = &pdev->dev;
963 	struct pinctrl_pin_desc *pindesc;
964 	struct pinctrl_desc *pctrldesc;
965 	struct pmic_gpio_pad *pad, *pads;
966 	struct pmic_gpio_state *state;
967 	struct gpio_irq_chip *girq;
968 	int ret, npins, i;
969 	u32 reg;
970 
971 	ret = of_property_read_u32(dev->of_node, "reg", &reg);
972 	if (ret < 0) {
973 		dev_err(dev, "missing base address");
974 		return ret;
975 	}
976 
977 	npins = (uintptr_t) device_get_match_data(&pdev->dev);
978 
979 	state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
980 	if (!state)
981 		return -ENOMEM;
982 
983 	platform_set_drvdata(pdev, state);
984 
985 	state->dev = &pdev->dev;
986 	state->map = dev_get_regmap(dev->parent, NULL);
987 
988 	pindesc = devm_kcalloc(dev, npins, sizeof(*pindesc), GFP_KERNEL);
989 	if (!pindesc)
990 		return -ENOMEM;
991 
992 	pads = devm_kcalloc(dev, npins, sizeof(*pads), GFP_KERNEL);
993 	if (!pads)
994 		return -ENOMEM;
995 
996 	pctrldesc = devm_kzalloc(dev, sizeof(*pctrldesc), GFP_KERNEL);
997 	if (!pctrldesc)
998 		return -ENOMEM;
999 
1000 	pctrldesc->pctlops = &pmic_gpio_pinctrl_ops;
1001 	pctrldesc->pmxops = &pmic_gpio_pinmux_ops;
1002 	pctrldesc->confops = &pmic_gpio_pinconf_ops;
1003 	pctrldesc->owner = THIS_MODULE;
1004 	pctrldesc->name = dev_name(dev);
1005 	pctrldesc->pins = pindesc;
1006 	pctrldesc->npins = npins;
1007 	pctrldesc->num_custom_params = ARRAY_SIZE(pmic_gpio_bindings);
1008 	pctrldesc->custom_params = pmic_gpio_bindings;
1009 #ifdef CONFIG_DEBUG_FS
1010 	pctrldesc->custom_conf_items = pmic_conf_items;
1011 #endif
1012 
1013 	for (i = 0; i < npins; i++, pindesc++) {
1014 		pad = &pads[i];
1015 		pindesc->drv_data = pad;
1016 		pindesc->number = i;
1017 		pindesc->name = pmic_gpio_groups[i];
1018 
1019 		pad->base = reg + i * PMIC_GPIO_ADDRESS_RANGE;
1020 
1021 		ret = pmic_gpio_populate(state, pad);
1022 		if (ret < 0)
1023 			return ret;
1024 	}
1025 
1026 	state->chip = pmic_gpio_gpio_template;
1027 	state->chip.parent = dev;
1028 	state->chip.base = -1;
1029 	state->chip.ngpio = npins;
1030 	state->chip.label = dev_name(dev);
1031 	state->chip.of_gpio_n_cells = 2;
1032 	state->chip.can_sleep = false;
1033 
1034 	state->ctrl = devm_pinctrl_register(dev, pctrldesc, state);
1035 	if (IS_ERR(state->ctrl))
1036 		return PTR_ERR(state->ctrl);
1037 
1038 	parent_node = of_irq_find_parent(state->dev->of_node);
1039 	if (!parent_node)
1040 		return -ENXIO;
1041 
1042 	parent_domain = irq_find_host(parent_node);
1043 	of_node_put(parent_node);
1044 	if (!parent_domain)
1045 		return -ENXIO;
1046 
1047 	state->irq.name = "spmi-gpio",
1048 	state->irq.irq_ack = irq_chip_ack_parent,
1049 	state->irq.irq_mask = irq_chip_mask_parent,
1050 	state->irq.irq_unmask = irq_chip_unmask_parent,
1051 	state->irq.irq_set_type = irq_chip_set_type_parent,
1052 	state->irq.irq_set_wake = irq_chip_set_wake_parent,
1053 	state->irq.flags = IRQCHIP_MASK_ON_SUSPEND,
1054 
1055 	girq = &state->chip.irq;
1056 	girq->chip = &state->irq;
1057 	girq->default_type = IRQ_TYPE_NONE;
1058 	girq->handler = handle_level_irq;
1059 	girq->fwnode = of_node_to_fwnode(state->dev->of_node);
1060 	girq->parent_domain = parent_domain;
1061 	girq->child_to_parent_hwirq = pmic_gpio_child_to_parent_hwirq;
1062 	girq->populate_parent_alloc_arg = gpiochip_populate_parent_fwspec_fourcell;
1063 	girq->child_offset_to_irq = pmic_gpio_child_offset_to_irq;
1064 	girq->child_irq_domain_ops.translate = pmic_gpio_domain_translate;
1065 
1066 	ret = gpiochip_add_data(&state->chip, state);
1067 	if (ret) {
1068 		dev_err(state->dev, "can't add gpio chip\n");
1069 		return ret;
1070 	}
1071 
1072 	/*
1073 	 * For DeviceTree-supported systems, the gpio core checks the
1074 	 * pinctrl's device node for the "gpio-ranges" property.
1075 	 * If it is present, it takes care of adding the pin ranges
1076 	 * for the driver. In this case the driver can skip ahead.
1077 	 *
1078 	 * In order to remain compatible with older, existing DeviceTree
1079 	 * files which don't set the "gpio-ranges" property or systems that
1080 	 * utilize ACPI the driver has to call gpiochip_add_pin_range().
1081 	 */
1082 	if (!of_property_read_bool(dev->of_node, "gpio-ranges")) {
1083 		ret = gpiochip_add_pin_range(&state->chip, dev_name(dev), 0, 0,
1084 					     npins);
1085 		if (ret) {
1086 			dev_err(dev, "failed to add pin range\n");
1087 			goto err_range;
1088 		}
1089 	}
1090 
1091 	return 0;
1092 
1093 err_range:
1094 	gpiochip_remove(&state->chip);
1095 	return ret;
1096 }
1097 
1098 static int pmic_gpio_remove(struct platform_device *pdev)
1099 {
1100 	struct pmic_gpio_state *state = platform_get_drvdata(pdev);
1101 
1102 	gpiochip_remove(&state->chip);
1103 	return 0;
1104 }
1105 
1106 static const struct of_device_id pmic_gpio_of_match[] = {
1107 	{ .compatible = "qcom,pm8005-gpio", .data = (void *) 4 },
1108 	{ .compatible = "qcom,pm8916-gpio", .data = (void *) 4 },
1109 	{ .compatible = "qcom,pm8941-gpio", .data = (void *) 36 },
1110 	/* pm8950 has 8 GPIOs with holes on 3 */
1111 	{ .compatible = "qcom,pm8950-gpio", .data = (void *) 8 },
1112 	{ .compatible = "qcom,pmi8950-gpio", .data = (void *) 2 },
1113 	{ .compatible = "qcom,pm8994-gpio", .data = (void *) 22 },
1114 	{ .compatible = "qcom,pmi8994-gpio", .data = (void *) 10 },
1115 	{ .compatible = "qcom,pm8998-gpio", .data = (void *) 26 },
1116 	{ .compatible = "qcom,pmi8998-gpio", .data = (void *) 14 },
1117 	{ .compatible = "qcom,pma8084-gpio", .data = (void *) 22 },
1118 	/* pms405 has 12 GPIOs with holes on 1, 9, and 10 */
1119 	{ .compatible = "qcom,pms405-gpio", .data = (void *) 12 },
1120 	/* pm660 has 13 GPIOs with holes on 1, 5, 6, 7, 8 and 10 */
1121 	{ .compatible = "qcom,pm660-gpio", .data = (void *) 13 },
1122 	/* pm660l has 12 GPIOs with holes on 1, 2, 10, 11 and 12 */
1123 	{ .compatible = "qcom,pm660l-gpio", .data = (void *) 12 },
1124 	/* pm8150 has 10 GPIOs with holes on 2, 5, 7 and 8 */
1125 	{ .compatible = "qcom,pm8150-gpio", .data = (void *) 10 },
1126 	/* pm8150b has 12 GPIOs with holes on 3, r and 7 */
1127 	{ .compatible = "qcom,pm8150b-gpio", .data = (void *) 12 },
1128 	/* pm8150l has 12 GPIOs with holes on 7 */
1129 	{ .compatible = "qcom,pm8150l-gpio", .data = (void *) 12 },
1130 	{ .compatible = "qcom,pm8350-gpio", .data = (void *) 10 },
1131 	{ .compatible = "qcom,pm8350b-gpio", .data = (void *) 8 },
1132 	{ .compatible = "qcom,pm8350c-gpio", .data = (void *) 9 },
1133 	{ .compatible = "qcom,pmk8350-gpio", .data = (void *) 4 },
1134 	{ .compatible = "qcom,pmr735a-gpio", .data = (void *) 4 },
1135 	{ .compatible = "qcom,pmr735b-gpio", .data = (void *) 4 },
1136 	{ .compatible = "qcom,pm6150-gpio", .data = (void *) 10 },
1137 	{ .compatible = "qcom,pm6150l-gpio", .data = (void *) 12 },
1138 	{ .compatible = "qcom,pm8008-gpio", .data = (void *) 2 },
1139 	/* pmx55 has 11 GPIOs with holes on 3, 7, 10, 11 */
1140 	{ .compatible = "qcom,pmx55-gpio", .data = (void *) 11 },
1141 	{ },
1142 };
1143 
1144 MODULE_DEVICE_TABLE(of, pmic_gpio_of_match);
1145 
1146 static struct platform_driver pmic_gpio_driver = {
1147 	.driver = {
1148 		   .name = "qcom-spmi-gpio",
1149 		   .of_match_table = pmic_gpio_of_match,
1150 	},
1151 	.probe	= pmic_gpio_probe,
1152 	.remove = pmic_gpio_remove,
1153 };
1154 
1155 module_platform_driver(pmic_gpio_driver);
1156 
1157 MODULE_AUTHOR("Ivan T. Ivanov <iivanov@mm-sol.com>");
1158 MODULE_DESCRIPTION("Qualcomm SPMI PMIC GPIO pin control driver");
1159 MODULE_ALIAS("platform:qcom-spmi-gpio");
1160 MODULE_LICENSE("GPL v2");
1161