1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Microsemi/Microchip SoCs serial gpio driver 4 * 5 * Author: Lars Povlsen <lars.povlsen@microchip.com> 6 * 7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/clk.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/io.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/reset.h> 21 22 #include "core.h" 23 #include "pinconf.h" 24 25 #define SGPIO_BITS_PER_WORD 32 26 #define SGPIO_MAX_BITS 4 27 #define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */ 28 29 enum { 30 REG_INPUT_DATA, 31 REG_PORT_CONFIG, 32 REG_PORT_ENABLE, 33 REG_SIO_CONFIG, 34 REG_SIO_CLOCK, 35 REG_INT_POLARITY, 36 REG_INT_TRIGGER, 37 REG_INT_ACK, 38 REG_INT_ENABLE, 39 REG_INT_IDENT, 40 MAXREG 41 }; 42 43 enum { 44 SGPIO_ARCH_LUTON, 45 SGPIO_ARCH_OCELOT, 46 SGPIO_ARCH_SPARX5, 47 }; 48 49 enum { 50 SGPIO_FLAGS_HAS_IRQ = BIT(0), 51 }; 52 53 struct sgpio_properties { 54 int arch; 55 int flags; 56 u8 regoff[MAXREG]; 57 }; 58 59 #define SGPIO_LUTON_AUTO_REPEAT BIT(5) 60 #define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2) 61 #define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0) 62 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0) 63 64 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10) 65 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7) 66 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8) 67 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12) 68 69 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6) 70 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3) 71 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) 72 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) 73 74 #define SGPIO_MASTER_INTR_ENA BIT(0) 75 76 #define SGPIO_INT_TRG_LEVEL 0 77 #define SGPIO_INT_TRG_EDGE 1 78 #define SGPIO_INT_TRG_EDGE_FALL 2 79 #define SGPIO_INT_TRG_EDGE_RISE 3 80 81 #define SGPIO_TRG_LEVEL_HIGH 0 82 #define SGPIO_TRG_LEVEL_LOW 1 83 84 static const struct sgpio_properties properties_luton = { 85 .arch = SGPIO_ARCH_LUTON, 86 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b }, 87 }; 88 89 static const struct sgpio_properties properties_ocelot = { 90 .arch = SGPIO_ARCH_OCELOT, 91 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, 92 }; 93 94 static const struct sgpio_properties properties_sparx5 = { 95 .arch = SGPIO_ARCH_SPARX5, 96 .flags = SGPIO_FLAGS_HAS_IRQ, 97 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 }, 98 }; 99 100 static const char * const functions[] = { "gpio" }; 101 102 struct sgpio_bank { 103 struct sgpio_priv *priv; 104 bool is_input; 105 struct gpio_chip gpio; 106 struct pinctrl_desc pctl_desc; 107 }; 108 109 struct sgpio_priv { 110 struct device *dev; 111 struct sgpio_bank in; 112 struct sgpio_bank out; 113 u32 bitcount; 114 u32 ports; 115 u32 clock; 116 u32 __iomem *regs; 117 const struct sgpio_properties *properties; 118 }; 119 120 struct sgpio_port_addr { 121 u8 port; 122 u8 bit; 123 }; 124 125 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin, 126 struct sgpio_port_addr *addr) 127 { 128 addr->port = pin / priv->bitcount; 129 addr->bit = pin % priv->bitcount; 130 } 131 132 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit) 133 { 134 return bit + port * priv->bitcount; 135 } 136 137 static inline u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) 138 { 139 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; 140 141 return readl(reg); 142 } 143 144 static inline void sgpio_writel(struct sgpio_priv *priv, 145 u32 val, u32 rno, u32 off) 146 { 147 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; 148 149 writel(val, reg); 150 } 151 152 static inline void sgpio_clrsetbits(struct sgpio_priv *priv, 153 u32 rno, u32 off, u32 clear, u32 set) 154 { 155 u32 __iomem *reg = &priv->regs[priv->properties->regoff[rno] + off]; 156 u32 val = readl(reg); 157 158 val &= ~clear; 159 val |= set; 160 161 writel(val, reg); 162 } 163 164 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) 165 { 166 int width = priv->bitcount - 1; 167 u32 clr, set; 168 169 switch (priv->properties->arch) { 170 case SGPIO_ARCH_LUTON: 171 clr = SGPIO_LUTON_PORT_WIDTH; 172 set = SGPIO_LUTON_AUTO_REPEAT | 173 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width); 174 break; 175 case SGPIO_ARCH_OCELOT: 176 clr = SGPIO_OCELOT_PORT_WIDTH; 177 set = SGPIO_OCELOT_AUTO_REPEAT | 178 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width); 179 break; 180 case SGPIO_ARCH_SPARX5: 181 clr = SGPIO_SPARX5_PORT_WIDTH; 182 set = SGPIO_SPARX5_AUTO_REPEAT | 183 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width); 184 break; 185 default: 186 return; 187 } 188 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); 189 } 190 191 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) 192 { 193 u32 clr, set; 194 195 switch (priv->properties->arch) { 196 case SGPIO_ARCH_LUTON: 197 clr = SGPIO_LUTON_CLK_FREQ; 198 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq); 199 break; 200 case SGPIO_ARCH_OCELOT: 201 clr = SGPIO_OCELOT_CLK_FREQ; 202 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq); 203 break; 204 case SGPIO_ARCH_SPARX5: 205 clr = SGPIO_SPARX5_CLK_FREQ; 206 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq); 207 break; 208 default: 209 return; 210 } 211 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); 212 } 213 214 static void sgpio_output_set(struct sgpio_priv *priv, 215 struct sgpio_port_addr *addr, 216 int value) 217 { 218 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 219 u32 clr, set; 220 221 switch (priv->properties->arch) { 222 case SGPIO_ARCH_LUTON: 223 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit)); 224 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit); 225 break; 226 case SGPIO_ARCH_OCELOT: 227 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit)); 228 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit); 229 break; 230 case SGPIO_ARCH_SPARX5: 231 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit)); 232 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit); 233 break; 234 default: 235 return; 236 } 237 sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set); 238 } 239 240 static int sgpio_output_get(struct sgpio_priv *priv, 241 struct sgpio_port_addr *addr) 242 { 243 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port); 244 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 245 246 switch (priv->properties->arch) { 247 case SGPIO_ARCH_LUTON: 248 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval); 249 break; 250 case SGPIO_ARCH_OCELOT: 251 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval); 252 break; 253 case SGPIO_ARCH_SPARX5: 254 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval); 255 break; 256 default: 257 val = 0; 258 break; 259 } 260 return !!(val & BIT(bit)); 261 } 262 263 static int sgpio_input_get(struct sgpio_priv *priv, 264 struct sgpio_port_addr *addr) 265 { 266 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port)); 267 } 268 269 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev, 270 unsigned int pin, unsigned long *config) 271 { 272 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 273 u32 param = pinconf_to_config_param(*config); 274 struct sgpio_priv *priv = bank->priv; 275 struct sgpio_port_addr addr; 276 int val; 277 278 sgpio_pin_to_addr(priv, pin, &addr); 279 280 switch (param) { 281 case PIN_CONFIG_INPUT_ENABLE: 282 val = bank->is_input; 283 break; 284 285 case PIN_CONFIG_OUTPUT_ENABLE: 286 val = !bank->is_input; 287 break; 288 289 case PIN_CONFIG_OUTPUT: 290 if (bank->is_input) 291 return -EINVAL; 292 val = sgpio_output_get(priv, &addr); 293 break; 294 295 default: 296 return -ENOTSUPP; 297 } 298 299 *config = pinconf_to_config_packed(param, val); 300 301 return 0; 302 } 303 304 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 305 unsigned long *configs, unsigned int num_configs) 306 { 307 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 308 struct sgpio_priv *priv = bank->priv; 309 struct sgpio_port_addr addr; 310 int cfg, err = 0; 311 u32 param, arg; 312 313 sgpio_pin_to_addr(priv, pin, &addr); 314 315 for (cfg = 0; cfg < num_configs; cfg++) { 316 param = pinconf_to_config_param(configs[cfg]); 317 arg = pinconf_to_config_argument(configs[cfg]); 318 319 switch (param) { 320 case PIN_CONFIG_OUTPUT: 321 if (bank->is_input) 322 return -EINVAL; 323 sgpio_output_set(priv, &addr, arg); 324 break; 325 326 default: 327 err = -ENOTSUPP; 328 } 329 } 330 331 return err; 332 } 333 334 static const struct pinconf_ops sgpio_confops = { 335 .is_generic = true, 336 .pin_config_get = sgpio_pinconf_get, 337 .pin_config_set = sgpio_pinconf_set, 338 .pin_config_config_dbg_show = pinconf_generic_dump_config, 339 }; 340 341 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev) 342 { 343 return 1; 344 } 345 346 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev, 347 unsigned int function) 348 { 349 return functions[0]; 350 } 351 352 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev, 353 unsigned int function, 354 const char *const **groups, 355 unsigned *const num_groups) 356 { 357 *groups = functions; 358 *num_groups = ARRAY_SIZE(functions); 359 360 return 0; 361 } 362 363 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev, 364 unsigned int selector, unsigned int group) 365 { 366 return 0; 367 } 368 369 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev, 370 struct pinctrl_gpio_range *range, 371 unsigned int pin, bool input) 372 { 373 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 374 375 return (input == bank->is_input) ? 0 : -EINVAL; 376 } 377 378 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev, 379 struct pinctrl_gpio_range *range, 380 unsigned int offset) 381 { 382 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 383 struct sgpio_priv *priv = bank->priv; 384 struct sgpio_port_addr addr; 385 386 sgpio_pin_to_addr(priv, offset, &addr); 387 388 if ((priv->ports & BIT(addr.port)) == 0) { 389 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n", 390 addr.port, addr.bit); 391 return -EINVAL; 392 } 393 394 return 0; 395 } 396 397 static const struct pinmux_ops sgpio_pmx_ops = { 398 .get_functions_count = sgpio_get_functions_count, 399 .get_function_name = sgpio_get_function_name, 400 .get_function_groups = sgpio_get_function_groups, 401 .set_mux = sgpio_pinmux_set_mux, 402 .gpio_set_direction = sgpio_gpio_set_direction, 403 .gpio_request_enable = sgpio_gpio_request_enable, 404 }; 405 406 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev) 407 { 408 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 409 410 return bank->pctl_desc.npins; 411 } 412 413 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev, 414 unsigned int group) 415 { 416 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 417 418 return bank->pctl_desc.pins[group].name; 419 } 420 421 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev, 422 unsigned int group, 423 const unsigned int **pins, 424 unsigned int *num_pins) 425 { 426 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 427 428 *pins = &bank->pctl_desc.pins[group].number; 429 *num_pins = 1; 430 431 return 0; 432 } 433 434 static const struct pinctrl_ops sgpio_pctl_ops = { 435 .get_groups_count = sgpio_pctl_get_groups_count, 436 .get_group_name = sgpio_pctl_get_group_name, 437 .get_group_pins = sgpio_pctl_get_group_pins, 438 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 439 .dt_free_map = pinconf_generic_dt_free_map, 440 }; 441 442 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio) 443 { 444 struct sgpio_bank *bank = gpiochip_get_data(gc); 445 446 /* Fixed-position function */ 447 return bank->is_input ? 0 : -EINVAL; 448 } 449 450 static int microchip_sgpio_direction_output(struct gpio_chip *gc, 451 unsigned int gpio, int value) 452 { 453 struct sgpio_bank *bank = gpiochip_get_data(gc); 454 struct sgpio_priv *priv = bank->priv; 455 struct sgpio_port_addr addr; 456 457 /* Fixed-position function */ 458 if (bank->is_input) 459 return -EINVAL; 460 461 sgpio_pin_to_addr(priv, gpio, &addr); 462 463 sgpio_output_set(priv, &addr, value); 464 465 return 0; 466 } 467 468 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 469 { 470 struct sgpio_bank *bank = gpiochip_get_data(gc); 471 472 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 473 } 474 475 static void microchip_sgpio_set_value(struct gpio_chip *gc, 476 unsigned int gpio, int value) 477 { 478 microchip_sgpio_direction_output(gc, gpio, value); 479 } 480 481 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio) 482 { 483 struct sgpio_bank *bank = gpiochip_get_data(gc); 484 struct sgpio_priv *priv = bank->priv; 485 struct sgpio_port_addr addr; 486 487 sgpio_pin_to_addr(priv, gpio, &addr); 488 489 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr); 490 } 491 492 static int microchip_sgpio_of_xlate(struct gpio_chip *gc, 493 const struct of_phandle_args *gpiospec, 494 u32 *flags) 495 { 496 struct sgpio_bank *bank = gpiochip_get_data(gc); 497 struct sgpio_priv *priv = bank->priv; 498 int pin; 499 500 /* 501 * Note that the SGIO pin is defined by *2* numbers, a port 502 * number between 0 and 31, and a bit index, 0 to 3. 503 */ 504 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD || 505 gpiospec->args[1] > priv->bitcount) 506 return -EINVAL; 507 508 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]); 509 510 if (pin > gc->ngpio) 511 return -EINVAL; 512 513 if (flags) 514 *flags = gpiospec->args[2]; 515 516 return pin; 517 } 518 519 static int microchip_sgpio_get_ports(struct sgpio_priv *priv) 520 { 521 const char *range_property_name = "microchip,sgpio-port-ranges"; 522 struct device *dev = priv->dev; 523 u32 range_params[64]; 524 int i, nranges, ret; 525 526 /* Calculate port mask */ 527 nranges = device_property_count_u32(dev, range_property_name); 528 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) { 529 dev_err(dev, "%s port range: '%s' property\n", 530 nranges == -EINVAL ? "Missing" : "Invalid", 531 range_property_name); 532 return -EINVAL; 533 } 534 535 ret = device_property_read_u32_array(dev, range_property_name, 536 range_params, nranges); 537 if (ret) { 538 dev_err(dev, "failed to parse '%s' property: %d\n", 539 range_property_name, ret); 540 return ret; 541 } 542 for (i = 0; i < nranges; i += 2) { 543 int start, end; 544 545 start = range_params[i]; 546 end = range_params[i + 1]; 547 if (start > end || end >= SGPIO_BITS_PER_WORD) { 548 dev_err(dev, "Ill-formed port-range [%d:%d]\n", 549 start, end); 550 } 551 priv->ports |= GENMASK(end, start); 552 } 553 554 return 0; 555 } 556 557 static void microchip_sgpio_irq_settype(struct irq_data *data, 558 int type, 559 int polarity) 560 { 561 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 562 struct sgpio_bank *bank = gpiochip_get_data(chip); 563 unsigned int gpio = irqd_to_hwirq(data); 564 struct sgpio_port_addr addr; 565 u32 ena; 566 567 sgpio_pin_to_addr(bank->priv, gpio, &addr); 568 569 /* Disable interrupt while changing type */ 570 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit); 571 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit); 572 573 /* Type value spread over 2 registers sets: low, high bit */ 574 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit, 575 BIT(addr.port), (!!(type & 0x1)) << addr.port); 576 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit, 577 BIT(addr.port), (!!(type & 0x2)) << addr.port); 578 579 if (type == SGPIO_INT_TRG_LEVEL) 580 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit, 581 BIT(addr.port), polarity << addr.port); 582 583 /* Possibly re-enable interrupts */ 584 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit); 585 } 586 587 static void microchip_sgpio_irq_setreg(struct irq_data *data, 588 int reg, 589 bool clear) 590 { 591 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 592 struct sgpio_bank *bank = gpiochip_get_data(chip); 593 unsigned int gpio = irqd_to_hwirq(data); 594 struct sgpio_port_addr addr; 595 596 sgpio_pin_to_addr(bank->priv, gpio, &addr); 597 598 if (clear) 599 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0); 600 else 601 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port)); 602 } 603 604 static void microchip_sgpio_irq_mask(struct irq_data *data) 605 { 606 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true); 607 } 608 609 static void microchip_sgpio_irq_unmask(struct irq_data *data) 610 { 611 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false); 612 } 613 614 static void microchip_sgpio_irq_ack(struct irq_data *data) 615 { 616 microchip_sgpio_irq_setreg(data, REG_INT_ACK, false); 617 } 618 619 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type) 620 { 621 type &= IRQ_TYPE_SENSE_MASK; 622 623 switch (type) { 624 case IRQ_TYPE_EDGE_BOTH: 625 irq_set_handler_locked(data, handle_edge_irq); 626 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0); 627 break; 628 case IRQ_TYPE_EDGE_RISING: 629 irq_set_handler_locked(data, handle_edge_irq); 630 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0); 631 break; 632 case IRQ_TYPE_EDGE_FALLING: 633 irq_set_handler_locked(data, handle_edge_irq); 634 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0); 635 break; 636 case IRQ_TYPE_LEVEL_HIGH: 637 irq_set_handler_locked(data, handle_level_irq); 638 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH); 639 break; 640 case IRQ_TYPE_LEVEL_LOW: 641 irq_set_handler_locked(data, handle_level_irq); 642 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW); 643 break; 644 default: 645 return -EINVAL; 646 } 647 648 return 0; 649 } 650 651 static const struct irq_chip microchip_sgpio_irqchip = { 652 .name = "gpio", 653 .irq_mask = microchip_sgpio_irq_mask, 654 .irq_ack = microchip_sgpio_irq_ack, 655 .irq_unmask = microchip_sgpio_irq_unmask, 656 .irq_set_type = microchip_sgpio_irq_set_type, 657 }; 658 659 static void sgpio_irq_handler(struct irq_desc *desc) 660 { 661 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 662 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 663 struct sgpio_bank *bank = gpiochip_get_data(chip); 664 struct sgpio_priv *priv = bank->priv; 665 int bit, port, gpio; 666 long val; 667 668 for (bit = 0; bit < priv->bitcount; bit++) { 669 val = sgpio_readl(priv, REG_INT_IDENT, bit); 670 if (!val) 671 continue; 672 673 chained_irq_enter(parent_chip, desc); 674 675 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) { 676 gpio = sgpio_addr_to_pin(priv, port, bit); 677 generic_handle_domain_irq(chip->irq.domain, gpio); 678 } 679 680 chained_irq_exit(parent_chip, desc); 681 } 682 } 683 684 static int microchip_sgpio_register_bank(struct device *dev, 685 struct sgpio_priv *priv, 686 struct fwnode_handle *fwnode, 687 int bankno) 688 { 689 struct pinctrl_pin_desc *pins; 690 struct pinctrl_desc *pctl_desc; 691 struct pinctrl_dev *pctldev; 692 struct sgpio_bank *bank; 693 struct gpio_chip *gc; 694 u32 ngpios; 695 int i, ret; 696 697 /* Get overall bank struct */ 698 bank = (bankno == 0) ? &priv->in : &priv->out; 699 bank->priv = priv; 700 701 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) { 702 dev_info(dev, "failed to get number of gpios for bank%d\n", 703 bankno); 704 ngpios = 64; 705 } 706 707 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD; 708 if (priv->bitcount > SGPIO_MAX_BITS) { 709 dev_err(dev, "Bit width exceeds maximum (%d)\n", 710 SGPIO_MAX_BITS); 711 return -EINVAL; 712 } 713 714 pctl_desc = &bank->pctl_desc; 715 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput", 716 dev_name(dev), 717 bank->is_input ? "in" : "out"); 718 pctl_desc->pctlops = &sgpio_pctl_ops; 719 pctl_desc->pmxops = &sgpio_pmx_ops; 720 pctl_desc->confops = &sgpio_confops; 721 pctl_desc->owner = THIS_MODULE; 722 723 pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL); 724 if (!pins) 725 return -ENOMEM; 726 727 pctl_desc->npins = ngpios; 728 pctl_desc->pins = pins; 729 730 for (i = 0; i < ngpios; i++) { 731 struct sgpio_port_addr addr; 732 733 sgpio_pin_to_addr(priv, i, &addr); 734 735 pins[i].number = i; 736 pins[i].name = devm_kasprintf(dev, GFP_KERNEL, 737 "SGPIO_%c_p%db%d", 738 bank->is_input ? 'I' : 'O', 739 addr.port, addr.bit); 740 if (!pins[i].name) 741 return -ENOMEM; 742 } 743 744 pctldev = devm_pinctrl_register(dev, pctl_desc, bank); 745 if (IS_ERR(pctldev)) 746 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n"); 747 748 gc = &bank->gpio; 749 gc->label = pctl_desc->name; 750 gc->parent = dev; 751 gc->of_node = to_of_node(fwnode); 752 gc->owner = THIS_MODULE; 753 gc->get_direction = microchip_sgpio_get_direction; 754 gc->direction_input = microchip_sgpio_direction_input; 755 gc->direction_output = microchip_sgpio_direction_output; 756 gc->get = microchip_sgpio_get_value; 757 gc->set = microchip_sgpio_set_value; 758 gc->request = gpiochip_generic_request; 759 gc->free = gpiochip_generic_free; 760 gc->of_xlate = microchip_sgpio_of_xlate; 761 gc->of_gpio_n_cells = 3; 762 gc->base = -1; 763 gc->ngpio = ngpios; 764 765 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) { 766 int irq = fwnode_irq_get(fwnode, 0); 767 768 if (irq) { 769 struct gpio_irq_chip *girq = &gc->irq; 770 771 girq->chip = devm_kmemdup(dev, µchip_sgpio_irqchip, 772 sizeof(microchip_sgpio_irqchip), 773 GFP_KERNEL); 774 if (!girq->chip) 775 return -ENOMEM; 776 girq->parent_handler = sgpio_irq_handler; 777 girq->num_parents = 1; 778 girq->parents = devm_kcalloc(dev, 1, 779 sizeof(*girq->parents), 780 GFP_KERNEL); 781 if (!girq->parents) 782 return -ENOMEM; 783 girq->parents[0] = irq; 784 girq->default_type = IRQ_TYPE_NONE; 785 girq->handler = handle_bad_irq; 786 787 /* Disable all individual pins */ 788 for (i = 0; i < SGPIO_MAX_BITS; i++) 789 sgpio_writel(priv, 0, REG_INT_ENABLE, i); 790 /* Master enable */ 791 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA); 792 } 793 } 794 795 ret = devm_gpiochip_add_data(dev, gc, bank); 796 if (ret) 797 dev_err(dev, "Failed to register: ret %d\n", ret); 798 799 return ret; 800 } 801 802 static int microchip_sgpio_probe(struct platform_device *pdev) 803 { 804 int div_clock = 0, ret, port, i, nbanks; 805 struct device *dev = &pdev->dev; 806 struct fwnode_handle *fwnode; 807 struct reset_control *reset; 808 struct sgpio_priv *priv; 809 struct clk *clk; 810 u32 val; 811 812 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 813 if (!priv) 814 return -ENOMEM; 815 816 priv->dev = dev; 817 818 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); 819 if (IS_ERR(reset)) 820 return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n"); 821 reset_control_reset(reset); 822 823 clk = devm_clk_get(dev, NULL); 824 if (IS_ERR(clk)) 825 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n"); 826 827 div_clock = clk_get_rate(clk); 828 if (device_property_read_u32(dev, "bus-frequency", &priv->clock)) 829 priv->clock = 12500000; 830 if (priv->clock == 0 || priv->clock > (div_clock / 2)) { 831 dev_err(dev, "Invalid frequency %d\n", priv->clock); 832 return -EINVAL; 833 } 834 835 priv->regs = devm_platform_ioremap_resource(pdev, 0); 836 if (IS_ERR(priv->regs)) 837 return PTR_ERR(priv->regs); 838 priv->properties = device_get_match_data(dev); 839 priv->in.is_input = true; 840 841 /* Get rest of device properties */ 842 ret = microchip_sgpio_get_ports(priv); 843 if (ret) 844 return ret; 845 846 nbanks = device_get_child_node_count(dev); 847 if (nbanks != 2) { 848 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks); 849 return -EINVAL; 850 } 851 852 i = 0; 853 device_for_each_child_node(dev, fwnode) { 854 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++); 855 if (ret) { 856 fwnode_handle_put(fwnode); 857 return ret; 858 } 859 } 860 861 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) { 862 dev_err(dev, "Banks must have same GPIO count\n"); 863 return -ERANGE; 864 } 865 866 sgpio_configure_bitstream(priv); 867 868 val = max(2U, div_clock / priv->clock); 869 sgpio_configure_clock(priv, val); 870 871 for (port = 0; port < SGPIO_BITS_PER_WORD; port++) 872 sgpio_writel(priv, 0, REG_PORT_CONFIG, port); 873 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0); 874 875 return 0; 876 } 877 878 static const struct of_device_id microchip_sgpio_gpio_of_match[] = { 879 { 880 .compatible = "microchip,sparx5-sgpio", 881 .data = &properties_sparx5, 882 }, { 883 .compatible = "mscc,luton-sgpio", 884 .data = &properties_luton, 885 }, { 886 .compatible = "mscc,ocelot-sgpio", 887 .data = &properties_ocelot, 888 }, { 889 /* sentinel */ 890 } 891 }; 892 893 static struct platform_driver microchip_sgpio_pinctrl_driver = { 894 .driver = { 895 .name = "pinctrl-microchip-sgpio", 896 .of_match_table = microchip_sgpio_gpio_of_match, 897 .suppress_bind_attrs = true, 898 }, 899 .probe = microchip_sgpio_probe, 900 }; 901 builtin_platform_driver(microchip_sgpio_pinctrl_driver); 902