1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Microsemi/Microchip SoCs serial gpio driver 4 * 5 * Author: Lars Povlsen <lars.povlsen@microchip.com> 6 * 7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/clk.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/io.h> 15 #include <linux/mfd/ocelot.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/pinctrl/pinmux.h> 19 #include <linux/platform_device.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/reset.h> 23 #include <linux/spinlock.h> 24 25 #include "core.h" 26 #include "pinconf.h" 27 28 #define SGPIO_BITS_PER_WORD 32 29 #define SGPIO_MAX_BITS 4 30 #define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */ 31 32 enum { 33 REG_INPUT_DATA, 34 REG_PORT_CONFIG, 35 REG_PORT_ENABLE, 36 REG_SIO_CONFIG, 37 REG_SIO_CLOCK, 38 REG_INT_POLARITY, 39 REG_INT_TRIGGER, 40 REG_INT_ACK, 41 REG_INT_ENABLE, 42 REG_INT_IDENT, 43 MAXREG 44 }; 45 46 enum { 47 SGPIO_ARCH_LUTON, 48 SGPIO_ARCH_OCELOT, 49 SGPIO_ARCH_SPARX5, 50 }; 51 52 enum { 53 SGPIO_FLAGS_HAS_IRQ = BIT(0), 54 }; 55 56 struct sgpio_properties { 57 int arch; 58 int flags; 59 u8 regoff[MAXREG]; 60 }; 61 62 #define SGPIO_LUTON_AUTO_REPEAT BIT(5) 63 #define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2) 64 #define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0) 65 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0) 66 67 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10) 68 #define SGPIO_OCELOT_SINGLE_SHOT BIT(11) 69 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7) 70 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8) 71 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12) 72 73 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6) 74 #define SGPIO_SPARX5_SINGLE_SHOT BIT(7) 75 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3) 76 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) 77 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) 78 79 #define SGPIO_MASTER_INTR_ENA BIT(0) 80 81 #define SGPIO_INT_TRG_LEVEL 0 82 #define SGPIO_INT_TRG_EDGE 1 83 #define SGPIO_INT_TRG_EDGE_FALL 2 84 #define SGPIO_INT_TRG_EDGE_RISE 3 85 86 #define SGPIO_TRG_LEVEL_HIGH 0 87 #define SGPIO_TRG_LEVEL_LOW 1 88 89 static const struct sgpio_properties properties_luton = { 90 .arch = SGPIO_ARCH_LUTON, 91 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b }, 92 }; 93 94 static const struct sgpio_properties properties_ocelot = { 95 .arch = SGPIO_ARCH_OCELOT, 96 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, 97 }; 98 99 static const struct sgpio_properties properties_sparx5 = { 100 .arch = SGPIO_ARCH_SPARX5, 101 .flags = SGPIO_FLAGS_HAS_IRQ, 102 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 }, 103 }; 104 105 static const char * const functions[] = { "gpio" }; 106 107 struct sgpio_bank { 108 struct sgpio_priv *priv; 109 bool is_input; 110 struct gpio_chip gpio; 111 struct pinctrl_desc pctl_desc; 112 }; 113 114 struct sgpio_priv { 115 struct device *dev; 116 struct sgpio_bank in; 117 struct sgpio_bank out; 118 u32 bitcount; 119 u32 ports; 120 u32 clock; 121 struct regmap *regs; 122 const struct sgpio_properties *properties; 123 spinlock_t lock; 124 /* protects the config register and single shot mode */ 125 struct mutex poll_lock; 126 }; 127 128 struct sgpio_port_addr { 129 u8 port; 130 u8 bit; 131 }; 132 133 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin, 134 struct sgpio_port_addr *addr) 135 { 136 addr->port = pin / priv->bitcount; 137 addr->bit = pin % priv->bitcount; 138 } 139 140 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit) 141 { 142 return bit + port * priv->bitcount; 143 } 144 145 static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off) 146 { 147 return (priv->properties->regoff[rno] + off) * 148 regmap_get_reg_stride(priv->regs); 149 } 150 151 static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) 152 { 153 u32 addr = sgpio_get_addr(priv, rno, off); 154 u32 val = 0; 155 int ret; 156 157 ret = regmap_read(priv->regs, addr, &val); 158 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret); 159 160 return val; 161 } 162 163 static void sgpio_writel(struct sgpio_priv *priv, 164 u32 val, u32 rno, u32 off) 165 { 166 u32 addr = sgpio_get_addr(priv, rno, off); 167 int ret; 168 169 ret = regmap_write(priv->regs, addr, val); 170 WARN_ONCE(ret, "error writing sgpio reg %d\n", ret); 171 } 172 173 static inline void sgpio_clrsetbits(struct sgpio_priv *priv, 174 u32 rno, u32 off, u32 clear, u32 set) 175 { 176 u32 addr = sgpio_get_addr(priv, rno, off); 177 int ret; 178 179 ret = regmap_update_bits(priv->regs, addr, clear | set, set); 180 WARN_ONCE(ret, "error updating sgpio reg %d\n", ret); 181 } 182 183 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) 184 { 185 int width = priv->bitcount - 1; 186 u32 clr, set; 187 188 switch (priv->properties->arch) { 189 case SGPIO_ARCH_LUTON: 190 clr = SGPIO_LUTON_PORT_WIDTH; 191 set = SGPIO_LUTON_AUTO_REPEAT | 192 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width); 193 break; 194 case SGPIO_ARCH_OCELOT: 195 clr = SGPIO_OCELOT_PORT_WIDTH; 196 set = SGPIO_OCELOT_AUTO_REPEAT | 197 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width); 198 break; 199 case SGPIO_ARCH_SPARX5: 200 clr = SGPIO_SPARX5_PORT_WIDTH; 201 set = SGPIO_SPARX5_AUTO_REPEAT | 202 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width); 203 break; 204 default: 205 return; 206 } 207 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); 208 } 209 210 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) 211 { 212 u32 clr, set; 213 214 switch (priv->properties->arch) { 215 case SGPIO_ARCH_LUTON: 216 clr = SGPIO_LUTON_CLK_FREQ; 217 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq); 218 break; 219 case SGPIO_ARCH_OCELOT: 220 clr = SGPIO_OCELOT_CLK_FREQ; 221 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq); 222 break; 223 case SGPIO_ARCH_SPARX5: 224 clr = SGPIO_SPARX5_CLK_FREQ; 225 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq); 226 break; 227 default: 228 return; 229 } 230 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); 231 } 232 233 static int sgpio_single_shot(struct sgpio_priv *priv) 234 { 235 u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0); 236 int ret, ret2; 237 u32 ctrl; 238 unsigned int single_shot; 239 unsigned int auto_repeat; 240 241 switch (priv->properties->arch) { 242 case SGPIO_ARCH_LUTON: 243 /* not supported for now */ 244 return 0; 245 case SGPIO_ARCH_OCELOT: 246 single_shot = SGPIO_OCELOT_SINGLE_SHOT; 247 auto_repeat = SGPIO_OCELOT_AUTO_REPEAT; 248 break; 249 case SGPIO_ARCH_SPARX5: 250 single_shot = SGPIO_SPARX5_SINGLE_SHOT; 251 auto_repeat = SGPIO_SPARX5_AUTO_REPEAT; 252 break; 253 default: 254 return -EINVAL; 255 } 256 257 /* 258 * Trigger immediate burst. This only works when auto repeat is turned 259 * off. Otherwise, the single shot bit will never be cleared by the 260 * hardware. Measurements showed that an update might take as long as 261 * the burst gap. On a LAN9668 this is about 50ms for the largest 262 * setting. 263 * After the manual burst, reenable the auto repeat mode again. 264 */ 265 mutex_lock(&priv->poll_lock); 266 ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat, 267 single_shot); 268 if (ret) 269 goto out; 270 271 ret = regmap_read_poll_timeout(priv->regs, addr, ctrl, 272 !(ctrl & single_shot), 100, 60000); 273 274 /* reenable auto repeat mode even if there was an error */ 275 ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat); 276 out: 277 mutex_unlock(&priv->poll_lock); 278 279 return ret ?: ret2; 280 } 281 282 static int sgpio_output_set(struct sgpio_priv *priv, 283 struct sgpio_port_addr *addr, 284 int value) 285 { 286 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 287 u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port); 288 bool changed; 289 u32 clr, set; 290 int ret; 291 292 switch (priv->properties->arch) { 293 case SGPIO_ARCH_LUTON: 294 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit)); 295 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit); 296 break; 297 case SGPIO_ARCH_OCELOT: 298 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit)); 299 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit); 300 break; 301 case SGPIO_ARCH_SPARX5: 302 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit)); 303 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit); 304 break; 305 default: 306 return -EINVAL; 307 } 308 309 ret = regmap_update_bits_check(priv->regs, reg, clr | set, set, 310 &changed); 311 if (ret) 312 return ret; 313 314 if (changed) { 315 ret = sgpio_single_shot(priv); 316 if (ret) 317 return ret; 318 } 319 320 return 0; 321 } 322 323 static int sgpio_output_get(struct sgpio_priv *priv, 324 struct sgpio_port_addr *addr) 325 { 326 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port); 327 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 328 329 switch (priv->properties->arch) { 330 case SGPIO_ARCH_LUTON: 331 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval); 332 break; 333 case SGPIO_ARCH_OCELOT: 334 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval); 335 break; 336 case SGPIO_ARCH_SPARX5: 337 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval); 338 break; 339 default: 340 val = 0; 341 break; 342 } 343 return !!(val & BIT(bit)); 344 } 345 346 static int sgpio_input_get(struct sgpio_priv *priv, 347 struct sgpio_port_addr *addr) 348 { 349 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port)); 350 } 351 352 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev, 353 unsigned int pin, unsigned long *config) 354 { 355 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 356 u32 param = pinconf_to_config_param(*config); 357 struct sgpio_priv *priv = bank->priv; 358 struct sgpio_port_addr addr; 359 int val; 360 361 sgpio_pin_to_addr(priv, pin, &addr); 362 363 switch (param) { 364 case PIN_CONFIG_INPUT_ENABLE: 365 val = bank->is_input; 366 break; 367 368 case PIN_CONFIG_OUTPUT_ENABLE: 369 val = !bank->is_input; 370 break; 371 372 case PIN_CONFIG_OUTPUT: 373 if (bank->is_input) 374 return -EINVAL; 375 val = sgpio_output_get(priv, &addr); 376 break; 377 378 default: 379 return -ENOTSUPP; 380 } 381 382 *config = pinconf_to_config_packed(param, val); 383 384 return 0; 385 } 386 387 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 388 unsigned long *configs, unsigned int num_configs) 389 { 390 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 391 struct sgpio_priv *priv = bank->priv; 392 struct sgpio_port_addr addr; 393 int cfg, err = 0; 394 u32 param, arg; 395 396 sgpio_pin_to_addr(priv, pin, &addr); 397 398 for (cfg = 0; cfg < num_configs; cfg++) { 399 param = pinconf_to_config_param(configs[cfg]); 400 arg = pinconf_to_config_argument(configs[cfg]); 401 402 switch (param) { 403 case PIN_CONFIG_OUTPUT: 404 if (bank->is_input) 405 return -EINVAL; 406 err = sgpio_output_set(priv, &addr, arg); 407 break; 408 409 default: 410 err = -ENOTSUPP; 411 } 412 } 413 414 return err; 415 } 416 417 static const struct pinconf_ops sgpio_confops = { 418 .is_generic = true, 419 .pin_config_get = sgpio_pinconf_get, 420 .pin_config_set = sgpio_pinconf_set, 421 .pin_config_config_dbg_show = pinconf_generic_dump_config, 422 }; 423 424 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev) 425 { 426 return 1; 427 } 428 429 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev, 430 unsigned int function) 431 { 432 return functions[0]; 433 } 434 435 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev, 436 unsigned int function, 437 const char *const **groups, 438 unsigned *const num_groups) 439 { 440 *groups = functions; 441 *num_groups = ARRAY_SIZE(functions); 442 443 return 0; 444 } 445 446 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev, 447 unsigned int selector, unsigned int group) 448 { 449 return 0; 450 } 451 452 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev, 453 struct pinctrl_gpio_range *range, 454 unsigned int pin, bool input) 455 { 456 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 457 458 return (input == bank->is_input) ? 0 : -EINVAL; 459 } 460 461 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev, 462 struct pinctrl_gpio_range *range, 463 unsigned int offset) 464 { 465 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 466 struct sgpio_priv *priv = bank->priv; 467 struct sgpio_port_addr addr; 468 469 sgpio_pin_to_addr(priv, offset, &addr); 470 471 if ((priv->ports & BIT(addr.port)) == 0) { 472 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n", 473 addr.port, addr.bit); 474 return -EINVAL; 475 } 476 477 return 0; 478 } 479 480 static const struct pinmux_ops sgpio_pmx_ops = { 481 .get_functions_count = sgpio_get_functions_count, 482 .get_function_name = sgpio_get_function_name, 483 .get_function_groups = sgpio_get_function_groups, 484 .set_mux = sgpio_pinmux_set_mux, 485 .gpio_set_direction = sgpio_gpio_set_direction, 486 .gpio_request_enable = sgpio_gpio_request_enable, 487 }; 488 489 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev) 490 { 491 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 492 493 return bank->pctl_desc.npins; 494 } 495 496 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev, 497 unsigned int group) 498 { 499 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 500 501 return bank->pctl_desc.pins[group].name; 502 } 503 504 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev, 505 unsigned int group, 506 const unsigned int **pins, 507 unsigned int *num_pins) 508 { 509 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 510 511 *pins = &bank->pctl_desc.pins[group].number; 512 *num_pins = 1; 513 514 return 0; 515 } 516 517 static const struct pinctrl_ops sgpio_pctl_ops = { 518 .get_groups_count = sgpio_pctl_get_groups_count, 519 .get_group_name = sgpio_pctl_get_group_name, 520 .get_group_pins = sgpio_pctl_get_group_pins, 521 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 522 .dt_free_map = pinconf_generic_dt_free_map, 523 }; 524 525 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio) 526 { 527 struct sgpio_bank *bank = gpiochip_get_data(gc); 528 529 /* Fixed-position function */ 530 return bank->is_input ? 0 : -EINVAL; 531 } 532 533 static int microchip_sgpio_direction_output(struct gpio_chip *gc, 534 unsigned int gpio, int value) 535 { 536 struct sgpio_bank *bank = gpiochip_get_data(gc); 537 struct sgpio_priv *priv = bank->priv; 538 struct sgpio_port_addr addr; 539 540 /* Fixed-position function */ 541 if (bank->is_input) 542 return -EINVAL; 543 544 sgpio_pin_to_addr(priv, gpio, &addr); 545 546 return sgpio_output_set(priv, &addr, value); 547 } 548 549 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 550 { 551 struct sgpio_bank *bank = gpiochip_get_data(gc); 552 553 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 554 } 555 556 static void microchip_sgpio_set_value(struct gpio_chip *gc, 557 unsigned int gpio, int value) 558 { 559 microchip_sgpio_direction_output(gc, gpio, value); 560 } 561 562 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio) 563 { 564 struct sgpio_bank *bank = gpiochip_get_data(gc); 565 struct sgpio_priv *priv = bank->priv; 566 struct sgpio_port_addr addr; 567 568 sgpio_pin_to_addr(priv, gpio, &addr); 569 570 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr); 571 } 572 573 static int microchip_sgpio_of_xlate(struct gpio_chip *gc, 574 const struct of_phandle_args *gpiospec, 575 u32 *flags) 576 { 577 struct sgpio_bank *bank = gpiochip_get_data(gc); 578 struct sgpio_priv *priv = bank->priv; 579 int pin; 580 581 /* 582 * Note that the SGIO pin is defined by *2* numbers, a port 583 * number between 0 and 31, and a bit index, 0 to 3. 584 */ 585 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD || 586 gpiospec->args[1] > priv->bitcount) 587 return -EINVAL; 588 589 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]); 590 591 if (pin > gc->ngpio) 592 return -EINVAL; 593 594 if (flags) 595 *flags = gpiospec->args[2]; 596 597 return pin; 598 } 599 600 static int microchip_sgpio_get_ports(struct sgpio_priv *priv) 601 { 602 const char *range_property_name = "microchip,sgpio-port-ranges"; 603 struct device *dev = priv->dev; 604 u32 range_params[64]; 605 int i, nranges, ret; 606 607 /* Calculate port mask */ 608 nranges = device_property_count_u32(dev, range_property_name); 609 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) { 610 dev_err(dev, "%s port range: '%s' property\n", 611 nranges == -EINVAL ? "Missing" : "Invalid", 612 range_property_name); 613 return -EINVAL; 614 } 615 616 ret = device_property_read_u32_array(dev, range_property_name, 617 range_params, nranges); 618 if (ret) { 619 dev_err(dev, "failed to parse '%s' property: %d\n", 620 range_property_name, ret); 621 return ret; 622 } 623 for (i = 0; i < nranges; i += 2) { 624 int start, end; 625 626 start = range_params[i]; 627 end = range_params[i + 1]; 628 if (start > end || end >= SGPIO_BITS_PER_WORD) { 629 dev_err(dev, "Ill-formed port-range [%d:%d]\n", 630 start, end); 631 } 632 priv->ports |= GENMASK(end, start); 633 } 634 635 return 0; 636 } 637 638 static void microchip_sgpio_irq_settype(struct irq_data *data, 639 int type, 640 int polarity) 641 { 642 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 643 struct sgpio_bank *bank = gpiochip_get_data(chip); 644 unsigned int gpio = irqd_to_hwirq(data); 645 struct sgpio_port_addr addr; 646 unsigned long flags; 647 u32 ena; 648 649 sgpio_pin_to_addr(bank->priv, gpio, &addr); 650 651 spin_lock_irqsave(&bank->priv->lock, flags); 652 653 /* Disable interrupt while changing type */ 654 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit); 655 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit); 656 657 /* Type value spread over 2 registers sets: low, high bit */ 658 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit, 659 BIT(addr.port), (!!(type & 0x1)) << addr.port); 660 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit, 661 BIT(addr.port), (!!(type & 0x2)) << addr.port); 662 663 if (type == SGPIO_INT_TRG_LEVEL) 664 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit, 665 BIT(addr.port), polarity << addr.port); 666 667 /* Possibly re-enable interrupts */ 668 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit); 669 670 spin_unlock_irqrestore(&bank->priv->lock, flags); 671 } 672 673 static void microchip_sgpio_irq_setreg(struct irq_data *data, 674 int reg, 675 bool clear) 676 { 677 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 678 struct sgpio_bank *bank = gpiochip_get_data(chip); 679 unsigned int gpio = irqd_to_hwirq(data); 680 struct sgpio_port_addr addr; 681 682 sgpio_pin_to_addr(bank->priv, gpio, &addr); 683 684 if (clear) 685 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0); 686 else 687 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port)); 688 } 689 690 static void microchip_sgpio_irq_mask(struct irq_data *data) 691 { 692 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 693 694 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true); 695 gpiochip_disable_irq(chip, data->hwirq); 696 } 697 698 static void microchip_sgpio_irq_unmask(struct irq_data *data) 699 { 700 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 701 702 gpiochip_enable_irq(chip, data->hwirq); 703 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false); 704 } 705 706 static void microchip_sgpio_irq_ack(struct irq_data *data) 707 { 708 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 709 struct sgpio_bank *bank = gpiochip_get_data(chip); 710 unsigned int gpio = irqd_to_hwirq(data); 711 struct sgpio_port_addr addr; 712 713 sgpio_pin_to_addr(bank->priv, gpio, &addr); 714 715 sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit); 716 } 717 718 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type) 719 { 720 type &= IRQ_TYPE_SENSE_MASK; 721 722 switch (type) { 723 case IRQ_TYPE_EDGE_BOTH: 724 irq_set_handler_locked(data, handle_edge_irq); 725 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0); 726 break; 727 case IRQ_TYPE_EDGE_RISING: 728 irq_set_handler_locked(data, handle_edge_irq); 729 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0); 730 break; 731 case IRQ_TYPE_EDGE_FALLING: 732 irq_set_handler_locked(data, handle_edge_irq); 733 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0); 734 break; 735 case IRQ_TYPE_LEVEL_HIGH: 736 irq_set_handler_locked(data, handle_level_irq); 737 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH); 738 break; 739 case IRQ_TYPE_LEVEL_LOW: 740 irq_set_handler_locked(data, handle_level_irq); 741 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW); 742 break; 743 default: 744 return -EINVAL; 745 } 746 747 return 0; 748 } 749 750 static const struct irq_chip microchip_sgpio_irqchip = { 751 .name = "gpio", 752 .irq_mask = microchip_sgpio_irq_mask, 753 .irq_ack = microchip_sgpio_irq_ack, 754 .irq_unmask = microchip_sgpio_irq_unmask, 755 .irq_set_type = microchip_sgpio_irq_set_type, 756 .flags = IRQCHIP_IMMUTABLE, 757 GPIOCHIP_IRQ_RESOURCE_HELPERS, 758 }; 759 760 static void sgpio_irq_handler(struct irq_desc *desc) 761 { 762 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 763 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 764 struct sgpio_bank *bank = gpiochip_get_data(chip); 765 struct sgpio_priv *priv = bank->priv; 766 int bit, port, gpio; 767 long val; 768 769 for (bit = 0; bit < priv->bitcount; bit++) { 770 val = sgpio_readl(priv, REG_INT_IDENT, bit); 771 if (!val) 772 continue; 773 774 chained_irq_enter(parent_chip, desc); 775 776 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) { 777 gpio = sgpio_addr_to_pin(priv, port, bit); 778 generic_handle_domain_irq(chip->irq.domain, gpio); 779 } 780 781 chained_irq_exit(parent_chip, desc); 782 } 783 } 784 785 static int microchip_sgpio_register_bank(struct device *dev, 786 struct sgpio_priv *priv, 787 struct fwnode_handle *fwnode, 788 int bankno) 789 { 790 struct pinctrl_pin_desc *pins; 791 struct pinctrl_desc *pctl_desc; 792 struct pinctrl_dev *pctldev; 793 struct sgpio_bank *bank; 794 struct gpio_chip *gc; 795 u32 ngpios; 796 int i, ret; 797 798 /* Get overall bank struct */ 799 bank = (bankno == 0) ? &priv->in : &priv->out; 800 bank->priv = priv; 801 802 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) { 803 dev_info(dev, "failed to get number of gpios for bank%d\n", 804 bankno); 805 ngpios = 64; 806 } 807 808 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD; 809 if (priv->bitcount > SGPIO_MAX_BITS) { 810 dev_err(dev, "Bit width exceeds maximum (%d)\n", 811 SGPIO_MAX_BITS); 812 return -EINVAL; 813 } 814 815 pctl_desc = &bank->pctl_desc; 816 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput", 817 dev_name(dev), 818 bank->is_input ? "in" : "out"); 819 pctl_desc->pctlops = &sgpio_pctl_ops; 820 pctl_desc->pmxops = &sgpio_pmx_ops; 821 pctl_desc->confops = &sgpio_confops; 822 pctl_desc->owner = THIS_MODULE; 823 824 pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL); 825 if (!pins) 826 return -ENOMEM; 827 828 pctl_desc->npins = ngpios; 829 pctl_desc->pins = pins; 830 831 for (i = 0; i < ngpios; i++) { 832 struct sgpio_port_addr addr; 833 834 sgpio_pin_to_addr(priv, i, &addr); 835 836 pins[i].number = i; 837 pins[i].name = devm_kasprintf(dev, GFP_KERNEL, 838 "SGPIO_%c_p%db%d", 839 bank->is_input ? 'I' : 'O', 840 addr.port, addr.bit); 841 if (!pins[i].name) 842 return -ENOMEM; 843 } 844 845 pctldev = devm_pinctrl_register(dev, pctl_desc, bank); 846 if (IS_ERR(pctldev)) 847 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n"); 848 849 gc = &bank->gpio; 850 gc->label = pctl_desc->name; 851 gc->parent = dev; 852 gc->fwnode = fwnode; 853 gc->owner = THIS_MODULE; 854 gc->get_direction = microchip_sgpio_get_direction; 855 gc->direction_input = microchip_sgpio_direction_input; 856 gc->direction_output = microchip_sgpio_direction_output; 857 gc->get = microchip_sgpio_get_value; 858 gc->set = microchip_sgpio_set_value; 859 gc->request = gpiochip_generic_request; 860 gc->free = gpiochip_generic_free; 861 gc->of_xlate = microchip_sgpio_of_xlate; 862 gc->of_gpio_n_cells = 3; 863 gc->base = -1; 864 gc->ngpio = ngpios; 865 gc->can_sleep = !bank->is_input; 866 867 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) { 868 int irq; 869 870 irq = fwnode_irq_get(fwnode, 0); 871 if (irq > 0) { 872 struct gpio_irq_chip *girq = &gc->irq; 873 874 gpio_irq_chip_set_chip(girq, µchip_sgpio_irqchip); 875 girq->parent_handler = sgpio_irq_handler; 876 girq->num_parents = 1; 877 girq->parents = devm_kcalloc(dev, 1, 878 sizeof(*girq->parents), 879 GFP_KERNEL); 880 if (!girq->parents) 881 return -ENOMEM; 882 girq->parents[0] = irq; 883 girq->default_type = IRQ_TYPE_NONE; 884 girq->handler = handle_bad_irq; 885 886 /* Disable all individual pins */ 887 for (i = 0; i < SGPIO_MAX_BITS; i++) 888 sgpio_writel(priv, 0, REG_INT_ENABLE, i); 889 /* Master enable */ 890 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA); 891 } 892 } 893 894 ret = devm_gpiochip_add_data(dev, gc, bank); 895 if (ret) 896 dev_err(dev, "Failed to register: ret %d\n", ret); 897 898 return ret; 899 } 900 901 static int microchip_sgpio_probe(struct platform_device *pdev) 902 { 903 int div_clock = 0, ret, port, i, nbanks; 904 struct device *dev = &pdev->dev; 905 struct fwnode_handle *fwnode; 906 struct reset_control *reset; 907 struct sgpio_priv *priv; 908 struct clk *clk; 909 u32 val; 910 struct regmap_config regmap_config = { 911 .reg_bits = 32, 912 .val_bits = 32, 913 .reg_stride = 4, 914 }; 915 916 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 917 if (!priv) 918 return -ENOMEM; 919 920 priv->dev = dev; 921 spin_lock_init(&priv->lock); 922 mutex_init(&priv->poll_lock); 923 924 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); 925 if (IS_ERR(reset)) 926 return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n"); 927 reset_control_reset(reset); 928 929 clk = devm_clk_get(dev, NULL); 930 if (IS_ERR(clk)) 931 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n"); 932 933 div_clock = clk_get_rate(clk); 934 if (device_property_read_u32(dev, "bus-frequency", &priv->clock)) 935 priv->clock = 12500000; 936 if (priv->clock == 0 || priv->clock > (div_clock / 2)) { 937 dev_err(dev, "Invalid frequency %d\n", priv->clock); 938 return -EINVAL; 939 } 940 941 priv->regs = ocelot_regmap_from_resource(pdev, 0, ®map_config); 942 if (IS_ERR(priv->regs)) 943 return PTR_ERR(priv->regs); 944 945 priv->properties = device_get_match_data(dev); 946 priv->in.is_input = true; 947 948 /* Get rest of device properties */ 949 ret = microchip_sgpio_get_ports(priv); 950 if (ret) 951 return ret; 952 953 nbanks = device_get_child_node_count(dev); 954 if (nbanks != 2) { 955 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks); 956 return -EINVAL; 957 } 958 959 i = 0; 960 device_for_each_child_node(dev, fwnode) { 961 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++); 962 if (ret) { 963 fwnode_handle_put(fwnode); 964 return ret; 965 } 966 } 967 968 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) { 969 dev_err(dev, "Banks must have same GPIO count\n"); 970 return -ERANGE; 971 } 972 973 sgpio_configure_bitstream(priv); 974 975 val = max(2U, div_clock / priv->clock); 976 sgpio_configure_clock(priv, val); 977 978 for (port = 0; port < SGPIO_BITS_PER_WORD; port++) 979 sgpio_writel(priv, 0, REG_PORT_CONFIG, port); 980 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0); 981 982 return 0; 983 } 984 985 static const struct of_device_id microchip_sgpio_gpio_of_match[] = { 986 { 987 .compatible = "microchip,sparx5-sgpio", 988 .data = &properties_sparx5, 989 }, { 990 .compatible = "mscc,luton-sgpio", 991 .data = &properties_luton, 992 }, { 993 .compatible = "mscc,ocelot-sgpio", 994 .data = &properties_ocelot, 995 }, { 996 /* sentinel */ 997 } 998 }; 999 MODULE_DEVICE_TABLE(of, microchip_sgpio_gpio_of_match); 1000 1001 static struct platform_driver microchip_sgpio_pinctrl_driver = { 1002 .driver = { 1003 .name = "pinctrl-microchip-sgpio", 1004 .of_match_table = microchip_sgpio_gpio_of_match, 1005 .suppress_bind_attrs = true, 1006 }, 1007 .probe = microchip_sgpio_probe, 1008 }; 1009 module_platform_driver(microchip_sgpio_pinctrl_driver); 1010 1011 MODULE_DESCRIPTION("Microchip SGPIO Pinctrl Driver"); 1012 MODULE_LICENSE("GPL"); 1013