1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Microsemi/Microchip SoCs serial gpio driver 4 * 5 * Author: Lars Povlsen <lars.povlsen@microchip.com> 6 * 7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/clk.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/io.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/reset.h> 22 23 #include "core.h" 24 #include "pinconf.h" 25 26 #define SGPIO_BITS_PER_WORD 32 27 #define SGPIO_MAX_BITS 4 28 #define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */ 29 30 enum { 31 REG_INPUT_DATA, 32 REG_PORT_CONFIG, 33 REG_PORT_ENABLE, 34 REG_SIO_CONFIG, 35 REG_SIO_CLOCK, 36 REG_INT_POLARITY, 37 REG_INT_TRIGGER, 38 REG_INT_ACK, 39 REG_INT_ENABLE, 40 REG_INT_IDENT, 41 MAXREG 42 }; 43 44 enum { 45 SGPIO_ARCH_LUTON, 46 SGPIO_ARCH_OCELOT, 47 SGPIO_ARCH_SPARX5, 48 }; 49 50 enum { 51 SGPIO_FLAGS_HAS_IRQ = BIT(0), 52 }; 53 54 struct sgpio_properties { 55 int arch; 56 int flags; 57 u8 regoff[MAXREG]; 58 }; 59 60 #define SGPIO_LUTON_AUTO_REPEAT BIT(5) 61 #define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2) 62 #define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0) 63 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0) 64 65 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10) 66 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7) 67 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8) 68 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12) 69 70 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6) 71 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3) 72 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) 73 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) 74 75 #define SGPIO_MASTER_INTR_ENA BIT(0) 76 77 #define SGPIO_INT_TRG_LEVEL 0 78 #define SGPIO_INT_TRG_EDGE 1 79 #define SGPIO_INT_TRG_EDGE_FALL 2 80 #define SGPIO_INT_TRG_EDGE_RISE 3 81 82 #define SGPIO_TRG_LEVEL_HIGH 0 83 #define SGPIO_TRG_LEVEL_LOW 1 84 85 static const struct sgpio_properties properties_luton = { 86 .arch = SGPIO_ARCH_LUTON, 87 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b }, 88 }; 89 90 static const struct sgpio_properties properties_ocelot = { 91 .arch = SGPIO_ARCH_OCELOT, 92 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, 93 }; 94 95 static const struct sgpio_properties properties_sparx5 = { 96 .arch = SGPIO_ARCH_SPARX5, 97 .flags = SGPIO_FLAGS_HAS_IRQ, 98 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 }, 99 }; 100 101 static const char * const functions[] = { "gpio" }; 102 103 struct sgpio_bank { 104 struct sgpio_priv *priv; 105 bool is_input; 106 struct gpio_chip gpio; 107 struct pinctrl_desc pctl_desc; 108 }; 109 110 struct sgpio_priv { 111 struct device *dev; 112 struct sgpio_bank in; 113 struct sgpio_bank out; 114 u32 bitcount; 115 u32 ports; 116 u32 clock; 117 struct regmap *regs; 118 const struct sgpio_properties *properties; 119 }; 120 121 struct sgpio_port_addr { 122 u8 port; 123 u8 bit; 124 }; 125 126 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin, 127 struct sgpio_port_addr *addr) 128 { 129 addr->port = pin / priv->bitcount; 130 addr->bit = pin % priv->bitcount; 131 } 132 133 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit) 134 { 135 return bit + port * priv->bitcount; 136 } 137 138 static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off) 139 { 140 return (priv->properties->regoff[rno] + off) * 141 regmap_get_reg_stride(priv->regs); 142 } 143 144 static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) 145 { 146 u32 addr = sgpio_get_addr(priv, rno, off); 147 u32 val = 0; 148 int ret; 149 150 ret = regmap_read(priv->regs, addr, &val); 151 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret); 152 153 return val; 154 } 155 156 static void sgpio_writel(struct sgpio_priv *priv, 157 u32 val, u32 rno, u32 off) 158 { 159 u32 addr = sgpio_get_addr(priv, rno, off); 160 int ret; 161 162 ret = regmap_write(priv->regs, addr, val); 163 WARN_ONCE(ret, "error writing sgpio reg %d\n", ret); 164 } 165 166 static inline void sgpio_clrsetbits(struct sgpio_priv *priv, 167 u32 rno, u32 off, u32 clear, u32 set) 168 { 169 u32 val = sgpio_readl(priv, rno, off); 170 171 val &= ~clear; 172 val |= set; 173 174 sgpio_writel(priv, val, rno, off); 175 } 176 177 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) 178 { 179 int width = priv->bitcount - 1; 180 u32 clr, set; 181 182 switch (priv->properties->arch) { 183 case SGPIO_ARCH_LUTON: 184 clr = SGPIO_LUTON_PORT_WIDTH; 185 set = SGPIO_LUTON_AUTO_REPEAT | 186 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width); 187 break; 188 case SGPIO_ARCH_OCELOT: 189 clr = SGPIO_OCELOT_PORT_WIDTH; 190 set = SGPIO_OCELOT_AUTO_REPEAT | 191 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width); 192 break; 193 case SGPIO_ARCH_SPARX5: 194 clr = SGPIO_SPARX5_PORT_WIDTH; 195 set = SGPIO_SPARX5_AUTO_REPEAT | 196 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width); 197 break; 198 default: 199 return; 200 } 201 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); 202 } 203 204 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) 205 { 206 u32 clr, set; 207 208 switch (priv->properties->arch) { 209 case SGPIO_ARCH_LUTON: 210 clr = SGPIO_LUTON_CLK_FREQ; 211 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq); 212 break; 213 case SGPIO_ARCH_OCELOT: 214 clr = SGPIO_OCELOT_CLK_FREQ; 215 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq); 216 break; 217 case SGPIO_ARCH_SPARX5: 218 clr = SGPIO_SPARX5_CLK_FREQ; 219 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq); 220 break; 221 default: 222 return; 223 } 224 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); 225 } 226 227 static void sgpio_output_set(struct sgpio_priv *priv, 228 struct sgpio_port_addr *addr, 229 int value) 230 { 231 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 232 u32 clr, set; 233 234 switch (priv->properties->arch) { 235 case SGPIO_ARCH_LUTON: 236 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit)); 237 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit); 238 break; 239 case SGPIO_ARCH_OCELOT: 240 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit)); 241 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit); 242 break; 243 case SGPIO_ARCH_SPARX5: 244 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit)); 245 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit); 246 break; 247 default: 248 return; 249 } 250 sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set); 251 } 252 253 static int sgpio_output_get(struct sgpio_priv *priv, 254 struct sgpio_port_addr *addr) 255 { 256 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port); 257 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 258 259 switch (priv->properties->arch) { 260 case SGPIO_ARCH_LUTON: 261 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval); 262 break; 263 case SGPIO_ARCH_OCELOT: 264 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval); 265 break; 266 case SGPIO_ARCH_SPARX5: 267 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval); 268 break; 269 default: 270 val = 0; 271 break; 272 } 273 return !!(val & BIT(bit)); 274 } 275 276 static int sgpio_input_get(struct sgpio_priv *priv, 277 struct sgpio_port_addr *addr) 278 { 279 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port)); 280 } 281 282 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev, 283 unsigned int pin, unsigned long *config) 284 { 285 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 286 u32 param = pinconf_to_config_param(*config); 287 struct sgpio_priv *priv = bank->priv; 288 struct sgpio_port_addr addr; 289 int val; 290 291 sgpio_pin_to_addr(priv, pin, &addr); 292 293 switch (param) { 294 case PIN_CONFIG_INPUT_ENABLE: 295 val = bank->is_input; 296 break; 297 298 case PIN_CONFIG_OUTPUT_ENABLE: 299 val = !bank->is_input; 300 break; 301 302 case PIN_CONFIG_OUTPUT: 303 if (bank->is_input) 304 return -EINVAL; 305 val = sgpio_output_get(priv, &addr); 306 break; 307 308 default: 309 return -ENOTSUPP; 310 } 311 312 *config = pinconf_to_config_packed(param, val); 313 314 return 0; 315 } 316 317 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 318 unsigned long *configs, unsigned int num_configs) 319 { 320 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 321 struct sgpio_priv *priv = bank->priv; 322 struct sgpio_port_addr addr; 323 int cfg, err = 0; 324 u32 param, arg; 325 326 sgpio_pin_to_addr(priv, pin, &addr); 327 328 for (cfg = 0; cfg < num_configs; cfg++) { 329 param = pinconf_to_config_param(configs[cfg]); 330 arg = pinconf_to_config_argument(configs[cfg]); 331 332 switch (param) { 333 case PIN_CONFIG_OUTPUT: 334 if (bank->is_input) 335 return -EINVAL; 336 sgpio_output_set(priv, &addr, arg); 337 break; 338 339 default: 340 err = -ENOTSUPP; 341 } 342 } 343 344 return err; 345 } 346 347 static const struct pinconf_ops sgpio_confops = { 348 .is_generic = true, 349 .pin_config_get = sgpio_pinconf_get, 350 .pin_config_set = sgpio_pinconf_set, 351 .pin_config_config_dbg_show = pinconf_generic_dump_config, 352 }; 353 354 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev) 355 { 356 return 1; 357 } 358 359 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev, 360 unsigned int function) 361 { 362 return functions[0]; 363 } 364 365 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev, 366 unsigned int function, 367 const char *const **groups, 368 unsigned *const num_groups) 369 { 370 *groups = functions; 371 *num_groups = ARRAY_SIZE(functions); 372 373 return 0; 374 } 375 376 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev, 377 unsigned int selector, unsigned int group) 378 { 379 return 0; 380 } 381 382 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev, 383 struct pinctrl_gpio_range *range, 384 unsigned int pin, bool input) 385 { 386 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 387 388 return (input == bank->is_input) ? 0 : -EINVAL; 389 } 390 391 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev, 392 struct pinctrl_gpio_range *range, 393 unsigned int offset) 394 { 395 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 396 struct sgpio_priv *priv = bank->priv; 397 struct sgpio_port_addr addr; 398 399 sgpio_pin_to_addr(priv, offset, &addr); 400 401 if ((priv->ports & BIT(addr.port)) == 0) { 402 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n", 403 addr.port, addr.bit); 404 return -EINVAL; 405 } 406 407 return 0; 408 } 409 410 static const struct pinmux_ops sgpio_pmx_ops = { 411 .get_functions_count = sgpio_get_functions_count, 412 .get_function_name = sgpio_get_function_name, 413 .get_function_groups = sgpio_get_function_groups, 414 .set_mux = sgpio_pinmux_set_mux, 415 .gpio_set_direction = sgpio_gpio_set_direction, 416 .gpio_request_enable = sgpio_gpio_request_enable, 417 }; 418 419 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev) 420 { 421 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 422 423 return bank->pctl_desc.npins; 424 } 425 426 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev, 427 unsigned int group) 428 { 429 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 430 431 return bank->pctl_desc.pins[group].name; 432 } 433 434 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev, 435 unsigned int group, 436 const unsigned int **pins, 437 unsigned int *num_pins) 438 { 439 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 440 441 *pins = &bank->pctl_desc.pins[group].number; 442 *num_pins = 1; 443 444 return 0; 445 } 446 447 static const struct pinctrl_ops sgpio_pctl_ops = { 448 .get_groups_count = sgpio_pctl_get_groups_count, 449 .get_group_name = sgpio_pctl_get_group_name, 450 .get_group_pins = sgpio_pctl_get_group_pins, 451 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 452 .dt_free_map = pinconf_generic_dt_free_map, 453 }; 454 455 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio) 456 { 457 struct sgpio_bank *bank = gpiochip_get_data(gc); 458 459 /* Fixed-position function */ 460 return bank->is_input ? 0 : -EINVAL; 461 } 462 463 static int microchip_sgpio_direction_output(struct gpio_chip *gc, 464 unsigned int gpio, int value) 465 { 466 struct sgpio_bank *bank = gpiochip_get_data(gc); 467 struct sgpio_priv *priv = bank->priv; 468 struct sgpio_port_addr addr; 469 470 /* Fixed-position function */ 471 if (bank->is_input) 472 return -EINVAL; 473 474 sgpio_pin_to_addr(priv, gpio, &addr); 475 476 sgpio_output_set(priv, &addr, value); 477 478 return 0; 479 } 480 481 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 482 { 483 struct sgpio_bank *bank = gpiochip_get_data(gc); 484 485 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 486 } 487 488 static void microchip_sgpio_set_value(struct gpio_chip *gc, 489 unsigned int gpio, int value) 490 { 491 microchip_sgpio_direction_output(gc, gpio, value); 492 } 493 494 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio) 495 { 496 struct sgpio_bank *bank = gpiochip_get_data(gc); 497 struct sgpio_priv *priv = bank->priv; 498 struct sgpio_port_addr addr; 499 500 sgpio_pin_to_addr(priv, gpio, &addr); 501 502 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr); 503 } 504 505 static int microchip_sgpio_of_xlate(struct gpio_chip *gc, 506 const struct of_phandle_args *gpiospec, 507 u32 *flags) 508 { 509 struct sgpio_bank *bank = gpiochip_get_data(gc); 510 struct sgpio_priv *priv = bank->priv; 511 int pin; 512 513 /* 514 * Note that the SGIO pin is defined by *2* numbers, a port 515 * number between 0 and 31, and a bit index, 0 to 3. 516 */ 517 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD || 518 gpiospec->args[1] > priv->bitcount) 519 return -EINVAL; 520 521 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]); 522 523 if (pin > gc->ngpio) 524 return -EINVAL; 525 526 if (flags) 527 *flags = gpiospec->args[2]; 528 529 return pin; 530 } 531 532 static int microchip_sgpio_get_ports(struct sgpio_priv *priv) 533 { 534 const char *range_property_name = "microchip,sgpio-port-ranges"; 535 struct device *dev = priv->dev; 536 u32 range_params[64]; 537 int i, nranges, ret; 538 539 /* Calculate port mask */ 540 nranges = device_property_count_u32(dev, range_property_name); 541 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) { 542 dev_err(dev, "%s port range: '%s' property\n", 543 nranges == -EINVAL ? "Missing" : "Invalid", 544 range_property_name); 545 return -EINVAL; 546 } 547 548 ret = device_property_read_u32_array(dev, range_property_name, 549 range_params, nranges); 550 if (ret) { 551 dev_err(dev, "failed to parse '%s' property: %d\n", 552 range_property_name, ret); 553 return ret; 554 } 555 for (i = 0; i < nranges; i += 2) { 556 int start, end; 557 558 start = range_params[i]; 559 end = range_params[i + 1]; 560 if (start > end || end >= SGPIO_BITS_PER_WORD) { 561 dev_err(dev, "Ill-formed port-range [%d:%d]\n", 562 start, end); 563 } 564 priv->ports |= GENMASK(end, start); 565 } 566 567 return 0; 568 } 569 570 static void microchip_sgpio_irq_settype(struct irq_data *data, 571 int type, 572 int polarity) 573 { 574 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 575 struct sgpio_bank *bank = gpiochip_get_data(chip); 576 unsigned int gpio = irqd_to_hwirq(data); 577 struct sgpio_port_addr addr; 578 u32 ena; 579 580 sgpio_pin_to_addr(bank->priv, gpio, &addr); 581 582 /* Disable interrupt while changing type */ 583 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit); 584 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit); 585 586 /* Type value spread over 2 registers sets: low, high bit */ 587 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit, 588 BIT(addr.port), (!!(type & 0x1)) << addr.port); 589 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit, 590 BIT(addr.port), (!!(type & 0x2)) << addr.port); 591 592 if (type == SGPIO_INT_TRG_LEVEL) 593 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit, 594 BIT(addr.port), polarity << addr.port); 595 596 /* Possibly re-enable interrupts */ 597 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit); 598 } 599 600 static void microchip_sgpio_irq_setreg(struct irq_data *data, 601 int reg, 602 bool clear) 603 { 604 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 605 struct sgpio_bank *bank = gpiochip_get_data(chip); 606 unsigned int gpio = irqd_to_hwirq(data); 607 struct sgpio_port_addr addr; 608 609 sgpio_pin_to_addr(bank->priv, gpio, &addr); 610 611 if (clear) 612 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0); 613 else 614 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port)); 615 } 616 617 static void microchip_sgpio_irq_mask(struct irq_data *data) 618 { 619 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true); 620 } 621 622 static void microchip_sgpio_irq_unmask(struct irq_data *data) 623 { 624 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false); 625 } 626 627 static void microchip_sgpio_irq_ack(struct irq_data *data) 628 { 629 microchip_sgpio_irq_setreg(data, REG_INT_ACK, false); 630 } 631 632 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type) 633 { 634 type &= IRQ_TYPE_SENSE_MASK; 635 636 switch (type) { 637 case IRQ_TYPE_EDGE_BOTH: 638 irq_set_handler_locked(data, handle_edge_irq); 639 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0); 640 break; 641 case IRQ_TYPE_EDGE_RISING: 642 irq_set_handler_locked(data, handle_edge_irq); 643 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0); 644 break; 645 case IRQ_TYPE_EDGE_FALLING: 646 irq_set_handler_locked(data, handle_edge_irq); 647 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0); 648 break; 649 case IRQ_TYPE_LEVEL_HIGH: 650 irq_set_handler_locked(data, handle_level_irq); 651 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH); 652 break; 653 case IRQ_TYPE_LEVEL_LOW: 654 irq_set_handler_locked(data, handle_level_irq); 655 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW); 656 break; 657 default: 658 return -EINVAL; 659 } 660 661 return 0; 662 } 663 664 static const struct irq_chip microchip_sgpio_irqchip = { 665 .name = "gpio", 666 .irq_mask = microchip_sgpio_irq_mask, 667 .irq_ack = microchip_sgpio_irq_ack, 668 .irq_unmask = microchip_sgpio_irq_unmask, 669 .irq_set_type = microchip_sgpio_irq_set_type, 670 }; 671 672 static void sgpio_irq_handler(struct irq_desc *desc) 673 { 674 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 675 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 676 struct sgpio_bank *bank = gpiochip_get_data(chip); 677 struct sgpio_priv *priv = bank->priv; 678 int bit, port, gpio; 679 long val; 680 681 for (bit = 0; bit < priv->bitcount; bit++) { 682 val = sgpio_readl(priv, REG_INT_IDENT, bit); 683 if (!val) 684 continue; 685 686 chained_irq_enter(parent_chip, desc); 687 688 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) { 689 gpio = sgpio_addr_to_pin(priv, port, bit); 690 generic_handle_domain_irq(chip->irq.domain, gpio); 691 } 692 693 chained_irq_exit(parent_chip, desc); 694 } 695 } 696 697 static int microchip_sgpio_register_bank(struct device *dev, 698 struct sgpio_priv *priv, 699 struct fwnode_handle *fwnode, 700 int bankno) 701 { 702 struct pinctrl_pin_desc *pins; 703 struct pinctrl_desc *pctl_desc; 704 struct pinctrl_dev *pctldev; 705 struct sgpio_bank *bank; 706 struct gpio_chip *gc; 707 u32 ngpios; 708 int i, ret; 709 710 /* Get overall bank struct */ 711 bank = (bankno == 0) ? &priv->in : &priv->out; 712 bank->priv = priv; 713 714 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) { 715 dev_info(dev, "failed to get number of gpios for bank%d\n", 716 bankno); 717 ngpios = 64; 718 } 719 720 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD; 721 if (priv->bitcount > SGPIO_MAX_BITS) { 722 dev_err(dev, "Bit width exceeds maximum (%d)\n", 723 SGPIO_MAX_BITS); 724 return -EINVAL; 725 } 726 727 pctl_desc = &bank->pctl_desc; 728 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput", 729 dev_name(dev), 730 bank->is_input ? "in" : "out"); 731 pctl_desc->pctlops = &sgpio_pctl_ops; 732 pctl_desc->pmxops = &sgpio_pmx_ops; 733 pctl_desc->confops = &sgpio_confops; 734 pctl_desc->owner = THIS_MODULE; 735 736 pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL); 737 if (!pins) 738 return -ENOMEM; 739 740 pctl_desc->npins = ngpios; 741 pctl_desc->pins = pins; 742 743 for (i = 0; i < ngpios; i++) { 744 struct sgpio_port_addr addr; 745 746 sgpio_pin_to_addr(priv, i, &addr); 747 748 pins[i].number = i; 749 pins[i].name = devm_kasprintf(dev, GFP_KERNEL, 750 "SGPIO_%c_p%db%d", 751 bank->is_input ? 'I' : 'O', 752 addr.port, addr.bit); 753 if (!pins[i].name) 754 return -ENOMEM; 755 } 756 757 pctldev = devm_pinctrl_register(dev, pctl_desc, bank); 758 if (IS_ERR(pctldev)) 759 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n"); 760 761 gc = &bank->gpio; 762 gc->label = pctl_desc->name; 763 gc->parent = dev; 764 gc->of_node = to_of_node(fwnode); 765 gc->owner = THIS_MODULE; 766 gc->get_direction = microchip_sgpio_get_direction; 767 gc->direction_input = microchip_sgpio_direction_input; 768 gc->direction_output = microchip_sgpio_direction_output; 769 gc->get = microchip_sgpio_get_value; 770 gc->set = microchip_sgpio_set_value; 771 gc->request = gpiochip_generic_request; 772 gc->free = gpiochip_generic_free; 773 gc->of_xlate = microchip_sgpio_of_xlate; 774 gc->of_gpio_n_cells = 3; 775 gc->base = -1; 776 gc->ngpio = ngpios; 777 778 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) { 779 int irq = fwnode_irq_get(fwnode, 0); 780 781 if (irq) { 782 struct gpio_irq_chip *girq = &gc->irq; 783 784 girq->chip = devm_kmemdup(dev, µchip_sgpio_irqchip, 785 sizeof(microchip_sgpio_irqchip), 786 GFP_KERNEL); 787 if (!girq->chip) 788 return -ENOMEM; 789 girq->parent_handler = sgpio_irq_handler; 790 girq->num_parents = 1; 791 girq->parents = devm_kcalloc(dev, 1, 792 sizeof(*girq->parents), 793 GFP_KERNEL); 794 if (!girq->parents) 795 return -ENOMEM; 796 girq->parents[0] = irq; 797 girq->default_type = IRQ_TYPE_NONE; 798 girq->handler = handle_bad_irq; 799 800 /* Disable all individual pins */ 801 for (i = 0; i < SGPIO_MAX_BITS; i++) 802 sgpio_writel(priv, 0, REG_INT_ENABLE, i); 803 /* Master enable */ 804 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA); 805 } 806 } 807 808 ret = devm_gpiochip_add_data(dev, gc, bank); 809 if (ret) 810 dev_err(dev, "Failed to register: ret %d\n", ret); 811 812 return ret; 813 } 814 815 static int microchip_sgpio_probe(struct platform_device *pdev) 816 { 817 int div_clock = 0, ret, port, i, nbanks; 818 struct device *dev = &pdev->dev; 819 struct fwnode_handle *fwnode; 820 struct reset_control *reset; 821 struct sgpio_priv *priv; 822 struct clk *clk; 823 u32 __iomem *regs; 824 u32 val; 825 struct regmap_config regmap_config = { 826 .reg_bits = 32, 827 .val_bits = 32, 828 .reg_stride = 4, 829 }; 830 831 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 832 if (!priv) 833 return -ENOMEM; 834 835 priv->dev = dev; 836 837 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); 838 if (IS_ERR(reset)) 839 return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n"); 840 reset_control_reset(reset); 841 842 clk = devm_clk_get(dev, NULL); 843 if (IS_ERR(clk)) 844 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n"); 845 846 div_clock = clk_get_rate(clk); 847 if (device_property_read_u32(dev, "bus-frequency", &priv->clock)) 848 priv->clock = 12500000; 849 if (priv->clock == 0 || priv->clock > (div_clock / 2)) { 850 dev_err(dev, "Invalid frequency %d\n", priv->clock); 851 return -EINVAL; 852 } 853 854 regs = devm_platform_ioremap_resource(pdev, 0); 855 if (IS_ERR(regs)) 856 return PTR_ERR(regs); 857 858 priv->regs = devm_regmap_init_mmio(dev, regs, ®map_config); 859 if (IS_ERR(priv->regs)) 860 return PTR_ERR(priv->regs); 861 862 priv->properties = device_get_match_data(dev); 863 priv->in.is_input = true; 864 865 /* Get rest of device properties */ 866 ret = microchip_sgpio_get_ports(priv); 867 if (ret) 868 return ret; 869 870 nbanks = device_get_child_node_count(dev); 871 if (nbanks != 2) { 872 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks); 873 return -EINVAL; 874 } 875 876 i = 0; 877 device_for_each_child_node(dev, fwnode) { 878 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++); 879 if (ret) { 880 fwnode_handle_put(fwnode); 881 return ret; 882 } 883 } 884 885 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) { 886 dev_err(dev, "Banks must have same GPIO count\n"); 887 return -ERANGE; 888 } 889 890 sgpio_configure_bitstream(priv); 891 892 val = max(2U, div_clock / priv->clock); 893 sgpio_configure_clock(priv, val); 894 895 for (port = 0; port < SGPIO_BITS_PER_WORD; port++) 896 sgpio_writel(priv, 0, REG_PORT_CONFIG, port); 897 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0); 898 899 return 0; 900 } 901 902 static const struct of_device_id microchip_sgpio_gpio_of_match[] = { 903 { 904 .compatible = "microchip,sparx5-sgpio", 905 .data = &properties_sparx5, 906 }, { 907 .compatible = "mscc,luton-sgpio", 908 .data = &properties_luton, 909 }, { 910 .compatible = "mscc,ocelot-sgpio", 911 .data = &properties_ocelot, 912 }, { 913 /* sentinel */ 914 } 915 }; 916 917 static struct platform_driver microchip_sgpio_pinctrl_driver = { 918 .driver = { 919 .name = "pinctrl-microchip-sgpio", 920 .of_match_table = microchip_sgpio_gpio_of_match, 921 .suppress_bind_attrs = true, 922 }, 923 .probe = microchip_sgpio_probe, 924 }; 925 builtin_platform_driver(microchip_sgpio_pinctrl_driver); 926