1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Microsemi/Microchip SoCs serial gpio driver 4 * 5 * Author: Lars Povlsen <lars.povlsen@microchip.com> 6 * 7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/clk.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/io.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/reset.h> 22 23 #include "core.h" 24 #include "pinconf.h" 25 26 #define SGPIO_BITS_PER_WORD 32 27 #define SGPIO_MAX_BITS 4 28 #define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */ 29 30 enum { 31 REG_INPUT_DATA, 32 REG_PORT_CONFIG, 33 REG_PORT_ENABLE, 34 REG_SIO_CONFIG, 35 REG_SIO_CLOCK, 36 REG_INT_POLARITY, 37 REG_INT_TRIGGER, 38 REG_INT_ACK, 39 REG_INT_ENABLE, 40 REG_INT_IDENT, 41 MAXREG 42 }; 43 44 enum { 45 SGPIO_ARCH_LUTON, 46 SGPIO_ARCH_OCELOT, 47 SGPIO_ARCH_SPARX5, 48 }; 49 50 enum { 51 SGPIO_FLAGS_HAS_IRQ = BIT(0), 52 }; 53 54 struct sgpio_properties { 55 int arch; 56 int flags; 57 u8 regoff[MAXREG]; 58 }; 59 60 #define SGPIO_LUTON_AUTO_REPEAT BIT(5) 61 #define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2) 62 #define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0) 63 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0) 64 65 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10) 66 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7) 67 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8) 68 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12) 69 70 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6) 71 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3) 72 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) 73 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) 74 75 #define SGPIO_MASTER_INTR_ENA BIT(0) 76 77 #define SGPIO_INT_TRG_LEVEL 0 78 #define SGPIO_INT_TRG_EDGE 1 79 #define SGPIO_INT_TRG_EDGE_FALL 2 80 #define SGPIO_INT_TRG_EDGE_RISE 3 81 82 #define SGPIO_TRG_LEVEL_HIGH 0 83 #define SGPIO_TRG_LEVEL_LOW 1 84 85 static const struct sgpio_properties properties_luton = { 86 .arch = SGPIO_ARCH_LUTON, 87 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b }, 88 }; 89 90 static const struct sgpio_properties properties_ocelot = { 91 .arch = SGPIO_ARCH_OCELOT, 92 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, 93 }; 94 95 static const struct sgpio_properties properties_sparx5 = { 96 .arch = SGPIO_ARCH_SPARX5, 97 .flags = SGPIO_FLAGS_HAS_IRQ, 98 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 }, 99 }; 100 101 static const char * const functions[] = { "gpio" }; 102 103 struct sgpio_bank { 104 struct sgpio_priv *priv; 105 bool is_input; 106 struct gpio_chip gpio; 107 struct pinctrl_desc pctl_desc; 108 }; 109 110 struct sgpio_priv { 111 struct device *dev; 112 struct sgpio_bank in; 113 struct sgpio_bank out; 114 u32 bitcount; 115 u32 ports; 116 u32 clock; 117 struct regmap *regs; 118 const struct sgpio_properties *properties; 119 }; 120 121 struct sgpio_port_addr { 122 u8 port; 123 u8 bit; 124 }; 125 126 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin, 127 struct sgpio_port_addr *addr) 128 { 129 addr->port = pin / priv->bitcount; 130 addr->bit = pin % priv->bitcount; 131 } 132 133 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit) 134 { 135 return bit + port * priv->bitcount; 136 } 137 138 static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off) 139 { 140 return priv->properties->regoff[rno] + off; 141 } 142 143 static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) 144 { 145 u32 addr = sgpio_get_addr(priv, rno, off); 146 u32 val = 0; 147 int ret; 148 149 ret = regmap_read(priv->regs, addr, &val); 150 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret); 151 152 return val; 153 } 154 155 static void sgpio_writel(struct sgpio_priv *priv, 156 u32 val, u32 rno, u32 off) 157 { 158 u32 addr = sgpio_get_addr(priv, rno, off); 159 int ret; 160 161 ret = regmap_write(priv->regs, addr, val); 162 WARN_ONCE(ret, "error writing sgpio reg %d\n", ret); 163 } 164 165 static inline void sgpio_clrsetbits(struct sgpio_priv *priv, 166 u32 rno, u32 off, u32 clear, u32 set) 167 { 168 u32 val = sgpio_readl(priv, rno, off); 169 170 val &= ~clear; 171 val |= set; 172 173 sgpio_writel(priv, val, rno, off); 174 } 175 176 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) 177 { 178 int width = priv->bitcount - 1; 179 u32 clr, set; 180 181 switch (priv->properties->arch) { 182 case SGPIO_ARCH_LUTON: 183 clr = SGPIO_LUTON_PORT_WIDTH; 184 set = SGPIO_LUTON_AUTO_REPEAT | 185 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width); 186 break; 187 case SGPIO_ARCH_OCELOT: 188 clr = SGPIO_OCELOT_PORT_WIDTH; 189 set = SGPIO_OCELOT_AUTO_REPEAT | 190 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width); 191 break; 192 case SGPIO_ARCH_SPARX5: 193 clr = SGPIO_SPARX5_PORT_WIDTH; 194 set = SGPIO_SPARX5_AUTO_REPEAT | 195 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width); 196 break; 197 default: 198 return; 199 } 200 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); 201 } 202 203 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) 204 { 205 u32 clr, set; 206 207 switch (priv->properties->arch) { 208 case SGPIO_ARCH_LUTON: 209 clr = SGPIO_LUTON_CLK_FREQ; 210 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq); 211 break; 212 case SGPIO_ARCH_OCELOT: 213 clr = SGPIO_OCELOT_CLK_FREQ; 214 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq); 215 break; 216 case SGPIO_ARCH_SPARX5: 217 clr = SGPIO_SPARX5_CLK_FREQ; 218 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq); 219 break; 220 default: 221 return; 222 } 223 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); 224 } 225 226 static void sgpio_output_set(struct sgpio_priv *priv, 227 struct sgpio_port_addr *addr, 228 int value) 229 { 230 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 231 u32 clr, set; 232 233 switch (priv->properties->arch) { 234 case SGPIO_ARCH_LUTON: 235 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit)); 236 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit); 237 break; 238 case SGPIO_ARCH_OCELOT: 239 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit)); 240 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit); 241 break; 242 case SGPIO_ARCH_SPARX5: 243 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit)); 244 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit); 245 break; 246 default: 247 return; 248 } 249 sgpio_clrsetbits(priv, REG_PORT_CONFIG, addr->port, clr, set); 250 } 251 252 static int sgpio_output_get(struct sgpio_priv *priv, 253 struct sgpio_port_addr *addr) 254 { 255 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port); 256 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 257 258 switch (priv->properties->arch) { 259 case SGPIO_ARCH_LUTON: 260 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval); 261 break; 262 case SGPIO_ARCH_OCELOT: 263 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval); 264 break; 265 case SGPIO_ARCH_SPARX5: 266 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval); 267 break; 268 default: 269 val = 0; 270 break; 271 } 272 return !!(val & BIT(bit)); 273 } 274 275 static int sgpio_input_get(struct sgpio_priv *priv, 276 struct sgpio_port_addr *addr) 277 { 278 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port)); 279 } 280 281 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev, 282 unsigned int pin, unsigned long *config) 283 { 284 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 285 u32 param = pinconf_to_config_param(*config); 286 struct sgpio_priv *priv = bank->priv; 287 struct sgpio_port_addr addr; 288 int val; 289 290 sgpio_pin_to_addr(priv, pin, &addr); 291 292 switch (param) { 293 case PIN_CONFIG_INPUT_ENABLE: 294 val = bank->is_input; 295 break; 296 297 case PIN_CONFIG_OUTPUT_ENABLE: 298 val = !bank->is_input; 299 break; 300 301 case PIN_CONFIG_OUTPUT: 302 if (bank->is_input) 303 return -EINVAL; 304 val = sgpio_output_get(priv, &addr); 305 break; 306 307 default: 308 return -ENOTSUPP; 309 } 310 311 *config = pinconf_to_config_packed(param, val); 312 313 return 0; 314 } 315 316 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 317 unsigned long *configs, unsigned int num_configs) 318 { 319 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 320 struct sgpio_priv *priv = bank->priv; 321 struct sgpio_port_addr addr; 322 int cfg, err = 0; 323 u32 param, arg; 324 325 sgpio_pin_to_addr(priv, pin, &addr); 326 327 for (cfg = 0; cfg < num_configs; cfg++) { 328 param = pinconf_to_config_param(configs[cfg]); 329 arg = pinconf_to_config_argument(configs[cfg]); 330 331 switch (param) { 332 case PIN_CONFIG_OUTPUT: 333 if (bank->is_input) 334 return -EINVAL; 335 sgpio_output_set(priv, &addr, arg); 336 break; 337 338 default: 339 err = -ENOTSUPP; 340 } 341 } 342 343 return err; 344 } 345 346 static const struct pinconf_ops sgpio_confops = { 347 .is_generic = true, 348 .pin_config_get = sgpio_pinconf_get, 349 .pin_config_set = sgpio_pinconf_set, 350 .pin_config_config_dbg_show = pinconf_generic_dump_config, 351 }; 352 353 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev) 354 { 355 return 1; 356 } 357 358 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev, 359 unsigned int function) 360 { 361 return functions[0]; 362 } 363 364 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev, 365 unsigned int function, 366 const char *const **groups, 367 unsigned *const num_groups) 368 { 369 *groups = functions; 370 *num_groups = ARRAY_SIZE(functions); 371 372 return 0; 373 } 374 375 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev, 376 unsigned int selector, unsigned int group) 377 { 378 return 0; 379 } 380 381 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev, 382 struct pinctrl_gpio_range *range, 383 unsigned int pin, bool input) 384 { 385 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 386 387 return (input == bank->is_input) ? 0 : -EINVAL; 388 } 389 390 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev, 391 struct pinctrl_gpio_range *range, 392 unsigned int offset) 393 { 394 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 395 struct sgpio_priv *priv = bank->priv; 396 struct sgpio_port_addr addr; 397 398 sgpio_pin_to_addr(priv, offset, &addr); 399 400 if ((priv->ports & BIT(addr.port)) == 0) { 401 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n", 402 addr.port, addr.bit); 403 return -EINVAL; 404 } 405 406 return 0; 407 } 408 409 static const struct pinmux_ops sgpio_pmx_ops = { 410 .get_functions_count = sgpio_get_functions_count, 411 .get_function_name = sgpio_get_function_name, 412 .get_function_groups = sgpio_get_function_groups, 413 .set_mux = sgpio_pinmux_set_mux, 414 .gpio_set_direction = sgpio_gpio_set_direction, 415 .gpio_request_enable = sgpio_gpio_request_enable, 416 }; 417 418 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev) 419 { 420 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 421 422 return bank->pctl_desc.npins; 423 } 424 425 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev, 426 unsigned int group) 427 { 428 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 429 430 return bank->pctl_desc.pins[group].name; 431 } 432 433 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev, 434 unsigned int group, 435 const unsigned int **pins, 436 unsigned int *num_pins) 437 { 438 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 439 440 *pins = &bank->pctl_desc.pins[group].number; 441 *num_pins = 1; 442 443 return 0; 444 } 445 446 static const struct pinctrl_ops sgpio_pctl_ops = { 447 .get_groups_count = sgpio_pctl_get_groups_count, 448 .get_group_name = sgpio_pctl_get_group_name, 449 .get_group_pins = sgpio_pctl_get_group_pins, 450 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 451 .dt_free_map = pinconf_generic_dt_free_map, 452 }; 453 454 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio) 455 { 456 struct sgpio_bank *bank = gpiochip_get_data(gc); 457 458 /* Fixed-position function */ 459 return bank->is_input ? 0 : -EINVAL; 460 } 461 462 static int microchip_sgpio_direction_output(struct gpio_chip *gc, 463 unsigned int gpio, int value) 464 { 465 struct sgpio_bank *bank = gpiochip_get_data(gc); 466 struct sgpio_priv *priv = bank->priv; 467 struct sgpio_port_addr addr; 468 469 /* Fixed-position function */ 470 if (bank->is_input) 471 return -EINVAL; 472 473 sgpio_pin_to_addr(priv, gpio, &addr); 474 475 sgpio_output_set(priv, &addr, value); 476 477 return 0; 478 } 479 480 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 481 { 482 struct sgpio_bank *bank = gpiochip_get_data(gc); 483 484 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 485 } 486 487 static void microchip_sgpio_set_value(struct gpio_chip *gc, 488 unsigned int gpio, int value) 489 { 490 microchip_sgpio_direction_output(gc, gpio, value); 491 } 492 493 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio) 494 { 495 struct sgpio_bank *bank = gpiochip_get_data(gc); 496 struct sgpio_priv *priv = bank->priv; 497 struct sgpio_port_addr addr; 498 499 sgpio_pin_to_addr(priv, gpio, &addr); 500 501 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr); 502 } 503 504 static int microchip_sgpio_of_xlate(struct gpio_chip *gc, 505 const struct of_phandle_args *gpiospec, 506 u32 *flags) 507 { 508 struct sgpio_bank *bank = gpiochip_get_data(gc); 509 struct sgpio_priv *priv = bank->priv; 510 int pin; 511 512 /* 513 * Note that the SGIO pin is defined by *2* numbers, a port 514 * number between 0 and 31, and a bit index, 0 to 3. 515 */ 516 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD || 517 gpiospec->args[1] > priv->bitcount) 518 return -EINVAL; 519 520 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]); 521 522 if (pin > gc->ngpio) 523 return -EINVAL; 524 525 if (flags) 526 *flags = gpiospec->args[2]; 527 528 return pin; 529 } 530 531 static int microchip_sgpio_get_ports(struct sgpio_priv *priv) 532 { 533 const char *range_property_name = "microchip,sgpio-port-ranges"; 534 struct device *dev = priv->dev; 535 u32 range_params[64]; 536 int i, nranges, ret; 537 538 /* Calculate port mask */ 539 nranges = device_property_count_u32(dev, range_property_name); 540 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) { 541 dev_err(dev, "%s port range: '%s' property\n", 542 nranges == -EINVAL ? "Missing" : "Invalid", 543 range_property_name); 544 return -EINVAL; 545 } 546 547 ret = device_property_read_u32_array(dev, range_property_name, 548 range_params, nranges); 549 if (ret) { 550 dev_err(dev, "failed to parse '%s' property: %d\n", 551 range_property_name, ret); 552 return ret; 553 } 554 for (i = 0; i < nranges; i += 2) { 555 int start, end; 556 557 start = range_params[i]; 558 end = range_params[i + 1]; 559 if (start > end || end >= SGPIO_BITS_PER_WORD) { 560 dev_err(dev, "Ill-formed port-range [%d:%d]\n", 561 start, end); 562 } 563 priv->ports |= GENMASK(end, start); 564 } 565 566 return 0; 567 } 568 569 static void microchip_sgpio_irq_settype(struct irq_data *data, 570 int type, 571 int polarity) 572 { 573 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 574 struct sgpio_bank *bank = gpiochip_get_data(chip); 575 unsigned int gpio = irqd_to_hwirq(data); 576 struct sgpio_port_addr addr; 577 u32 ena; 578 579 sgpio_pin_to_addr(bank->priv, gpio, &addr); 580 581 /* Disable interrupt while changing type */ 582 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit); 583 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit); 584 585 /* Type value spread over 2 registers sets: low, high bit */ 586 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit, 587 BIT(addr.port), (!!(type & 0x1)) << addr.port); 588 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit, 589 BIT(addr.port), (!!(type & 0x2)) << addr.port); 590 591 if (type == SGPIO_INT_TRG_LEVEL) 592 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit, 593 BIT(addr.port), polarity << addr.port); 594 595 /* Possibly re-enable interrupts */ 596 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit); 597 } 598 599 static void microchip_sgpio_irq_setreg(struct irq_data *data, 600 int reg, 601 bool clear) 602 { 603 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 604 struct sgpio_bank *bank = gpiochip_get_data(chip); 605 unsigned int gpio = irqd_to_hwirq(data); 606 struct sgpio_port_addr addr; 607 608 sgpio_pin_to_addr(bank->priv, gpio, &addr); 609 610 if (clear) 611 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0); 612 else 613 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port)); 614 } 615 616 static void microchip_sgpio_irq_mask(struct irq_data *data) 617 { 618 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true); 619 } 620 621 static void microchip_sgpio_irq_unmask(struct irq_data *data) 622 { 623 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false); 624 } 625 626 static void microchip_sgpio_irq_ack(struct irq_data *data) 627 { 628 microchip_sgpio_irq_setreg(data, REG_INT_ACK, false); 629 } 630 631 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type) 632 { 633 type &= IRQ_TYPE_SENSE_MASK; 634 635 switch (type) { 636 case IRQ_TYPE_EDGE_BOTH: 637 irq_set_handler_locked(data, handle_edge_irq); 638 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0); 639 break; 640 case IRQ_TYPE_EDGE_RISING: 641 irq_set_handler_locked(data, handle_edge_irq); 642 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0); 643 break; 644 case IRQ_TYPE_EDGE_FALLING: 645 irq_set_handler_locked(data, handle_edge_irq); 646 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0); 647 break; 648 case IRQ_TYPE_LEVEL_HIGH: 649 irq_set_handler_locked(data, handle_level_irq); 650 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH); 651 break; 652 case IRQ_TYPE_LEVEL_LOW: 653 irq_set_handler_locked(data, handle_level_irq); 654 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW); 655 break; 656 default: 657 return -EINVAL; 658 } 659 660 return 0; 661 } 662 663 static const struct irq_chip microchip_sgpio_irqchip = { 664 .name = "gpio", 665 .irq_mask = microchip_sgpio_irq_mask, 666 .irq_ack = microchip_sgpio_irq_ack, 667 .irq_unmask = microchip_sgpio_irq_unmask, 668 .irq_set_type = microchip_sgpio_irq_set_type, 669 }; 670 671 static void sgpio_irq_handler(struct irq_desc *desc) 672 { 673 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 674 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 675 struct sgpio_bank *bank = gpiochip_get_data(chip); 676 struct sgpio_priv *priv = bank->priv; 677 int bit, port, gpio; 678 long val; 679 680 for (bit = 0; bit < priv->bitcount; bit++) { 681 val = sgpio_readl(priv, REG_INT_IDENT, bit); 682 if (!val) 683 continue; 684 685 chained_irq_enter(parent_chip, desc); 686 687 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) { 688 gpio = sgpio_addr_to_pin(priv, port, bit); 689 generic_handle_domain_irq(chip->irq.domain, gpio); 690 } 691 692 chained_irq_exit(parent_chip, desc); 693 } 694 } 695 696 static int microchip_sgpio_register_bank(struct device *dev, 697 struct sgpio_priv *priv, 698 struct fwnode_handle *fwnode, 699 int bankno) 700 { 701 struct pinctrl_pin_desc *pins; 702 struct pinctrl_desc *pctl_desc; 703 struct pinctrl_dev *pctldev; 704 struct sgpio_bank *bank; 705 struct gpio_chip *gc; 706 u32 ngpios; 707 int i, ret; 708 709 /* Get overall bank struct */ 710 bank = (bankno == 0) ? &priv->in : &priv->out; 711 bank->priv = priv; 712 713 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) { 714 dev_info(dev, "failed to get number of gpios for bank%d\n", 715 bankno); 716 ngpios = 64; 717 } 718 719 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD; 720 if (priv->bitcount > SGPIO_MAX_BITS) { 721 dev_err(dev, "Bit width exceeds maximum (%d)\n", 722 SGPIO_MAX_BITS); 723 return -EINVAL; 724 } 725 726 pctl_desc = &bank->pctl_desc; 727 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput", 728 dev_name(dev), 729 bank->is_input ? "in" : "out"); 730 pctl_desc->pctlops = &sgpio_pctl_ops; 731 pctl_desc->pmxops = &sgpio_pmx_ops; 732 pctl_desc->confops = &sgpio_confops; 733 pctl_desc->owner = THIS_MODULE; 734 735 pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL); 736 if (!pins) 737 return -ENOMEM; 738 739 pctl_desc->npins = ngpios; 740 pctl_desc->pins = pins; 741 742 for (i = 0; i < ngpios; i++) { 743 struct sgpio_port_addr addr; 744 745 sgpio_pin_to_addr(priv, i, &addr); 746 747 pins[i].number = i; 748 pins[i].name = devm_kasprintf(dev, GFP_KERNEL, 749 "SGPIO_%c_p%db%d", 750 bank->is_input ? 'I' : 'O', 751 addr.port, addr.bit); 752 if (!pins[i].name) 753 return -ENOMEM; 754 } 755 756 pctldev = devm_pinctrl_register(dev, pctl_desc, bank); 757 if (IS_ERR(pctldev)) 758 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n"); 759 760 gc = &bank->gpio; 761 gc->label = pctl_desc->name; 762 gc->parent = dev; 763 gc->of_node = to_of_node(fwnode); 764 gc->owner = THIS_MODULE; 765 gc->get_direction = microchip_sgpio_get_direction; 766 gc->direction_input = microchip_sgpio_direction_input; 767 gc->direction_output = microchip_sgpio_direction_output; 768 gc->get = microchip_sgpio_get_value; 769 gc->set = microchip_sgpio_set_value; 770 gc->request = gpiochip_generic_request; 771 gc->free = gpiochip_generic_free; 772 gc->of_xlate = microchip_sgpio_of_xlate; 773 gc->of_gpio_n_cells = 3; 774 gc->base = -1; 775 gc->ngpio = ngpios; 776 777 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) { 778 int irq = fwnode_irq_get(fwnode, 0); 779 780 if (irq) { 781 struct gpio_irq_chip *girq = &gc->irq; 782 783 girq->chip = devm_kmemdup(dev, µchip_sgpio_irqchip, 784 sizeof(microchip_sgpio_irqchip), 785 GFP_KERNEL); 786 if (!girq->chip) 787 return -ENOMEM; 788 girq->parent_handler = sgpio_irq_handler; 789 girq->num_parents = 1; 790 girq->parents = devm_kcalloc(dev, 1, 791 sizeof(*girq->parents), 792 GFP_KERNEL); 793 if (!girq->parents) 794 return -ENOMEM; 795 girq->parents[0] = irq; 796 girq->default_type = IRQ_TYPE_NONE; 797 girq->handler = handle_bad_irq; 798 799 /* Disable all individual pins */ 800 for (i = 0; i < SGPIO_MAX_BITS; i++) 801 sgpio_writel(priv, 0, REG_INT_ENABLE, i); 802 /* Master enable */ 803 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA); 804 } 805 } 806 807 ret = devm_gpiochip_add_data(dev, gc, bank); 808 if (ret) 809 dev_err(dev, "Failed to register: ret %d\n", ret); 810 811 return ret; 812 } 813 814 static int microchip_sgpio_probe(struct platform_device *pdev) 815 { 816 int div_clock = 0, ret, port, i, nbanks; 817 struct device *dev = &pdev->dev; 818 struct fwnode_handle *fwnode; 819 struct reset_control *reset; 820 struct sgpio_priv *priv; 821 struct clk *clk; 822 u32 __iomem *regs; 823 u32 val; 824 struct regmap_config regmap_config = { 825 .reg_bits = 32, 826 .val_bits = 32, 827 .reg_stride = 4, 828 }; 829 830 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 831 if (!priv) 832 return -ENOMEM; 833 834 priv->dev = dev; 835 836 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); 837 if (IS_ERR(reset)) 838 return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n"); 839 reset_control_reset(reset); 840 841 clk = devm_clk_get(dev, NULL); 842 if (IS_ERR(clk)) 843 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n"); 844 845 div_clock = clk_get_rate(clk); 846 if (device_property_read_u32(dev, "bus-frequency", &priv->clock)) 847 priv->clock = 12500000; 848 if (priv->clock == 0 || priv->clock > (div_clock / 2)) { 849 dev_err(dev, "Invalid frequency %d\n", priv->clock); 850 return -EINVAL; 851 } 852 853 regs = devm_platform_ioremap_resource(pdev, 0); 854 if (IS_ERR(regs)) 855 return PTR_ERR(regs); 856 857 priv->regs = devm_regmap_init_mmio(dev, regs, ®map_config); 858 if (IS_ERR(priv->regs)) 859 return PTR_ERR(priv->regs); 860 861 priv->properties = device_get_match_data(dev); 862 priv->in.is_input = true; 863 864 /* Get rest of device properties */ 865 ret = microchip_sgpio_get_ports(priv); 866 if (ret) 867 return ret; 868 869 nbanks = device_get_child_node_count(dev); 870 if (nbanks != 2) { 871 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks); 872 return -EINVAL; 873 } 874 875 i = 0; 876 device_for_each_child_node(dev, fwnode) { 877 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++); 878 if (ret) { 879 fwnode_handle_put(fwnode); 880 return ret; 881 } 882 } 883 884 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) { 885 dev_err(dev, "Banks must have same GPIO count\n"); 886 return -ERANGE; 887 } 888 889 sgpio_configure_bitstream(priv); 890 891 val = max(2U, div_clock / priv->clock); 892 sgpio_configure_clock(priv, val); 893 894 for (port = 0; port < SGPIO_BITS_PER_WORD; port++) 895 sgpio_writel(priv, 0, REG_PORT_CONFIG, port); 896 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0); 897 898 return 0; 899 } 900 901 static const struct of_device_id microchip_sgpio_gpio_of_match[] = { 902 { 903 .compatible = "microchip,sparx5-sgpio", 904 .data = &properties_sparx5, 905 }, { 906 .compatible = "mscc,luton-sgpio", 907 .data = &properties_luton, 908 }, { 909 .compatible = "mscc,ocelot-sgpio", 910 .data = &properties_ocelot, 911 }, { 912 /* sentinel */ 913 } 914 }; 915 916 static struct platform_driver microchip_sgpio_pinctrl_driver = { 917 .driver = { 918 .name = "pinctrl-microchip-sgpio", 919 .of_match_table = microchip_sgpio_gpio_of_match, 920 .suppress_bind_attrs = true, 921 }, 922 .probe = microchip_sgpio_probe, 923 }; 924 builtin_platform_driver(microchip_sgpio_pinctrl_driver); 925