1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Microsemi/Microchip SoCs serial gpio driver 4 * 5 * Author: Lars Povlsen <lars.povlsen@microchip.com> 6 * 7 * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/clk.h> 13 #include <linux/gpio/driver.h> 14 #include <linux/io.h> 15 #include <linux/mod_devicetable.h> 16 #include <linux/module.h> 17 #include <linux/pinctrl/pinmux.h> 18 #include <linux/platform_device.h> 19 #include <linux/property.h> 20 #include <linux/regmap.h> 21 #include <linux/reset.h> 22 #include <linux/spinlock.h> 23 24 #include "core.h" 25 #include "pinconf.h" 26 27 #define SGPIO_BITS_PER_WORD 32 28 #define SGPIO_MAX_BITS 4 29 #define SGPIO_SRC_BITS 3 /* 3 bit wide field per pin */ 30 31 enum { 32 REG_INPUT_DATA, 33 REG_PORT_CONFIG, 34 REG_PORT_ENABLE, 35 REG_SIO_CONFIG, 36 REG_SIO_CLOCK, 37 REG_INT_POLARITY, 38 REG_INT_TRIGGER, 39 REG_INT_ACK, 40 REG_INT_ENABLE, 41 REG_INT_IDENT, 42 MAXREG 43 }; 44 45 enum { 46 SGPIO_ARCH_LUTON, 47 SGPIO_ARCH_OCELOT, 48 SGPIO_ARCH_SPARX5, 49 }; 50 51 enum { 52 SGPIO_FLAGS_HAS_IRQ = BIT(0), 53 }; 54 55 struct sgpio_properties { 56 int arch; 57 int flags; 58 u8 regoff[MAXREG]; 59 }; 60 61 #define SGPIO_LUTON_AUTO_REPEAT BIT(5) 62 #define SGPIO_LUTON_PORT_WIDTH GENMASK(3, 2) 63 #define SGPIO_LUTON_CLK_FREQ GENMASK(11, 0) 64 #define SGPIO_LUTON_BIT_SOURCE GENMASK(11, 0) 65 66 #define SGPIO_OCELOT_AUTO_REPEAT BIT(10) 67 #define SGPIO_OCELOT_SINGLE_SHOT BIT(11) 68 #define SGPIO_OCELOT_PORT_WIDTH GENMASK(8, 7) 69 #define SGPIO_OCELOT_CLK_FREQ GENMASK(19, 8) 70 #define SGPIO_OCELOT_BIT_SOURCE GENMASK(23, 12) 71 72 #define SGPIO_SPARX5_AUTO_REPEAT BIT(6) 73 #define SGPIO_SPARX5_SINGLE_SHOT BIT(7) 74 #define SGPIO_SPARX5_PORT_WIDTH GENMASK(4, 3) 75 #define SGPIO_SPARX5_CLK_FREQ GENMASK(19, 8) 76 #define SGPIO_SPARX5_BIT_SOURCE GENMASK(23, 12) 77 78 #define SGPIO_MASTER_INTR_ENA BIT(0) 79 80 #define SGPIO_INT_TRG_LEVEL 0 81 #define SGPIO_INT_TRG_EDGE 1 82 #define SGPIO_INT_TRG_EDGE_FALL 2 83 #define SGPIO_INT_TRG_EDGE_RISE 3 84 85 #define SGPIO_TRG_LEVEL_HIGH 0 86 #define SGPIO_TRG_LEVEL_LOW 1 87 88 static const struct sgpio_properties properties_luton = { 89 .arch = SGPIO_ARCH_LUTON, 90 .regoff = { 0x00, 0x09, 0x29, 0x2a, 0x2b }, 91 }; 92 93 static const struct sgpio_properties properties_ocelot = { 94 .arch = SGPIO_ARCH_OCELOT, 95 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05 }, 96 }; 97 98 static const struct sgpio_properties properties_sparx5 = { 99 .arch = SGPIO_ARCH_SPARX5, 100 .flags = SGPIO_FLAGS_HAS_IRQ, 101 .regoff = { 0x00, 0x06, 0x26, 0x04, 0x05, 0x2a, 0x32, 0x3a, 0x3e, 0x42 }, 102 }; 103 104 static const char * const functions[] = { "gpio" }; 105 106 struct sgpio_bank { 107 struct sgpio_priv *priv; 108 bool is_input; 109 struct gpio_chip gpio; 110 struct pinctrl_desc pctl_desc; 111 }; 112 113 struct sgpio_priv { 114 struct device *dev; 115 struct sgpio_bank in; 116 struct sgpio_bank out; 117 u32 bitcount; 118 u32 ports; 119 u32 clock; 120 struct regmap *regs; 121 const struct sgpio_properties *properties; 122 spinlock_t lock; 123 /* protects the config register and single shot mode */ 124 struct mutex poll_lock; 125 }; 126 127 struct sgpio_port_addr { 128 u8 port; 129 u8 bit; 130 }; 131 132 static inline void sgpio_pin_to_addr(struct sgpio_priv *priv, int pin, 133 struct sgpio_port_addr *addr) 134 { 135 addr->port = pin / priv->bitcount; 136 addr->bit = pin % priv->bitcount; 137 } 138 139 static inline int sgpio_addr_to_pin(struct sgpio_priv *priv, int port, int bit) 140 { 141 return bit + port * priv->bitcount; 142 } 143 144 static inline u32 sgpio_get_addr(struct sgpio_priv *priv, u32 rno, u32 off) 145 { 146 return (priv->properties->regoff[rno] + off) * 147 regmap_get_reg_stride(priv->regs); 148 } 149 150 static u32 sgpio_readl(struct sgpio_priv *priv, u32 rno, u32 off) 151 { 152 u32 addr = sgpio_get_addr(priv, rno, off); 153 u32 val = 0; 154 int ret; 155 156 ret = regmap_read(priv->regs, addr, &val); 157 WARN_ONCE(ret, "error reading sgpio reg %d\n", ret); 158 159 return val; 160 } 161 162 static void sgpio_writel(struct sgpio_priv *priv, 163 u32 val, u32 rno, u32 off) 164 { 165 u32 addr = sgpio_get_addr(priv, rno, off); 166 int ret; 167 168 ret = regmap_write(priv->regs, addr, val); 169 WARN_ONCE(ret, "error writing sgpio reg %d\n", ret); 170 } 171 172 static inline void sgpio_clrsetbits(struct sgpio_priv *priv, 173 u32 rno, u32 off, u32 clear, u32 set) 174 { 175 u32 addr = sgpio_get_addr(priv, rno, off); 176 int ret; 177 178 ret = regmap_update_bits(priv->regs, addr, clear | set, set); 179 WARN_ONCE(ret, "error updating sgpio reg %d\n", ret); 180 } 181 182 static inline void sgpio_configure_bitstream(struct sgpio_priv *priv) 183 { 184 int width = priv->bitcount - 1; 185 u32 clr, set; 186 187 switch (priv->properties->arch) { 188 case SGPIO_ARCH_LUTON: 189 clr = SGPIO_LUTON_PORT_WIDTH; 190 set = SGPIO_LUTON_AUTO_REPEAT | 191 FIELD_PREP(SGPIO_LUTON_PORT_WIDTH, width); 192 break; 193 case SGPIO_ARCH_OCELOT: 194 clr = SGPIO_OCELOT_PORT_WIDTH; 195 set = SGPIO_OCELOT_AUTO_REPEAT | 196 FIELD_PREP(SGPIO_OCELOT_PORT_WIDTH, width); 197 break; 198 case SGPIO_ARCH_SPARX5: 199 clr = SGPIO_SPARX5_PORT_WIDTH; 200 set = SGPIO_SPARX5_AUTO_REPEAT | 201 FIELD_PREP(SGPIO_SPARX5_PORT_WIDTH, width); 202 break; 203 default: 204 return; 205 } 206 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, clr, set); 207 } 208 209 static inline void sgpio_configure_clock(struct sgpio_priv *priv, u32 clkfrq) 210 { 211 u32 clr, set; 212 213 switch (priv->properties->arch) { 214 case SGPIO_ARCH_LUTON: 215 clr = SGPIO_LUTON_CLK_FREQ; 216 set = FIELD_PREP(SGPIO_LUTON_CLK_FREQ, clkfrq); 217 break; 218 case SGPIO_ARCH_OCELOT: 219 clr = SGPIO_OCELOT_CLK_FREQ; 220 set = FIELD_PREP(SGPIO_OCELOT_CLK_FREQ, clkfrq); 221 break; 222 case SGPIO_ARCH_SPARX5: 223 clr = SGPIO_SPARX5_CLK_FREQ; 224 set = FIELD_PREP(SGPIO_SPARX5_CLK_FREQ, clkfrq); 225 break; 226 default: 227 return; 228 } 229 sgpio_clrsetbits(priv, REG_SIO_CLOCK, 0, clr, set); 230 } 231 232 static int sgpio_single_shot(struct sgpio_priv *priv) 233 { 234 u32 addr = sgpio_get_addr(priv, REG_SIO_CONFIG, 0); 235 int ret, ret2; 236 u32 ctrl; 237 unsigned int single_shot; 238 unsigned int auto_repeat; 239 240 switch (priv->properties->arch) { 241 case SGPIO_ARCH_LUTON: 242 /* not supported for now */ 243 return 0; 244 case SGPIO_ARCH_OCELOT: 245 single_shot = SGPIO_OCELOT_SINGLE_SHOT; 246 auto_repeat = SGPIO_OCELOT_AUTO_REPEAT; 247 break; 248 case SGPIO_ARCH_SPARX5: 249 single_shot = SGPIO_SPARX5_SINGLE_SHOT; 250 auto_repeat = SGPIO_SPARX5_AUTO_REPEAT; 251 break; 252 default: 253 return -EINVAL; 254 } 255 256 /* 257 * Trigger immediate burst. This only works when auto repeat is turned 258 * off. Otherwise, the single shot bit will never be cleared by the 259 * hardware. Measurements showed that an update might take as long as 260 * the burst gap. On a LAN9668 this is about 50ms for the largest 261 * setting. 262 * After the manual burst, reenable the auto repeat mode again. 263 */ 264 mutex_lock(&priv->poll_lock); 265 ret = regmap_update_bits(priv->regs, addr, single_shot | auto_repeat, 266 single_shot); 267 if (ret) 268 goto out; 269 270 ret = regmap_read_poll_timeout(priv->regs, addr, ctrl, 271 !(ctrl & single_shot), 100, 60000); 272 273 /* reenable auto repeat mode even if there was an error */ 274 ret2 = regmap_update_bits(priv->regs, addr, auto_repeat, auto_repeat); 275 out: 276 mutex_unlock(&priv->poll_lock); 277 278 return ret ?: ret2; 279 } 280 281 static int sgpio_output_set(struct sgpio_priv *priv, 282 struct sgpio_port_addr *addr, 283 int value) 284 { 285 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 286 u32 reg = sgpio_get_addr(priv, REG_PORT_CONFIG, addr->port); 287 bool changed; 288 u32 clr, set; 289 int ret; 290 291 switch (priv->properties->arch) { 292 case SGPIO_ARCH_LUTON: 293 clr = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, BIT(bit)); 294 set = FIELD_PREP(SGPIO_LUTON_BIT_SOURCE, value << bit); 295 break; 296 case SGPIO_ARCH_OCELOT: 297 clr = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, BIT(bit)); 298 set = FIELD_PREP(SGPIO_OCELOT_BIT_SOURCE, value << bit); 299 break; 300 case SGPIO_ARCH_SPARX5: 301 clr = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, BIT(bit)); 302 set = FIELD_PREP(SGPIO_SPARX5_BIT_SOURCE, value << bit); 303 break; 304 default: 305 return -EINVAL; 306 } 307 308 ret = regmap_update_bits_check(priv->regs, reg, clr | set, set, 309 &changed); 310 if (ret) 311 return ret; 312 313 if (changed) { 314 ret = sgpio_single_shot(priv); 315 if (ret) 316 return ret; 317 } 318 319 return 0; 320 } 321 322 static int sgpio_output_get(struct sgpio_priv *priv, 323 struct sgpio_port_addr *addr) 324 { 325 u32 val, portval = sgpio_readl(priv, REG_PORT_CONFIG, addr->port); 326 unsigned int bit = SGPIO_SRC_BITS * addr->bit; 327 328 switch (priv->properties->arch) { 329 case SGPIO_ARCH_LUTON: 330 val = FIELD_GET(SGPIO_LUTON_BIT_SOURCE, portval); 331 break; 332 case SGPIO_ARCH_OCELOT: 333 val = FIELD_GET(SGPIO_OCELOT_BIT_SOURCE, portval); 334 break; 335 case SGPIO_ARCH_SPARX5: 336 val = FIELD_GET(SGPIO_SPARX5_BIT_SOURCE, portval); 337 break; 338 default: 339 val = 0; 340 break; 341 } 342 return !!(val & BIT(bit)); 343 } 344 345 static int sgpio_input_get(struct sgpio_priv *priv, 346 struct sgpio_port_addr *addr) 347 { 348 return !!(sgpio_readl(priv, REG_INPUT_DATA, addr->bit) & BIT(addr->port)); 349 } 350 351 static int sgpio_pinconf_get(struct pinctrl_dev *pctldev, 352 unsigned int pin, unsigned long *config) 353 { 354 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 355 u32 param = pinconf_to_config_param(*config); 356 struct sgpio_priv *priv = bank->priv; 357 struct sgpio_port_addr addr; 358 int val; 359 360 sgpio_pin_to_addr(priv, pin, &addr); 361 362 switch (param) { 363 case PIN_CONFIG_INPUT_ENABLE: 364 val = bank->is_input; 365 break; 366 367 case PIN_CONFIG_OUTPUT_ENABLE: 368 val = !bank->is_input; 369 break; 370 371 case PIN_CONFIG_OUTPUT: 372 if (bank->is_input) 373 return -EINVAL; 374 val = sgpio_output_get(priv, &addr); 375 break; 376 377 default: 378 return -ENOTSUPP; 379 } 380 381 *config = pinconf_to_config_packed(param, val); 382 383 return 0; 384 } 385 386 static int sgpio_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 387 unsigned long *configs, unsigned int num_configs) 388 { 389 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 390 struct sgpio_priv *priv = bank->priv; 391 struct sgpio_port_addr addr; 392 int cfg, err = 0; 393 u32 param, arg; 394 395 sgpio_pin_to_addr(priv, pin, &addr); 396 397 for (cfg = 0; cfg < num_configs; cfg++) { 398 param = pinconf_to_config_param(configs[cfg]); 399 arg = pinconf_to_config_argument(configs[cfg]); 400 401 switch (param) { 402 case PIN_CONFIG_OUTPUT: 403 if (bank->is_input) 404 return -EINVAL; 405 err = sgpio_output_set(priv, &addr, arg); 406 break; 407 408 default: 409 err = -ENOTSUPP; 410 } 411 } 412 413 return err; 414 } 415 416 static const struct pinconf_ops sgpio_confops = { 417 .is_generic = true, 418 .pin_config_get = sgpio_pinconf_get, 419 .pin_config_set = sgpio_pinconf_set, 420 .pin_config_config_dbg_show = pinconf_generic_dump_config, 421 }; 422 423 static int sgpio_get_functions_count(struct pinctrl_dev *pctldev) 424 { 425 return 1; 426 } 427 428 static const char *sgpio_get_function_name(struct pinctrl_dev *pctldev, 429 unsigned int function) 430 { 431 return functions[0]; 432 } 433 434 static int sgpio_get_function_groups(struct pinctrl_dev *pctldev, 435 unsigned int function, 436 const char *const **groups, 437 unsigned *const num_groups) 438 { 439 *groups = functions; 440 *num_groups = ARRAY_SIZE(functions); 441 442 return 0; 443 } 444 445 static int sgpio_pinmux_set_mux(struct pinctrl_dev *pctldev, 446 unsigned int selector, unsigned int group) 447 { 448 return 0; 449 } 450 451 static int sgpio_gpio_set_direction(struct pinctrl_dev *pctldev, 452 struct pinctrl_gpio_range *range, 453 unsigned int pin, bool input) 454 { 455 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 456 457 return (input == bank->is_input) ? 0 : -EINVAL; 458 } 459 460 static int sgpio_gpio_request_enable(struct pinctrl_dev *pctldev, 461 struct pinctrl_gpio_range *range, 462 unsigned int offset) 463 { 464 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 465 struct sgpio_priv *priv = bank->priv; 466 struct sgpio_port_addr addr; 467 468 sgpio_pin_to_addr(priv, offset, &addr); 469 470 if ((priv->ports & BIT(addr.port)) == 0) { 471 dev_warn(priv->dev, "Request port %d.%d: Port is not enabled\n", 472 addr.port, addr.bit); 473 return -EINVAL; 474 } 475 476 return 0; 477 } 478 479 static const struct pinmux_ops sgpio_pmx_ops = { 480 .get_functions_count = sgpio_get_functions_count, 481 .get_function_name = sgpio_get_function_name, 482 .get_function_groups = sgpio_get_function_groups, 483 .set_mux = sgpio_pinmux_set_mux, 484 .gpio_set_direction = sgpio_gpio_set_direction, 485 .gpio_request_enable = sgpio_gpio_request_enable, 486 }; 487 488 static int sgpio_pctl_get_groups_count(struct pinctrl_dev *pctldev) 489 { 490 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 491 492 return bank->pctl_desc.npins; 493 } 494 495 static const char *sgpio_pctl_get_group_name(struct pinctrl_dev *pctldev, 496 unsigned int group) 497 { 498 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 499 500 return bank->pctl_desc.pins[group].name; 501 } 502 503 static int sgpio_pctl_get_group_pins(struct pinctrl_dev *pctldev, 504 unsigned int group, 505 const unsigned int **pins, 506 unsigned int *num_pins) 507 { 508 struct sgpio_bank *bank = pinctrl_dev_get_drvdata(pctldev); 509 510 *pins = &bank->pctl_desc.pins[group].number; 511 *num_pins = 1; 512 513 return 0; 514 } 515 516 static const struct pinctrl_ops sgpio_pctl_ops = { 517 .get_groups_count = sgpio_pctl_get_groups_count, 518 .get_group_name = sgpio_pctl_get_group_name, 519 .get_group_pins = sgpio_pctl_get_group_pins, 520 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 521 .dt_free_map = pinconf_generic_dt_free_map, 522 }; 523 524 static int microchip_sgpio_direction_input(struct gpio_chip *gc, unsigned int gpio) 525 { 526 struct sgpio_bank *bank = gpiochip_get_data(gc); 527 528 /* Fixed-position function */ 529 return bank->is_input ? 0 : -EINVAL; 530 } 531 532 static int microchip_sgpio_direction_output(struct gpio_chip *gc, 533 unsigned int gpio, int value) 534 { 535 struct sgpio_bank *bank = gpiochip_get_data(gc); 536 struct sgpio_priv *priv = bank->priv; 537 struct sgpio_port_addr addr; 538 539 /* Fixed-position function */ 540 if (bank->is_input) 541 return -EINVAL; 542 543 sgpio_pin_to_addr(priv, gpio, &addr); 544 545 return sgpio_output_set(priv, &addr, value); 546 } 547 548 static int microchip_sgpio_get_direction(struct gpio_chip *gc, unsigned int gpio) 549 { 550 struct sgpio_bank *bank = gpiochip_get_data(gc); 551 552 return bank->is_input ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT; 553 } 554 555 static void microchip_sgpio_set_value(struct gpio_chip *gc, 556 unsigned int gpio, int value) 557 { 558 microchip_sgpio_direction_output(gc, gpio, value); 559 } 560 561 static int microchip_sgpio_get_value(struct gpio_chip *gc, unsigned int gpio) 562 { 563 struct sgpio_bank *bank = gpiochip_get_data(gc); 564 struct sgpio_priv *priv = bank->priv; 565 struct sgpio_port_addr addr; 566 567 sgpio_pin_to_addr(priv, gpio, &addr); 568 569 return bank->is_input ? sgpio_input_get(priv, &addr) : sgpio_output_get(priv, &addr); 570 } 571 572 static int microchip_sgpio_of_xlate(struct gpio_chip *gc, 573 const struct of_phandle_args *gpiospec, 574 u32 *flags) 575 { 576 struct sgpio_bank *bank = gpiochip_get_data(gc); 577 struct sgpio_priv *priv = bank->priv; 578 int pin; 579 580 /* 581 * Note that the SGIO pin is defined by *2* numbers, a port 582 * number between 0 and 31, and a bit index, 0 to 3. 583 */ 584 if (gpiospec->args[0] > SGPIO_BITS_PER_WORD || 585 gpiospec->args[1] > priv->bitcount) 586 return -EINVAL; 587 588 pin = sgpio_addr_to_pin(priv, gpiospec->args[0], gpiospec->args[1]); 589 590 if (pin > gc->ngpio) 591 return -EINVAL; 592 593 if (flags) 594 *flags = gpiospec->args[2]; 595 596 return pin; 597 } 598 599 static int microchip_sgpio_get_ports(struct sgpio_priv *priv) 600 { 601 const char *range_property_name = "microchip,sgpio-port-ranges"; 602 struct device *dev = priv->dev; 603 u32 range_params[64]; 604 int i, nranges, ret; 605 606 /* Calculate port mask */ 607 nranges = device_property_count_u32(dev, range_property_name); 608 if (nranges < 2 || nranges % 2 || nranges > ARRAY_SIZE(range_params)) { 609 dev_err(dev, "%s port range: '%s' property\n", 610 nranges == -EINVAL ? "Missing" : "Invalid", 611 range_property_name); 612 return -EINVAL; 613 } 614 615 ret = device_property_read_u32_array(dev, range_property_name, 616 range_params, nranges); 617 if (ret) { 618 dev_err(dev, "failed to parse '%s' property: %d\n", 619 range_property_name, ret); 620 return ret; 621 } 622 for (i = 0; i < nranges; i += 2) { 623 int start, end; 624 625 start = range_params[i]; 626 end = range_params[i + 1]; 627 if (start > end || end >= SGPIO_BITS_PER_WORD) { 628 dev_err(dev, "Ill-formed port-range [%d:%d]\n", 629 start, end); 630 } 631 priv->ports |= GENMASK(end, start); 632 } 633 634 return 0; 635 } 636 637 static void microchip_sgpio_irq_settype(struct irq_data *data, 638 int type, 639 int polarity) 640 { 641 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 642 struct sgpio_bank *bank = gpiochip_get_data(chip); 643 unsigned int gpio = irqd_to_hwirq(data); 644 struct sgpio_port_addr addr; 645 unsigned long flags; 646 u32 ena; 647 648 sgpio_pin_to_addr(bank->priv, gpio, &addr); 649 650 spin_lock_irqsave(&bank->priv->lock, flags); 651 652 /* Disable interrupt while changing type */ 653 ena = sgpio_readl(bank->priv, REG_INT_ENABLE, addr.bit); 654 sgpio_writel(bank->priv, ena & ~BIT(addr.port), REG_INT_ENABLE, addr.bit); 655 656 /* Type value spread over 2 registers sets: low, high bit */ 657 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, addr.bit, 658 BIT(addr.port), (!!(type & 0x1)) << addr.port); 659 sgpio_clrsetbits(bank->priv, REG_INT_TRIGGER, SGPIO_MAX_BITS + addr.bit, 660 BIT(addr.port), (!!(type & 0x2)) << addr.port); 661 662 if (type == SGPIO_INT_TRG_LEVEL) 663 sgpio_clrsetbits(bank->priv, REG_INT_POLARITY, addr.bit, 664 BIT(addr.port), polarity << addr.port); 665 666 /* Possibly re-enable interrupts */ 667 sgpio_writel(bank->priv, ena, REG_INT_ENABLE, addr.bit); 668 669 spin_unlock_irqrestore(&bank->priv->lock, flags); 670 } 671 672 static void microchip_sgpio_irq_setreg(struct irq_data *data, 673 int reg, 674 bool clear) 675 { 676 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 677 struct sgpio_bank *bank = gpiochip_get_data(chip); 678 unsigned int gpio = irqd_to_hwirq(data); 679 struct sgpio_port_addr addr; 680 681 sgpio_pin_to_addr(bank->priv, gpio, &addr); 682 683 if (clear) 684 sgpio_clrsetbits(bank->priv, reg, addr.bit, BIT(addr.port), 0); 685 else 686 sgpio_clrsetbits(bank->priv, reg, addr.bit, 0, BIT(addr.port)); 687 } 688 689 static void microchip_sgpio_irq_mask(struct irq_data *data) 690 { 691 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 692 693 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, true); 694 gpiochip_disable_irq(chip, data->hwirq); 695 } 696 697 static void microchip_sgpio_irq_unmask(struct irq_data *data) 698 { 699 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 700 701 gpiochip_enable_irq(chip, data->hwirq); 702 microchip_sgpio_irq_setreg(data, REG_INT_ENABLE, false); 703 } 704 705 static void microchip_sgpio_irq_ack(struct irq_data *data) 706 { 707 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 708 struct sgpio_bank *bank = gpiochip_get_data(chip); 709 unsigned int gpio = irqd_to_hwirq(data); 710 struct sgpio_port_addr addr; 711 712 sgpio_pin_to_addr(bank->priv, gpio, &addr); 713 714 sgpio_writel(bank->priv, BIT(addr.port), REG_INT_ACK, addr.bit); 715 } 716 717 static int microchip_sgpio_irq_set_type(struct irq_data *data, unsigned int type) 718 { 719 type &= IRQ_TYPE_SENSE_MASK; 720 721 switch (type) { 722 case IRQ_TYPE_EDGE_BOTH: 723 irq_set_handler_locked(data, handle_edge_irq); 724 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE, 0); 725 break; 726 case IRQ_TYPE_EDGE_RISING: 727 irq_set_handler_locked(data, handle_edge_irq); 728 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_RISE, 0); 729 break; 730 case IRQ_TYPE_EDGE_FALLING: 731 irq_set_handler_locked(data, handle_edge_irq); 732 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_EDGE_FALL, 0); 733 break; 734 case IRQ_TYPE_LEVEL_HIGH: 735 irq_set_handler_locked(data, handle_level_irq); 736 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_HIGH); 737 break; 738 case IRQ_TYPE_LEVEL_LOW: 739 irq_set_handler_locked(data, handle_level_irq); 740 microchip_sgpio_irq_settype(data, SGPIO_INT_TRG_LEVEL, SGPIO_TRG_LEVEL_LOW); 741 break; 742 default: 743 return -EINVAL; 744 } 745 746 return 0; 747 } 748 749 static const struct irq_chip microchip_sgpio_irqchip = { 750 .name = "gpio", 751 .irq_mask = microchip_sgpio_irq_mask, 752 .irq_ack = microchip_sgpio_irq_ack, 753 .irq_unmask = microchip_sgpio_irq_unmask, 754 .irq_set_type = microchip_sgpio_irq_set_type, 755 .flags = IRQCHIP_IMMUTABLE, 756 GPIOCHIP_IRQ_RESOURCE_HELPERS, 757 }; 758 759 static void sgpio_irq_handler(struct irq_desc *desc) 760 { 761 struct irq_chip *parent_chip = irq_desc_get_chip(desc); 762 struct gpio_chip *chip = irq_desc_get_handler_data(desc); 763 struct sgpio_bank *bank = gpiochip_get_data(chip); 764 struct sgpio_priv *priv = bank->priv; 765 int bit, port, gpio; 766 long val; 767 768 for (bit = 0; bit < priv->bitcount; bit++) { 769 val = sgpio_readl(priv, REG_INT_IDENT, bit); 770 if (!val) 771 continue; 772 773 chained_irq_enter(parent_chip, desc); 774 775 for_each_set_bit(port, &val, SGPIO_BITS_PER_WORD) { 776 gpio = sgpio_addr_to_pin(priv, port, bit); 777 generic_handle_domain_irq(chip->irq.domain, gpio); 778 } 779 780 chained_irq_exit(parent_chip, desc); 781 } 782 } 783 784 static int microchip_sgpio_register_bank(struct device *dev, 785 struct sgpio_priv *priv, 786 struct fwnode_handle *fwnode, 787 int bankno) 788 { 789 struct pinctrl_pin_desc *pins; 790 struct pinctrl_desc *pctl_desc; 791 struct pinctrl_dev *pctldev; 792 struct sgpio_bank *bank; 793 struct gpio_chip *gc; 794 u32 ngpios; 795 int i, ret; 796 797 /* Get overall bank struct */ 798 bank = (bankno == 0) ? &priv->in : &priv->out; 799 bank->priv = priv; 800 801 if (fwnode_property_read_u32(fwnode, "ngpios", &ngpios)) { 802 dev_info(dev, "failed to get number of gpios for bank%d\n", 803 bankno); 804 ngpios = 64; 805 } 806 807 priv->bitcount = ngpios / SGPIO_BITS_PER_WORD; 808 if (priv->bitcount > SGPIO_MAX_BITS) { 809 dev_err(dev, "Bit width exceeds maximum (%d)\n", 810 SGPIO_MAX_BITS); 811 return -EINVAL; 812 } 813 814 pctl_desc = &bank->pctl_desc; 815 pctl_desc->name = devm_kasprintf(dev, GFP_KERNEL, "%s-%sput", 816 dev_name(dev), 817 bank->is_input ? "in" : "out"); 818 pctl_desc->pctlops = &sgpio_pctl_ops; 819 pctl_desc->pmxops = &sgpio_pmx_ops; 820 pctl_desc->confops = &sgpio_confops; 821 pctl_desc->owner = THIS_MODULE; 822 823 pins = devm_kzalloc(dev, sizeof(*pins)*ngpios, GFP_KERNEL); 824 if (!pins) 825 return -ENOMEM; 826 827 pctl_desc->npins = ngpios; 828 pctl_desc->pins = pins; 829 830 for (i = 0; i < ngpios; i++) { 831 struct sgpio_port_addr addr; 832 833 sgpio_pin_to_addr(priv, i, &addr); 834 835 pins[i].number = i; 836 pins[i].name = devm_kasprintf(dev, GFP_KERNEL, 837 "SGPIO_%c_p%db%d", 838 bank->is_input ? 'I' : 'O', 839 addr.port, addr.bit); 840 if (!pins[i].name) 841 return -ENOMEM; 842 } 843 844 pctldev = devm_pinctrl_register(dev, pctl_desc, bank); 845 if (IS_ERR(pctldev)) 846 return dev_err_probe(dev, PTR_ERR(pctldev), "Failed to register pinctrl\n"); 847 848 gc = &bank->gpio; 849 gc->label = pctl_desc->name; 850 gc->parent = dev; 851 gc->fwnode = fwnode; 852 gc->owner = THIS_MODULE; 853 gc->get_direction = microchip_sgpio_get_direction; 854 gc->direction_input = microchip_sgpio_direction_input; 855 gc->direction_output = microchip_sgpio_direction_output; 856 gc->get = microchip_sgpio_get_value; 857 gc->set = microchip_sgpio_set_value; 858 gc->request = gpiochip_generic_request; 859 gc->free = gpiochip_generic_free; 860 gc->of_xlate = microchip_sgpio_of_xlate; 861 gc->of_gpio_n_cells = 3; 862 gc->base = -1; 863 gc->ngpio = ngpios; 864 gc->can_sleep = !bank->is_input; 865 866 if (bank->is_input && priv->properties->flags & SGPIO_FLAGS_HAS_IRQ) { 867 int irq = fwnode_irq_get(fwnode, 0); 868 869 if (irq) { 870 struct gpio_irq_chip *girq = &gc->irq; 871 872 gpio_irq_chip_set_chip(girq, µchip_sgpio_irqchip); 873 girq->parent_handler = sgpio_irq_handler; 874 girq->num_parents = 1; 875 girq->parents = devm_kcalloc(dev, 1, 876 sizeof(*girq->parents), 877 GFP_KERNEL); 878 if (!girq->parents) 879 return -ENOMEM; 880 girq->parents[0] = irq; 881 girq->default_type = IRQ_TYPE_NONE; 882 girq->handler = handle_bad_irq; 883 884 /* Disable all individual pins */ 885 for (i = 0; i < SGPIO_MAX_BITS; i++) 886 sgpio_writel(priv, 0, REG_INT_ENABLE, i); 887 /* Master enable */ 888 sgpio_clrsetbits(priv, REG_SIO_CONFIG, 0, 0, SGPIO_MASTER_INTR_ENA); 889 } 890 } 891 892 ret = devm_gpiochip_add_data(dev, gc, bank); 893 if (ret) 894 dev_err(dev, "Failed to register: ret %d\n", ret); 895 896 return ret; 897 } 898 899 static int microchip_sgpio_probe(struct platform_device *pdev) 900 { 901 int div_clock = 0, ret, port, i, nbanks; 902 struct device *dev = &pdev->dev; 903 struct fwnode_handle *fwnode; 904 struct reset_control *reset; 905 struct sgpio_priv *priv; 906 struct clk *clk; 907 u32 __iomem *regs; 908 u32 val; 909 struct regmap_config regmap_config = { 910 .reg_bits = 32, 911 .val_bits = 32, 912 .reg_stride = 4, 913 }; 914 915 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 916 if (!priv) 917 return -ENOMEM; 918 919 priv->dev = dev; 920 spin_lock_init(&priv->lock); 921 mutex_init(&priv->poll_lock); 922 923 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); 924 if (IS_ERR(reset)) 925 return dev_err_probe(dev, PTR_ERR(reset), "Failed to get reset\n"); 926 reset_control_reset(reset); 927 928 clk = devm_clk_get(dev, NULL); 929 if (IS_ERR(clk)) 930 return dev_err_probe(dev, PTR_ERR(clk), "Failed to get clock\n"); 931 932 div_clock = clk_get_rate(clk); 933 if (device_property_read_u32(dev, "bus-frequency", &priv->clock)) 934 priv->clock = 12500000; 935 if (priv->clock == 0 || priv->clock > (div_clock / 2)) { 936 dev_err(dev, "Invalid frequency %d\n", priv->clock); 937 return -EINVAL; 938 } 939 940 regs = devm_platform_ioremap_resource(pdev, 0); 941 if (IS_ERR(regs)) 942 return PTR_ERR(regs); 943 944 priv->regs = devm_regmap_init_mmio(dev, regs, ®map_config); 945 if (IS_ERR(priv->regs)) 946 return PTR_ERR(priv->regs); 947 948 priv->properties = device_get_match_data(dev); 949 priv->in.is_input = true; 950 951 /* Get rest of device properties */ 952 ret = microchip_sgpio_get_ports(priv); 953 if (ret) 954 return ret; 955 956 nbanks = device_get_child_node_count(dev); 957 if (nbanks != 2) { 958 dev_err(dev, "Must have 2 banks (have %d)\n", nbanks); 959 return -EINVAL; 960 } 961 962 i = 0; 963 device_for_each_child_node(dev, fwnode) { 964 ret = microchip_sgpio_register_bank(dev, priv, fwnode, i++); 965 if (ret) { 966 fwnode_handle_put(fwnode); 967 return ret; 968 } 969 } 970 971 if (priv->in.gpio.ngpio != priv->out.gpio.ngpio) { 972 dev_err(dev, "Banks must have same GPIO count\n"); 973 return -ERANGE; 974 } 975 976 sgpio_configure_bitstream(priv); 977 978 val = max(2U, div_clock / priv->clock); 979 sgpio_configure_clock(priv, val); 980 981 for (port = 0; port < SGPIO_BITS_PER_WORD; port++) 982 sgpio_writel(priv, 0, REG_PORT_CONFIG, port); 983 sgpio_writel(priv, priv->ports, REG_PORT_ENABLE, 0); 984 985 return 0; 986 } 987 988 static const struct of_device_id microchip_sgpio_gpio_of_match[] = { 989 { 990 .compatible = "microchip,sparx5-sgpio", 991 .data = &properties_sparx5, 992 }, { 993 .compatible = "mscc,luton-sgpio", 994 .data = &properties_luton, 995 }, { 996 .compatible = "mscc,ocelot-sgpio", 997 .data = &properties_ocelot, 998 }, { 999 /* sentinel */ 1000 } 1001 }; 1002 1003 static struct platform_driver microchip_sgpio_pinctrl_driver = { 1004 .driver = { 1005 .name = "pinctrl-microchip-sgpio", 1006 .of_match_table = microchip_sgpio_gpio_of_match, 1007 .suppress_bind_attrs = true, 1008 }, 1009 .probe = microchip_sgpio_probe, 1010 }; 1011 builtin_platform_driver(microchip_sgpio_pinctrl_driver); 1012