1 /* 2 * MAX77620 pin control driver. 3 * 4 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 5 * 6 * Author: 7 * Chaitanya Bandi <bandik@nvidia.com> 8 * Laxman Dewangan <ldewangan@nvidia.com> 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms and conditions of the GNU General Public License, 12 * version 2, as published by the Free Software Foundation. 13 */ 14 15 #include <linux/mfd/max77620.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/pinctrl/pinctrl.h> 19 #include <linux/pinctrl/pinconf-generic.h> 20 #include <linux/pinctrl/pinconf.h> 21 #include <linux/pinctrl/pinmux.h> 22 #include <linux/platform_device.h> 23 #include <linux/regmap.h> 24 25 #include "core.h" 26 #include "pinconf.h" 27 #include "pinctrl-utils.h" 28 29 #define MAX77620_PIN_NUM 8 30 31 enum max77620_pin_ppdrv { 32 MAX77620_PIN_UNCONFIG_DRV, 33 MAX77620_PIN_OD_DRV, 34 MAX77620_PIN_PP_DRV, 35 }; 36 37 enum max77620_pinconf_param { 38 MAX77620_ACTIVE_FPS_SOURCE = PIN_CONFIG_END + 1, 39 MAX77620_ACTIVE_FPS_POWER_ON_SLOTS, 40 MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS, 41 MAX77620_SUSPEND_FPS_SOURCE, 42 MAX77620_SUSPEND_FPS_POWER_ON_SLOTS, 43 MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS, 44 }; 45 46 struct max77620_pin_function { 47 const char *name; 48 const char * const *groups; 49 unsigned int ngroups; 50 int mux_option; 51 }; 52 53 struct max77620_cfg_param { 54 const char *property; 55 enum max77620_pinconf_param param; 56 }; 57 58 static const struct pinconf_generic_params max77620_cfg_params[] = { 59 { 60 .property = "maxim,active-fps-source", 61 .param = MAX77620_ACTIVE_FPS_SOURCE, 62 }, { 63 .property = "maxim,active-fps-power-up-slot", 64 .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS, 65 }, { 66 .property = "maxim,active-fps-power-down-slot", 67 .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS, 68 }, { 69 .property = "maxim,suspend-fps-source", 70 .param = MAX77620_SUSPEND_FPS_SOURCE, 71 }, { 72 .property = "maxim,suspend-fps-power-up-slot", 73 .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS, 74 }, { 75 .property = "maxim,suspend-fps-power-down-slot", 76 .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS, 77 }, 78 }; 79 80 enum max77620_alternate_pinmux_option { 81 MAX77620_PINMUX_GPIO = 0, 82 MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1, 83 MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2, 84 MAX77620_PINMUX_32K_OUT1 = 3, 85 MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4, 86 MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5, 87 MAX77620_PINMUX_REFERENCE_OUT = 6, 88 }; 89 90 struct max77620_pingroup { 91 const char *name; 92 const unsigned int pins[1]; 93 unsigned int npins; 94 enum max77620_alternate_pinmux_option alt_option; 95 }; 96 97 struct max77620_pin_info { 98 enum max77620_pin_ppdrv drv_type; 99 int pull_config; 100 }; 101 102 struct max77620_fps_config { 103 int active_fps_src; 104 int active_power_up_slots; 105 int active_power_down_slots; 106 int suspend_fps_src; 107 int suspend_power_up_slots; 108 int suspend_power_down_slots; 109 }; 110 111 struct max77620_pctrl_info { 112 struct device *dev; 113 struct pinctrl_dev *pctl; 114 struct regmap *rmap; 115 int pins_current_opt[MAX77620_GPIO_NR]; 116 const struct max77620_pin_function *functions; 117 unsigned int num_functions; 118 const struct max77620_pingroup *pin_groups; 119 int num_pin_groups; 120 const struct pinctrl_pin_desc *pins; 121 unsigned int num_pins; 122 struct max77620_pin_info pin_info[MAX77620_PIN_NUM]; 123 struct max77620_fps_config fps_config[MAX77620_PIN_NUM]; 124 }; 125 126 static const struct pinctrl_pin_desc max77620_pins_desc[] = { 127 PINCTRL_PIN(MAX77620_GPIO0, "gpio0"), 128 PINCTRL_PIN(MAX77620_GPIO1, "gpio1"), 129 PINCTRL_PIN(MAX77620_GPIO2, "gpio2"), 130 PINCTRL_PIN(MAX77620_GPIO3, "gpio3"), 131 PINCTRL_PIN(MAX77620_GPIO4, "gpio4"), 132 PINCTRL_PIN(MAX77620_GPIO5, "gpio5"), 133 PINCTRL_PIN(MAX77620_GPIO6, "gpio6"), 134 PINCTRL_PIN(MAX77620_GPIO7, "gpio7"), 135 }; 136 137 static const char * const gpio_groups[] = { 138 "gpio0", 139 "gpio1", 140 "gpio2", 141 "gpio3", 142 "gpio4", 143 "gpio5", 144 "gpio6", 145 "gpio7", 146 }; 147 148 #define FUNCTION_GROUP(fname, mux) \ 149 { \ 150 .name = fname, \ 151 .groups = gpio_groups, \ 152 .ngroups = ARRAY_SIZE(gpio_groups), \ 153 .mux_option = MAX77620_PINMUX_##mux, \ 154 } 155 156 static const struct max77620_pin_function max77620_pin_function[] = { 157 FUNCTION_GROUP("gpio", GPIO), 158 FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN), 159 FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT), 160 FUNCTION_GROUP("32k-out1", 32K_OUT1), 161 FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN), 162 FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN), 163 FUNCTION_GROUP("reference-out", REFERENCE_OUT), 164 }; 165 166 #define MAX77620_PINGROUP(pg_name, pin_id, option) \ 167 { \ 168 .name = #pg_name, \ 169 .pins = {MAX77620_##pin_id}, \ 170 .npins = 1, \ 171 .alt_option = MAX77620_PINMUX_##option, \ 172 } 173 174 static const struct max77620_pingroup max77620_pingroups[] = { 175 MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN), 176 MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT), 177 MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT), 178 MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT), 179 MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1), 180 MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN), 181 MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN), 182 MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT), 183 }; 184 185 static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 186 { 187 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 188 189 return mpci->num_pin_groups; 190 } 191 192 static const char *max77620_pinctrl_get_group_name( 193 struct pinctrl_dev *pctldev, unsigned int group) 194 { 195 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 196 197 return mpci->pin_groups[group].name; 198 } 199 200 static int max77620_pinctrl_get_group_pins( 201 struct pinctrl_dev *pctldev, unsigned int group, 202 const unsigned int **pins, unsigned int *num_pins) 203 { 204 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 205 206 *pins = mpci->pin_groups[group].pins; 207 *num_pins = mpci->pin_groups[group].npins; 208 209 return 0; 210 } 211 212 static const struct pinctrl_ops max77620_pinctrl_ops = { 213 .get_groups_count = max77620_pinctrl_get_groups_count, 214 .get_group_name = max77620_pinctrl_get_group_name, 215 .get_group_pins = max77620_pinctrl_get_group_pins, 216 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 217 .dt_free_map = pinctrl_utils_free_map, 218 }; 219 220 static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) 221 { 222 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 223 224 return mpci->num_functions; 225 } 226 227 static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 228 unsigned int function) 229 { 230 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 231 232 return mpci->functions[function].name; 233 } 234 235 static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, 236 unsigned int function, 237 const char * const **groups, 238 unsigned int * const num_groups) 239 { 240 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 241 242 *groups = mpci->functions[function].groups; 243 *num_groups = mpci->functions[function].ngroups; 244 245 return 0; 246 } 247 248 static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev, 249 unsigned int function, unsigned int group) 250 { 251 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 252 u8 val; 253 int ret; 254 255 if (function == MAX77620_PINMUX_GPIO) { 256 val = 0; 257 } else if (function == mpci->pin_groups[group].alt_option) { 258 val = 1 << group; 259 } else { 260 dev_err(mpci->dev, "GPIO %u doesn't have function %u\n", 261 group, function); 262 return -EINVAL; 263 } 264 ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO, 265 BIT(group), val); 266 if (ret < 0) 267 dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret); 268 269 return ret; 270 } 271 272 static const struct pinmux_ops max77620_pinmux_ops = { 273 .get_functions_count = max77620_pinctrl_get_funcs_count, 274 .get_function_name = max77620_pinctrl_get_func_name, 275 .get_function_groups = max77620_pinctrl_get_func_groups, 276 .set_mux = max77620_pinctrl_enable, 277 }; 278 279 static int max77620_pinconf_get(struct pinctrl_dev *pctldev, 280 unsigned int pin, unsigned long *config) 281 { 282 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 283 struct device *dev = mpci->dev; 284 enum pin_config_param param = pinconf_to_config_param(*config); 285 unsigned int val; 286 int arg = 0; 287 int ret; 288 289 switch (param) { 290 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 291 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV) 292 arg = 1; 293 break; 294 295 case PIN_CONFIG_DRIVE_PUSH_PULL: 296 if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV) 297 arg = 1; 298 break; 299 300 case PIN_CONFIG_BIAS_PULL_UP: 301 ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val); 302 if (ret < 0) { 303 dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret); 304 return ret; 305 } 306 if (val & BIT(pin)) 307 arg = 1; 308 break; 309 310 case PIN_CONFIG_BIAS_PULL_DOWN: 311 ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val); 312 if (ret < 0) { 313 dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret); 314 return ret; 315 } 316 if (val & BIT(pin)) 317 arg = 1; 318 break; 319 320 default: 321 dev_err(dev, "Properties not supported\n"); 322 return -ENOTSUPP; 323 } 324 325 *config = pinconf_to_config_packed(param, (u16)arg); 326 327 return 0; 328 } 329 330 static int max77620_get_default_fps(struct max77620_pctrl_info *mpci, 331 int addr, int *fps) 332 { 333 unsigned int val; 334 int ret; 335 336 ret = regmap_read(mpci->rmap, addr, &val); 337 if (ret < 0) { 338 dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret); 339 return ret; 340 } 341 *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT; 342 343 return 0; 344 } 345 346 static int max77620_set_fps_param(struct max77620_pctrl_info *mpci, 347 int pin, int param) 348 { 349 struct max77620_fps_config *fps_config = &mpci->fps_config[pin]; 350 int addr, ret; 351 int param_val; 352 int mask, shift; 353 354 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) 355 return 0; 356 357 addr = MAX77620_REG_FPS_GPIO1 + pin - 1; 358 switch (param) { 359 case MAX77620_ACTIVE_FPS_SOURCE: 360 case MAX77620_SUSPEND_FPS_SOURCE: 361 mask = MAX77620_FPS_SRC_MASK; 362 shift = MAX77620_FPS_SRC_SHIFT; 363 param_val = fps_config->active_fps_src; 364 if (param == MAX77620_SUSPEND_FPS_SOURCE) 365 param_val = fps_config->suspend_fps_src; 366 break; 367 368 case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS: 369 case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS: 370 mask = MAX77620_FPS_PU_PERIOD_MASK; 371 shift = MAX77620_FPS_PU_PERIOD_SHIFT; 372 param_val = fps_config->active_power_up_slots; 373 if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS) 374 param_val = fps_config->suspend_power_up_slots; 375 break; 376 377 case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS: 378 case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS: 379 mask = MAX77620_FPS_PD_PERIOD_MASK; 380 shift = MAX77620_FPS_PD_PERIOD_SHIFT; 381 param_val = fps_config->active_power_down_slots; 382 if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS) 383 param_val = fps_config->suspend_power_down_slots; 384 break; 385 386 default: 387 dev_err(mpci->dev, "Invalid parameter %d for pin %d\n", 388 param, pin); 389 return -EINVAL; 390 } 391 392 if (param_val < 0) 393 return 0; 394 395 ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift); 396 if (ret < 0) 397 dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret); 398 399 return ret; 400 } 401 402 static int max77620_pinconf_set(struct pinctrl_dev *pctldev, 403 unsigned int pin, unsigned long *configs, 404 unsigned int num_configs) 405 { 406 struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 407 struct device *dev = mpci->dev; 408 struct max77620_fps_config *fps_config; 409 int param; 410 u16 param_val; 411 unsigned int val; 412 unsigned int pu_val; 413 unsigned int pd_val; 414 int addr, ret; 415 int i; 416 417 for (i = 0; i < num_configs; i++) { 418 param = pinconf_to_config_param(configs[i]); 419 param_val = pinconf_to_config_argument(configs[i]); 420 421 switch (param) { 422 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 423 val = param_val ? 0 : 1; 424 ret = regmap_update_bits(mpci->rmap, 425 MAX77620_REG_GPIO0 + pin, 426 MAX77620_CNFG_GPIO_DRV_MASK, 427 val); 428 if (ret < 0) { 429 dev_err(dev, "Reg 0x%02x update failed %d\n", 430 MAX77620_REG_GPIO0 + pin, ret); 431 return ret; 432 } 433 mpci->pin_info[pin].drv_type = val ? 434 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV; 435 break; 436 437 case PIN_CONFIG_DRIVE_PUSH_PULL: 438 val = param_val ? 1 : 0; 439 ret = regmap_update_bits(mpci->rmap, 440 MAX77620_REG_GPIO0 + pin, 441 MAX77620_CNFG_GPIO_DRV_MASK, 442 val); 443 if (ret < 0) { 444 dev_err(dev, "Reg 0x%02x update failed %d\n", 445 MAX77620_REG_GPIO0 + pin, ret); 446 return ret; 447 } 448 mpci->pin_info[pin].drv_type = val ? 449 MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV; 450 break; 451 452 case MAX77620_ACTIVE_FPS_SOURCE: 453 case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS: 454 case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS: 455 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) 456 return -EINVAL; 457 458 fps_config = &mpci->fps_config[pin]; 459 460 if ((param == MAX77620_ACTIVE_FPS_SOURCE) && 461 (param_val == MAX77620_FPS_SRC_DEF)) { 462 addr = MAX77620_REG_FPS_GPIO1 + pin - 1; 463 ret = max77620_get_default_fps( 464 mpci, addr, 465 &fps_config->active_fps_src); 466 if (ret < 0) 467 return ret; 468 break; 469 } 470 471 if (param == MAX77620_ACTIVE_FPS_SOURCE) 472 fps_config->active_fps_src = param_val; 473 else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS) 474 fps_config->active_power_up_slots = param_val; 475 else 476 fps_config->active_power_down_slots = param_val; 477 478 ret = max77620_set_fps_param(mpci, pin, param); 479 if (ret < 0) 480 return ret; 481 break; 482 483 case MAX77620_SUSPEND_FPS_SOURCE: 484 case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS: 485 case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS: 486 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) 487 return -EINVAL; 488 489 fps_config = &mpci->fps_config[pin]; 490 491 if ((param == MAX77620_SUSPEND_FPS_SOURCE) && 492 (param_val == MAX77620_FPS_SRC_DEF)) { 493 addr = MAX77620_REG_FPS_GPIO1 + pin - 1; 494 ret = max77620_get_default_fps( 495 mpci, addr, 496 &fps_config->suspend_fps_src); 497 if (ret < 0) 498 return ret; 499 break; 500 } 501 502 if (param == MAX77620_SUSPEND_FPS_SOURCE) 503 fps_config->suspend_fps_src = param_val; 504 else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS) 505 fps_config->suspend_power_up_slots = param_val; 506 else 507 fps_config->suspend_power_down_slots = 508 param_val; 509 break; 510 511 case PIN_CONFIG_BIAS_PULL_UP: 512 case PIN_CONFIG_BIAS_PULL_DOWN: 513 pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ? 514 BIT(pin) : 0; 515 pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ? 516 BIT(pin) : 0; 517 518 ret = regmap_update_bits(mpci->rmap, 519 MAX77620_REG_PUE_GPIO, 520 BIT(pin), pu_val); 521 if (ret < 0) { 522 dev_err(dev, "PUE_GPIO update failed: %d\n", 523 ret); 524 return ret; 525 } 526 527 ret = regmap_update_bits(mpci->rmap, 528 MAX77620_REG_PDE_GPIO, 529 BIT(pin), pd_val); 530 if (ret < 0) { 531 dev_err(dev, "PDE_GPIO update failed: %d\n", 532 ret); 533 return ret; 534 } 535 break; 536 537 default: 538 dev_err(dev, "Properties not supported\n"); 539 return -ENOTSUPP; 540 } 541 } 542 543 return 0; 544 } 545 546 static const struct pinconf_ops max77620_pinconf_ops = { 547 .pin_config_get = max77620_pinconf_get, 548 .pin_config_set = max77620_pinconf_set, 549 }; 550 551 static struct pinctrl_desc max77620_pinctrl_desc = { 552 .pctlops = &max77620_pinctrl_ops, 553 .pmxops = &max77620_pinmux_ops, 554 .confops = &max77620_pinconf_ops, 555 }; 556 557 static int max77620_pinctrl_probe(struct platform_device *pdev) 558 { 559 struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent); 560 struct max77620_pctrl_info *mpci; 561 int i; 562 563 mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL); 564 if (!mpci) 565 return -ENOMEM; 566 567 mpci->dev = &pdev->dev; 568 mpci->dev->of_node = pdev->dev.parent->of_node; 569 mpci->rmap = max77620->rmap; 570 571 mpci->pins = max77620_pins_desc; 572 mpci->num_pins = ARRAY_SIZE(max77620_pins_desc); 573 mpci->functions = max77620_pin_function; 574 mpci->num_functions = ARRAY_SIZE(max77620_pin_function); 575 mpci->pin_groups = max77620_pingroups; 576 mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups); 577 platform_set_drvdata(pdev, mpci); 578 579 max77620_pinctrl_desc.name = dev_name(&pdev->dev); 580 max77620_pinctrl_desc.pins = max77620_pins_desc; 581 max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc); 582 max77620_pinctrl_desc.num_custom_params = 583 ARRAY_SIZE(max77620_cfg_params); 584 max77620_pinctrl_desc.custom_params = max77620_cfg_params; 585 586 for (i = 0; i < MAX77620_PIN_NUM; ++i) { 587 mpci->fps_config[i].active_fps_src = -1; 588 mpci->fps_config[i].active_power_up_slots = -1; 589 mpci->fps_config[i].active_power_down_slots = -1; 590 mpci->fps_config[i].suspend_fps_src = -1; 591 mpci->fps_config[i].suspend_power_up_slots = -1; 592 mpci->fps_config[i].suspend_power_down_slots = -1; 593 } 594 595 mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc, 596 mpci); 597 if (IS_ERR(mpci->pctl)) { 598 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 599 return PTR_ERR(mpci->pctl); 600 } 601 602 return 0; 603 } 604 605 #ifdef CONFIG_PM_SLEEP 606 static int max77620_suspend_fps_param[] = { 607 MAX77620_SUSPEND_FPS_SOURCE, 608 MAX77620_SUSPEND_FPS_POWER_ON_SLOTS, 609 MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS, 610 }; 611 612 static int max77620_active_fps_param[] = { 613 MAX77620_ACTIVE_FPS_SOURCE, 614 MAX77620_ACTIVE_FPS_POWER_ON_SLOTS, 615 MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS, 616 }; 617 618 static int max77620_pinctrl_suspend(struct device *dev) 619 { 620 struct max77620_pctrl_info *mpci = dev_get_drvdata(dev); 621 int pin, p; 622 623 for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) { 624 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) 625 continue; 626 for (p = 0; p < 3; ++p) 627 max77620_set_fps_param( 628 mpci, pin, max77620_suspend_fps_param[p]); 629 } 630 631 return 0; 632 }; 633 634 static int max77620_pinctrl_resume(struct device *dev) 635 { 636 struct max77620_pctrl_info *mpci = dev_get_drvdata(dev); 637 int pin, p; 638 639 for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) { 640 if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) 641 continue; 642 for (p = 0; p < 3; ++p) 643 max77620_set_fps_param( 644 mpci, pin, max77620_active_fps_param[p]); 645 } 646 647 return 0; 648 } 649 #endif 650 651 static const struct dev_pm_ops max77620_pinctrl_pm_ops = { 652 SET_SYSTEM_SLEEP_PM_OPS( 653 max77620_pinctrl_suspend, max77620_pinctrl_resume) 654 }; 655 656 static const struct platform_device_id max77620_pinctrl_devtype[] = { 657 { .name = "max77620-pinctrl", }, 658 { .name = "max20024-pinctrl", }, 659 {}, 660 }; 661 MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype); 662 663 static struct platform_driver max77620_pinctrl_driver = { 664 .driver = { 665 .name = "max77620-pinctrl", 666 .pm = &max77620_pinctrl_pm_ops, 667 }, 668 .probe = max77620_pinctrl_probe, 669 .id_table = max77620_pinctrl_devtype, 670 }; 671 672 module_platform_driver(max77620_pinctrl_driver); 673 674 MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver"); 675 MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>"); 676 MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>"); 677 MODULE_ALIAS("platform:max77620-pinctrl"); 678 MODULE_LICENSE("GPL v2"); 679