175a6faf6SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 22df723d4SLaxman Dewangan /* 32df723d4SLaxman Dewangan * MAX77620 pin control driver. 42df723d4SLaxman Dewangan * 52df723d4SLaxman Dewangan * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. 62df723d4SLaxman Dewangan * 72df723d4SLaxman Dewangan * Author: 82df723d4SLaxman Dewangan * Chaitanya Bandi <bandik@nvidia.com> 92df723d4SLaxman Dewangan * Laxman Dewangan <ldewangan@nvidia.com> 102df723d4SLaxman Dewangan */ 112df723d4SLaxman Dewangan 122df723d4SLaxman Dewangan #include <linux/mfd/max77620.h> 13*ce852837SAndy Shevchenko #include <linux/mod_devicetable.h> 142df723d4SLaxman Dewangan #include <linux/module.h> 15*ce852837SAndy Shevchenko #include <linux/platform_device.h> 16*ce852837SAndy Shevchenko #include <linux/property.h> 17*ce852837SAndy Shevchenko #include <linux/regmap.h> 18*ce852837SAndy Shevchenko 192df723d4SLaxman Dewangan #include <linux/pinctrl/pinctrl.h> 202df723d4SLaxman Dewangan #include <linux/pinctrl/pinconf-generic.h> 212df723d4SLaxman Dewangan #include <linux/pinctrl/pinconf.h> 222df723d4SLaxman Dewangan #include <linux/pinctrl/pinmux.h> 232df723d4SLaxman Dewangan 242df723d4SLaxman Dewangan #include "core.h" 252df723d4SLaxman Dewangan #include "pinconf.h" 262df723d4SLaxman Dewangan #include "pinctrl-utils.h" 272df723d4SLaxman Dewangan 282df723d4SLaxman Dewangan #define MAX77620_PIN_NUM 8 292df723d4SLaxman Dewangan 302df723d4SLaxman Dewangan enum max77620_pin_ppdrv { 312df723d4SLaxman Dewangan MAX77620_PIN_UNCONFIG_DRV, 322df723d4SLaxman Dewangan MAX77620_PIN_OD_DRV, 332df723d4SLaxman Dewangan MAX77620_PIN_PP_DRV, 342df723d4SLaxman Dewangan }; 352df723d4SLaxman Dewangan 361f60652dSNathan Chancellor #define MAX77620_ACTIVE_FPS_SOURCE (PIN_CONFIG_END + 1) 371f60652dSNathan Chancellor #define MAX77620_ACTIVE_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 2) 381f60652dSNathan Chancellor #define MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 3) 391f60652dSNathan Chancellor #define MAX77620_SUSPEND_FPS_SOURCE (PIN_CONFIG_END + 4) 401f60652dSNathan Chancellor #define MAX77620_SUSPEND_FPS_POWER_ON_SLOTS (PIN_CONFIG_END + 5) 411f60652dSNathan Chancellor #define MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS (PIN_CONFIG_END + 6) 422df723d4SLaxman Dewangan 432df723d4SLaxman Dewangan struct max77620_pin_function { 442df723d4SLaxman Dewangan const char *name; 452df723d4SLaxman Dewangan const char * const *groups; 462df723d4SLaxman Dewangan unsigned int ngroups; 472df723d4SLaxman Dewangan int mux_option; 482df723d4SLaxman Dewangan }; 492df723d4SLaxman Dewangan 502df723d4SLaxman Dewangan static const struct pinconf_generic_params max77620_cfg_params[] = { 512df723d4SLaxman Dewangan { 522df723d4SLaxman Dewangan .property = "maxim,active-fps-source", 532df723d4SLaxman Dewangan .param = MAX77620_ACTIVE_FPS_SOURCE, 542df723d4SLaxman Dewangan }, { 552df723d4SLaxman Dewangan .property = "maxim,active-fps-power-up-slot", 562df723d4SLaxman Dewangan .param = MAX77620_ACTIVE_FPS_POWER_ON_SLOTS, 572df723d4SLaxman Dewangan }, { 582df723d4SLaxman Dewangan .property = "maxim,active-fps-power-down-slot", 592df723d4SLaxman Dewangan .param = MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS, 602df723d4SLaxman Dewangan }, { 612df723d4SLaxman Dewangan .property = "maxim,suspend-fps-source", 622df723d4SLaxman Dewangan .param = MAX77620_SUSPEND_FPS_SOURCE, 632df723d4SLaxman Dewangan }, { 642df723d4SLaxman Dewangan .property = "maxim,suspend-fps-power-up-slot", 652df723d4SLaxman Dewangan .param = MAX77620_SUSPEND_FPS_POWER_ON_SLOTS, 662df723d4SLaxman Dewangan }, { 672df723d4SLaxman Dewangan .property = "maxim,suspend-fps-power-down-slot", 682df723d4SLaxman Dewangan .param = MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS, 692df723d4SLaxman Dewangan }, 702df723d4SLaxman Dewangan }; 712df723d4SLaxman Dewangan 722df723d4SLaxman Dewangan enum max77620_alternate_pinmux_option { 732df723d4SLaxman Dewangan MAX77620_PINMUX_GPIO = 0, 742df723d4SLaxman Dewangan MAX77620_PINMUX_LOW_POWER_MODE_CONTROL_IN = 1, 752df723d4SLaxman Dewangan MAX77620_PINMUX_FLEXIBLE_POWER_SEQUENCER_OUT = 2, 762df723d4SLaxman Dewangan MAX77620_PINMUX_32K_OUT1 = 3, 772df723d4SLaxman Dewangan MAX77620_PINMUX_SD0_DYNAMIC_VOLTAGE_SCALING_IN = 4, 782df723d4SLaxman Dewangan MAX77620_PINMUX_SD1_DYNAMIC_VOLTAGE_SCALING_IN = 5, 792df723d4SLaxman Dewangan MAX77620_PINMUX_REFERENCE_OUT = 6, 802df723d4SLaxman Dewangan }; 812df723d4SLaxman Dewangan 822df723d4SLaxman Dewangan struct max77620_pingroup { 832df723d4SLaxman Dewangan const char *name; 842df723d4SLaxman Dewangan const unsigned int pins[1]; 852df723d4SLaxman Dewangan unsigned int npins; 862df723d4SLaxman Dewangan enum max77620_alternate_pinmux_option alt_option; 872df723d4SLaxman Dewangan }; 882df723d4SLaxman Dewangan 892df723d4SLaxman Dewangan struct max77620_pin_info { 902df723d4SLaxman Dewangan enum max77620_pin_ppdrv drv_type; 912df723d4SLaxman Dewangan int pull_config; 922df723d4SLaxman Dewangan }; 932df723d4SLaxman Dewangan 942df723d4SLaxman Dewangan struct max77620_fps_config { 952df723d4SLaxman Dewangan int active_fps_src; 962df723d4SLaxman Dewangan int active_power_up_slots; 972df723d4SLaxman Dewangan int active_power_down_slots; 982df723d4SLaxman Dewangan int suspend_fps_src; 992df723d4SLaxman Dewangan int suspend_power_up_slots; 1002df723d4SLaxman Dewangan int suspend_power_down_slots; 1012df723d4SLaxman Dewangan }; 1022df723d4SLaxman Dewangan 1032df723d4SLaxman Dewangan struct max77620_pctrl_info { 1042df723d4SLaxman Dewangan struct device *dev; 1052df723d4SLaxman Dewangan struct pinctrl_dev *pctl; 1062df723d4SLaxman Dewangan struct regmap *rmap; 1072df723d4SLaxman Dewangan int pins_current_opt[MAX77620_GPIO_NR]; 1082df723d4SLaxman Dewangan const struct max77620_pin_function *functions; 1092df723d4SLaxman Dewangan unsigned int num_functions; 1102df723d4SLaxman Dewangan const struct max77620_pingroup *pin_groups; 1112df723d4SLaxman Dewangan int num_pin_groups; 1122df723d4SLaxman Dewangan const struct pinctrl_pin_desc *pins; 1132df723d4SLaxman Dewangan unsigned int num_pins; 1142df723d4SLaxman Dewangan struct max77620_pin_info pin_info[MAX77620_PIN_NUM]; 1152df723d4SLaxman Dewangan struct max77620_fps_config fps_config[MAX77620_PIN_NUM]; 1162df723d4SLaxman Dewangan }; 1172df723d4SLaxman Dewangan 1182df723d4SLaxman Dewangan static const struct pinctrl_pin_desc max77620_pins_desc[] = { 1192df723d4SLaxman Dewangan PINCTRL_PIN(MAX77620_GPIO0, "gpio0"), 1202df723d4SLaxman Dewangan PINCTRL_PIN(MAX77620_GPIO1, "gpio1"), 1212df723d4SLaxman Dewangan PINCTRL_PIN(MAX77620_GPIO2, "gpio2"), 1222df723d4SLaxman Dewangan PINCTRL_PIN(MAX77620_GPIO3, "gpio3"), 1232df723d4SLaxman Dewangan PINCTRL_PIN(MAX77620_GPIO4, "gpio4"), 1242df723d4SLaxman Dewangan PINCTRL_PIN(MAX77620_GPIO5, "gpio5"), 1252df723d4SLaxman Dewangan PINCTRL_PIN(MAX77620_GPIO6, "gpio6"), 1262df723d4SLaxman Dewangan PINCTRL_PIN(MAX77620_GPIO7, "gpio7"), 1272df723d4SLaxman Dewangan }; 1282df723d4SLaxman Dewangan 1292df723d4SLaxman Dewangan static const char * const gpio_groups[] = { 1302df723d4SLaxman Dewangan "gpio0", 1312df723d4SLaxman Dewangan "gpio1", 1322df723d4SLaxman Dewangan "gpio2", 1332df723d4SLaxman Dewangan "gpio3", 1342df723d4SLaxman Dewangan "gpio4", 1352df723d4SLaxman Dewangan "gpio5", 1362df723d4SLaxman Dewangan "gpio6", 1372df723d4SLaxman Dewangan "gpio7", 1382df723d4SLaxman Dewangan }; 1392df723d4SLaxman Dewangan 1402df723d4SLaxman Dewangan #define FUNCTION_GROUP(fname, mux) \ 1412df723d4SLaxman Dewangan { \ 1422df723d4SLaxman Dewangan .name = fname, \ 1432df723d4SLaxman Dewangan .groups = gpio_groups, \ 1442df723d4SLaxman Dewangan .ngroups = ARRAY_SIZE(gpio_groups), \ 1452df723d4SLaxman Dewangan .mux_option = MAX77620_PINMUX_##mux, \ 1462df723d4SLaxman Dewangan } 1472df723d4SLaxman Dewangan 1482df723d4SLaxman Dewangan static const struct max77620_pin_function max77620_pin_function[] = { 1492df723d4SLaxman Dewangan FUNCTION_GROUP("gpio", GPIO), 1502df723d4SLaxman Dewangan FUNCTION_GROUP("lpm-control-in", LOW_POWER_MODE_CONTROL_IN), 1512df723d4SLaxman Dewangan FUNCTION_GROUP("fps-out", FLEXIBLE_POWER_SEQUENCER_OUT), 1522df723d4SLaxman Dewangan FUNCTION_GROUP("32k-out1", 32K_OUT1), 1532df723d4SLaxman Dewangan FUNCTION_GROUP("sd0-dvs-in", SD0_DYNAMIC_VOLTAGE_SCALING_IN), 1542df723d4SLaxman Dewangan FUNCTION_GROUP("sd1-dvs-in", SD1_DYNAMIC_VOLTAGE_SCALING_IN), 1552df723d4SLaxman Dewangan FUNCTION_GROUP("reference-out", REFERENCE_OUT), 1562df723d4SLaxman Dewangan }; 1572df723d4SLaxman Dewangan 1582df723d4SLaxman Dewangan #define MAX77620_PINGROUP(pg_name, pin_id, option) \ 1592df723d4SLaxman Dewangan { \ 1602df723d4SLaxman Dewangan .name = #pg_name, \ 1612df723d4SLaxman Dewangan .pins = {MAX77620_##pin_id}, \ 1622df723d4SLaxman Dewangan .npins = 1, \ 1632df723d4SLaxman Dewangan .alt_option = MAX77620_PINMUX_##option, \ 1642df723d4SLaxman Dewangan } 1652df723d4SLaxman Dewangan 1662df723d4SLaxman Dewangan static const struct max77620_pingroup max77620_pingroups[] = { 1672df723d4SLaxman Dewangan MAX77620_PINGROUP(gpio0, GPIO0, LOW_POWER_MODE_CONTROL_IN), 1682df723d4SLaxman Dewangan MAX77620_PINGROUP(gpio1, GPIO1, FLEXIBLE_POWER_SEQUENCER_OUT), 1692df723d4SLaxman Dewangan MAX77620_PINGROUP(gpio2, GPIO2, FLEXIBLE_POWER_SEQUENCER_OUT), 1702df723d4SLaxman Dewangan MAX77620_PINGROUP(gpio3, GPIO3, FLEXIBLE_POWER_SEQUENCER_OUT), 1712df723d4SLaxman Dewangan MAX77620_PINGROUP(gpio4, GPIO4, 32K_OUT1), 1722df723d4SLaxman Dewangan MAX77620_PINGROUP(gpio5, GPIO5, SD0_DYNAMIC_VOLTAGE_SCALING_IN), 1732df723d4SLaxman Dewangan MAX77620_PINGROUP(gpio6, GPIO6, SD1_DYNAMIC_VOLTAGE_SCALING_IN), 1742df723d4SLaxman Dewangan MAX77620_PINGROUP(gpio7, GPIO7, REFERENCE_OUT), 1752df723d4SLaxman Dewangan }; 1762df723d4SLaxman Dewangan 1772df723d4SLaxman Dewangan static int max77620_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) 1782df723d4SLaxman Dewangan { 1792df723d4SLaxman Dewangan struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 1802df723d4SLaxman Dewangan 1812df723d4SLaxman Dewangan return mpci->num_pin_groups; 1822df723d4SLaxman Dewangan } 1832df723d4SLaxman Dewangan 1842df723d4SLaxman Dewangan static const char *max77620_pinctrl_get_group_name( 1852df723d4SLaxman Dewangan struct pinctrl_dev *pctldev, unsigned int group) 1862df723d4SLaxman Dewangan { 1872df723d4SLaxman Dewangan struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 1882df723d4SLaxman Dewangan 1892df723d4SLaxman Dewangan return mpci->pin_groups[group].name; 1902df723d4SLaxman Dewangan } 1912df723d4SLaxman Dewangan 1922df723d4SLaxman Dewangan static int max77620_pinctrl_get_group_pins( 1932df723d4SLaxman Dewangan struct pinctrl_dev *pctldev, unsigned int group, 1942df723d4SLaxman Dewangan const unsigned int **pins, unsigned int *num_pins) 1952df723d4SLaxman Dewangan { 1962df723d4SLaxman Dewangan struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 1972df723d4SLaxman Dewangan 1982df723d4SLaxman Dewangan *pins = mpci->pin_groups[group].pins; 1992df723d4SLaxman Dewangan *num_pins = mpci->pin_groups[group].npins; 2002df723d4SLaxman Dewangan 2012df723d4SLaxman Dewangan return 0; 2022df723d4SLaxman Dewangan } 2032df723d4SLaxman Dewangan 2042df723d4SLaxman Dewangan static const struct pinctrl_ops max77620_pinctrl_ops = { 2052df723d4SLaxman Dewangan .get_groups_count = max77620_pinctrl_get_groups_count, 2062df723d4SLaxman Dewangan .get_group_name = max77620_pinctrl_get_group_name, 2072df723d4SLaxman Dewangan .get_group_pins = max77620_pinctrl_get_group_pins, 2082df723d4SLaxman Dewangan .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, 2092df723d4SLaxman Dewangan .dt_free_map = pinctrl_utils_free_map, 2102df723d4SLaxman Dewangan }; 2112df723d4SLaxman Dewangan 2122df723d4SLaxman Dewangan static int max77620_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) 2132df723d4SLaxman Dewangan { 2142df723d4SLaxman Dewangan struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 2152df723d4SLaxman Dewangan 2162df723d4SLaxman Dewangan return mpci->num_functions; 2172df723d4SLaxman Dewangan } 2182df723d4SLaxman Dewangan 2192df723d4SLaxman Dewangan static const char *max77620_pinctrl_get_func_name(struct pinctrl_dev *pctldev, 2202df723d4SLaxman Dewangan unsigned int function) 2212df723d4SLaxman Dewangan { 2222df723d4SLaxman Dewangan struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 2232df723d4SLaxman Dewangan 2242df723d4SLaxman Dewangan return mpci->functions[function].name; 2252df723d4SLaxman Dewangan } 2262df723d4SLaxman Dewangan 2272df723d4SLaxman Dewangan static int max77620_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, 2282df723d4SLaxman Dewangan unsigned int function, 2292df723d4SLaxman Dewangan const char * const **groups, 2302df723d4SLaxman Dewangan unsigned int * const num_groups) 2312df723d4SLaxman Dewangan { 2322df723d4SLaxman Dewangan struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 2332df723d4SLaxman Dewangan 2342df723d4SLaxman Dewangan *groups = mpci->functions[function].groups; 2352df723d4SLaxman Dewangan *num_groups = mpci->functions[function].ngroups; 2362df723d4SLaxman Dewangan 2372df723d4SLaxman Dewangan return 0; 2382df723d4SLaxman Dewangan } 2392df723d4SLaxman Dewangan 2402df723d4SLaxman Dewangan static int max77620_pinctrl_enable(struct pinctrl_dev *pctldev, 2412df723d4SLaxman Dewangan unsigned int function, unsigned int group) 2422df723d4SLaxman Dewangan { 2432df723d4SLaxman Dewangan struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 2442df723d4SLaxman Dewangan u8 val; 2452df723d4SLaxman Dewangan int ret; 2462df723d4SLaxman Dewangan 2472df723d4SLaxman Dewangan if (function == MAX77620_PINMUX_GPIO) { 2482df723d4SLaxman Dewangan val = 0; 2492df723d4SLaxman Dewangan } else if (function == mpci->pin_groups[group].alt_option) { 2502df723d4SLaxman Dewangan val = 1 << group; 2512df723d4SLaxman Dewangan } else { 2522df723d4SLaxman Dewangan dev_err(mpci->dev, "GPIO %u doesn't have function %u\n", 2532df723d4SLaxman Dewangan group, function); 2542df723d4SLaxman Dewangan return -EINVAL; 2552df723d4SLaxman Dewangan } 2562df723d4SLaxman Dewangan ret = regmap_update_bits(mpci->rmap, MAX77620_REG_AME_GPIO, 2572df723d4SLaxman Dewangan BIT(group), val); 2582df723d4SLaxman Dewangan if (ret < 0) 2592df723d4SLaxman Dewangan dev_err(mpci->dev, "REG AME GPIO update failed: %d\n", ret); 2602df723d4SLaxman Dewangan 2612df723d4SLaxman Dewangan return ret; 2622df723d4SLaxman Dewangan } 2632df723d4SLaxman Dewangan 2642df723d4SLaxman Dewangan static const struct pinmux_ops max77620_pinmux_ops = { 2652df723d4SLaxman Dewangan .get_functions_count = max77620_pinctrl_get_funcs_count, 2662df723d4SLaxman Dewangan .get_function_name = max77620_pinctrl_get_func_name, 2672df723d4SLaxman Dewangan .get_function_groups = max77620_pinctrl_get_func_groups, 2682df723d4SLaxman Dewangan .set_mux = max77620_pinctrl_enable, 2692df723d4SLaxman Dewangan }; 2702df723d4SLaxman Dewangan 2712df723d4SLaxman Dewangan static int max77620_pinconf_get(struct pinctrl_dev *pctldev, 2722df723d4SLaxman Dewangan unsigned int pin, unsigned long *config) 2732df723d4SLaxman Dewangan { 2742df723d4SLaxman Dewangan struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 2752df723d4SLaxman Dewangan struct device *dev = mpci->dev; 2762df723d4SLaxman Dewangan enum pin_config_param param = pinconf_to_config_param(*config); 2772df723d4SLaxman Dewangan unsigned int val; 2782df723d4SLaxman Dewangan int arg = 0; 2792df723d4SLaxman Dewangan int ret; 2802df723d4SLaxman Dewangan 2812df723d4SLaxman Dewangan switch (param) { 2822df723d4SLaxman Dewangan case PIN_CONFIG_DRIVE_OPEN_DRAIN: 2832df723d4SLaxman Dewangan if (mpci->pin_info[pin].drv_type == MAX77620_PIN_OD_DRV) 2842df723d4SLaxman Dewangan arg = 1; 2852df723d4SLaxman Dewangan break; 2862df723d4SLaxman Dewangan 2872df723d4SLaxman Dewangan case PIN_CONFIG_DRIVE_PUSH_PULL: 2882df723d4SLaxman Dewangan if (mpci->pin_info[pin].drv_type == MAX77620_PIN_PP_DRV) 2892df723d4SLaxman Dewangan arg = 1; 2902df723d4SLaxman Dewangan break; 2912df723d4SLaxman Dewangan 2922df723d4SLaxman Dewangan case PIN_CONFIG_BIAS_PULL_UP: 2932df723d4SLaxman Dewangan ret = regmap_read(mpci->rmap, MAX77620_REG_PUE_GPIO, &val); 2942df723d4SLaxman Dewangan if (ret < 0) { 2952df723d4SLaxman Dewangan dev_err(dev, "Reg PUE_GPIO read failed: %d\n", ret); 2962df723d4SLaxman Dewangan return ret; 2972df723d4SLaxman Dewangan } 2982df723d4SLaxman Dewangan if (val & BIT(pin)) 2992df723d4SLaxman Dewangan arg = 1; 3002df723d4SLaxman Dewangan break; 3012df723d4SLaxman Dewangan 3022df723d4SLaxman Dewangan case PIN_CONFIG_BIAS_PULL_DOWN: 3032df723d4SLaxman Dewangan ret = regmap_read(mpci->rmap, MAX77620_REG_PDE_GPIO, &val); 3042df723d4SLaxman Dewangan if (ret < 0) { 3052df723d4SLaxman Dewangan dev_err(dev, "Reg PDE_GPIO read failed: %d\n", ret); 3062df723d4SLaxman Dewangan return ret; 3072df723d4SLaxman Dewangan } 3082df723d4SLaxman Dewangan if (val & BIT(pin)) 3092df723d4SLaxman Dewangan arg = 1; 3102df723d4SLaxman Dewangan break; 3112df723d4SLaxman Dewangan 3122df723d4SLaxman Dewangan default: 3132df723d4SLaxman Dewangan dev_err(dev, "Properties not supported\n"); 3142df723d4SLaxman Dewangan return -ENOTSUPP; 3152df723d4SLaxman Dewangan } 3162df723d4SLaxman Dewangan 3172df723d4SLaxman Dewangan *config = pinconf_to_config_packed(param, (u16)arg); 3182df723d4SLaxman Dewangan 3192df723d4SLaxman Dewangan return 0; 3202df723d4SLaxman Dewangan } 3212df723d4SLaxman Dewangan 3222df723d4SLaxman Dewangan static int max77620_get_default_fps(struct max77620_pctrl_info *mpci, 3232df723d4SLaxman Dewangan int addr, int *fps) 3242df723d4SLaxman Dewangan { 3252df723d4SLaxman Dewangan unsigned int val; 3262df723d4SLaxman Dewangan int ret; 3272df723d4SLaxman Dewangan 3282df723d4SLaxman Dewangan ret = regmap_read(mpci->rmap, addr, &val); 3292df723d4SLaxman Dewangan if (ret < 0) { 3302df723d4SLaxman Dewangan dev_err(mpci->dev, "Reg PUE_GPIO read failed: %d\n", ret); 3312df723d4SLaxman Dewangan return ret; 3322df723d4SLaxman Dewangan } 3332df723d4SLaxman Dewangan *fps = (val & MAX77620_FPS_SRC_MASK) >> MAX77620_FPS_SRC_SHIFT; 3342df723d4SLaxman Dewangan 3352df723d4SLaxman Dewangan return 0; 3362df723d4SLaxman Dewangan } 3372df723d4SLaxman Dewangan 3382df723d4SLaxman Dewangan static int max77620_set_fps_param(struct max77620_pctrl_info *mpci, 3392df723d4SLaxman Dewangan int pin, int param) 3402df723d4SLaxman Dewangan { 3412df723d4SLaxman Dewangan struct max77620_fps_config *fps_config = &mpci->fps_config[pin]; 3422df723d4SLaxman Dewangan int addr, ret; 3432df723d4SLaxman Dewangan int param_val; 3442df723d4SLaxman Dewangan int mask, shift; 3452df723d4SLaxman Dewangan 3462df723d4SLaxman Dewangan if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) 3472df723d4SLaxman Dewangan return 0; 3482df723d4SLaxman Dewangan 3492df723d4SLaxman Dewangan addr = MAX77620_REG_FPS_GPIO1 + pin - 1; 3502df723d4SLaxman Dewangan switch (param) { 3512df723d4SLaxman Dewangan case MAX77620_ACTIVE_FPS_SOURCE: 3522df723d4SLaxman Dewangan case MAX77620_SUSPEND_FPS_SOURCE: 3532df723d4SLaxman Dewangan mask = MAX77620_FPS_SRC_MASK; 3542df723d4SLaxman Dewangan shift = MAX77620_FPS_SRC_SHIFT; 3552df723d4SLaxman Dewangan param_val = fps_config->active_fps_src; 3562df723d4SLaxman Dewangan if (param == MAX77620_SUSPEND_FPS_SOURCE) 3572df723d4SLaxman Dewangan param_val = fps_config->suspend_fps_src; 3582df723d4SLaxman Dewangan break; 3592df723d4SLaxman Dewangan 3602df723d4SLaxman Dewangan case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS: 3612df723d4SLaxman Dewangan case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS: 3622df723d4SLaxman Dewangan mask = MAX77620_FPS_PU_PERIOD_MASK; 3632df723d4SLaxman Dewangan shift = MAX77620_FPS_PU_PERIOD_SHIFT; 3642df723d4SLaxman Dewangan param_val = fps_config->active_power_up_slots; 3652df723d4SLaxman Dewangan if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS) 3662df723d4SLaxman Dewangan param_val = fps_config->suspend_power_up_slots; 3672df723d4SLaxman Dewangan break; 3682df723d4SLaxman Dewangan 3692df723d4SLaxman Dewangan case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS: 3702df723d4SLaxman Dewangan case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS: 3712df723d4SLaxman Dewangan mask = MAX77620_FPS_PD_PERIOD_MASK; 3722df723d4SLaxman Dewangan shift = MAX77620_FPS_PD_PERIOD_SHIFT; 3732df723d4SLaxman Dewangan param_val = fps_config->active_power_down_slots; 3742df723d4SLaxman Dewangan if (param == MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS) 3752df723d4SLaxman Dewangan param_val = fps_config->suspend_power_down_slots; 3762df723d4SLaxman Dewangan break; 3772df723d4SLaxman Dewangan 3782df723d4SLaxman Dewangan default: 3792df723d4SLaxman Dewangan dev_err(mpci->dev, "Invalid parameter %d for pin %d\n", 3802df723d4SLaxman Dewangan param, pin); 3812df723d4SLaxman Dewangan return -EINVAL; 3822df723d4SLaxman Dewangan } 3832df723d4SLaxman Dewangan 3842df723d4SLaxman Dewangan if (param_val < 0) 3852df723d4SLaxman Dewangan return 0; 3862df723d4SLaxman Dewangan 3872df723d4SLaxman Dewangan ret = regmap_update_bits(mpci->rmap, addr, mask, param_val << shift); 3882df723d4SLaxman Dewangan if (ret < 0) 3892df723d4SLaxman Dewangan dev_err(mpci->dev, "Reg 0x%02x update failed %d\n", addr, ret); 3902df723d4SLaxman Dewangan 3912df723d4SLaxman Dewangan return ret; 3922df723d4SLaxman Dewangan } 3932df723d4SLaxman Dewangan 3942df723d4SLaxman Dewangan static int max77620_pinconf_set(struct pinctrl_dev *pctldev, 3952df723d4SLaxman Dewangan unsigned int pin, unsigned long *configs, 3962df723d4SLaxman Dewangan unsigned int num_configs) 3972df723d4SLaxman Dewangan { 3982df723d4SLaxman Dewangan struct max77620_pctrl_info *mpci = pinctrl_dev_get_drvdata(pctldev); 3992df723d4SLaxman Dewangan struct device *dev = mpci->dev; 4002df723d4SLaxman Dewangan struct max77620_fps_config *fps_config; 4012df723d4SLaxman Dewangan int param; 40258957d2eSMika Westerberg u32 param_val; 4032df723d4SLaxman Dewangan unsigned int val; 4042df723d4SLaxman Dewangan unsigned int pu_val; 4052df723d4SLaxman Dewangan unsigned int pd_val; 4062df723d4SLaxman Dewangan int addr, ret; 4072df723d4SLaxman Dewangan int i; 4082df723d4SLaxman Dewangan 4092df723d4SLaxman Dewangan for (i = 0; i < num_configs; i++) { 4102df723d4SLaxman Dewangan param = pinconf_to_config_param(configs[i]); 4112df723d4SLaxman Dewangan param_val = pinconf_to_config_argument(configs[i]); 4122df723d4SLaxman Dewangan 4132df723d4SLaxman Dewangan switch (param) { 4142df723d4SLaxman Dewangan case PIN_CONFIG_DRIVE_OPEN_DRAIN: 4152df723d4SLaxman Dewangan val = param_val ? 0 : 1; 4162df723d4SLaxman Dewangan ret = regmap_update_bits(mpci->rmap, 4172df723d4SLaxman Dewangan MAX77620_REG_GPIO0 + pin, 4182df723d4SLaxman Dewangan MAX77620_CNFG_GPIO_DRV_MASK, 4192df723d4SLaxman Dewangan val); 420752caf9aSMarkus Elfring if (ret) 421752caf9aSMarkus Elfring goto report_update_failure; 422752caf9aSMarkus Elfring 4232df723d4SLaxman Dewangan mpci->pin_info[pin].drv_type = val ? 4242df723d4SLaxman Dewangan MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV; 4252df723d4SLaxman Dewangan break; 4262df723d4SLaxman Dewangan 4272df723d4SLaxman Dewangan case PIN_CONFIG_DRIVE_PUSH_PULL: 4282df723d4SLaxman Dewangan val = param_val ? 1 : 0; 4292df723d4SLaxman Dewangan ret = regmap_update_bits(mpci->rmap, 4302df723d4SLaxman Dewangan MAX77620_REG_GPIO0 + pin, 4312df723d4SLaxman Dewangan MAX77620_CNFG_GPIO_DRV_MASK, 4322df723d4SLaxman Dewangan val); 433752caf9aSMarkus Elfring if (ret) 434752caf9aSMarkus Elfring goto report_update_failure; 435752caf9aSMarkus Elfring 4362df723d4SLaxman Dewangan mpci->pin_info[pin].drv_type = val ? 4372df723d4SLaxman Dewangan MAX77620_PIN_PP_DRV : MAX77620_PIN_OD_DRV; 4382df723d4SLaxman Dewangan break; 4392df723d4SLaxman Dewangan 4402df723d4SLaxman Dewangan case MAX77620_ACTIVE_FPS_SOURCE: 4412df723d4SLaxman Dewangan case MAX77620_ACTIVE_FPS_POWER_ON_SLOTS: 4422df723d4SLaxman Dewangan case MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS: 4432df723d4SLaxman Dewangan if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) 4442df723d4SLaxman Dewangan return -EINVAL; 4452df723d4SLaxman Dewangan 4462df723d4SLaxman Dewangan fps_config = &mpci->fps_config[pin]; 4472df723d4SLaxman Dewangan 4482df723d4SLaxman Dewangan if ((param == MAX77620_ACTIVE_FPS_SOURCE) && 4492df723d4SLaxman Dewangan (param_val == MAX77620_FPS_SRC_DEF)) { 4502df723d4SLaxman Dewangan addr = MAX77620_REG_FPS_GPIO1 + pin - 1; 4512df723d4SLaxman Dewangan ret = max77620_get_default_fps( 4522df723d4SLaxman Dewangan mpci, addr, 4532df723d4SLaxman Dewangan &fps_config->active_fps_src); 4542df723d4SLaxman Dewangan if (ret < 0) 4552df723d4SLaxman Dewangan return ret; 4562df723d4SLaxman Dewangan break; 4572df723d4SLaxman Dewangan } 4582df723d4SLaxman Dewangan 4592df723d4SLaxman Dewangan if (param == MAX77620_ACTIVE_FPS_SOURCE) 4602df723d4SLaxman Dewangan fps_config->active_fps_src = param_val; 4612df723d4SLaxman Dewangan else if (param == MAX77620_ACTIVE_FPS_POWER_ON_SLOTS) 4622df723d4SLaxman Dewangan fps_config->active_power_up_slots = param_val; 4632df723d4SLaxman Dewangan else 4642df723d4SLaxman Dewangan fps_config->active_power_down_slots = param_val; 4652df723d4SLaxman Dewangan 4662df723d4SLaxman Dewangan ret = max77620_set_fps_param(mpci, pin, param); 4672df723d4SLaxman Dewangan if (ret < 0) 4682df723d4SLaxman Dewangan return ret; 4692df723d4SLaxman Dewangan break; 4702df723d4SLaxman Dewangan 4712df723d4SLaxman Dewangan case MAX77620_SUSPEND_FPS_SOURCE: 4722df723d4SLaxman Dewangan case MAX77620_SUSPEND_FPS_POWER_ON_SLOTS: 4732df723d4SLaxman Dewangan case MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS: 4742df723d4SLaxman Dewangan if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) 4752df723d4SLaxman Dewangan return -EINVAL; 4762df723d4SLaxman Dewangan 4772df723d4SLaxman Dewangan fps_config = &mpci->fps_config[pin]; 4782df723d4SLaxman Dewangan 4792df723d4SLaxman Dewangan if ((param == MAX77620_SUSPEND_FPS_SOURCE) && 4802df723d4SLaxman Dewangan (param_val == MAX77620_FPS_SRC_DEF)) { 4812df723d4SLaxman Dewangan addr = MAX77620_REG_FPS_GPIO1 + pin - 1; 4822df723d4SLaxman Dewangan ret = max77620_get_default_fps( 4832df723d4SLaxman Dewangan mpci, addr, 4842df723d4SLaxman Dewangan &fps_config->suspend_fps_src); 4852df723d4SLaxman Dewangan if (ret < 0) 4862df723d4SLaxman Dewangan return ret; 4872df723d4SLaxman Dewangan break; 4882df723d4SLaxman Dewangan } 4892df723d4SLaxman Dewangan 4902df723d4SLaxman Dewangan if (param == MAX77620_SUSPEND_FPS_SOURCE) 4912df723d4SLaxman Dewangan fps_config->suspend_fps_src = param_val; 4922df723d4SLaxman Dewangan else if (param == MAX77620_SUSPEND_FPS_POWER_ON_SLOTS) 4932df723d4SLaxman Dewangan fps_config->suspend_power_up_slots = param_val; 4942df723d4SLaxman Dewangan else 4952df723d4SLaxman Dewangan fps_config->suspend_power_down_slots = 4962df723d4SLaxman Dewangan param_val; 4972df723d4SLaxman Dewangan break; 4982df723d4SLaxman Dewangan 4992df723d4SLaxman Dewangan case PIN_CONFIG_BIAS_PULL_UP: 5002df723d4SLaxman Dewangan case PIN_CONFIG_BIAS_PULL_DOWN: 5012df723d4SLaxman Dewangan pu_val = (param == PIN_CONFIG_BIAS_PULL_UP) ? 5022df723d4SLaxman Dewangan BIT(pin) : 0; 5032df723d4SLaxman Dewangan pd_val = (param == PIN_CONFIG_BIAS_PULL_DOWN) ? 5042df723d4SLaxman Dewangan BIT(pin) : 0; 5052df723d4SLaxman Dewangan 5062df723d4SLaxman Dewangan ret = regmap_update_bits(mpci->rmap, 5072df723d4SLaxman Dewangan MAX77620_REG_PUE_GPIO, 5082df723d4SLaxman Dewangan BIT(pin), pu_val); 5092df723d4SLaxman Dewangan if (ret < 0) { 5102df723d4SLaxman Dewangan dev_err(dev, "PUE_GPIO update failed: %d\n", 5112df723d4SLaxman Dewangan ret); 5122df723d4SLaxman Dewangan return ret; 5132df723d4SLaxman Dewangan } 5142df723d4SLaxman Dewangan 5152df723d4SLaxman Dewangan ret = regmap_update_bits(mpci->rmap, 5162df723d4SLaxman Dewangan MAX77620_REG_PDE_GPIO, 5172df723d4SLaxman Dewangan BIT(pin), pd_val); 5182df723d4SLaxman Dewangan if (ret < 0) { 5192df723d4SLaxman Dewangan dev_err(dev, "PDE_GPIO update failed: %d\n", 5202df723d4SLaxman Dewangan ret); 5212df723d4SLaxman Dewangan return ret; 5222df723d4SLaxman Dewangan } 5232df723d4SLaxman Dewangan break; 5242df723d4SLaxman Dewangan 5252df723d4SLaxman Dewangan default: 5262df723d4SLaxman Dewangan dev_err(dev, "Properties not supported\n"); 5272df723d4SLaxman Dewangan return -ENOTSUPP; 5282df723d4SLaxman Dewangan } 5292df723d4SLaxman Dewangan } 5302df723d4SLaxman Dewangan 5312df723d4SLaxman Dewangan return 0; 532752caf9aSMarkus Elfring 533752caf9aSMarkus Elfring report_update_failure: 534752caf9aSMarkus Elfring dev_err(dev, "Reg 0x%02x update failed %d\n", 535752caf9aSMarkus Elfring MAX77620_REG_GPIO0 + pin, ret); 536752caf9aSMarkus Elfring return ret; 5372df723d4SLaxman Dewangan } 5382df723d4SLaxman Dewangan 5392df723d4SLaxman Dewangan static const struct pinconf_ops max77620_pinconf_ops = { 5402df723d4SLaxman Dewangan .pin_config_get = max77620_pinconf_get, 5412df723d4SLaxman Dewangan .pin_config_set = max77620_pinconf_set, 5422df723d4SLaxman Dewangan }; 5432df723d4SLaxman Dewangan 5442df723d4SLaxman Dewangan static struct pinctrl_desc max77620_pinctrl_desc = { 5452df723d4SLaxman Dewangan .pctlops = &max77620_pinctrl_ops, 5462df723d4SLaxman Dewangan .pmxops = &max77620_pinmux_ops, 5472df723d4SLaxman Dewangan .confops = &max77620_pinconf_ops, 5482df723d4SLaxman Dewangan }; 5492df723d4SLaxman Dewangan 5502df723d4SLaxman Dewangan static int max77620_pinctrl_probe(struct platform_device *pdev) 5512df723d4SLaxman Dewangan { 5522df723d4SLaxman Dewangan struct max77620_chip *max77620 = dev_get_drvdata(pdev->dev.parent); 5532df723d4SLaxman Dewangan struct max77620_pctrl_info *mpci; 5542df723d4SLaxman Dewangan int i; 5552df723d4SLaxman Dewangan 556*ce852837SAndy Shevchenko device_set_node(&pdev->dev, dev_fwnode(pdev->dev.parent)); 557*ce852837SAndy Shevchenko 5582df723d4SLaxman Dewangan mpci = devm_kzalloc(&pdev->dev, sizeof(*mpci), GFP_KERNEL); 5592df723d4SLaxman Dewangan if (!mpci) 5602df723d4SLaxman Dewangan return -ENOMEM; 5612df723d4SLaxman Dewangan 5622df723d4SLaxman Dewangan mpci->dev = &pdev->dev; 5632df723d4SLaxman Dewangan mpci->rmap = max77620->rmap; 5642df723d4SLaxman Dewangan 5652df723d4SLaxman Dewangan mpci->pins = max77620_pins_desc; 5662df723d4SLaxman Dewangan mpci->num_pins = ARRAY_SIZE(max77620_pins_desc); 5672df723d4SLaxman Dewangan mpci->functions = max77620_pin_function; 5682df723d4SLaxman Dewangan mpci->num_functions = ARRAY_SIZE(max77620_pin_function); 5692df723d4SLaxman Dewangan mpci->pin_groups = max77620_pingroups; 5702df723d4SLaxman Dewangan mpci->num_pin_groups = ARRAY_SIZE(max77620_pingroups); 5712df723d4SLaxman Dewangan platform_set_drvdata(pdev, mpci); 5722df723d4SLaxman Dewangan 5732df723d4SLaxman Dewangan max77620_pinctrl_desc.name = dev_name(&pdev->dev); 5742df723d4SLaxman Dewangan max77620_pinctrl_desc.pins = max77620_pins_desc; 5752df723d4SLaxman Dewangan max77620_pinctrl_desc.npins = ARRAY_SIZE(max77620_pins_desc); 5762df723d4SLaxman Dewangan max77620_pinctrl_desc.num_custom_params = 5772df723d4SLaxman Dewangan ARRAY_SIZE(max77620_cfg_params); 5782df723d4SLaxman Dewangan max77620_pinctrl_desc.custom_params = max77620_cfg_params; 5792df723d4SLaxman Dewangan 5802df723d4SLaxman Dewangan for (i = 0; i < MAX77620_PIN_NUM; ++i) { 5812df723d4SLaxman Dewangan mpci->fps_config[i].active_fps_src = -1; 5822df723d4SLaxman Dewangan mpci->fps_config[i].active_power_up_slots = -1; 5832df723d4SLaxman Dewangan mpci->fps_config[i].active_power_down_slots = -1; 5842df723d4SLaxman Dewangan mpci->fps_config[i].suspend_fps_src = -1; 5852df723d4SLaxman Dewangan mpci->fps_config[i].suspend_power_up_slots = -1; 5862df723d4SLaxman Dewangan mpci->fps_config[i].suspend_power_down_slots = -1; 5872df723d4SLaxman Dewangan } 5882df723d4SLaxman Dewangan 5892df723d4SLaxman Dewangan mpci->pctl = devm_pinctrl_register(&pdev->dev, &max77620_pinctrl_desc, 5902df723d4SLaxman Dewangan mpci); 5912df723d4SLaxman Dewangan if (IS_ERR(mpci->pctl)) { 5922df723d4SLaxman Dewangan dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 5932df723d4SLaxman Dewangan return PTR_ERR(mpci->pctl); 5942df723d4SLaxman Dewangan } 5952df723d4SLaxman Dewangan 5962df723d4SLaxman Dewangan return 0; 5972df723d4SLaxman Dewangan } 5982df723d4SLaxman Dewangan 5992df723d4SLaxman Dewangan #ifdef CONFIG_PM_SLEEP 6002df723d4SLaxman Dewangan static int max77620_suspend_fps_param[] = { 6012df723d4SLaxman Dewangan MAX77620_SUSPEND_FPS_SOURCE, 6022df723d4SLaxman Dewangan MAX77620_SUSPEND_FPS_POWER_ON_SLOTS, 6032df723d4SLaxman Dewangan MAX77620_SUSPEND_FPS_POWER_DOWN_SLOTS, 6042df723d4SLaxman Dewangan }; 6052df723d4SLaxman Dewangan 6062df723d4SLaxman Dewangan static int max77620_active_fps_param[] = { 6072df723d4SLaxman Dewangan MAX77620_ACTIVE_FPS_SOURCE, 6082df723d4SLaxman Dewangan MAX77620_ACTIVE_FPS_POWER_ON_SLOTS, 6092df723d4SLaxman Dewangan MAX77620_ACTIVE_FPS_POWER_DOWN_SLOTS, 6102df723d4SLaxman Dewangan }; 6112df723d4SLaxman Dewangan 6122df723d4SLaxman Dewangan static int max77620_pinctrl_suspend(struct device *dev) 6132df723d4SLaxman Dewangan { 6142df723d4SLaxman Dewangan struct max77620_pctrl_info *mpci = dev_get_drvdata(dev); 6152df723d4SLaxman Dewangan int pin, p; 6162df723d4SLaxman Dewangan 6172df723d4SLaxman Dewangan for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) { 6182df723d4SLaxman Dewangan if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) 6192df723d4SLaxman Dewangan continue; 6202df723d4SLaxman Dewangan for (p = 0; p < 3; ++p) 6212df723d4SLaxman Dewangan max77620_set_fps_param( 6222df723d4SLaxman Dewangan mpci, pin, max77620_suspend_fps_param[p]); 6232df723d4SLaxman Dewangan } 6242df723d4SLaxman Dewangan 6252df723d4SLaxman Dewangan return 0; 6262df723d4SLaxman Dewangan }; 6272df723d4SLaxman Dewangan 6282df723d4SLaxman Dewangan static int max77620_pinctrl_resume(struct device *dev) 6292df723d4SLaxman Dewangan { 6302df723d4SLaxman Dewangan struct max77620_pctrl_info *mpci = dev_get_drvdata(dev); 6312df723d4SLaxman Dewangan int pin, p; 6322df723d4SLaxman Dewangan 6332df723d4SLaxman Dewangan for (pin = 0; pin < MAX77620_PIN_NUM; ++pin) { 6342df723d4SLaxman Dewangan if ((pin < MAX77620_GPIO1) || (pin > MAX77620_GPIO3)) 6352df723d4SLaxman Dewangan continue; 6362df723d4SLaxman Dewangan for (p = 0; p < 3; ++p) 6372df723d4SLaxman Dewangan max77620_set_fps_param( 6382df723d4SLaxman Dewangan mpci, pin, max77620_active_fps_param[p]); 6392df723d4SLaxman Dewangan } 6402df723d4SLaxman Dewangan 6412df723d4SLaxman Dewangan return 0; 6422df723d4SLaxman Dewangan } 6432df723d4SLaxman Dewangan #endif 6442df723d4SLaxman Dewangan 6452df723d4SLaxman Dewangan static const struct dev_pm_ops max77620_pinctrl_pm_ops = { 6462df723d4SLaxman Dewangan SET_SYSTEM_SLEEP_PM_OPS( 6472df723d4SLaxman Dewangan max77620_pinctrl_suspend, max77620_pinctrl_resume) 6482df723d4SLaxman Dewangan }; 6492df723d4SLaxman Dewangan 6502df723d4SLaxman Dewangan static const struct platform_device_id max77620_pinctrl_devtype[] = { 6512df723d4SLaxman Dewangan { .name = "max77620-pinctrl", }, 6522df723d4SLaxman Dewangan { .name = "max20024-pinctrl", }, 6532df723d4SLaxman Dewangan {}, 6542df723d4SLaxman Dewangan }; 6552df723d4SLaxman Dewangan MODULE_DEVICE_TABLE(platform, max77620_pinctrl_devtype); 6562df723d4SLaxman Dewangan 6572df723d4SLaxman Dewangan static struct platform_driver max77620_pinctrl_driver = { 6582df723d4SLaxman Dewangan .driver = { 6592df723d4SLaxman Dewangan .name = "max77620-pinctrl", 6602df723d4SLaxman Dewangan .pm = &max77620_pinctrl_pm_ops, 6612df723d4SLaxman Dewangan }, 6622df723d4SLaxman Dewangan .probe = max77620_pinctrl_probe, 6632df723d4SLaxman Dewangan .id_table = max77620_pinctrl_devtype, 6642df723d4SLaxman Dewangan }; 6652df723d4SLaxman Dewangan 6662df723d4SLaxman Dewangan module_platform_driver(max77620_pinctrl_driver); 6672df723d4SLaxman Dewangan 6682df723d4SLaxman Dewangan MODULE_DESCRIPTION("MAX77620/MAX20024 pin control driver"); 6692df723d4SLaxman Dewangan MODULE_AUTHOR("Chaitanya Bandi<bandik@nvidia.com>"); 6702df723d4SLaxman Dewangan MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>"); 6712df723d4SLaxman Dewangan MODULE_ALIAS("platform:max77620-pinctrl"); 6722df723d4SLaxman Dewangan MODULE_LICENSE("GPL v2"); 673