xref: /openbmc/linux/drivers/pinctrl/pinctrl-amd.c (revision f17f06a0)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * GPIO driver for AMD
4  *
5  * Copyright (c) 2014,2015 AMD Corporation.
6  * Authors: Ken Xue <Ken.Xue@amd.com>
7  *      Wu, Jeff <Jeff.Wu@amd.com>
8  *
9  * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com>
10  *			Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
11  */
12 
13 #include <linux/err.h>
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
22 #include <linux/io.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/slab.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/acpi.h>
28 #include <linux/seq_file.h>
29 #include <linux/interrupt.h>
30 #include <linux/list.h>
31 #include <linux/bitops.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinconf-generic.h>
34 
35 #include "core.h"
36 #include "pinctrl-utils.h"
37 #include "pinctrl-amd.h"
38 
39 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset)
40 {
41 	unsigned long flags;
42 	u32 pin_reg;
43 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
44 
45 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
46 	pin_reg = readl(gpio_dev->base + offset * 4);
47 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
48 
49 	return !(pin_reg & BIT(OUTPUT_ENABLE_OFF));
50 }
51 
52 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
53 {
54 	unsigned long flags;
55 	u32 pin_reg;
56 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
57 
58 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
59 	pin_reg = readl(gpio_dev->base + offset * 4);
60 	pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
61 	writel(pin_reg, gpio_dev->base + offset * 4);
62 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
63 
64 	return 0;
65 }
66 
67 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
68 		int value)
69 {
70 	u32 pin_reg;
71 	unsigned long flags;
72 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
73 
74 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
75 	pin_reg = readl(gpio_dev->base + offset * 4);
76 	pin_reg |= BIT(OUTPUT_ENABLE_OFF);
77 	if (value)
78 		pin_reg |= BIT(OUTPUT_VALUE_OFF);
79 	else
80 		pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
81 	writel(pin_reg, gpio_dev->base + offset * 4);
82 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
83 
84 	return 0;
85 }
86 
87 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
88 {
89 	u32 pin_reg;
90 	unsigned long flags;
91 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
92 
93 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
94 	pin_reg = readl(gpio_dev->base + offset * 4);
95 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
96 
97 	return !!(pin_reg & BIT(PIN_STS_OFF));
98 }
99 
100 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
101 {
102 	u32 pin_reg;
103 	unsigned long flags;
104 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
105 
106 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
107 	pin_reg = readl(gpio_dev->base + offset * 4);
108 	if (value)
109 		pin_reg |= BIT(OUTPUT_VALUE_OFF);
110 	else
111 		pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
112 	writel(pin_reg, gpio_dev->base + offset * 4);
113 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
114 }
115 
116 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
117 		unsigned debounce)
118 {
119 	u32 time;
120 	u32 pin_reg;
121 	int ret = 0;
122 	unsigned long flags;
123 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
124 
125 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
126 	pin_reg = readl(gpio_dev->base + offset * 4);
127 
128 	if (debounce) {
129 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
130 		pin_reg &= ~DB_TMR_OUT_MASK;
131 		/*
132 		Debounce	Debounce	Timer	Max
133 		TmrLarge	TmrOutUnit	Unit	Debounce
134 							Time
135 		0	0	61 usec (2 RtcClk)	976 usec
136 		0	1	244 usec (8 RtcClk)	3.9 msec
137 		1	0	15.6 msec (512 RtcClk)	250 msec
138 		1	1	62.5 msec (2048 RtcClk)	1 sec
139 		*/
140 
141 		if (debounce < 61) {
142 			pin_reg |= 1;
143 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
144 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
145 		} else if (debounce < 976) {
146 			time = debounce / 61;
147 			pin_reg |= time & DB_TMR_OUT_MASK;
148 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
149 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
150 		} else if (debounce < 3900) {
151 			time = debounce / 244;
152 			pin_reg |= time & DB_TMR_OUT_MASK;
153 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
154 			pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
155 		} else if (debounce < 250000) {
156 			time = debounce / 15600;
157 			pin_reg |= time & DB_TMR_OUT_MASK;
158 			pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
159 			pin_reg |= BIT(DB_TMR_LARGE_OFF);
160 		} else if (debounce < 1000000) {
161 			time = debounce / 62500;
162 			pin_reg |= time & DB_TMR_OUT_MASK;
163 			pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
164 			pin_reg |= BIT(DB_TMR_LARGE_OFF);
165 		} else {
166 			pin_reg &= ~DB_CNTRl_MASK;
167 			ret = -EINVAL;
168 		}
169 	} else {
170 		pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
171 		pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
172 		pin_reg &= ~DB_TMR_OUT_MASK;
173 		pin_reg &= ~DB_CNTRl_MASK;
174 	}
175 	writel(pin_reg, gpio_dev->base + offset * 4);
176 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
177 
178 	return ret;
179 }
180 
181 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset,
182 			       unsigned long config)
183 {
184 	u32 debounce;
185 
186 	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
187 		return -ENOTSUPP;
188 
189 	debounce = pinconf_to_config_argument(config);
190 	return amd_gpio_set_debounce(gc, offset, debounce);
191 }
192 
193 #ifdef CONFIG_DEBUG_FS
194 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
195 {
196 	u32 pin_reg;
197 	unsigned long flags;
198 	unsigned int bank, i, pin_num;
199 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
200 
201 	char *level_trig;
202 	char *active_level;
203 	char *interrupt_enable;
204 	char *interrupt_mask;
205 	char *wake_cntrl0;
206 	char *wake_cntrl1;
207 	char *wake_cntrl2;
208 	char *pin_sts;
209 	char *pull_up_sel;
210 	char *pull_up_enable;
211 	char *pull_down_enable;
212 	char *output_value;
213 	char *output_enable;
214 
215 	for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
216 		seq_printf(s, "GPIO bank%d\t", bank);
217 
218 		switch (bank) {
219 		case 0:
220 			i = 0;
221 			pin_num = AMD_GPIO_PINS_BANK0;
222 			break;
223 		case 1:
224 			i = 64;
225 			pin_num = AMD_GPIO_PINS_BANK1 + i;
226 			break;
227 		case 2:
228 			i = 128;
229 			pin_num = AMD_GPIO_PINS_BANK2 + i;
230 			break;
231 		case 3:
232 			i = 192;
233 			pin_num = AMD_GPIO_PINS_BANK3 + i;
234 			break;
235 		default:
236 			/* Illegal bank number, ignore */
237 			continue;
238 		}
239 		for (; i < pin_num; i++) {
240 			seq_printf(s, "pin%d\t", i);
241 			raw_spin_lock_irqsave(&gpio_dev->lock, flags);
242 			pin_reg = readl(gpio_dev->base + i * 4);
243 			raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
244 
245 			if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
246 				u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) &
247 						ACTIVE_LEVEL_MASK;
248 				interrupt_enable = "interrupt is enabled|";
249 
250 				if (level == ACTIVE_LEVEL_HIGH)
251 					active_level = "Active high|";
252 				else if (level == ACTIVE_LEVEL_LOW)
253 					active_level = "Active low|";
254 				else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) &&
255 					 level == ACTIVE_LEVEL_BOTH)
256 					active_level = "Active on both|";
257 				else
258 					active_level = "Unknown Active level|";
259 
260 				if (pin_reg & BIT(LEVEL_TRIG_OFF))
261 					level_trig = "Level trigger|";
262 				else
263 					level_trig = "Edge trigger|";
264 
265 			} else {
266 				interrupt_enable =
267 					"interrupt is disabled|";
268 				active_level = " ";
269 				level_trig = " ";
270 			}
271 
272 			if (pin_reg & BIT(INTERRUPT_MASK_OFF))
273 				interrupt_mask =
274 					"interrupt is unmasked|";
275 			else
276 				interrupt_mask =
277 					"interrupt is masked|";
278 
279 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
280 				wake_cntrl0 = "enable wakeup in S0i3 state|";
281 			else
282 				wake_cntrl0 = "disable wakeup in S0i3 state|";
283 
284 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
285 				wake_cntrl1 = "enable wakeup in S3 state|";
286 			else
287 				wake_cntrl1 = "disable wakeup in S3 state|";
288 
289 			if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
290 				wake_cntrl2 = "enable wakeup in S4/S5 state|";
291 			else
292 				wake_cntrl2 = "disable wakeup in S4/S5 state|";
293 
294 			if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
295 				pull_up_enable = "pull-up is enabled|";
296 				if (pin_reg & BIT(PULL_UP_SEL_OFF))
297 					pull_up_sel = "8k pull-up|";
298 				else
299 					pull_up_sel = "4k pull-up|";
300 			} else {
301 				pull_up_enable = "pull-up is disabled|";
302 				pull_up_sel = " ";
303 			}
304 
305 			if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
306 				pull_down_enable = "pull-down is enabled|";
307 			else
308 				pull_down_enable = "Pull-down is disabled|";
309 
310 			if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
311 				pin_sts = " ";
312 				output_enable = "output is enabled|";
313 				if (pin_reg & BIT(OUTPUT_VALUE_OFF))
314 					output_value = "output is high|";
315 				else
316 					output_value = "output is low|";
317 			} else {
318 				output_enable = "output is disabled|";
319 				output_value = " ";
320 
321 				if (pin_reg & BIT(PIN_STS_OFF))
322 					pin_sts = "input is high|";
323 				else
324 					pin_sts = "input is low|";
325 			}
326 
327 			seq_printf(s, "%s %s %s %s %s %s\n"
328 				" %s %s %s %s %s %s %s 0x%x\n",
329 				level_trig, active_level, interrupt_enable,
330 				interrupt_mask, wake_cntrl0, wake_cntrl1,
331 				wake_cntrl2, pin_sts, pull_up_sel,
332 				pull_up_enable, pull_down_enable,
333 				output_value, output_enable, pin_reg);
334 		}
335 	}
336 }
337 #else
338 #define amd_gpio_dbg_show NULL
339 #endif
340 
341 static void amd_gpio_irq_enable(struct irq_data *d)
342 {
343 	u32 pin_reg;
344 	unsigned long flags;
345 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
346 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
347 
348 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
349 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
350 	pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
351 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
352 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
353 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
354 }
355 
356 static void amd_gpio_irq_disable(struct irq_data *d)
357 {
358 	u32 pin_reg;
359 	unsigned long flags;
360 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
361 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
362 
363 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
364 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
365 	pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
366 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
367 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
368 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
369 }
370 
371 static void amd_gpio_irq_mask(struct irq_data *d)
372 {
373 	u32 pin_reg;
374 	unsigned long flags;
375 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
376 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
377 
378 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
379 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
380 	pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
381 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
382 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
383 }
384 
385 static void amd_gpio_irq_unmask(struct irq_data *d)
386 {
387 	u32 pin_reg;
388 	unsigned long flags;
389 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
390 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
391 
392 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
393 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
394 	pin_reg |= BIT(INTERRUPT_MASK_OFF);
395 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
396 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
397 }
398 
399 static void amd_gpio_irq_eoi(struct irq_data *d)
400 {
401 	u32 reg;
402 	unsigned long flags;
403 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
404 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
405 
406 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
407 	reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
408 	reg |= EOI_MASK;
409 	writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
410 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
411 }
412 
413 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
414 {
415 	int ret = 0;
416 	u32 pin_reg, pin_reg_irq_en, mask;
417 	unsigned long flags, irq_flags;
418 	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
419 	struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
420 
421 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
422 	pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
423 
424 	/* Ignore the settings coming from the client and
425 	 * read the values from the ACPI tables
426 	 * while setting the trigger type
427 	 */
428 
429 	irq_flags = irq_get_trigger_type(d->irq);
430 	if (irq_flags != IRQ_TYPE_NONE)
431 		type = irq_flags;
432 
433 	switch (type & IRQ_TYPE_SENSE_MASK) {
434 	case IRQ_TYPE_EDGE_RISING:
435 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
436 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
437 		pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
438 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
439 		irq_set_handler_locked(d, handle_edge_irq);
440 		break;
441 
442 	case IRQ_TYPE_EDGE_FALLING:
443 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
444 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
445 		pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
446 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
447 		irq_set_handler_locked(d, handle_edge_irq);
448 		break;
449 
450 	case IRQ_TYPE_EDGE_BOTH:
451 		pin_reg &= ~BIT(LEVEL_TRIG_OFF);
452 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
453 		pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
454 		pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
455 		irq_set_handler_locked(d, handle_edge_irq);
456 		break;
457 
458 	case IRQ_TYPE_LEVEL_HIGH:
459 		pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
460 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
461 		pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
462 		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
463 		pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
464 		irq_set_handler_locked(d, handle_level_irq);
465 		break;
466 
467 	case IRQ_TYPE_LEVEL_LOW:
468 		pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
469 		pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
470 		pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
471 		pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
472 		pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
473 		irq_set_handler_locked(d, handle_level_irq);
474 		break;
475 
476 	case IRQ_TYPE_NONE:
477 		break;
478 
479 	default:
480 		dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
481 		ret = -EINVAL;
482 	}
483 
484 	pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
485 	/*
486 	 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
487 	 * debounce registers of any GPIO will block wake/interrupt status
488 	 * generation for *all* GPIOs for a length of time that depends on
489 	 * WAKE_INT_MASTER_REG.MaskStsLength[11:0].  During this period the
490 	 * INTERRUPT_ENABLE bit will read as 0.
491 	 *
492 	 * We temporarily enable irq for the GPIO whose configuration is
493 	 * changing, and then wait for it to read back as 1 to know when
494 	 * debounce has settled and then disable the irq again.
495 	 * We do this polling with the spinlock held to ensure other GPIO
496 	 * access routines do not read an incorrect value for the irq enable
497 	 * bit of other GPIOs.  We keep the GPIO masked while polling to avoid
498 	 * spurious irqs, and disable the irq again after polling.
499 	 */
500 	mask = BIT(INTERRUPT_ENABLE_OFF);
501 	pin_reg_irq_en = pin_reg;
502 	pin_reg_irq_en |= mask;
503 	pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF);
504 	writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4);
505 	while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask)
506 		continue;
507 	writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
508 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
509 
510 	return ret;
511 }
512 
513 static void amd_irq_ack(struct irq_data *d)
514 {
515 	/*
516 	 * based on HW design,there is no need to ack HW
517 	 * before handle current irq. But this routine is
518 	 * necessary for handle_edge_irq
519 	*/
520 }
521 
522 static struct irq_chip amd_gpio_irqchip = {
523 	.name         = "amd_gpio",
524 	.irq_ack      = amd_irq_ack,
525 	.irq_enable   = amd_gpio_irq_enable,
526 	.irq_disable  = amd_gpio_irq_disable,
527 	.irq_mask     = amd_gpio_irq_mask,
528 	.irq_unmask   = amd_gpio_irq_unmask,
529 	.irq_eoi      = amd_gpio_irq_eoi,
530 	.irq_set_type = amd_gpio_irq_set_type,
531 	.flags        = IRQCHIP_SKIP_SET_WAKE,
532 };
533 
534 #define PIN_IRQ_PENDING	(BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))
535 
536 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id)
537 {
538 	struct amd_gpio *gpio_dev = dev_id;
539 	struct gpio_chip *gc = &gpio_dev->gc;
540 	irqreturn_t ret = IRQ_NONE;
541 	unsigned int i, irqnr;
542 	unsigned long flags;
543 	u32 __iomem *regs;
544 	u32  regval;
545 	u64 status, mask;
546 
547 	/* Read the wake status */
548 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
549 	status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
550 	status <<= 32;
551 	status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
552 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
553 
554 	/* Bit 0-45 contain the relevant status bits */
555 	status &= (1ULL << 46) - 1;
556 	regs = gpio_dev->base;
557 	for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) {
558 		if (!(status & mask))
559 			continue;
560 		status &= ~mask;
561 
562 		/* Each status bit covers four pins */
563 		for (i = 0; i < 4; i++) {
564 			regval = readl(regs + i);
565 			if (!(regval & PIN_IRQ_PENDING) ||
566 			    !(regval & BIT(INTERRUPT_MASK_OFF)))
567 				continue;
568 			irq = irq_find_mapping(gc->irq.domain, irqnr + i);
569 			if (irq != 0)
570 				generic_handle_irq(irq);
571 
572 			/* Clear interrupt.
573 			 * We must read the pin register again, in case the
574 			 * value was changed while executing
575 			 * generic_handle_irq() above.
576 			 * If we didn't find a mapping for the interrupt,
577 			 * disable it in order to avoid a system hang caused
578 			 * by an interrupt storm.
579 			 */
580 			raw_spin_lock_irqsave(&gpio_dev->lock, flags);
581 			regval = readl(regs + i);
582 			if (irq == 0) {
583 				regval &= ~BIT(INTERRUPT_ENABLE_OFF);
584 				dev_dbg(&gpio_dev->pdev->dev,
585 					"Disabling spurious GPIO IRQ %d\n",
586 					irqnr + i);
587 			}
588 			writel(regval, regs + i);
589 			raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
590 			ret = IRQ_HANDLED;
591 		}
592 	}
593 
594 	/* Signal EOI to the GPIO unit */
595 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
596 	regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
597 	regval |= EOI_MASK;
598 	writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG);
599 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
600 
601 	return ret;
602 }
603 
604 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
605 {
606 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
607 
608 	return gpio_dev->ngroups;
609 }
610 
611 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
612 				      unsigned group)
613 {
614 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
615 
616 	return gpio_dev->groups[group].name;
617 }
618 
619 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
620 			      unsigned group,
621 			      const unsigned **pins,
622 			      unsigned *num_pins)
623 {
624 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
625 
626 	*pins = gpio_dev->groups[group].pins;
627 	*num_pins = gpio_dev->groups[group].npins;
628 	return 0;
629 }
630 
631 static const struct pinctrl_ops amd_pinctrl_ops = {
632 	.get_groups_count	= amd_get_groups_count,
633 	.get_group_name		= amd_get_group_name,
634 	.get_group_pins		= amd_get_group_pins,
635 #ifdef CONFIG_OF
636 	.dt_node_to_map		= pinconf_generic_dt_node_to_map_group,
637 	.dt_free_map		= pinctrl_utils_free_map,
638 #endif
639 };
640 
641 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
642 			  unsigned int pin,
643 			  unsigned long *config)
644 {
645 	u32 pin_reg;
646 	unsigned arg;
647 	unsigned long flags;
648 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
649 	enum pin_config_param param = pinconf_to_config_param(*config);
650 
651 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
652 	pin_reg = readl(gpio_dev->base + pin*4);
653 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
654 	switch (param) {
655 	case PIN_CONFIG_INPUT_DEBOUNCE:
656 		arg = pin_reg & DB_TMR_OUT_MASK;
657 		break;
658 
659 	case PIN_CONFIG_BIAS_PULL_DOWN:
660 		arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
661 		break;
662 
663 	case PIN_CONFIG_BIAS_PULL_UP:
664 		arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
665 		break;
666 
667 	case PIN_CONFIG_DRIVE_STRENGTH:
668 		arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
669 		break;
670 
671 	default:
672 		dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
673 			param);
674 		return -ENOTSUPP;
675 	}
676 
677 	*config = pinconf_to_config_packed(param, arg);
678 
679 	return 0;
680 }
681 
682 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
683 				unsigned long *configs, unsigned num_configs)
684 {
685 	int i;
686 	u32 arg;
687 	int ret = 0;
688 	u32 pin_reg;
689 	unsigned long flags;
690 	enum pin_config_param param;
691 	struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
692 
693 	raw_spin_lock_irqsave(&gpio_dev->lock, flags);
694 	for (i = 0; i < num_configs; i++) {
695 		param = pinconf_to_config_param(configs[i]);
696 		arg = pinconf_to_config_argument(configs[i]);
697 		pin_reg = readl(gpio_dev->base + pin*4);
698 
699 		switch (param) {
700 		case PIN_CONFIG_INPUT_DEBOUNCE:
701 			pin_reg &= ~DB_TMR_OUT_MASK;
702 			pin_reg |= arg & DB_TMR_OUT_MASK;
703 			break;
704 
705 		case PIN_CONFIG_BIAS_PULL_DOWN:
706 			pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
707 			pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
708 			break;
709 
710 		case PIN_CONFIG_BIAS_PULL_UP:
711 			pin_reg &= ~BIT(PULL_UP_SEL_OFF);
712 			pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
713 			pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
714 			pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
715 			break;
716 
717 		case PIN_CONFIG_DRIVE_STRENGTH:
718 			pin_reg &= ~(DRV_STRENGTH_SEL_MASK
719 					<< DRV_STRENGTH_SEL_OFF);
720 			pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
721 					<< DRV_STRENGTH_SEL_OFF;
722 			break;
723 
724 		default:
725 			dev_err(&gpio_dev->pdev->dev,
726 				"Invalid config param %04x\n", param);
727 			ret = -ENOTSUPP;
728 		}
729 
730 		writel(pin_reg, gpio_dev->base + pin*4);
731 	}
732 	raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
733 
734 	return ret;
735 }
736 
737 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
738 				unsigned int group,
739 				unsigned long *config)
740 {
741 	const unsigned *pins;
742 	unsigned npins;
743 	int ret;
744 
745 	ret = amd_get_group_pins(pctldev, group, &pins, &npins);
746 	if (ret)
747 		return ret;
748 
749 	if (amd_pinconf_get(pctldev, pins[0], config))
750 			return -ENOTSUPP;
751 
752 	return 0;
753 }
754 
755 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
756 				unsigned group, unsigned long *configs,
757 				unsigned num_configs)
758 {
759 	const unsigned *pins;
760 	unsigned npins;
761 	int i, ret;
762 
763 	ret = amd_get_group_pins(pctldev, group, &pins, &npins);
764 	if (ret)
765 		return ret;
766 	for (i = 0; i < npins; i++) {
767 		if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
768 			return -ENOTSUPP;
769 	}
770 	return 0;
771 }
772 
773 static const struct pinconf_ops amd_pinconf_ops = {
774 	.pin_config_get		= amd_pinconf_get,
775 	.pin_config_set		= amd_pinconf_set,
776 	.pin_config_group_get = amd_pinconf_group_get,
777 	.pin_config_group_set = amd_pinconf_group_set,
778 };
779 
780 #ifdef CONFIG_PM_SLEEP
781 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin)
782 {
783 	const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin);
784 
785 	if (!pd)
786 		return false;
787 
788 	/*
789 	 * Only restore the pin if it is actually in use by the kernel (or
790 	 * by userspace).
791 	 */
792 	if (pd->mux_owner || pd->gpio_owner ||
793 	    gpiochip_line_is_irq(&gpio_dev->gc, pin))
794 		return true;
795 
796 	return false;
797 }
798 
799 static int amd_gpio_suspend(struct device *dev)
800 {
801 	struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
802 	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
803 	int i;
804 
805 	for (i = 0; i < desc->npins; i++) {
806 		int pin = desc->pins[i].number;
807 
808 		if (!amd_gpio_should_save(gpio_dev, pin))
809 			continue;
810 
811 		gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4);
812 	}
813 
814 	return 0;
815 }
816 
817 static int amd_gpio_resume(struct device *dev)
818 {
819 	struct amd_gpio *gpio_dev = dev_get_drvdata(dev);
820 	struct pinctrl_desc *desc = gpio_dev->pctrl->desc;
821 	int i;
822 
823 	for (i = 0; i < desc->npins; i++) {
824 		int pin = desc->pins[i].number;
825 
826 		if (!amd_gpio_should_save(gpio_dev, pin))
827 			continue;
828 
829 		writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4);
830 	}
831 
832 	return 0;
833 }
834 
835 static const struct dev_pm_ops amd_gpio_pm_ops = {
836 	SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend,
837 				     amd_gpio_resume)
838 };
839 #endif
840 
841 static struct pinctrl_desc amd_pinctrl_desc = {
842 	.pins	= kerncz_pins,
843 	.npins = ARRAY_SIZE(kerncz_pins),
844 	.pctlops = &amd_pinctrl_ops,
845 	.confops = &amd_pinconf_ops,
846 	.owner = THIS_MODULE,
847 };
848 
849 static int amd_gpio_probe(struct platform_device *pdev)
850 {
851 	int ret = 0;
852 	int irq_base;
853 	struct resource *res;
854 	struct amd_gpio *gpio_dev;
855 
856 	gpio_dev = devm_kzalloc(&pdev->dev,
857 				sizeof(struct amd_gpio), GFP_KERNEL);
858 	if (!gpio_dev)
859 		return -ENOMEM;
860 
861 	raw_spin_lock_init(&gpio_dev->lock);
862 
863 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
864 	if (!res) {
865 		dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
866 		return -EINVAL;
867 	}
868 
869 	gpio_dev->base = devm_ioremap(&pdev->dev, res->start,
870 						resource_size(res));
871 	if (!gpio_dev->base)
872 		return -ENOMEM;
873 
874 	irq_base = platform_get_irq(pdev, 0);
875 	if (irq_base < 0)
876 		return irq_base;
877 
878 #ifdef CONFIG_PM_SLEEP
879 	gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins,
880 					    sizeof(*gpio_dev->saved_regs),
881 					    GFP_KERNEL);
882 	if (!gpio_dev->saved_regs)
883 		return -ENOMEM;
884 #endif
885 
886 	gpio_dev->pdev = pdev;
887 	gpio_dev->gc.get_direction	= amd_gpio_get_direction;
888 	gpio_dev->gc.direction_input	= amd_gpio_direction_input;
889 	gpio_dev->gc.direction_output	= amd_gpio_direction_output;
890 	gpio_dev->gc.get			= amd_gpio_get_value;
891 	gpio_dev->gc.set			= amd_gpio_set_value;
892 	gpio_dev->gc.set_config		= amd_gpio_set_config;
893 	gpio_dev->gc.dbg_show		= amd_gpio_dbg_show;
894 
895 	gpio_dev->gc.base		= -1;
896 	gpio_dev->gc.label			= pdev->name;
897 	gpio_dev->gc.owner			= THIS_MODULE;
898 	gpio_dev->gc.parent			= &pdev->dev;
899 	gpio_dev->gc.ngpio			= resource_size(res) / 4;
900 #if defined(CONFIG_OF_GPIO)
901 	gpio_dev->gc.of_node			= pdev->dev.of_node;
902 #endif
903 
904 	gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
905 	gpio_dev->groups = kerncz_groups;
906 	gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
907 
908 	amd_pinctrl_desc.name = dev_name(&pdev->dev);
909 	gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
910 						gpio_dev);
911 	if (IS_ERR(gpio_dev->pctrl)) {
912 		dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
913 		return PTR_ERR(gpio_dev->pctrl);
914 	}
915 
916 	ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
917 	if (ret)
918 		return ret;
919 
920 	ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
921 				0, 0, gpio_dev->gc.ngpio);
922 	if (ret) {
923 		dev_err(&pdev->dev, "Failed to add pin range\n");
924 		goto out2;
925 	}
926 
927 	ret = gpiochip_irqchip_add(&gpio_dev->gc,
928 				&amd_gpio_irqchip,
929 				0,
930 				handle_simple_irq,
931 				IRQ_TYPE_NONE);
932 	if (ret) {
933 		dev_err(&pdev->dev, "could not add irqchip\n");
934 		ret = -ENODEV;
935 		goto out2;
936 	}
937 
938 	ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler,
939 			       IRQF_SHARED, KBUILD_MODNAME, gpio_dev);
940 	if (ret)
941 		goto out2;
942 
943 	platform_set_drvdata(pdev, gpio_dev);
944 
945 	dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
946 	return ret;
947 
948 out2:
949 	gpiochip_remove(&gpio_dev->gc);
950 
951 	return ret;
952 }
953 
954 static int amd_gpio_remove(struct platform_device *pdev)
955 {
956 	struct amd_gpio *gpio_dev;
957 
958 	gpio_dev = platform_get_drvdata(pdev);
959 
960 	gpiochip_remove(&gpio_dev->gc);
961 
962 	return 0;
963 }
964 
965 static const struct acpi_device_id amd_gpio_acpi_match[] = {
966 	{ "AMD0030", 0 },
967 	{ "AMDI0030", 0},
968 	{ },
969 };
970 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
971 
972 static struct platform_driver amd_gpio_driver = {
973 	.driver		= {
974 		.name	= "amd_gpio",
975 		.acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
976 #ifdef CONFIG_PM_SLEEP
977 		.pm	= &amd_gpio_pm_ops,
978 #endif
979 	},
980 	.probe		= amd_gpio_probe,
981 	.remove		= amd_gpio_remove,
982 };
983 
984 module_platform_driver(amd_gpio_driver);
985 
986 MODULE_LICENSE("GPL v2");
987 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
988 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
989