1 /* 2 * GPIO driver for AMD 3 * 4 * Copyright (c) 2014,2015 AMD Corporation. 5 * Authors: Ken Xue <Ken.Xue@amd.com> 6 * Wu, Jeff <Jeff.Wu@amd.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 */ 12 13 #include <linux/err.h> 14 #include <linux/bug.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/compiler.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/log2.h> 22 #include <linux/io.h> 23 #include <linux/gpio.h> 24 #include <linux/slab.h> 25 #include <linux/platform_device.h> 26 #include <linux/mutex.h> 27 #include <linux/acpi.h> 28 #include <linux/seq_file.h> 29 #include <linux/interrupt.h> 30 #include <linux/list.h> 31 #include <linux/bitops.h> 32 #include <linux/pinctrl/pinconf.h> 33 #include <linux/pinctrl/pinconf-generic.h> 34 35 #include "pinctrl-utils.h" 36 #include "pinctrl-amd.h" 37 38 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 39 { 40 unsigned long flags; 41 u32 pin_reg; 42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 43 44 spin_lock_irqsave(&gpio_dev->lock, flags); 45 pin_reg = readl(gpio_dev->base + offset * 4); 46 /* 47 * Suppose BIOS or Bootloader sets specific debounce for the 48 * GPIO. if not, set debounce to be 2.75ms and remove glitch. 49 */ 50 if ((pin_reg & DB_TMR_OUT_MASK) == 0) { 51 pin_reg |= 0xf; 52 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 53 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 54 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 55 } 56 57 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 58 writel(pin_reg, gpio_dev->base + offset * 4); 59 spin_unlock_irqrestore(&gpio_dev->lock, flags); 60 61 return 0; 62 } 63 64 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 65 int value) 66 { 67 u32 pin_reg; 68 unsigned long flags; 69 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 70 71 spin_lock_irqsave(&gpio_dev->lock, flags); 72 pin_reg = readl(gpio_dev->base + offset * 4); 73 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 74 if (value) 75 pin_reg |= BIT(OUTPUT_VALUE_OFF); 76 else 77 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 78 writel(pin_reg, gpio_dev->base + offset * 4); 79 spin_unlock_irqrestore(&gpio_dev->lock, flags); 80 81 return 0; 82 } 83 84 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 85 { 86 u32 pin_reg; 87 unsigned long flags; 88 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 89 90 spin_lock_irqsave(&gpio_dev->lock, flags); 91 pin_reg = readl(gpio_dev->base + offset * 4); 92 spin_unlock_irqrestore(&gpio_dev->lock, flags); 93 94 return !!(pin_reg & BIT(PIN_STS_OFF)); 95 } 96 97 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 98 { 99 u32 pin_reg; 100 unsigned long flags; 101 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 102 103 spin_lock_irqsave(&gpio_dev->lock, flags); 104 pin_reg = readl(gpio_dev->base + offset * 4); 105 if (value) 106 pin_reg |= BIT(OUTPUT_VALUE_OFF); 107 else 108 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 109 writel(pin_reg, gpio_dev->base + offset * 4); 110 spin_unlock_irqrestore(&gpio_dev->lock, flags); 111 } 112 113 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 114 unsigned debounce) 115 { 116 u32 time; 117 u32 pin_reg; 118 int ret = 0; 119 unsigned long flags; 120 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 121 122 spin_lock_irqsave(&gpio_dev->lock, flags); 123 pin_reg = readl(gpio_dev->base + offset * 4); 124 125 if (debounce) { 126 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 127 pin_reg &= ~DB_TMR_OUT_MASK; 128 /* 129 Debounce Debounce Timer Max 130 TmrLarge TmrOutUnit Unit Debounce 131 Time 132 0 0 61 usec (2 RtcClk) 976 usec 133 0 1 244 usec (8 RtcClk) 3.9 msec 134 1 0 15.6 msec (512 RtcClk) 250 msec 135 1 1 62.5 msec (2048 RtcClk) 1 sec 136 */ 137 138 if (debounce < 61) { 139 pin_reg |= 1; 140 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 141 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 142 } else if (debounce < 976) { 143 time = debounce / 61; 144 pin_reg |= time & DB_TMR_OUT_MASK; 145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 146 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 147 } else if (debounce < 3900) { 148 time = debounce / 244; 149 pin_reg |= time & DB_TMR_OUT_MASK; 150 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 152 } else if (debounce < 250000) { 153 time = debounce / 15600; 154 pin_reg |= time & DB_TMR_OUT_MASK; 155 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 156 pin_reg |= BIT(DB_TMR_LARGE_OFF); 157 } else if (debounce < 1000000) { 158 time = debounce / 62500; 159 pin_reg |= time & DB_TMR_OUT_MASK; 160 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 161 pin_reg |= BIT(DB_TMR_LARGE_OFF); 162 } else { 163 pin_reg &= ~DB_CNTRl_MASK; 164 ret = -EINVAL; 165 } 166 } else { 167 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 168 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 169 pin_reg &= ~DB_TMR_OUT_MASK; 170 pin_reg &= ~DB_CNTRl_MASK; 171 } 172 writel(pin_reg, gpio_dev->base + offset * 4); 173 spin_unlock_irqrestore(&gpio_dev->lock, flags); 174 175 return ret; 176 } 177 178 #ifdef CONFIG_DEBUG_FS 179 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 180 { 181 u32 pin_reg; 182 unsigned long flags; 183 unsigned int bank, i, pin_num; 184 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 185 186 char *level_trig; 187 char *active_level; 188 char *interrupt_enable; 189 char *interrupt_mask; 190 char *wake_cntrl0; 191 char *wake_cntrl1; 192 char *wake_cntrl2; 193 char *pin_sts; 194 char *pull_up_sel; 195 char *pull_up_enable; 196 char *pull_down_enable; 197 char *output_value; 198 char *output_enable; 199 200 for (bank = 0; bank < AMD_GPIO_TOTAL_BANKS; bank++) { 201 seq_printf(s, "GPIO bank%d\t", bank); 202 203 switch (bank) { 204 case 0: 205 i = 0; 206 pin_num = AMD_GPIO_PINS_BANK0; 207 break; 208 case 1: 209 i = 64; 210 pin_num = AMD_GPIO_PINS_BANK1 + i; 211 break; 212 case 2: 213 i = 128; 214 pin_num = AMD_GPIO_PINS_BANK2 + i; 215 break; 216 } 217 218 for (; i < pin_num; i++) { 219 seq_printf(s, "pin%d\t", i); 220 spin_lock_irqsave(&gpio_dev->lock, flags); 221 pin_reg = readl(gpio_dev->base + i * 4); 222 spin_unlock_irqrestore(&gpio_dev->lock, flags); 223 224 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 225 interrupt_enable = "interrupt is enabled|"; 226 227 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) 228 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) 229 active_level = "Active low|"; 230 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) 231 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1))) 232 active_level = "Active high|"; 233 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) 234 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1)) 235 active_level = "Active on both|"; 236 else 237 active_level = "Unknow Active level|"; 238 239 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 240 level_trig = "Level trigger|"; 241 else 242 level_trig = "Edge trigger|"; 243 244 } else { 245 interrupt_enable = 246 "interrupt is disabled|"; 247 active_level = " "; 248 level_trig = " "; 249 } 250 251 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 252 interrupt_mask = 253 "interrupt is unmasked|"; 254 else 255 interrupt_mask = 256 "interrupt is masked|"; 257 258 if (pin_reg & BIT(WAKE_CNTRL_OFF)) 259 wake_cntrl0 = "enable wakeup in S0i3 state|"; 260 else 261 wake_cntrl0 = "disable wakeup in S0i3 state|"; 262 263 if (pin_reg & BIT(WAKE_CNTRL_OFF)) 264 wake_cntrl1 = "enable wakeup in S3 state|"; 265 else 266 wake_cntrl1 = "disable wakeup in S3 state|"; 267 268 if (pin_reg & BIT(WAKE_CNTRL_OFF)) 269 wake_cntrl2 = "enable wakeup in S4/S5 state|"; 270 else 271 wake_cntrl2 = "disable wakeup in S4/S5 state|"; 272 273 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 274 pull_up_enable = "pull-up is enabled|"; 275 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 276 pull_up_sel = "8k pull-up|"; 277 else 278 pull_up_sel = "4k pull-up|"; 279 } else { 280 pull_up_enable = "pull-up is disabled|"; 281 pull_up_sel = " "; 282 } 283 284 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 285 pull_down_enable = "pull-down is enabled|"; 286 else 287 pull_down_enable = "Pull-down is disabled|"; 288 289 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 290 pin_sts = " "; 291 output_enable = "output is enabled|"; 292 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 293 output_value = "output is high|"; 294 else 295 output_value = "output is low|"; 296 } else { 297 output_enable = "output is disabled|"; 298 output_value = " "; 299 300 if (pin_reg & BIT(PIN_STS_OFF)) 301 pin_sts = "input is high|"; 302 else 303 pin_sts = "input is low|"; 304 } 305 306 seq_printf(s, "%s %s %s %s %s %s\n" 307 " %s %s %s %s %s %s %s 0x%x\n", 308 level_trig, active_level, interrupt_enable, 309 interrupt_mask, wake_cntrl0, wake_cntrl1, 310 wake_cntrl2, pin_sts, pull_up_sel, 311 pull_up_enable, pull_down_enable, 312 output_value, output_enable, pin_reg); 313 } 314 } 315 } 316 #else 317 #define amd_gpio_dbg_show NULL 318 #endif 319 320 static void amd_gpio_irq_enable(struct irq_data *d) 321 { 322 u32 pin_reg; 323 unsigned long flags; 324 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 325 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 326 327 spin_lock_irqsave(&gpio_dev->lock, flags); 328 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 329 /* 330 Suppose BIOS or Bootloader sets specific debounce for the 331 GPIO. if not, set debounce to be 2.75ms. 332 */ 333 if ((pin_reg & DB_TMR_OUT_MASK) == 0) { 334 pin_reg |= 0xf; 335 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 336 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 337 } 338 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 339 pin_reg |= BIT(INTERRUPT_MASK_OFF); 340 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 341 spin_unlock_irqrestore(&gpio_dev->lock, flags); 342 } 343 344 static void amd_gpio_irq_disable(struct irq_data *d) 345 { 346 u32 pin_reg; 347 unsigned long flags; 348 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 349 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 350 351 spin_lock_irqsave(&gpio_dev->lock, flags); 352 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 353 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 354 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 355 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 356 spin_unlock_irqrestore(&gpio_dev->lock, flags); 357 } 358 359 static void amd_gpio_irq_mask(struct irq_data *d) 360 { 361 u32 pin_reg; 362 unsigned long flags; 363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 364 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 365 366 spin_lock_irqsave(&gpio_dev->lock, flags); 367 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 368 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 369 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 370 spin_unlock_irqrestore(&gpio_dev->lock, flags); 371 } 372 373 static void amd_gpio_irq_unmask(struct irq_data *d) 374 { 375 u32 pin_reg; 376 unsigned long flags; 377 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 378 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 379 380 spin_lock_irqsave(&gpio_dev->lock, flags); 381 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 382 pin_reg |= BIT(INTERRUPT_MASK_OFF); 383 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 384 spin_unlock_irqrestore(&gpio_dev->lock, flags); 385 } 386 387 static void amd_gpio_irq_eoi(struct irq_data *d) 388 { 389 u32 reg; 390 unsigned long flags; 391 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 392 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 393 394 spin_lock_irqsave(&gpio_dev->lock, flags); 395 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 396 reg |= EOI_MASK; 397 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 398 spin_unlock_irqrestore(&gpio_dev->lock, flags); 399 } 400 401 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 402 { 403 int ret = 0; 404 u32 pin_reg; 405 unsigned long flags; 406 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 407 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 408 409 spin_lock_irqsave(&gpio_dev->lock, flags); 410 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 411 412 switch (type & IRQ_TYPE_SENSE_MASK) { 413 case IRQ_TYPE_EDGE_RISING: 414 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 415 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 416 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 417 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 418 irq_set_handler_locked(d, handle_edge_irq); 419 break; 420 421 case IRQ_TYPE_EDGE_FALLING: 422 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 423 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 424 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 425 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 426 irq_set_handler_locked(d, handle_edge_irq); 427 break; 428 429 case IRQ_TYPE_EDGE_BOTH: 430 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 431 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 432 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 433 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 434 irq_set_handler_locked(d, handle_edge_irq); 435 break; 436 437 case IRQ_TYPE_LEVEL_HIGH: 438 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 439 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 440 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 441 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 442 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 443 irq_set_handler_locked(d, handle_level_irq); 444 break; 445 446 case IRQ_TYPE_LEVEL_LOW: 447 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 448 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 449 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 450 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 451 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 452 irq_set_handler_locked(d, handle_level_irq); 453 break; 454 455 case IRQ_TYPE_NONE: 456 break; 457 458 default: 459 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 460 ret = -EINVAL; 461 } 462 463 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 464 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 465 spin_unlock_irqrestore(&gpio_dev->lock, flags); 466 467 return ret; 468 } 469 470 static void amd_irq_ack(struct irq_data *d) 471 { 472 /* 473 * based on HW design,there is no need to ack HW 474 * before handle current irq. But this routine is 475 * necessary for handle_edge_irq 476 */ 477 } 478 479 static struct irq_chip amd_gpio_irqchip = { 480 .name = "amd_gpio", 481 .irq_ack = amd_irq_ack, 482 .irq_enable = amd_gpio_irq_enable, 483 .irq_disable = amd_gpio_irq_disable, 484 .irq_mask = amd_gpio_irq_mask, 485 .irq_unmask = amd_gpio_irq_unmask, 486 .irq_eoi = amd_gpio_irq_eoi, 487 .irq_set_type = amd_gpio_irq_set_type, 488 }; 489 490 static void amd_gpio_irq_handler(struct irq_desc *desc) 491 { 492 u32 i; 493 u32 off; 494 u32 reg; 495 u32 pin_reg; 496 u64 reg64; 497 int handled = 0; 498 unsigned int irq; 499 unsigned long flags; 500 struct irq_chip *chip = irq_desc_get_chip(desc); 501 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 502 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 503 504 chained_irq_enter(chip, desc); 505 /*enable GPIO interrupt again*/ 506 spin_lock_irqsave(&gpio_dev->lock, flags); 507 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 508 reg64 = reg; 509 reg64 = reg64 << 32; 510 511 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 512 reg64 |= reg; 513 spin_unlock_irqrestore(&gpio_dev->lock, flags); 514 515 /* 516 * first 46 bits indicates interrupt status. 517 * one bit represents four interrupt sources. 518 */ 519 for (off = 0; off < 46 ; off++) { 520 if (reg64 & BIT(off)) { 521 for (i = 0; i < 4; i++) { 522 pin_reg = readl(gpio_dev->base + 523 (off * 4 + i) * 4); 524 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) || 525 (pin_reg & BIT(WAKE_STS_OFF))) { 526 irq = irq_find_mapping(gc->irqdomain, 527 off * 4 + i); 528 generic_handle_irq(irq); 529 writel(pin_reg, 530 gpio_dev->base 531 + (off * 4 + i) * 4); 532 handled++; 533 } 534 } 535 } 536 } 537 538 if (handled == 0) 539 handle_bad_irq(desc); 540 541 spin_lock_irqsave(&gpio_dev->lock, flags); 542 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 543 reg |= EOI_MASK; 544 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 545 spin_unlock_irqrestore(&gpio_dev->lock, flags); 546 547 chained_irq_exit(chip, desc); 548 } 549 550 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 551 { 552 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 553 554 return gpio_dev->ngroups; 555 } 556 557 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 558 unsigned group) 559 { 560 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 561 562 return gpio_dev->groups[group].name; 563 } 564 565 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 566 unsigned group, 567 const unsigned **pins, 568 unsigned *num_pins) 569 { 570 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 571 572 *pins = gpio_dev->groups[group].pins; 573 *num_pins = gpio_dev->groups[group].npins; 574 return 0; 575 } 576 577 static const struct pinctrl_ops amd_pinctrl_ops = { 578 .get_groups_count = amd_get_groups_count, 579 .get_group_name = amd_get_group_name, 580 .get_group_pins = amd_get_group_pins, 581 #ifdef CONFIG_OF 582 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 583 .dt_free_map = pinctrl_utils_dt_free_map, 584 #endif 585 }; 586 587 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 588 unsigned int pin, 589 unsigned long *config) 590 { 591 u32 pin_reg; 592 unsigned arg; 593 unsigned long flags; 594 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 595 enum pin_config_param param = pinconf_to_config_param(*config); 596 597 spin_lock_irqsave(&gpio_dev->lock, flags); 598 pin_reg = readl(gpio_dev->base + pin*4); 599 spin_unlock_irqrestore(&gpio_dev->lock, flags); 600 switch (param) { 601 case PIN_CONFIG_INPUT_DEBOUNCE: 602 arg = pin_reg & DB_TMR_OUT_MASK; 603 break; 604 605 case PIN_CONFIG_BIAS_PULL_DOWN: 606 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 607 break; 608 609 case PIN_CONFIG_BIAS_PULL_UP: 610 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 611 break; 612 613 case PIN_CONFIG_DRIVE_STRENGTH: 614 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 615 break; 616 617 default: 618 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 619 param); 620 return -ENOTSUPP; 621 } 622 623 *config = pinconf_to_config_packed(param, arg); 624 625 return 0; 626 } 627 628 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 629 unsigned long *configs, unsigned num_configs) 630 { 631 int i; 632 u32 arg; 633 int ret = 0; 634 u32 pin_reg; 635 unsigned long flags; 636 enum pin_config_param param; 637 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 638 639 spin_lock_irqsave(&gpio_dev->lock, flags); 640 for (i = 0; i < num_configs; i++) { 641 param = pinconf_to_config_param(configs[i]); 642 arg = pinconf_to_config_argument(configs[i]); 643 pin_reg = readl(gpio_dev->base + pin*4); 644 645 switch (param) { 646 case PIN_CONFIG_INPUT_DEBOUNCE: 647 pin_reg &= ~DB_TMR_OUT_MASK; 648 pin_reg |= arg & DB_TMR_OUT_MASK; 649 break; 650 651 case PIN_CONFIG_BIAS_PULL_DOWN: 652 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 653 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 654 break; 655 656 case PIN_CONFIG_BIAS_PULL_UP: 657 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 658 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 659 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 660 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 661 break; 662 663 case PIN_CONFIG_DRIVE_STRENGTH: 664 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 665 << DRV_STRENGTH_SEL_OFF); 666 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 667 << DRV_STRENGTH_SEL_OFF; 668 break; 669 670 default: 671 dev_err(&gpio_dev->pdev->dev, 672 "Invalid config param %04x\n", param); 673 ret = -ENOTSUPP; 674 } 675 676 writel(pin_reg, gpio_dev->base + pin*4); 677 } 678 spin_unlock_irqrestore(&gpio_dev->lock, flags); 679 680 return ret; 681 } 682 683 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 684 unsigned int group, 685 unsigned long *config) 686 { 687 const unsigned *pins; 688 unsigned npins; 689 int ret; 690 691 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 692 if (ret) 693 return ret; 694 695 if (amd_pinconf_get(pctldev, pins[0], config)) 696 return -ENOTSUPP; 697 698 return 0; 699 } 700 701 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 702 unsigned group, unsigned long *configs, 703 unsigned num_configs) 704 { 705 const unsigned *pins; 706 unsigned npins; 707 int i, ret; 708 709 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 710 if (ret) 711 return ret; 712 for (i = 0; i < npins; i++) { 713 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 714 return -ENOTSUPP; 715 } 716 return 0; 717 } 718 719 static const struct pinconf_ops amd_pinconf_ops = { 720 .pin_config_get = amd_pinconf_get, 721 .pin_config_set = amd_pinconf_set, 722 .pin_config_group_get = amd_pinconf_group_get, 723 .pin_config_group_set = amd_pinconf_group_set, 724 }; 725 726 static struct pinctrl_desc amd_pinctrl_desc = { 727 .pins = kerncz_pins, 728 .npins = ARRAY_SIZE(kerncz_pins), 729 .pctlops = &amd_pinctrl_ops, 730 .confops = &amd_pinconf_ops, 731 .owner = THIS_MODULE, 732 }; 733 734 static int amd_gpio_probe(struct platform_device *pdev) 735 { 736 int ret = 0; 737 int irq_base; 738 struct resource *res; 739 struct amd_gpio *gpio_dev; 740 741 gpio_dev = devm_kzalloc(&pdev->dev, 742 sizeof(struct amd_gpio), GFP_KERNEL); 743 if (!gpio_dev) 744 return -ENOMEM; 745 746 spin_lock_init(&gpio_dev->lock); 747 748 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 749 if (!res) { 750 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 751 return -EINVAL; 752 } 753 754 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, 755 resource_size(res)); 756 if (!gpio_dev->base) 757 return -ENOMEM; 758 759 irq_base = platform_get_irq(pdev, 0); 760 if (irq_base < 0) { 761 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n"); 762 return -EINVAL; 763 } 764 765 gpio_dev->pdev = pdev; 766 gpio_dev->gc.direction_input = amd_gpio_direction_input; 767 gpio_dev->gc.direction_output = amd_gpio_direction_output; 768 gpio_dev->gc.get = amd_gpio_get_value; 769 gpio_dev->gc.set = amd_gpio_set_value; 770 gpio_dev->gc.set_debounce = amd_gpio_set_debounce; 771 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 772 773 gpio_dev->gc.base = 0; 774 gpio_dev->gc.label = pdev->name; 775 gpio_dev->gc.owner = THIS_MODULE; 776 gpio_dev->gc.parent = &pdev->dev; 777 gpio_dev->gc.ngpio = TOTAL_NUMBER_OF_PINS; 778 #if defined(CONFIG_OF_GPIO) 779 gpio_dev->gc.of_node = pdev->dev.of_node; 780 #endif 781 782 gpio_dev->groups = kerncz_groups; 783 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 784 785 amd_pinctrl_desc.name = dev_name(&pdev->dev); 786 gpio_dev->pctrl = pinctrl_register(&amd_pinctrl_desc, 787 &pdev->dev, gpio_dev); 788 if (IS_ERR(gpio_dev->pctrl)) { 789 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 790 return PTR_ERR(gpio_dev->pctrl); 791 } 792 793 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 794 if (ret) 795 goto out1; 796 797 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 798 0, 0, TOTAL_NUMBER_OF_PINS); 799 if (ret) { 800 dev_err(&pdev->dev, "Failed to add pin range\n"); 801 goto out2; 802 } 803 804 ret = gpiochip_irqchip_add(&gpio_dev->gc, 805 &amd_gpio_irqchip, 806 0, 807 handle_simple_irq, 808 IRQ_TYPE_NONE); 809 if (ret) { 810 dev_err(&pdev->dev, "could not add irqchip\n"); 811 ret = -ENODEV; 812 goto out2; 813 } 814 815 gpiochip_set_chained_irqchip(&gpio_dev->gc, 816 &amd_gpio_irqchip, 817 irq_base, 818 amd_gpio_irq_handler); 819 820 platform_set_drvdata(pdev, gpio_dev); 821 822 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 823 return ret; 824 825 out2: 826 gpiochip_remove(&gpio_dev->gc); 827 828 out1: 829 pinctrl_unregister(gpio_dev->pctrl); 830 return ret; 831 } 832 833 static int amd_gpio_remove(struct platform_device *pdev) 834 { 835 struct amd_gpio *gpio_dev; 836 837 gpio_dev = platform_get_drvdata(pdev); 838 839 gpiochip_remove(&gpio_dev->gc); 840 pinctrl_unregister(gpio_dev->pctrl); 841 842 return 0; 843 } 844 845 static const struct acpi_device_id amd_gpio_acpi_match[] = { 846 { "AMD0030", 0 }, 847 { }, 848 }; 849 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 850 851 static struct platform_driver amd_gpio_driver = { 852 .driver = { 853 .name = "amd_gpio", 854 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 855 }, 856 .probe = amd_gpio_probe, 857 .remove = amd_gpio_remove, 858 }; 859 860 module_platform_driver(amd_gpio_driver); 861 862 MODULE_LICENSE("GPL v2"); 863 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 864 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 865