1 /* 2 * GPIO driver for AMD 3 * 4 * Copyright (c) 2014,2015 AMD Corporation. 5 * Authors: Ken Xue <Ken.Xue@amd.com> 6 * Wu, Jeff <Jeff.Wu@amd.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms and conditions of the GNU General Public License, 10 * version 2, as published by the Free Software Foundation. 11 */ 12 13 #include <linux/err.h> 14 #include <linux/bug.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/compiler.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/log2.h> 22 #include <linux/io.h> 23 #include <linux/gpio.h> 24 #include <linux/slab.h> 25 #include <linux/platform_device.h> 26 #include <linux/mutex.h> 27 #include <linux/acpi.h> 28 #include <linux/seq_file.h> 29 #include <linux/interrupt.h> 30 #include <linux/list.h> 31 #include <linux/bitops.h> 32 #include <linux/pinctrl/pinconf.h> 33 #include <linux/pinctrl/pinconf-generic.h> 34 35 #include "pinctrl-utils.h" 36 #include "pinctrl-amd.h" 37 38 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 39 { 40 unsigned long flags; 41 u32 pin_reg; 42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 43 44 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 45 pin_reg = readl(gpio_dev->base + offset * 4); 46 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 47 writel(pin_reg, gpio_dev->base + offset * 4); 48 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 49 50 return 0; 51 } 52 53 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 54 int value) 55 { 56 u32 pin_reg; 57 unsigned long flags; 58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 59 60 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 61 pin_reg = readl(gpio_dev->base + offset * 4); 62 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 63 if (value) 64 pin_reg |= BIT(OUTPUT_VALUE_OFF); 65 else 66 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 67 writel(pin_reg, gpio_dev->base + offset * 4); 68 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 69 70 return 0; 71 } 72 73 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 74 { 75 u32 pin_reg; 76 unsigned long flags; 77 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 78 79 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 80 pin_reg = readl(gpio_dev->base + offset * 4); 81 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 82 83 return !!(pin_reg & BIT(PIN_STS_OFF)); 84 } 85 86 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 87 { 88 u32 pin_reg; 89 unsigned long flags; 90 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 91 92 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 93 pin_reg = readl(gpio_dev->base + offset * 4); 94 if (value) 95 pin_reg |= BIT(OUTPUT_VALUE_OFF); 96 else 97 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 98 writel(pin_reg, gpio_dev->base + offset * 4); 99 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 100 } 101 102 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 103 unsigned debounce) 104 { 105 u32 time; 106 u32 pin_reg; 107 int ret = 0; 108 unsigned long flags; 109 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 110 111 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 112 pin_reg = readl(gpio_dev->base + offset * 4); 113 114 if (debounce) { 115 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 116 pin_reg &= ~DB_TMR_OUT_MASK; 117 /* 118 Debounce Debounce Timer Max 119 TmrLarge TmrOutUnit Unit Debounce 120 Time 121 0 0 61 usec (2 RtcClk) 976 usec 122 0 1 244 usec (8 RtcClk) 3.9 msec 123 1 0 15.6 msec (512 RtcClk) 250 msec 124 1 1 62.5 msec (2048 RtcClk) 1 sec 125 */ 126 127 if (debounce < 61) { 128 pin_reg |= 1; 129 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 130 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 131 } else if (debounce < 976) { 132 time = debounce / 61; 133 pin_reg |= time & DB_TMR_OUT_MASK; 134 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 135 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 136 } else if (debounce < 3900) { 137 time = debounce / 244; 138 pin_reg |= time & DB_TMR_OUT_MASK; 139 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 140 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 141 } else if (debounce < 250000) { 142 time = debounce / 15600; 143 pin_reg |= time & DB_TMR_OUT_MASK; 144 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 145 pin_reg |= BIT(DB_TMR_LARGE_OFF); 146 } else if (debounce < 1000000) { 147 time = debounce / 62500; 148 pin_reg |= time & DB_TMR_OUT_MASK; 149 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 150 pin_reg |= BIT(DB_TMR_LARGE_OFF); 151 } else { 152 pin_reg &= ~DB_CNTRl_MASK; 153 ret = -EINVAL; 154 } 155 } else { 156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 158 pin_reg &= ~DB_TMR_OUT_MASK; 159 pin_reg &= ~DB_CNTRl_MASK; 160 } 161 writel(pin_reg, gpio_dev->base + offset * 4); 162 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 163 164 return ret; 165 } 166 167 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 168 unsigned long config) 169 { 170 u32 debounce; 171 172 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 173 return -ENOTSUPP; 174 175 debounce = pinconf_to_config_argument(config); 176 return amd_gpio_set_debounce(gc, offset, debounce); 177 } 178 179 #ifdef CONFIG_DEBUG_FS 180 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 181 { 182 u32 pin_reg; 183 unsigned long flags; 184 unsigned int bank, i, pin_num; 185 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 186 187 char *level_trig; 188 char *active_level; 189 char *interrupt_enable; 190 char *interrupt_mask; 191 char *wake_cntrl0; 192 char *wake_cntrl1; 193 char *wake_cntrl2; 194 char *pin_sts; 195 char *pull_up_sel; 196 char *pull_up_enable; 197 char *pull_down_enable; 198 char *output_value; 199 char *output_enable; 200 201 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 202 seq_printf(s, "GPIO bank%d\t", bank); 203 204 switch (bank) { 205 case 0: 206 i = 0; 207 pin_num = AMD_GPIO_PINS_BANK0; 208 break; 209 case 1: 210 i = 64; 211 pin_num = AMD_GPIO_PINS_BANK1 + i; 212 break; 213 case 2: 214 i = 128; 215 pin_num = AMD_GPIO_PINS_BANK2 + i; 216 break; 217 case 3: 218 i = 192; 219 pin_num = AMD_GPIO_PINS_BANK3 + i; 220 break; 221 default: 222 /* Illegal bank number, ignore */ 223 continue; 224 } 225 for (; i < pin_num; i++) { 226 seq_printf(s, "pin%d\t", i); 227 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 228 pin_reg = readl(gpio_dev->base + i * 4); 229 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 230 231 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 232 interrupt_enable = "interrupt is enabled|"; 233 234 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && 235 !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) 236 active_level = "Active low|"; 237 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF) && 238 !(pin_reg & BIT(ACTIVE_LEVEL_OFF + 1))) 239 active_level = "Active high|"; 240 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF)) && 241 pin_reg & BIT(ACTIVE_LEVEL_OFF + 1)) 242 active_level = "Active on both|"; 243 else 244 active_level = "Unknown Active level|"; 245 246 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 247 level_trig = "Level trigger|"; 248 else 249 level_trig = "Edge trigger|"; 250 251 } else { 252 interrupt_enable = 253 "interrupt is disabled|"; 254 active_level = " "; 255 level_trig = " "; 256 } 257 258 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 259 interrupt_mask = 260 "interrupt is unmasked|"; 261 else 262 interrupt_mask = 263 "interrupt is masked|"; 264 265 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 266 wake_cntrl0 = "enable wakeup in S0i3 state|"; 267 else 268 wake_cntrl0 = "disable wakeup in S0i3 state|"; 269 270 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 271 wake_cntrl1 = "enable wakeup in S3 state|"; 272 else 273 wake_cntrl1 = "disable wakeup in S3 state|"; 274 275 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 276 wake_cntrl2 = "enable wakeup in S4/S5 state|"; 277 else 278 wake_cntrl2 = "disable wakeup in S4/S5 state|"; 279 280 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 281 pull_up_enable = "pull-up is enabled|"; 282 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 283 pull_up_sel = "8k pull-up|"; 284 else 285 pull_up_sel = "4k pull-up|"; 286 } else { 287 pull_up_enable = "pull-up is disabled|"; 288 pull_up_sel = " "; 289 } 290 291 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 292 pull_down_enable = "pull-down is enabled|"; 293 else 294 pull_down_enable = "Pull-down is disabled|"; 295 296 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 297 pin_sts = " "; 298 output_enable = "output is enabled|"; 299 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 300 output_value = "output is high|"; 301 else 302 output_value = "output is low|"; 303 } else { 304 output_enable = "output is disabled|"; 305 output_value = " "; 306 307 if (pin_reg & BIT(PIN_STS_OFF)) 308 pin_sts = "input is high|"; 309 else 310 pin_sts = "input is low|"; 311 } 312 313 seq_printf(s, "%s %s %s %s %s %s\n" 314 " %s %s %s %s %s %s %s 0x%x\n", 315 level_trig, active_level, interrupt_enable, 316 interrupt_mask, wake_cntrl0, wake_cntrl1, 317 wake_cntrl2, pin_sts, pull_up_sel, 318 pull_up_enable, pull_down_enable, 319 output_value, output_enable, pin_reg); 320 } 321 } 322 } 323 #else 324 #define amd_gpio_dbg_show NULL 325 #endif 326 327 static void amd_gpio_irq_enable(struct irq_data *d) 328 { 329 u32 pin_reg; 330 unsigned long flags; 331 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 332 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 333 334 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 335 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 336 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 337 pin_reg |= BIT(INTERRUPT_MASK_OFF); 338 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 339 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 340 } 341 342 static void amd_gpio_irq_disable(struct irq_data *d) 343 { 344 u32 pin_reg; 345 unsigned long flags; 346 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 347 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 348 349 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 350 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 351 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 352 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 353 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 354 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 355 } 356 357 static void amd_gpio_irq_mask(struct irq_data *d) 358 { 359 u32 pin_reg; 360 unsigned long flags; 361 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 362 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 363 364 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 365 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 366 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 367 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 368 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 369 } 370 371 static void amd_gpio_irq_unmask(struct irq_data *d) 372 { 373 u32 pin_reg; 374 unsigned long flags; 375 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 376 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 377 378 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 379 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 380 pin_reg |= BIT(INTERRUPT_MASK_OFF); 381 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 382 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 383 } 384 385 static void amd_gpio_irq_eoi(struct irq_data *d) 386 { 387 u32 reg; 388 unsigned long flags; 389 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 390 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 391 392 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 393 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 394 reg |= EOI_MASK; 395 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 396 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 397 } 398 399 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 400 { 401 int ret = 0; 402 u32 pin_reg; 403 unsigned long flags, irq_flags; 404 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 405 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 406 407 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 408 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 409 410 /* Ignore the settings coming from the client and 411 * read the values from the ACPI tables 412 * while setting the trigger type 413 */ 414 415 irq_flags = irq_get_trigger_type(d->irq); 416 if (irq_flags != IRQ_TYPE_NONE) 417 type = irq_flags; 418 419 switch (type & IRQ_TYPE_SENSE_MASK) { 420 case IRQ_TYPE_EDGE_RISING: 421 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 422 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 423 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 424 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 425 irq_set_handler_locked(d, handle_edge_irq); 426 break; 427 428 case IRQ_TYPE_EDGE_FALLING: 429 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 430 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 431 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 432 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 433 irq_set_handler_locked(d, handle_edge_irq); 434 break; 435 436 case IRQ_TYPE_EDGE_BOTH: 437 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 438 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 439 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 440 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 441 irq_set_handler_locked(d, handle_edge_irq); 442 break; 443 444 case IRQ_TYPE_LEVEL_HIGH: 445 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 446 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 447 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 448 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 449 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 450 irq_set_handler_locked(d, handle_level_irq); 451 break; 452 453 case IRQ_TYPE_LEVEL_LOW: 454 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 455 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 456 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 457 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 458 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 459 irq_set_handler_locked(d, handle_level_irq); 460 break; 461 462 case IRQ_TYPE_NONE: 463 break; 464 465 default: 466 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 467 ret = -EINVAL; 468 } 469 470 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 471 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 472 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 473 474 return ret; 475 } 476 477 static void amd_irq_ack(struct irq_data *d) 478 { 479 /* 480 * based on HW design,there is no need to ack HW 481 * before handle current irq. But this routine is 482 * necessary for handle_edge_irq 483 */ 484 } 485 486 static struct irq_chip amd_gpio_irqchip = { 487 .name = "amd_gpio", 488 .irq_ack = amd_irq_ack, 489 .irq_enable = amd_gpio_irq_enable, 490 .irq_disable = amd_gpio_irq_disable, 491 .irq_mask = amd_gpio_irq_mask, 492 .irq_unmask = amd_gpio_irq_unmask, 493 .irq_eoi = amd_gpio_irq_eoi, 494 .irq_set_type = amd_gpio_irq_set_type, 495 .flags = IRQCHIP_SKIP_SET_WAKE, 496 }; 497 498 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 499 500 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 501 { 502 struct amd_gpio *gpio_dev = dev_id; 503 struct gpio_chip *gc = &gpio_dev->gc; 504 irqreturn_t ret = IRQ_NONE; 505 unsigned int i, irqnr; 506 unsigned long flags; 507 u32 *regs, regval; 508 u64 status, mask; 509 510 /* Read the wake status */ 511 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 512 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 513 status <<= 32; 514 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 515 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 516 517 /* Bit 0-45 contain the relevant status bits */ 518 status &= (1ULL << 46) - 1; 519 regs = gpio_dev->base; 520 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 521 if (!(status & mask)) 522 continue; 523 status &= ~mask; 524 525 /* Each status bit covers four pins */ 526 for (i = 0; i < 4; i++) { 527 regval = readl(regs + i); 528 if (!(regval & PIN_IRQ_PENDING)) 529 continue; 530 irq = irq_find_mapping(gc->irqdomain, irqnr + i); 531 generic_handle_irq(irq); 532 /* Clear interrupt */ 533 writel(regval, regs + i); 534 ret = IRQ_HANDLED; 535 } 536 } 537 538 /* Signal EOI to the GPIO unit */ 539 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 540 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 541 regval |= EOI_MASK; 542 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 543 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 544 545 return ret; 546 } 547 548 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 549 { 550 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 551 552 return gpio_dev->ngroups; 553 } 554 555 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 556 unsigned group) 557 { 558 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 559 560 return gpio_dev->groups[group].name; 561 } 562 563 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 564 unsigned group, 565 const unsigned **pins, 566 unsigned *num_pins) 567 { 568 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 569 570 *pins = gpio_dev->groups[group].pins; 571 *num_pins = gpio_dev->groups[group].npins; 572 return 0; 573 } 574 575 static const struct pinctrl_ops amd_pinctrl_ops = { 576 .get_groups_count = amd_get_groups_count, 577 .get_group_name = amd_get_group_name, 578 .get_group_pins = amd_get_group_pins, 579 #ifdef CONFIG_OF 580 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 581 .dt_free_map = pinctrl_utils_free_map, 582 #endif 583 }; 584 585 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 586 unsigned int pin, 587 unsigned long *config) 588 { 589 u32 pin_reg; 590 unsigned arg; 591 unsigned long flags; 592 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 593 enum pin_config_param param = pinconf_to_config_param(*config); 594 595 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 596 pin_reg = readl(gpio_dev->base + pin*4); 597 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 598 switch (param) { 599 case PIN_CONFIG_INPUT_DEBOUNCE: 600 arg = pin_reg & DB_TMR_OUT_MASK; 601 break; 602 603 case PIN_CONFIG_BIAS_PULL_DOWN: 604 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 605 break; 606 607 case PIN_CONFIG_BIAS_PULL_UP: 608 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 609 break; 610 611 case PIN_CONFIG_DRIVE_STRENGTH: 612 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 613 break; 614 615 default: 616 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 617 param); 618 return -ENOTSUPP; 619 } 620 621 *config = pinconf_to_config_packed(param, arg); 622 623 return 0; 624 } 625 626 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 627 unsigned long *configs, unsigned num_configs) 628 { 629 int i; 630 u32 arg; 631 int ret = 0; 632 u32 pin_reg; 633 unsigned long flags; 634 enum pin_config_param param; 635 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 636 637 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 638 for (i = 0; i < num_configs; i++) { 639 param = pinconf_to_config_param(configs[i]); 640 arg = pinconf_to_config_argument(configs[i]); 641 pin_reg = readl(gpio_dev->base + pin*4); 642 643 switch (param) { 644 case PIN_CONFIG_INPUT_DEBOUNCE: 645 pin_reg &= ~DB_TMR_OUT_MASK; 646 pin_reg |= arg & DB_TMR_OUT_MASK; 647 break; 648 649 case PIN_CONFIG_BIAS_PULL_DOWN: 650 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 651 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 652 break; 653 654 case PIN_CONFIG_BIAS_PULL_UP: 655 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 656 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 657 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 658 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 659 break; 660 661 case PIN_CONFIG_DRIVE_STRENGTH: 662 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 663 << DRV_STRENGTH_SEL_OFF); 664 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 665 << DRV_STRENGTH_SEL_OFF; 666 break; 667 668 default: 669 dev_err(&gpio_dev->pdev->dev, 670 "Invalid config param %04x\n", param); 671 ret = -ENOTSUPP; 672 } 673 674 writel(pin_reg, gpio_dev->base + pin*4); 675 } 676 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 677 678 return ret; 679 } 680 681 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 682 unsigned int group, 683 unsigned long *config) 684 { 685 const unsigned *pins; 686 unsigned npins; 687 int ret; 688 689 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 690 if (ret) 691 return ret; 692 693 if (amd_pinconf_get(pctldev, pins[0], config)) 694 return -ENOTSUPP; 695 696 return 0; 697 } 698 699 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 700 unsigned group, unsigned long *configs, 701 unsigned num_configs) 702 { 703 const unsigned *pins; 704 unsigned npins; 705 int i, ret; 706 707 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 708 if (ret) 709 return ret; 710 for (i = 0; i < npins; i++) { 711 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 712 return -ENOTSUPP; 713 } 714 return 0; 715 } 716 717 static const struct pinconf_ops amd_pinconf_ops = { 718 .pin_config_get = amd_pinconf_get, 719 .pin_config_set = amd_pinconf_set, 720 .pin_config_group_get = amd_pinconf_group_get, 721 .pin_config_group_set = amd_pinconf_group_set, 722 }; 723 724 static struct pinctrl_desc amd_pinctrl_desc = { 725 .pins = kerncz_pins, 726 .npins = ARRAY_SIZE(kerncz_pins), 727 .pctlops = &amd_pinctrl_ops, 728 .confops = &amd_pinconf_ops, 729 .owner = THIS_MODULE, 730 }; 731 732 static int amd_gpio_probe(struct platform_device *pdev) 733 { 734 int ret = 0; 735 int irq_base; 736 struct resource *res; 737 struct amd_gpio *gpio_dev; 738 739 gpio_dev = devm_kzalloc(&pdev->dev, 740 sizeof(struct amd_gpio), GFP_KERNEL); 741 if (!gpio_dev) 742 return -ENOMEM; 743 744 raw_spin_lock_init(&gpio_dev->lock); 745 746 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 747 if (!res) { 748 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 749 return -EINVAL; 750 } 751 752 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start, 753 resource_size(res)); 754 if (!gpio_dev->base) 755 return -ENOMEM; 756 757 irq_base = platform_get_irq(pdev, 0); 758 if (irq_base < 0) { 759 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n"); 760 return -EINVAL; 761 } 762 763 gpio_dev->pdev = pdev; 764 gpio_dev->gc.direction_input = amd_gpio_direction_input; 765 gpio_dev->gc.direction_output = amd_gpio_direction_output; 766 gpio_dev->gc.get = amd_gpio_get_value; 767 gpio_dev->gc.set = amd_gpio_set_value; 768 gpio_dev->gc.set_config = amd_gpio_set_config; 769 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 770 771 gpio_dev->gc.base = -1; 772 gpio_dev->gc.label = pdev->name; 773 gpio_dev->gc.owner = THIS_MODULE; 774 gpio_dev->gc.parent = &pdev->dev; 775 gpio_dev->gc.ngpio = resource_size(res) / 4; 776 #if defined(CONFIG_OF_GPIO) 777 gpio_dev->gc.of_node = pdev->dev.of_node; 778 #endif 779 780 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 781 gpio_dev->groups = kerncz_groups; 782 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 783 784 amd_pinctrl_desc.name = dev_name(&pdev->dev); 785 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 786 gpio_dev); 787 if (IS_ERR(gpio_dev->pctrl)) { 788 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 789 return PTR_ERR(gpio_dev->pctrl); 790 } 791 792 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 793 if (ret) 794 return ret; 795 796 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 797 0, 0, gpio_dev->gc.ngpio); 798 if (ret) { 799 dev_err(&pdev->dev, "Failed to add pin range\n"); 800 goto out2; 801 } 802 803 ret = gpiochip_irqchip_add(&gpio_dev->gc, 804 &amd_gpio_irqchip, 805 0, 806 handle_simple_irq, 807 IRQ_TYPE_NONE); 808 if (ret) { 809 dev_err(&pdev->dev, "could not add irqchip\n"); 810 ret = -ENODEV; 811 goto out2; 812 } 813 814 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 0, 815 KBUILD_MODNAME, gpio_dev); 816 if (ret) 817 goto out2; 818 819 platform_set_drvdata(pdev, gpio_dev); 820 821 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 822 return ret; 823 824 out2: 825 gpiochip_remove(&gpio_dev->gc); 826 827 return ret; 828 } 829 830 static int amd_gpio_remove(struct platform_device *pdev) 831 { 832 struct amd_gpio *gpio_dev; 833 834 gpio_dev = platform_get_drvdata(pdev); 835 836 gpiochip_remove(&gpio_dev->gc); 837 838 return 0; 839 } 840 841 static const struct acpi_device_id amd_gpio_acpi_match[] = { 842 { "AMD0030", 0 }, 843 { "AMDI0030", 0}, 844 { }, 845 }; 846 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 847 848 static struct platform_driver amd_gpio_driver = { 849 .driver = { 850 .name = "amd_gpio", 851 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 852 }, 853 .probe = amd_gpio_probe, 854 .remove = amd_gpio_remove, 855 }; 856 857 module_platform_driver(amd_gpio_driver); 858 859 MODULE_LICENSE("GPL v2"); 860 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 861 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 862