1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 */ 10 11 #include <linux/err.h> 12 #include <linux/bug.h> 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/spinlock.h> 16 #include <linux/compiler.h> 17 #include <linux/types.h> 18 #include <linux/errno.h> 19 #include <linux/log2.h> 20 #include <linux/io.h> 21 #include <linux/gpio/driver.h> 22 #include <linux/slab.h> 23 #include <linux/platform_device.h> 24 #include <linux/mutex.h> 25 #include <linux/acpi.h> 26 #include <linux/seq_file.h> 27 #include <linux/interrupt.h> 28 #include <linux/list.h> 29 #include <linux/bitops.h> 30 #include <linux/pinctrl/pinconf.h> 31 #include <linux/pinctrl/pinconf-generic.h> 32 #include <linux/pinctrl/pinmux.h> 33 34 #include "core.h" 35 #include "pinctrl-utils.h" 36 #include "pinctrl-amd.h" 37 38 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 39 { 40 unsigned long flags; 41 u32 pin_reg; 42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 43 44 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 45 pin_reg = readl(gpio_dev->base + offset * 4); 46 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 47 48 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 49 return GPIO_LINE_DIRECTION_OUT; 50 51 return GPIO_LINE_DIRECTION_IN; 52 } 53 54 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 55 { 56 unsigned long flags; 57 u32 pin_reg; 58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 59 60 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 61 pin_reg = readl(gpio_dev->base + offset * 4); 62 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 63 writel(pin_reg, gpio_dev->base + offset * 4); 64 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 65 66 return 0; 67 } 68 69 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 70 int value) 71 { 72 u32 pin_reg; 73 unsigned long flags; 74 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 75 76 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 77 pin_reg = readl(gpio_dev->base + offset * 4); 78 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 79 if (value) 80 pin_reg |= BIT(OUTPUT_VALUE_OFF); 81 else 82 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 83 writel(pin_reg, gpio_dev->base + offset * 4); 84 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 85 86 return 0; 87 } 88 89 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 90 { 91 u32 pin_reg; 92 unsigned long flags; 93 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 94 95 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 96 pin_reg = readl(gpio_dev->base + offset * 4); 97 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 98 99 return !!(pin_reg & BIT(PIN_STS_OFF)); 100 } 101 102 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 103 { 104 u32 pin_reg; 105 unsigned long flags; 106 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 107 108 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 109 pin_reg = readl(gpio_dev->base + offset * 4); 110 if (value) 111 pin_reg |= BIT(OUTPUT_VALUE_OFF); 112 else 113 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 114 writel(pin_reg, gpio_dev->base + offset * 4); 115 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 116 } 117 118 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 119 unsigned debounce) 120 { 121 u32 time; 122 u32 pin_reg; 123 int ret = 0; 124 unsigned long flags; 125 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 126 127 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 128 pin_reg = readl(gpio_dev->base + offset * 4); 129 130 if (debounce) { 131 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 132 pin_reg &= ~DB_TMR_OUT_MASK; 133 /* 134 Debounce Debounce Timer Max 135 TmrLarge TmrOutUnit Unit Debounce 136 Time 137 0 0 61 usec (2 RtcClk) 976 usec 138 0 1 244 usec (8 RtcClk) 3.9 msec 139 1 0 15.6 msec (512 RtcClk) 250 msec 140 1 1 62.5 msec (2048 RtcClk) 1 sec 141 */ 142 143 if (debounce < 61) { 144 pin_reg |= 1; 145 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 146 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 147 } else if (debounce < 976) { 148 time = debounce / 61; 149 pin_reg |= time & DB_TMR_OUT_MASK; 150 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 151 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 152 } else if (debounce < 3900) { 153 time = debounce / 244; 154 pin_reg |= time & DB_TMR_OUT_MASK; 155 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 156 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 157 } else if (debounce < 250000) { 158 time = debounce / 15625; 159 pin_reg |= time & DB_TMR_OUT_MASK; 160 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 161 pin_reg |= BIT(DB_TMR_LARGE_OFF); 162 } else if (debounce < 1000000) { 163 time = debounce / 62500; 164 pin_reg |= time & DB_TMR_OUT_MASK; 165 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 166 pin_reg |= BIT(DB_TMR_LARGE_OFF); 167 } else { 168 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 169 ret = -EINVAL; 170 } 171 } else { 172 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 173 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 174 pin_reg &= ~DB_TMR_OUT_MASK; 175 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 176 } 177 writel(pin_reg, gpio_dev->base + offset * 4); 178 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 179 180 return ret; 181 } 182 183 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 184 unsigned long config) 185 { 186 u32 debounce; 187 188 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 189 return -ENOTSUPP; 190 191 debounce = pinconf_to_config_argument(config); 192 return amd_gpio_set_debounce(gc, offset, debounce); 193 } 194 195 #ifdef CONFIG_DEBUG_FS 196 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 197 { 198 u32 pin_reg; 199 u32 db_cntrl; 200 unsigned long flags; 201 unsigned int bank, i, pin_num; 202 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 203 204 bool tmr_out_unit; 205 bool tmr_large; 206 207 char *level_trig; 208 char *active_level; 209 char *interrupt_enable; 210 char *interrupt_mask; 211 char *wake_cntrl0; 212 char *wake_cntrl1; 213 char *wake_cntrl2; 214 char *pin_sts; 215 char *pull_up_sel; 216 char *pull_up_enable; 217 char *pull_down_enable; 218 char *orientation; 219 char debounce_value[40]; 220 char *debounce_enable; 221 char *wake_cntrlz; 222 223 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 224 unsigned int time = 0; 225 unsigned int unit = 0; 226 227 switch (bank) { 228 case 0: 229 i = 0; 230 pin_num = AMD_GPIO_PINS_BANK0; 231 break; 232 case 1: 233 i = 64; 234 pin_num = AMD_GPIO_PINS_BANK1 + i; 235 break; 236 case 2: 237 i = 128; 238 pin_num = AMD_GPIO_PINS_BANK2 + i; 239 break; 240 case 3: 241 i = 192; 242 pin_num = AMD_GPIO_PINS_BANK3 + i; 243 break; 244 default: 245 /* Illegal bank number, ignore */ 246 continue; 247 } 248 seq_printf(s, "GPIO bank%d\n", bank); 249 for (; i < pin_num; i++) { 250 seq_printf(s, "#%d\t", i); 251 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 252 pin_reg = readl(gpio_dev->base + i * 4); 253 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 254 255 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 256 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 257 ACTIVE_LEVEL_MASK; 258 interrupt_enable = "+"; 259 260 if (level == ACTIVE_LEVEL_HIGH) 261 active_level = "↑"; 262 else if (level == ACTIVE_LEVEL_LOW) 263 active_level = "↓"; 264 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 265 level == ACTIVE_LEVEL_BOTH) 266 active_level = "b"; 267 else 268 active_level = "?"; 269 270 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 271 level_trig = "level"; 272 else 273 level_trig = " edge"; 274 275 } else { 276 interrupt_enable = "∅"; 277 active_level = "∅"; 278 level_trig = " ∅"; 279 } 280 281 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 282 interrupt_mask = "��"; 283 else 284 interrupt_mask = "��"; 285 seq_printf(s, "int %s (%s)| active-%s| %s-⚡| ", 286 interrupt_enable, 287 interrupt_mask, 288 active_level, 289 level_trig); 290 291 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 292 wake_cntrl0 = "⏰"; 293 else 294 wake_cntrl0 = " ∅"; 295 seq_printf(s, "S0i3 %s| ", wake_cntrl0); 296 297 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 298 wake_cntrl1 = "⏰"; 299 else 300 wake_cntrl1 = " ∅"; 301 seq_printf(s, "S3 %s| ", wake_cntrl1); 302 303 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 304 wake_cntrl2 = "⏰"; 305 else 306 wake_cntrl2 = " ∅"; 307 seq_printf(s, "S4/S5 %s| ", wake_cntrl2); 308 309 if (pin_reg & BIT(WAKECNTRL_Z_OFF)) 310 wake_cntrlz = "⏰"; 311 else 312 wake_cntrlz = " ∅"; 313 seq_printf(s, "Z %s| ", wake_cntrlz); 314 315 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 316 pull_up_enable = "+"; 317 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 318 pull_up_sel = "8k"; 319 else 320 pull_up_sel = "4k"; 321 } else { 322 pull_up_enable = "∅"; 323 pull_up_sel = " "; 324 } 325 seq_printf(s, "pull-↑ %s (%s)| ", 326 pull_up_enable, 327 pull_up_sel); 328 329 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 330 pull_down_enable = "+"; 331 else 332 pull_down_enable = "∅"; 333 seq_printf(s, "pull-↓ %s| ", pull_down_enable); 334 335 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 336 pin_sts = "output"; 337 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 338 orientation = "↑"; 339 else 340 orientation = "↓"; 341 } else { 342 pin_sts = "input "; 343 if (pin_reg & BIT(PIN_STS_OFF)) 344 orientation = "↑"; 345 else 346 orientation = "↓"; 347 } 348 seq_printf(s, "%s %s| ", pin_sts, orientation); 349 350 db_cntrl = (DB_CNTRl_MASK << DB_CNTRL_OFF) & pin_reg; 351 if (db_cntrl) { 352 tmr_out_unit = pin_reg & BIT(DB_TMR_OUT_UNIT_OFF); 353 tmr_large = pin_reg & BIT(DB_TMR_LARGE_OFF); 354 time = pin_reg & DB_TMR_OUT_MASK; 355 if (tmr_large) { 356 if (tmr_out_unit) 357 unit = 62500; 358 else 359 unit = 15625; 360 } else { 361 if (tmr_out_unit) 362 unit = 244; 363 else 364 unit = 61; 365 } 366 if ((DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF) == db_cntrl) 367 debounce_enable = "b +"; 368 else if ((DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF) == db_cntrl) 369 debounce_enable = "↓ +"; 370 else 371 debounce_enable = "↑ +"; 372 373 } else { 374 debounce_enable = " ∅"; 375 } 376 snprintf(debounce_value, sizeof(debounce_value), "%u", time * unit); 377 seq_printf(s, "debounce %s (�� %sus)| ", debounce_enable, debounce_value); 378 seq_printf(s, " 0x%x\n", pin_reg); 379 } 380 } 381 } 382 #else 383 #define amd_gpio_dbg_show NULL 384 #endif 385 386 static void amd_gpio_irq_enable(struct irq_data *d) 387 { 388 u32 pin_reg; 389 unsigned long flags; 390 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 391 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 392 393 gpiochip_enable_irq(gc, d->hwirq); 394 395 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 396 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 397 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 398 pin_reg |= BIT(INTERRUPT_MASK_OFF); 399 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 400 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 401 } 402 403 static void amd_gpio_irq_disable(struct irq_data *d) 404 { 405 u32 pin_reg; 406 unsigned long flags; 407 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 408 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 409 410 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 411 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 412 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 413 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 414 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 415 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 416 417 gpiochip_disable_irq(gc, d->hwirq); 418 } 419 420 static void amd_gpio_irq_mask(struct irq_data *d) 421 { 422 u32 pin_reg; 423 unsigned long flags; 424 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 425 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 426 427 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 428 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 429 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 430 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 431 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 432 } 433 434 static void amd_gpio_irq_unmask(struct irq_data *d) 435 { 436 u32 pin_reg; 437 unsigned long flags; 438 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 439 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 440 441 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 442 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 443 pin_reg |= BIT(INTERRUPT_MASK_OFF); 444 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 445 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 446 } 447 448 static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 449 { 450 u32 pin_reg; 451 unsigned long flags; 452 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 453 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 454 u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3); 455 int err; 456 457 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 458 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 459 460 if (on) 461 pin_reg |= wake_mask; 462 else 463 pin_reg &= ~wake_mask; 464 465 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 466 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 467 468 if (on) 469 err = enable_irq_wake(gpio_dev->irq); 470 else 471 err = disable_irq_wake(gpio_dev->irq); 472 473 if (err) 474 dev_err(&gpio_dev->pdev->dev, "failed to %s wake-up interrupt\n", 475 on ? "enable" : "disable"); 476 477 return 0; 478 } 479 480 static void amd_gpio_irq_eoi(struct irq_data *d) 481 { 482 u32 reg; 483 unsigned long flags; 484 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 485 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 486 487 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 488 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 489 reg |= EOI_MASK; 490 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 491 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 492 } 493 494 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 495 { 496 int ret = 0; 497 u32 pin_reg, pin_reg_irq_en, mask; 498 unsigned long flags; 499 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 500 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 501 502 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 503 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 504 505 switch (type & IRQ_TYPE_SENSE_MASK) { 506 case IRQ_TYPE_EDGE_RISING: 507 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 508 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 509 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 510 irq_set_handler_locked(d, handle_edge_irq); 511 break; 512 513 case IRQ_TYPE_EDGE_FALLING: 514 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 515 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 516 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 517 irq_set_handler_locked(d, handle_edge_irq); 518 break; 519 520 case IRQ_TYPE_EDGE_BOTH: 521 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 522 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 523 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 524 irq_set_handler_locked(d, handle_edge_irq); 525 break; 526 527 case IRQ_TYPE_LEVEL_HIGH: 528 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 529 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 530 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 531 irq_set_handler_locked(d, handle_level_irq); 532 break; 533 534 case IRQ_TYPE_LEVEL_LOW: 535 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 536 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 537 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 538 irq_set_handler_locked(d, handle_level_irq); 539 break; 540 541 case IRQ_TYPE_NONE: 542 break; 543 544 default: 545 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 546 ret = -EINVAL; 547 } 548 549 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 550 /* 551 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 552 * debounce registers of any GPIO will block wake/interrupt status 553 * generation for *all* GPIOs for a length of time that depends on 554 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 555 * INTERRUPT_ENABLE bit will read as 0. 556 * 557 * We temporarily enable irq for the GPIO whose configuration is 558 * changing, and then wait for it to read back as 1 to know when 559 * debounce has settled and then disable the irq again. 560 * We do this polling with the spinlock held to ensure other GPIO 561 * access routines do not read an incorrect value for the irq enable 562 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 563 * spurious irqs, and disable the irq again after polling. 564 */ 565 mask = BIT(INTERRUPT_ENABLE_OFF); 566 pin_reg_irq_en = pin_reg; 567 pin_reg_irq_en |= mask; 568 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 569 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 570 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 571 continue; 572 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 573 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 574 575 return ret; 576 } 577 578 static void amd_irq_ack(struct irq_data *d) 579 { 580 /* 581 * based on HW design,there is no need to ack HW 582 * before handle current irq. But this routine is 583 * necessary for handle_edge_irq 584 */ 585 } 586 587 static const struct irq_chip amd_gpio_irqchip = { 588 .name = "amd_gpio", 589 .irq_ack = amd_irq_ack, 590 .irq_enable = amd_gpio_irq_enable, 591 .irq_disable = amd_gpio_irq_disable, 592 .irq_mask = amd_gpio_irq_mask, 593 .irq_unmask = amd_gpio_irq_unmask, 594 .irq_set_wake = amd_gpio_irq_set_wake, 595 .irq_eoi = amd_gpio_irq_eoi, 596 .irq_set_type = amd_gpio_irq_set_type, 597 /* 598 * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event 599 * also generates an IRQ. We need the IRQ so the irq_handler can clear 600 * the wake event. Otherwise the wake event will never clear and 601 * prevent the system from suspending. 602 */ 603 .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND | IRQCHIP_IMMUTABLE, 604 GPIOCHIP_IRQ_RESOURCE_HELPERS, 605 }; 606 607 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 608 609 static bool do_amd_gpio_irq_handler(int irq, void *dev_id) 610 { 611 struct amd_gpio *gpio_dev = dev_id; 612 struct gpio_chip *gc = &gpio_dev->gc; 613 unsigned int i, irqnr; 614 unsigned long flags; 615 u32 __iomem *regs; 616 bool ret = false; 617 u32 regval; 618 u64 status, mask; 619 620 /* Read the wake status */ 621 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 622 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 623 status <<= 32; 624 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 625 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 626 627 /* Bit 0-45 contain the relevant status bits */ 628 status &= (1ULL << 46) - 1; 629 regs = gpio_dev->base; 630 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 631 if (!(status & mask)) 632 continue; 633 status &= ~mask; 634 635 /* Each status bit covers four pins */ 636 for (i = 0; i < 4; i++) { 637 regval = readl(regs + i); 638 639 if (regval & PIN_IRQ_PENDING) 640 dev_dbg(&gpio_dev->pdev->dev, 641 "GPIO %d is active: 0x%x", 642 irqnr + i, regval); 643 644 /* caused wake on resume context for shared IRQ */ 645 if (irq < 0 && (regval & BIT(WAKE_STS_OFF))) 646 return true; 647 648 if (!(regval & PIN_IRQ_PENDING) || 649 !(regval & BIT(INTERRUPT_MASK_OFF))) 650 continue; 651 generic_handle_domain_irq_safe(gc->irq.domain, irqnr + i); 652 653 /* Clear interrupt. 654 * We must read the pin register again, in case the 655 * value was changed while executing 656 * generic_handle_domain_irq() above. 657 * If we didn't find a mapping for the interrupt, 658 * disable it in order to avoid a system hang caused 659 * by an interrupt storm. 660 */ 661 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 662 regval = readl(regs + i); 663 if (irq == 0) { 664 regval &= ~BIT(INTERRUPT_ENABLE_OFF); 665 dev_dbg(&gpio_dev->pdev->dev, 666 "Disabling spurious GPIO IRQ %d\n", 667 irqnr + i); 668 } 669 writel(regval, regs + i); 670 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 671 ret = true; 672 } 673 } 674 /* did not cause wake on resume context for shared IRQ */ 675 if (irq < 0) 676 return false; 677 678 /* Signal EOI to the GPIO unit */ 679 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 680 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 681 regval |= EOI_MASK; 682 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 683 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 684 685 return ret; 686 } 687 688 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 689 { 690 return IRQ_RETVAL(do_amd_gpio_irq_handler(irq, dev_id)); 691 } 692 693 static bool __maybe_unused amd_gpio_check_wake(void *dev_id) 694 { 695 return do_amd_gpio_irq_handler(-1, dev_id); 696 } 697 698 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 699 { 700 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 701 702 return gpio_dev->ngroups; 703 } 704 705 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 706 unsigned group) 707 { 708 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 709 710 return gpio_dev->groups[group].name; 711 } 712 713 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 714 unsigned group, 715 const unsigned **pins, 716 unsigned *num_pins) 717 { 718 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 719 720 *pins = gpio_dev->groups[group].pins; 721 *num_pins = gpio_dev->groups[group].npins; 722 return 0; 723 } 724 725 static const struct pinctrl_ops amd_pinctrl_ops = { 726 .get_groups_count = amd_get_groups_count, 727 .get_group_name = amd_get_group_name, 728 .get_group_pins = amd_get_group_pins, 729 #ifdef CONFIG_OF 730 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 731 .dt_free_map = pinctrl_utils_free_map, 732 #endif 733 }; 734 735 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 736 unsigned int pin, 737 unsigned long *config) 738 { 739 u32 pin_reg; 740 unsigned arg; 741 unsigned long flags; 742 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 743 enum pin_config_param param = pinconf_to_config_param(*config); 744 745 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 746 pin_reg = readl(gpio_dev->base + pin*4); 747 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 748 switch (param) { 749 case PIN_CONFIG_INPUT_DEBOUNCE: 750 arg = pin_reg & DB_TMR_OUT_MASK; 751 break; 752 753 case PIN_CONFIG_BIAS_PULL_DOWN: 754 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 755 break; 756 757 case PIN_CONFIG_BIAS_PULL_UP: 758 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 759 break; 760 761 case PIN_CONFIG_DRIVE_STRENGTH: 762 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 763 break; 764 765 default: 766 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 767 param); 768 return -ENOTSUPP; 769 } 770 771 *config = pinconf_to_config_packed(param, arg); 772 773 return 0; 774 } 775 776 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 777 unsigned long *configs, unsigned num_configs) 778 { 779 int i; 780 u32 arg; 781 int ret = 0; 782 u32 pin_reg; 783 unsigned long flags; 784 enum pin_config_param param; 785 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 786 787 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 788 for (i = 0; i < num_configs; i++) { 789 param = pinconf_to_config_param(configs[i]); 790 arg = pinconf_to_config_argument(configs[i]); 791 pin_reg = readl(gpio_dev->base + pin*4); 792 793 switch (param) { 794 case PIN_CONFIG_INPUT_DEBOUNCE: 795 pin_reg &= ~DB_TMR_OUT_MASK; 796 pin_reg |= arg & DB_TMR_OUT_MASK; 797 break; 798 799 case PIN_CONFIG_BIAS_PULL_DOWN: 800 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 801 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 802 break; 803 804 case PIN_CONFIG_BIAS_PULL_UP: 805 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 806 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 807 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 808 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 809 break; 810 811 case PIN_CONFIG_DRIVE_STRENGTH: 812 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 813 << DRV_STRENGTH_SEL_OFF); 814 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 815 << DRV_STRENGTH_SEL_OFF; 816 break; 817 818 default: 819 dev_err(&gpio_dev->pdev->dev, 820 "Invalid config param %04x\n", param); 821 ret = -ENOTSUPP; 822 } 823 824 writel(pin_reg, gpio_dev->base + pin*4); 825 } 826 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 827 828 return ret; 829 } 830 831 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 832 unsigned int group, 833 unsigned long *config) 834 { 835 const unsigned *pins; 836 unsigned npins; 837 int ret; 838 839 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 840 if (ret) 841 return ret; 842 843 if (amd_pinconf_get(pctldev, pins[0], config)) 844 return -ENOTSUPP; 845 846 return 0; 847 } 848 849 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 850 unsigned group, unsigned long *configs, 851 unsigned num_configs) 852 { 853 const unsigned *pins; 854 unsigned npins; 855 int i, ret; 856 857 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 858 if (ret) 859 return ret; 860 for (i = 0; i < npins; i++) { 861 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 862 return -ENOTSUPP; 863 } 864 return 0; 865 } 866 867 static const struct pinconf_ops amd_pinconf_ops = { 868 .pin_config_get = amd_pinconf_get, 869 .pin_config_set = amd_pinconf_set, 870 .pin_config_group_get = amd_pinconf_group_get, 871 .pin_config_group_set = amd_pinconf_group_set, 872 }; 873 874 static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) 875 { 876 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 877 unsigned long flags; 878 u32 pin_reg, mask; 879 int i; 880 881 mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) | 882 BIT(INTERRUPT_MASK_OFF) | BIT(INTERRUPT_ENABLE_OFF) | 883 BIT(WAKE_CNTRL_OFF_S4); 884 885 for (i = 0; i < desc->npins; i++) { 886 int pin = desc->pins[i].number; 887 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 888 889 if (!pd) 890 continue; 891 892 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 893 894 pin_reg = readl(gpio_dev->base + i * 4); 895 pin_reg &= ~mask; 896 writel(pin_reg, gpio_dev->base + i * 4); 897 898 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 899 } 900 } 901 902 #ifdef CONFIG_PM_SLEEP 903 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 904 { 905 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 906 907 if (!pd) 908 return false; 909 910 /* 911 * Only restore the pin if it is actually in use by the kernel (or 912 * by userspace). 913 */ 914 if (pd->mux_owner || pd->gpio_owner || 915 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 916 return true; 917 918 return false; 919 } 920 921 static int amd_gpio_suspend(struct device *dev) 922 { 923 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 924 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 925 unsigned long flags; 926 int i; 927 928 for (i = 0; i < desc->npins; i++) { 929 int pin = desc->pins[i].number; 930 931 if (!amd_gpio_should_save(gpio_dev, pin)) 932 continue; 933 934 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 935 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin * 4) & ~PIN_IRQ_PENDING; 936 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 937 } 938 939 return 0; 940 } 941 942 static int amd_gpio_resume(struct device *dev) 943 { 944 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 945 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 946 unsigned long flags; 947 int i; 948 949 for (i = 0; i < desc->npins; i++) { 950 int pin = desc->pins[i].number; 951 952 if (!amd_gpio_should_save(gpio_dev, pin)) 953 continue; 954 955 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 956 gpio_dev->saved_regs[i] |= readl(gpio_dev->base + pin * 4) & PIN_IRQ_PENDING; 957 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin * 4); 958 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 959 } 960 961 return 0; 962 } 963 964 static const struct dev_pm_ops amd_gpio_pm_ops = { 965 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 966 amd_gpio_resume) 967 }; 968 #endif 969 970 static int amd_get_functions_count(struct pinctrl_dev *pctldev) 971 { 972 return ARRAY_SIZE(pmx_functions); 973 } 974 975 static const char *amd_get_fname(struct pinctrl_dev *pctrldev, unsigned int selector) 976 { 977 return pmx_functions[selector].name; 978 } 979 980 static int amd_get_groups(struct pinctrl_dev *pctrldev, unsigned int selector, 981 const char * const **groups, 982 unsigned int * const num_groups) 983 { 984 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 985 986 if (!gpio_dev->iomux_base) { 987 dev_err(&gpio_dev->pdev->dev, "iomux function %d group not supported\n", selector); 988 return -EINVAL; 989 } 990 991 *groups = pmx_functions[selector].groups; 992 *num_groups = pmx_functions[selector].ngroups; 993 return 0; 994 } 995 996 static int amd_set_mux(struct pinctrl_dev *pctrldev, unsigned int function, unsigned int group) 997 { 998 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctrldev); 999 struct device *dev = &gpio_dev->pdev->dev; 1000 struct pin_desc *pd; 1001 int ind, index; 1002 1003 if (!gpio_dev->iomux_base) 1004 return -EINVAL; 1005 1006 for (index = 0; index < NSELECTS; index++) { 1007 if (strcmp(gpio_dev->groups[group].name, pmx_functions[function].groups[index])) 1008 continue; 1009 1010 if (readb(gpio_dev->iomux_base + pmx_functions[function].index) == 1011 FUNCTION_INVALID) { 1012 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1013 pmx_functions[function].index); 1014 return -EINVAL; 1015 } 1016 1017 writeb(index, gpio_dev->iomux_base + pmx_functions[function].index); 1018 1019 if (index != (readb(gpio_dev->iomux_base + pmx_functions[function].index) & 1020 FUNCTION_MASK)) { 1021 dev_err(dev, "IOMUX_GPIO 0x%x not present or supported\n", 1022 pmx_functions[function].index); 1023 return -EINVAL; 1024 } 1025 1026 for (ind = 0; ind < gpio_dev->groups[group].npins; ind++) { 1027 if (strncmp(gpio_dev->groups[group].name, "IMX_F", strlen("IMX_F"))) 1028 continue; 1029 1030 pd = pin_desc_get(gpio_dev->pctrl, gpio_dev->groups[group].pins[ind]); 1031 pd->mux_owner = gpio_dev->groups[group].name; 1032 } 1033 break; 1034 } 1035 1036 return 0; 1037 } 1038 1039 static const struct pinmux_ops amd_pmxops = { 1040 .get_functions_count = amd_get_functions_count, 1041 .get_function_name = amd_get_fname, 1042 .get_function_groups = amd_get_groups, 1043 .set_mux = amd_set_mux, 1044 }; 1045 1046 static struct pinctrl_desc amd_pinctrl_desc = { 1047 .pins = kerncz_pins, 1048 .npins = ARRAY_SIZE(kerncz_pins), 1049 .pctlops = &amd_pinctrl_ops, 1050 .pmxops = &amd_pmxops, 1051 .confops = &amd_pinconf_ops, 1052 .owner = THIS_MODULE, 1053 }; 1054 1055 static void amd_get_iomux_res(struct amd_gpio *gpio_dev) 1056 { 1057 struct pinctrl_desc *desc = &amd_pinctrl_desc; 1058 struct device *dev = &gpio_dev->pdev->dev; 1059 int index; 1060 1061 index = device_property_match_string(dev, "pinctrl-resource-names", "iomux"); 1062 if (index < 0) { 1063 dev_dbg(dev, "iomux not supported\n"); 1064 goto out_no_pinmux; 1065 } 1066 1067 gpio_dev->iomux_base = devm_platform_ioremap_resource(gpio_dev->pdev, index); 1068 if (IS_ERR(gpio_dev->iomux_base)) { 1069 dev_dbg(dev, "iomux not supported %d io resource\n", index); 1070 goto out_no_pinmux; 1071 } 1072 1073 return; 1074 1075 out_no_pinmux: 1076 desc->pmxops = NULL; 1077 } 1078 1079 static int amd_gpio_probe(struct platform_device *pdev) 1080 { 1081 int ret = 0; 1082 struct resource *res; 1083 struct amd_gpio *gpio_dev; 1084 struct gpio_irq_chip *girq; 1085 1086 gpio_dev = devm_kzalloc(&pdev->dev, 1087 sizeof(struct amd_gpio), GFP_KERNEL); 1088 if (!gpio_dev) 1089 return -ENOMEM; 1090 1091 raw_spin_lock_init(&gpio_dev->lock); 1092 1093 gpio_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1094 if (IS_ERR(gpio_dev->base)) { 1095 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 1096 return PTR_ERR(gpio_dev->base); 1097 } 1098 1099 gpio_dev->irq = platform_get_irq(pdev, 0); 1100 if (gpio_dev->irq < 0) 1101 return gpio_dev->irq; 1102 1103 #ifdef CONFIG_PM_SLEEP 1104 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 1105 sizeof(*gpio_dev->saved_regs), 1106 GFP_KERNEL); 1107 if (!gpio_dev->saved_regs) 1108 return -ENOMEM; 1109 #endif 1110 1111 gpio_dev->pdev = pdev; 1112 gpio_dev->gc.get_direction = amd_gpio_get_direction; 1113 gpio_dev->gc.direction_input = amd_gpio_direction_input; 1114 gpio_dev->gc.direction_output = amd_gpio_direction_output; 1115 gpio_dev->gc.get = amd_gpio_get_value; 1116 gpio_dev->gc.set = amd_gpio_set_value; 1117 gpio_dev->gc.set_config = amd_gpio_set_config; 1118 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 1119 1120 gpio_dev->gc.base = -1; 1121 gpio_dev->gc.label = pdev->name; 1122 gpio_dev->gc.owner = THIS_MODULE; 1123 gpio_dev->gc.parent = &pdev->dev; 1124 gpio_dev->gc.ngpio = resource_size(res) / 4; 1125 1126 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 1127 gpio_dev->groups = kerncz_groups; 1128 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 1129 1130 amd_pinctrl_desc.name = dev_name(&pdev->dev); 1131 amd_get_iomux_res(gpio_dev); 1132 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 1133 gpio_dev); 1134 if (IS_ERR(gpio_dev->pctrl)) { 1135 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 1136 return PTR_ERR(gpio_dev->pctrl); 1137 } 1138 1139 /* Disable and mask interrupts */ 1140 amd_gpio_irq_init(gpio_dev); 1141 1142 girq = &gpio_dev->gc.irq; 1143 gpio_irq_chip_set_chip(girq, &amd_gpio_irqchip); 1144 /* This will let us handle the parent IRQ in the driver */ 1145 girq->parent_handler = NULL; 1146 girq->num_parents = 0; 1147 girq->parents = NULL; 1148 girq->default_type = IRQ_TYPE_NONE; 1149 girq->handler = handle_simple_irq; 1150 1151 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 1152 if (ret) 1153 return ret; 1154 1155 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 1156 0, 0, gpio_dev->gc.ngpio); 1157 if (ret) { 1158 dev_err(&pdev->dev, "Failed to add pin range\n"); 1159 goto out2; 1160 } 1161 1162 ret = devm_request_irq(&pdev->dev, gpio_dev->irq, amd_gpio_irq_handler, 1163 IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 1164 if (ret) 1165 goto out2; 1166 1167 platform_set_drvdata(pdev, gpio_dev); 1168 acpi_register_wakeup_handler(gpio_dev->irq, amd_gpio_check_wake, gpio_dev); 1169 1170 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 1171 return ret; 1172 1173 out2: 1174 gpiochip_remove(&gpio_dev->gc); 1175 1176 return ret; 1177 } 1178 1179 static int amd_gpio_remove(struct platform_device *pdev) 1180 { 1181 struct amd_gpio *gpio_dev; 1182 1183 gpio_dev = platform_get_drvdata(pdev); 1184 1185 gpiochip_remove(&gpio_dev->gc); 1186 acpi_unregister_wakeup_handler(amd_gpio_check_wake, gpio_dev); 1187 1188 return 0; 1189 } 1190 1191 #ifdef CONFIG_ACPI 1192 static const struct acpi_device_id amd_gpio_acpi_match[] = { 1193 { "AMD0030", 0 }, 1194 { "AMDI0030", 0}, 1195 { "AMDI0031", 0}, 1196 { }, 1197 }; 1198 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 1199 #endif 1200 1201 static struct platform_driver amd_gpio_driver = { 1202 .driver = { 1203 .name = "amd_gpio", 1204 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 1205 #ifdef CONFIG_PM_SLEEP 1206 .pm = &amd_gpio_pm_ops, 1207 #endif 1208 }, 1209 .probe = amd_gpio_probe, 1210 .remove = amd_gpio_remove, 1211 }; 1212 1213 module_platform_driver(amd_gpio_driver); 1214 1215 MODULE_LICENSE("GPL v2"); 1216 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 1217 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 1218