1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for AMD 4 * 5 * Copyright (c) 2014,2015 AMD Corporation. 6 * Authors: Ken Xue <Ken.Xue@amd.com> 7 * Wu, Jeff <Jeff.Wu@amd.com> 8 * 9 * Contact Information: Nehal Shah <Nehal-bakulchandra.Shah@amd.com> 10 * Shyam Sundar S K <Shyam-sundar.S-k@amd.com> 11 */ 12 13 #include <linux/err.h> 14 #include <linux/bug.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/spinlock.h> 18 #include <linux/compiler.h> 19 #include <linux/types.h> 20 #include <linux/errno.h> 21 #include <linux/log2.h> 22 #include <linux/io.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/slab.h> 25 #include <linux/platform_device.h> 26 #include <linux/mutex.h> 27 #include <linux/acpi.h> 28 #include <linux/seq_file.h> 29 #include <linux/interrupt.h> 30 #include <linux/list.h> 31 #include <linux/bitops.h> 32 #include <linux/pinctrl/pinconf.h> 33 #include <linux/pinctrl/pinconf-generic.h> 34 35 #include "core.h" 36 #include "pinctrl-utils.h" 37 #include "pinctrl-amd.h" 38 39 static int amd_gpio_get_direction(struct gpio_chip *gc, unsigned offset) 40 { 41 unsigned long flags; 42 u32 pin_reg; 43 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 44 45 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 46 pin_reg = readl(gpio_dev->base + offset * 4); 47 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 48 49 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) 50 return GPIO_LINE_DIRECTION_OUT; 51 52 return GPIO_LINE_DIRECTION_IN; 53 } 54 55 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset) 56 { 57 unsigned long flags; 58 u32 pin_reg; 59 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 60 61 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 62 pin_reg = readl(gpio_dev->base + offset * 4); 63 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF); 64 writel(pin_reg, gpio_dev->base + offset * 4); 65 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 66 67 return 0; 68 } 69 70 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset, 71 int value) 72 { 73 u32 pin_reg; 74 unsigned long flags; 75 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 76 77 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 78 pin_reg = readl(gpio_dev->base + offset * 4); 79 pin_reg |= BIT(OUTPUT_ENABLE_OFF); 80 if (value) 81 pin_reg |= BIT(OUTPUT_VALUE_OFF); 82 else 83 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 84 writel(pin_reg, gpio_dev->base + offset * 4); 85 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 86 87 return 0; 88 } 89 90 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset) 91 { 92 u32 pin_reg; 93 unsigned long flags; 94 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 95 96 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 97 pin_reg = readl(gpio_dev->base + offset * 4); 98 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 99 100 return !!(pin_reg & BIT(PIN_STS_OFF)); 101 } 102 103 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value) 104 { 105 u32 pin_reg; 106 unsigned long flags; 107 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 108 109 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 110 pin_reg = readl(gpio_dev->base + offset * 4); 111 if (value) 112 pin_reg |= BIT(OUTPUT_VALUE_OFF); 113 else 114 pin_reg &= ~BIT(OUTPUT_VALUE_OFF); 115 writel(pin_reg, gpio_dev->base + offset * 4); 116 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 117 } 118 119 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset, 120 unsigned debounce) 121 { 122 u32 time; 123 u32 pin_reg; 124 int ret = 0; 125 unsigned long flags; 126 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 127 128 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 129 pin_reg = readl(gpio_dev->base + offset * 4); 130 131 if (debounce) { 132 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 133 pin_reg &= ~DB_TMR_OUT_MASK; 134 /* 135 Debounce Debounce Timer Max 136 TmrLarge TmrOutUnit Unit Debounce 137 Time 138 0 0 61 usec (2 RtcClk) 976 usec 139 0 1 244 usec (8 RtcClk) 3.9 msec 140 1 0 15.6 msec (512 RtcClk) 250 msec 141 1 1 62.5 msec (2048 RtcClk) 1 sec 142 */ 143 144 if (debounce < 61) { 145 pin_reg |= 1; 146 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 147 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 148 } else if (debounce < 976) { 149 time = debounce / 61; 150 pin_reg |= time & DB_TMR_OUT_MASK; 151 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 152 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 153 } else if (debounce < 3900) { 154 time = debounce / 244; 155 pin_reg |= time & DB_TMR_OUT_MASK; 156 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 158 } else if (debounce < 250000) { 159 time = debounce / 15600; 160 pin_reg |= time & DB_TMR_OUT_MASK; 161 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 162 pin_reg |= BIT(DB_TMR_LARGE_OFF); 163 } else if (debounce < 1000000) { 164 time = debounce / 62500; 165 pin_reg |= time & DB_TMR_OUT_MASK; 166 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF); 167 pin_reg |= BIT(DB_TMR_LARGE_OFF); 168 } else { 169 pin_reg &= ~DB_CNTRl_MASK; 170 ret = -EINVAL; 171 } 172 } else { 173 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF); 174 pin_reg &= ~BIT(DB_TMR_LARGE_OFF); 175 pin_reg &= ~DB_TMR_OUT_MASK; 176 pin_reg &= ~DB_CNTRl_MASK; 177 } 178 writel(pin_reg, gpio_dev->base + offset * 4); 179 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 180 181 return ret; 182 } 183 184 static int amd_gpio_set_config(struct gpio_chip *gc, unsigned offset, 185 unsigned long config) 186 { 187 u32 debounce; 188 189 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 190 return -ENOTSUPP; 191 192 debounce = pinconf_to_config_argument(config); 193 return amd_gpio_set_debounce(gc, offset, debounce); 194 } 195 196 #ifdef CONFIG_DEBUG_FS 197 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc) 198 { 199 u32 pin_reg; 200 unsigned long flags; 201 unsigned int bank, i, pin_num; 202 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 203 204 char *level_trig; 205 char *active_level; 206 char *interrupt_enable; 207 char *interrupt_mask; 208 char *wake_cntrl0; 209 char *wake_cntrl1; 210 char *wake_cntrl2; 211 char *pin_sts; 212 char *pull_up_sel; 213 char *pull_up_enable; 214 char *pull_down_enable; 215 char *output_value; 216 char *output_enable; 217 218 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) { 219 seq_printf(s, "GPIO bank%d\t", bank); 220 221 switch (bank) { 222 case 0: 223 i = 0; 224 pin_num = AMD_GPIO_PINS_BANK0; 225 break; 226 case 1: 227 i = 64; 228 pin_num = AMD_GPIO_PINS_BANK1 + i; 229 break; 230 case 2: 231 i = 128; 232 pin_num = AMD_GPIO_PINS_BANK2 + i; 233 break; 234 case 3: 235 i = 192; 236 pin_num = AMD_GPIO_PINS_BANK3 + i; 237 break; 238 default: 239 /* Illegal bank number, ignore */ 240 continue; 241 } 242 for (; i < pin_num; i++) { 243 seq_printf(s, "pin%d\t", i); 244 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 245 pin_reg = readl(gpio_dev->base + i * 4); 246 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 247 248 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) { 249 u8 level = (pin_reg >> ACTIVE_LEVEL_OFF) & 250 ACTIVE_LEVEL_MASK; 251 interrupt_enable = "interrupt is enabled|"; 252 253 if (level == ACTIVE_LEVEL_HIGH) 254 active_level = "Active high|"; 255 else if (level == ACTIVE_LEVEL_LOW) 256 active_level = "Active low|"; 257 else if (!(pin_reg & BIT(LEVEL_TRIG_OFF)) && 258 level == ACTIVE_LEVEL_BOTH) 259 active_level = "Active on both|"; 260 else 261 active_level = "Unknown Active level|"; 262 263 if (pin_reg & BIT(LEVEL_TRIG_OFF)) 264 level_trig = "Level trigger|"; 265 else 266 level_trig = "Edge trigger|"; 267 268 } else { 269 interrupt_enable = 270 "interrupt is disabled|"; 271 active_level = " "; 272 level_trig = " "; 273 } 274 275 if (pin_reg & BIT(INTERRUPT_MASK_OFF)) 276 interrupt_mask = 277 "interrupt is unmasked|"; 278 else 279 interrupt_mask = 280 "interrupt is masked|"; 281 282 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3)) 283 wake_cntrl0 = "enable wakeup in S0i3 state|"; 284 else 285 wake_cntrl0 = "disable wakeup in S0i3 state|"; 286 287 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3)) 288 wake_cntrl1 = "enable wakeup in S3 state|"; 289 else 290 wake_cntrl1 = "disable wakeup in S3 state|"; 291 292 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4)) 293 wake_cntrl2 = "enable wakeup in S4/S5 state|"; 294 else 295 wake_cntrl2 = "disable wakeup in S4/S5 state|"; 296 297 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) { 298 pull_up_enable = "pull-up is enabled|"; 299 if (pin_reg & BIT(PULL_UP_SEL_OFF)) 300 pull_up_sel = "8k pull-up|"; 301 else 302 pull_up_sel = "4k pull-up|"; 303 } else { 304 pull_up_enable = "pull-up is disabled|"; 305 pull_up_sel = " "; 306 } 307 308 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF)) 309 pull_down_enable = "pull-down is enabled|"; 310 else 311 pull_down_enable = "Pull-down is disabled|"; 312 313 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) { 314 pin_sts = " "; 315 output_enable = "output is enabled|"; 316 if (pin_reg & BIT(OUTPUT_VALUE_OFF)) 317 output_value = "output is high|"; 318 else 319 output_value = "output is low|"; 320 } else { 321 output_enable = "output is disabled|"; 322 output_value = " "; 323 324 if (pin_reg & BIT(PIN_STS_OFF)) 325 pin_sts = "input is high|"; 326 else 327 pin_sts = "input is low|"; 328 } 329 330 seq_printf(s, "%s %s %s %s %s %s\n" 331 " %s %s %s %s %s %s %s 0x%x\n", 332 level_trig, active_level, interrupt_enable, 333 interrupt_mask, wake_cntrl0, wake_cntrl1, 334 wake_cntrl2, pin_sts, pull_up_sel, 335 pull_up_enable, pull_down_enable, 336 output_value, output_enable, pin_reg); 337 } 338 } 339 } 340 #else 341 #define amd_gpio_dbg_show NULL 342 #endif 343 344 static void amd_gpio_irq_enable(struct irq_data *d) 345 { 346 u32 pin_reg; 347 unsigned long flags; 348 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 349 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 350 351 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 352 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 353 pin_reg |= BIT(INTERRUPT_ENABLE_OFF); 354 pin_reg |= BIT(INTERRUPT_MASK_OFF); 355 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 356 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 357 } 358 359 static void amd_gpio_irq_disable(struct irq_data *d) 360 { 361 u32 pin_reg; 362 unsigned long flags; 363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 364 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 365 366 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 367 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 368 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF); 369 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 370 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 371 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 372 } 373 374 static void amd_gpio_irq_mask(struct irq_data *d) 375 { 376 u32 pin_reg; 377 unsigned long flags; 378 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 379 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 380 381 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 382 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 383 pin_reg &= ~BIT(INTERRUPT_MASK_OFF); 384 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 385 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 386 } 387 388 static void amd_gpio_irq_unmask(struct irq_data *d) 389 { 390 u32 pin_reg; 391 unsigned long flags; 392 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 393 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 394 395 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 396 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 397 pin_reg |= BIT(INTERRUPT_MASK_OFF); 398 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 399 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 400 } 401 402 static void amd_gpio_irq_eoi(struct irq_data *d) 403 { 404 u32 reg; 405 unsigned long flags; 406 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 407 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 408 409 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 410 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 411 reg |= EOI_MASK; 412 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG); 413 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 414 } 415 416 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type) 417 { 418 int ret = 0; 419 u32 pin_reg, pin_reg_irq_en, mask; 420 unsigned long flags, irq_flags; 421 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 422 struct amd_gpio *gpio_dev = gpiochip_get_data(gc); 423 424 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 425 pin_reg = readl(gpio_dev->base + (d->hwirq)*4); 426 427 /* Ignore the settings coming from the client and 428 * read the values from the ACPI tables 429 * while setting the trigger type 430 */ 431 432 irq_flags = irq_get_trigger_type(d->irq); 433 if (irq_flags != IRQ_TYPE_NONE) 434 type = irq_flags; 435 436 switch (type & IRQ_TYPE_SENSE_MASK) { 437 case IRQ_TYPE_EDGE_RISING: 438 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 439 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 440 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 441 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 442 irq_set_handler_locked(d, handle_edge_irq); 443 break; 444 445 case IRQ_TYPE_EDGE_FALLING: 446 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 447 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 448 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 449 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 450 irq_set_handler_locked(d, handle_edge_irq); 451 break; 452 453 case IRQ_TYPE_EDGE_BOTH: 454 pin_reg &= ~BIT(LEVEL_TRIG_OFF); 455 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 456 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF; 457 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF; 458 irq_set_handler_locked(d, handle_edge_irq); 459 break; 460 461 case IRQ_TYPE_LEVEL_HIGH: 462 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 463 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 464 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF; 465 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 466 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF; 467 irq_set_handler_locked(d, handle_level_irq); 468 break; 469 470 case IRQ_TYPE_LEVEL_LOW: 471 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF; 472 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF); 473 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF; 474 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF); 475 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF; 476 irq_set_handler_locked(d, handle_level_irq); 477 break; 478 479 case IRQ_TYPE_NONE: 480 break; 481 482 default: 483 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n"); 484 ret = -EINVAL; 485 } 486 487 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF; 488 /* 489 * If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the 490 * debounce registers of any GPIO will block wake/interrupt status 491 * generation for *all* GPIOs for a length of time that depends on 492 * WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the 493 * INTERRUPT_ENABLE bit will read as 0. 494 * 495 * We temporarily enable irq for the GPIO whose configuration is 496 * changing, and then wait for it to read back as 1 to know when 497 * debounce has settled and then disable the irq again. 498 * We do this polling with the spinlock held to ensure other GPIO 499 * access routines do not read an incorrect value for the irq enable 500 * bit of other GPIOs. We keep the GPIO masked while polling to avoid 501 * spurious irqs, and disable the irq again after polling. 502 */ 503 mask = BIT(INTERRUPT_ENABLE_OFF); 504 pin_reg_irq_en = pin_reg; 505 pin_reg_irq_en |= mask; 506 pin_reg_irq_en &= ~BIT(INTERRUPT_MASK_OFF); 507 writel(pin_reg_irq_en, gpio_dev->base + (d->hwirq)*4); 508 while ((readl(gpio_dev->base + (d->hwirq)*4) & mask) != mask) 509 continue; 510 writel(pin_reg, gpio_dev->base + (d->hwirq)*4); 511 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 512 513 return ret; 514 } 515 516 static void amd_irq_ack(struct irq_data *d) 517 { 518 /* 519 * based on HW design,there is no need to ack HW 520 * before handle current irq. But this routine is 521 * necessary for handle_edge_irq 522 */ 523 } 524 525 static struct irq_chip amd_gpio_irqchip = { 526 .name = "amd_gpio", 527 .irq_ack = amd_irq_ack, 528 .irq_enable = amd_gpio_irq_enable, 529 .irq_disable = amd_gpio_irq_disable, 530 .irq_mask = amd_gpio_irq_mask, 531 .irq_unmask = amd_gpio_irq_unmask, 532 .irq_eoi = amd_gpio_irq_eoi, 533 .irq_set_type = amd_gpio_irq_set_type, 534 .flags = IRQCHIP_SKIP_SET_WAKE, 535 }; 536 537 #define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF)) 538 539 static irqreturn_t amd_gpio_irq_handler(int irq, void *dev_id) 540 { 541 struct amd_gpio *gpio_dev = dev_id; 542 struct gpio_chip *gc = &gpio_dev->gc; 543 irqreturn_t ret = IRQ_NONE; 544 unsigned int i, irqnr; 545 unsigned long flags; 546 u32 __iomem *regs; 547 u32 regval; 548 u64 status, mask; 549 550 /* Read the wake status */ 551 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 552 status = readl(gpio_dev->base + WAKE_INT_STATUS_REG1); 553 status <<= 32; 554 status |= readl(gpio_dev->base + WAKE_INT_STATUS_REG0); 555 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 556 557 /* Bit 0-45 contain the relevant status bits */ 558 status &= (1ULL << 46) - 1; 559 regs = gpio_dev->base; 560 for (mask = 1, irqnr = 0; status; mask <<= 1, regs += 4, irqnr += 4) { 561 if (!(status & mask)) 562 continue; 563 status &= ~mask; 564 565 /* Each status bit covers four pins */ 566 for (i = 0; i < 4; i++) { 567 regval = readl(regs + i); 568 if (!(regval & PIN_IRQ_PENDING) || 569 !(regval & BIT(INTERRUPT_MASK_OFF))) 570 continue; 571 irq = irq_find_mapping(gc->irq.domain, irqnr + i); 572 if (irq != 0) 573 generic_handle_irq(irq); 574 575 /* Clear interrupt. 576 * We must read the pin register again, in case the 577 * value was changed while executing 578 * generic_handle_irq() above. 579 * If we didn't find a mapping for the interrupt, 580 * disable it in order to avoid a system hang caused 581 * by an interrupt storm. 582 */ 583 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 584 regval = readl(regs + i); 585 if (irq == 0) { 586 regval &= ~BIT(INTERRUPT_ENABLE_OFF); 587 dev_dbg(&gpio_dev->pdev->dev, 588 "Disabling spurious GPIO IRQ %d\n", 589 irqnr + i); 590 } 591 writel(regval, regs + i); 592 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 593 ret = IRQ_HANDLED; 594 } 595 } 596 597 /* Signal EOI to the GPIO unit */ 598 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 599 regval = readl(gpio_dev->base + WAKE_INT_MASTER_REG); 600 regval |= EOI_MASK; 601 writel(regval, gpio_dev->base + WAKE_INT_MASTER_REG); 602 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 603 604 return ret; 605 } 606 607 static int amd_get_groups_count(struct pinctrl_dev *pctldev) 608 { 609 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 610 611 return gpio_dev->ngroups; 612 } 613 614 static const char *amd_get_group_name(struct pinctrl_dev *pctldev, 615 unsigned group) 616 { 617 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 618 619 return gpio_dev->groups[group].name; 620 } 621 622 static int amd_get_group_pins(struct pinctrl_dev *pctldev, 623 unsigned group, 624 const unsigned **pins, 625 unsigned *num_pins) 626 { 627 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 628 629 *pins = gpio_dev->groups[group].pins; 630 *num_pins = gpio_dev->groups[group].npins; 631 return 0; 632 } 633 634 static const struct pinctrl_ops amd_pinctrl_ops = { 635 .get_groups_count = amd_get_groups_count, 636 .get_group_name = amd_get_group_name, 637 .get_group_pins = amd_get_group_pins, 638 #ifdef CONFIG_OF 639 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 640 .dt_free_map = pinctrl_utils_free_map, 641 #endif 642 }; 643 644 static int amd_pinconf_get(struct pinctrl_dev *pctldev, 645 unsigned int pin, 646 unsigned long *config) 647 { 648 u32 pin_reg; 649 unsigned arg; 650 unsigned long flags; 651 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 652 enum pin_config_param param = pinconf_to_config_param(*config); 653 654 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 655 pin_reg = readl(gpio_dev->base + pin*4); 656 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 657 switch (param) { 658 case PIN_CONFIG_INPUT_DEBOUNCE: 659 arg = pin_reg & DB_TMR_OUT_MASK; 660 break; 661 662 case PIN_CONFIG_BIAS_PULL_DOWN: 663 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0); 664 break; 665 666 case PIN_CONFIG_BIAS_PULL_UP: 667 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1)); 668 break; 669 670 case PIN_CONFIG_DRIVE_STRENGTH: 671 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK; 672 break; 673 674 default: 675 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n", 676 param); 677 return -ENOTSUPP; 678 } 679 680 *config = pinconf_to_config_packed(param, arg); 681 682 return 0; 683 } 684 685 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin, 686 unsigned long *configs, unsigned num_configs) 687 { 688 int i; 689 u32 arg; 690 int ret = 0; 691 u32 pin_reg; 692 unsigned long flags; 693 enum pin_config_param param; 694 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev); 695 696 raw_spin_lock_irqsave(&gpio_dev->lock, flags); 697 for (i = 0; i < num_configs; i++) { 698 param = pinconf_to_config_param(configs[i]); 699 arg = pinconf_to_config_argument(configs[i]); 700 pin_reg = readl(gpio_dev->base + pin*4); 701 702 switch (param) { 703 case PIN_CONFIG_INPUT_DEBOUNCE: 704 pin_reg &= ~DB_TMR_OUT_MASK; 705 pin_reg |= arg & DB_TMR_OUT_MASK; 706 break; 707 708 case PIN_CONFIG_BIAS_PULL_DOWN: 709 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF); 710 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF; 711 break; 712 713 case PIN_CONFIG_BIAS_PULL_UP: 714 pin_reg &= ~BIT(PULL_UP_SEL_OFF); 715 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF; 716 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF); 717 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF; 718 break; 719 720 case PIN_CONFIG_DRIVE_STRENGTH: 721 pin_reg &= ~(DRV_STRENGTH_SEL_MASK 722 << DRV_STRENGTH_SEL_OFF); 723 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK) 724 << DRV_STRENGTH_SEL_OFF; 725 break; 726 727 default: 728 dev_err(&gpio_dev->pdev->dev, 729 "Invalid config param %04x\n", param); 730 ret = -ENOTSUPP; 731 } 732 733 writel(pin_reg, gpio_dev->base + pin*4); 734 } 735 raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); 736 737 return ret; 738 } 739 740 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev, 741 unsigned int group, 742 unsigned long *config) 743 { 744 const unsigned *pins; 745 unsigned npins; 746 int ret; 747 748 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 749 if (ret) 750 return ret; 751 752 if (amd_pinconf_get(pctldev, pins[0], config)) 753 return -ENOTSUPP; 754 755 return 0; 756 } 757 758 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev, 759 unsigned group, unsigned long *configs, 760 unsigned num_configs) 761 { 762 const unsigned *pins; 763 unsigned npins; 764 int i, ret; 765 766 ret = amd_get_group_pins(pctldev, group, &pins, &npins); 767 if (ret) 768 return ret; 769 for (i = 0; i < npins; i++) { 770 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs)) 771 return -ENOTSUPP; 772 } 773 return 0; 774 } 775 776 static const struct pinconf_ops amd_pinconf_ops = { 777 .pin_config_get = amd_pinconf_get, 778 .pin_config_set = amd_pinconf_set, 779 .pin_config_group_get = amd_pinconf_group_get, 780 .pin_config_group_set = amd_pinconf_group_set, 781 }; 782 783 #ifdef CONFIG_PM_SLEEP 784 static bool amd_gpio_should_save(struct amd_gpio *gpio_dev, unsigned int pin) 785 { 786 const struct pin_desc *pd = pin_desc_get(gpio_dev->pctrl, pin); 787 788 if (!pd) 789 return false; 790 791 /* 792 * Only restore the pin if it is actually in use by the kernel (or 793 * by userspace). 794 */ 795 if (pd->mux_owner || pd->gpio_owner || 796 gpiochip_line_is_irq(&gpio_dev->gc, pin)) 797 return true; 798 799 return false; 800 } 801 802 static int amd_gpio_suspend(struct device *dev) 803 { 804 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 805 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 806 int i; 807 808 for (i = 0; i < desc->npins; i++) { 809 int pin = desc->pins[i].number; 810 811 if (!amd_gpio_should_save(gpio_dev, pin)) 812 continue; 813 814 gpio_dev->saved_regs[i] = readl(gpio_dev->base + pin*4); 815 } 816 817 return 0; 818 } 819 820 static int amd_gpio_resume(struct device *dev) 821 { 822 struct amd_gpio *gpio_dev = dev_get_drvdata(dev); 823 struct pinctrl_desc *desc = gpio_dev->pctrl->desc; 824 int i; 825 826 for (i = 0; i < desc->npins; i++) { 827 int pin = desc->pins[i].number; 828 829 if (!amd_gpio_should_save(gpio_dev, pin)) 830 continue; 831 832 writel(gpio_dev->saved_regs[i], gpio_dev->base + pin*4); 833 } 834 835 return 0; 836 } 837 838 static const struct dev_pm_ops amd_gpio_pm_ops = { 839 SET_LATE_SYSTEM_SLEEP_PM_OPS(amd_gpio_suspend, 840 amd_gpio_resume) 841 }; 842 #endif 843 844 static struct pinctrl_desc amd_pinctrl_desc = { 845 .pins = kerncz_pins, 846 .npins = ARRAY_SIZE(kerncz_pins), 847 .pctlops = &amd_pinctrl_ops, 848 .confops = &amd_pinconf_ops, 849 .owner = THIS_MODULE, 850 }; 851 852 static int amd_gpio_probe(struct platform_device *pdev) 853 { 854 int ret = 0; 855 int irq_base; 856 struct resource *res; 857 struct amd_gpio *gpio_dev; 858 859 gpio_dev = devm_kzalloc(&pdev->dev, 860 sizeof(struct amd_gpio), GFP_KERNEL); 861 if (!gpio_dev) 862 return -ENOMEM; 863 864 raw_spin_lock_init(&gpio_dev->lock); 865 866 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 867 if (!res) { 868 dev_err(&pdev->dev, "Failed to get gpio io resource.\n"); 869 return -EINVAL; 870 } 871 872 gpio_dev->base = devm_ioremap(&pdev->dev, res->start, 873 resource_size(res)); 874 if (!gpio_dev->base) 875 return -ENOMEM; 876 877 irq_base = platform_get_irq(pdev, 0); 878 if (irq_base < 0) 879 return irq_base; 880 881 #ifdef CONFIG_PM_SLEEP 882 gpio_dev->saved_regs = devm_kcalloc(&pdev->dev, amd_pinctrl_desc.npins, 883 sizeof(*gpio_dev->saved_regs), 884 GFP_KERNEL); 885 if (!gpio_dev->saved_regs) 886 return -ENOMEM; 887 #endif 888 889 gpio_dev->pdev = pdev; 890 gpio_dev->gc.get_direction = amd_gpio_get_direction; 891 gpio_dev->gc.direction_input = amd_gpio_direction_input; 892 gpio_dev->gc.direction_output = amd_gpio_direction_output; 893 gpio_dev->gc.get = amd_gpio_get_value; 894 gpio_dev->gc.set = amd_gpio_set_value; 895 gpio_dev->gc.set_config = amd_gpio_set_config; 896 gpio_dev->gc.dbg_show = amd_gpio_dbg_show; 897 898 gpio_dev->gc.base = -1; 899 gpio_dev->gc.label = pdev->name; 900 gpio_dev->gc.owner = THIS_MODULE; 901 gpio_dev->gc.parent = &pdev->dev; 902 gpio_dev->gc.ngpio = resource_size(res) / 4; 903 #if defined(CONFIG_OF_GPIO) 904 gpio_dev->gc.of_node = pdev->dev.of_node; 905 #endif 906 907 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64; 908 gpio_dev->groups = kerncz_groups; 909 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups); 910 911 amd_pinctrl_desc.name = dev_name(&pdev->dev); 912 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc, 913 gpio_dev); 914 if (IS_ERR(gpio_dev->pctrl)) { 915 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); 916 return PTR_ERR(gpio_dev->pctrl); 917 } 918 919 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev); 920 if (ret) 921 return ret; 922 923 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev), 924 0, 0, gpio_dev->gc.ngpio); 925 if (ret) { 926 dev_err(&pdev->dev, "Failed to add pin range\n"); 927 goto out2; 928 } 929 930 ret = gpiochip_irqchip_add(&gpio_dev->gc, 931 &amd_gpio_irqchip, 932 0, 933 handle_simple_irq, 934 IRQ_TYPE_NONE); 935 if (ret) { 936 dev_err(&pdev->dev, "could not add irqchip\n"); 937 ret = -ENODEV; 938 goto out2; 939 } 940 941 ret = devm_request_irq(&pdev->dev, irq_base, amd_gpio_irq_handler, 942 IRQF_SHARED, KBUILD_MODNAME, gpio_dev); 943 if (ret) 944 goto out2; 945 946 platform_set_drvdata(pdev, gpio_dev); 947 948 dev_dbg(&pdev->dev, "amd gpio driver loaded\n"); 949 return ret; 950 951 out2: 952 gpiochip_remove(&gpio_dev->gc); 953 954 return ret; 955 } 956 957 static int amd_gpio_remove(struct platform_device *pdev) 958 { 959 struct amd_gpio *gpio_dev; 960 961 gpio_dev = platform_get_drvdata(pdev); 962 963 gpiochip_remove(&gpio_dev->gc); 964 965 return 0; 966 } 967 968 static const struct acpi_device_id amd_gpio_acpi_match[] = { 969 { "AMD0030", 0 }, 970 { "AMDI0030", 0}, 971 { }, 972 }; 973 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match); 974 975 static struct platform_driver amd_gpio_driver = { 976 .driver = { 977 .name = "amd_gpio", 978 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match), 979 #ifdef CONFIG_PM_SLEEP 980 .pm = &amd_gpio_pm_ops, 981 #endif 982 }, 983 .probe = amd_gpio_probe, 984 .remove = amd_gpio_remove, 985 }; 986 987 module_platform_driver(amd_gpio_driver); 988 989 MODULE_LICENSE("GPL v2"); 990 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>"); 991 MODULE_DESCRIPTION("AMD GPIO pinctrl driver"); 992